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This is a multi-part message in MIME format. --------------21974C5A0B239DB706EEAB42 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dear Jeremy, I have toagree with the other newsgroup members. Your solicitation is not really what this news group is about. I my not sound as emotional as some of the other responses but my feelings are in agreement. Aside from the fact that I think your pyramid scheme preys on people who are desperate and need better help than you are offering. Please respect the wishes of the newsgroup and leave your advertisement off this thread. I would be surprised if you get even one positive response on this thread. Hope to never hear from you again. Best Regards Terry J Klukan wrote: > Want a free computer? I mean REALLY free--no gimmicks or gags and > really easy to do! Don't pass up this superb offer. Here's what you > get: > -IBM Pentium 233 MMX-classified processor (faster than Intel) > -Mini-tower case > -7 expansion slots (5 open) > -32mb RAM > -4.3gb hard drive (Quantum or Cyrix) > -3.5 floppy drive > -56k flex Fax/Modem > -Acer 24X CD-ROM drive > -16-bit MMX sound card > -Cyrix Logic 5466 full-3D video card (DVD Compatible) > -80-watt speakers > -L2 meg cache w/ TXPIO motherboard > -Digi-View 15" SVGA monitor > -Windows95 and over 70 software titles > Software includes: > Microsoft Office97 Professional, Microsoft Internet Explorer 4.0, > Groliers Multimedia Encyclopedia, 3D Key Design Center, 3D Card > Design, Video Game Pack, Master Clip 6000 (clipart), Media Wizard > Design, Bitware, Zoo Explorer, and much more! > > And...it's all FREE!!! > "What's the catch?" you ask. The catch is not really a catch at all. > All you need to do is sign up 6 people for this program under you. > That's it! Sign up 6 people for this great program with you as their > sponsor and you're done. You never need to do anything else with this > program again. You will have 30 days to sign up these 6 > people...which should be no problem. If you don't sign up all 6 in > time, you will have to begin paying the lease until you have signed up > 6 people. If you sign up 6 or more people, the lease will be paid for > you and as an added bonus, you will receive $150 for every person that > you signed up. Even if you don't get 6 people within 30 days, if you > get one person you will have $150, which can be applied to the lease > payment. > "What happens when I've signed up all 6 people?" you ask. Once you > have signed up 6 or more people, you are under no obligation to > continue participating in this program. This program is incredible! > "How do I get involved?" It's easy. Go to this web site: > http://www.camelotenterprises.com/jklukan/ > read through the information presented there, and if you're still > interested, follow the instructions there. If you have any questions, > feel free to e-mail me (this address and the one listed there end up > at the same mailbox) and I'll try to answer them. > Thank you for your interest! > > -Jeremy > > PS: This is not spam. I have posted it to newsgroups that I have > found computer-related material in. Please do not criticize me for > that. -- ___ ___ / ^/ /\ /___/ \ / Terry L. Zumwalt Xilinx Inc. \ \ v 4100 McEwen Field Applications Engineer \ \ Suite 237 Phone: (972) 960-1043 / / Dallas, TX Fax: (972) 960-0927 /___/ ^ 75244 E-Mail: terry.zumwalt@xilinx.com \ \ / \ USA Applications Hotline: 800-255-7778 \___v\__\/ Xilinx Home Page - http://www.xilinx.com --------------21974C5A0B239DB706EEAB42 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Terry L. Zumwalt Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Terry L. Zumwalt n: Zumwalt;Terry L. org: Xilinx Inc. adr: 4100 McEwen Suite #237;;;Dallas;Texas;75244;USA email;internet: terry.zumwalt@xilinx.com title: Field Applications Engineer tel;work: (972) 960-1043 tel;fax: (972) 960-0927 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------21974C5A0B239DB706EEAB42--Article: 10876
ems wrote: > > On Fri, 26 Jun 1998 12:07:51 GMT, timolmst@cyberramp.net wrote: > > >Have you tried using the design that worked as a guide file for making > >the changes? This might help. > > good idea - except that i've never managed a successful guided design > on a 4KE with foundation. the normal problem is a crash, but i seem to > remember that there's a second problem as well. i think that there's > now a patch for the crash; i'll give this a go if everything else > fails. > > thanks > > evan I had the same crash result when I attempted to perform a guided design on a 4013XL. Is this a known bug in M1.4? -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10877
ems wrote: > > On Fri, 26 Jun 1998 10:36:52 -0400, Ray Andraka > <no_spam_randraka@ids.net> wrote: > > >I am not a big fan of doing timing analysis by simulation for this very > >reason. It is too easy to miss something critical by not supplying the > >correct timing in the simulation vectors > > true enough, but a static analysis doesn't get around this. By this, I assume that you mean the static timing analysis doesn't find any problems? > > or by not adequately simulating all the min/max, min/min and max/max > > situations. > > ditto above. the other problem, of course, is that xilinx only > supplies one number, which makes sophisticated analysis rather > difficult. If you are using a fully synchronous design, you don't need min delays except to assure hold times. As long as you are guaranteed (as Xilinx does) adequate hold time internal to the chip, you won't have a problem. > >I advocate a thorough > >static timing analysis instead (another good reason to keep the design > >synchronous). > > i personally prefer timing by constraint. however, since this doesn't > work well (particularly in multiple-clock devices), i also have to do > a simulation to find out what the constraints actually did, or didn't > do. When you say you have multiple clocks, are you interfacing data or control signals between different clock domains? If so, do you take precautions against metastability in the control and data signals? For control signals, you need to run them through two clocked FFs before fanning out to multiple circuits. Otherwise a metastable signal can be interpreted differently by one destination vs. another. For a data path, the only way to prevent metastability is to use the reclocked control logic to assure that setup times are met. > the problems with static analysis include multiple clocks, clock > enables, and signals which cross clock boundaries. this device > has a main clock of 64MHz. it's a fairly large device, and some > of the logic wont cycle at 15ns, so i generate lower-frequency > clocks, which are also used as clock enables on the high > frequency. the enable timing is a function of the logic, and > a static analysis wont be able to deduce this. it'll simply > assume that a block that's clocked at 15ns is meant to cycle at 15ns > when, in fact, it's meant to cycle at 2*15ns, 3*15ns, or whatever. You can tell the tools that the data path (or control path) is slower than the CE path. There is a note on this in issue 28 of XCELL, the Xilinx news/info/advertising "journal". The title is cryptically "Reduce Compile Times". I guess they are suggesting that the use of distinct timing constraints on data path and clock enable will allow the router to complete in a shorter time, rather than just making a design possible. True, but not my goal in life. I am concerned about "making it work", most of the time. Anyway, the article should be on their web site. You may need the title or issue number to find it. Or you could try searching on "clock enable" or "multi-cycle". > >The timing tools are accurate; The reports can be trusted > >to be correct. > > i wish i believed this! i've checked the speed files, and there > doesn't seem to be anything later than the ones which came > with F1.4. i'm afraid that i'm (slowly) coming to the conclusion that > the tools simply aren't up to coping with multiple-clock devices. Have you checked the web site? I believe that I found some updated speed files for some parts since the M1.4 release. -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10878
The best way to deal with such things is for everyone to reply to the sender. I have already sent him a message indicating what I think. If enough people did that, it would make the posting not worth the junk replies. In fact this guy took the time to send me a reply! The real problem is with the spammers that are advertising a web site or post a long distance phone number. There is not much point in wasting your time and money to reply to those. But if they post a valid email address, then they are fair game! Terry L. Zumwalt wrote: > > Dear Jeremy, > > I have toagree with the other newsgroup members. Your solicitation is not really > what this news group is about. I my not sound as emotional as some of the other > responses but my feelings are in agreement. Aside from the fact that I think > your pyramid scheme preys on people who are desperate and need better help than > you are offering. Please respect the wishes of the newsgroup and leave your > advertisement off this thread. I would be surprised if you get even one positive > response on this thread. > > Hope to never hear from you again. > Best Regards > Terry > > J Klukan wrote: ...snip... > > All you need to do is sign up 6 people for this program under you. > > That's it! Sign up 6 people for this great program with you as their > > sponsor and you're done. You never need to do anything else with this > > program again. You will have 30 days to sign up these 6 > > people...which should be no problem. If you don't sign up all 6 in > > time, you will have to begin paying the lease until you have signed ...snip... > > > > -Jeremy > > > > PS: This is not spam. I have posted it to newsgroups that I have > > found computer-related material in. Please do not criticize me for > > that. > > -- > ___ ___ > / ^/ /\ > /___/ \ / Terry L. Zumwalt Xilinx Inc. > \ \ v 4100 McEwen Field Applications Engineer > \ \ Suite 237 Phone: (972) 960-1043 > / / Dallas, TX Fax: (972) 960-0927 > /___/ ^ 75244 E-Mail: terry.zumwalt@xilinx.com > \ \ / \ USA Applications Hotline: 800-255-7778 > \___v\__\/ Xilinx Home Page - http://www.xilinx.com > -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10879
0.136A79A4@yahoo.com>
Organization: Compaq Systems Research Center
Keywords:
I apologize for adding to the clutter, but...
In article <35943C40.136A79A4@yahoo.com>, Rickman <spamgoeshere2@yahoo.com> writ
es:
> The best way to deal with such things is for everyone to reply to the
> sender. I have already sent him a message indicating what I think. If
> enough people did that, it would make the posting not worth the junk
> replies. In fact this guy took the time to send me a reply!
Beware: The from/reply-to address is easily forged. If you just
use the Reply command your complaint will most likely bounce or
harrass an innocent person.
There is a lot of good anti-spam info on the web. Many pages have
links to other anti-spam sites. You can spend a lot of time surfing
without leaving the anti-spam zone. Some pages are better than others.
Browse around and look for several opinions until you get a feel that
makes sense.
If you want to complain, here is a good place to start:
http://www.tezcat.com/~gbyshenk/ive.been.spammed.html
For general background on spam, try these:
shuksan 93> cat !$
cat dea*
From murray Fri Jun 26 19:22:44 1998
From: murray@pa.dec.com (Hal Murray)
Subject: Re: Free Computer (Read--Easy, No money down)
Path: murray
Newsgroups: comp.arch.embedded,comp.arch.fpga,comp.arch.storage
Distribution:
Followup-To: sender
References: <3580c820.0@news.bigsky.net> <35943018.45BB35E4@xilinx.com> <35943C40.136A79A4@yahoo.com>
Organization: Compaq Systems Research Center
Keywords:
I apologize for adding to the clutter, but...
In article <35943C40.136A79A4@yahoo.com>, Rickman <spamgoeshere2@yahoo.com> writes:
> The best way to deal with such things is for everyone to reply to the
> sender. I have already sent him a message indicating what I think. If
> enough people did that, it would make the posting not worth the junk
> replies. In fact this guy took the time to send me a reply!
Beware: The from/reply-to address is easily forged. If you just
use the Reply command your complaint will most likely bounce or
harrass an innocent person.
There is a lot of good anti-spam info on the web. Many pages have
links to other anti-spam sites. You can spend a lot of time surfing
without leaving the anti-spam zone. Some pages are better than others.
Browse around and look for several opinions until you get a feel that
makes sense.
If you want to complain, here is a good place to start:
http://www.tezcat.com/~gbyshenk/ive.been.spammed.html
For general background on spam, try these:
http://spam.abuse.net/spam/
http://www.cauce.org/
http://www.ybecker.net/
--
These are my opinions, not necessarily my employers.
Article: 10880Hi, We're Hunter International, and we are currently looking for qualified DSP based Engineering Professionals from a broad variety of disciplines. Our client is one of, if not THE, best firms you could be associated with in the Northern California area. This beautiful firm, located in the Silicon Valley, is simply at the top of it's class with opportunities and care for it's employees. The benefits are second to none, and the technology is stellar, so you can't go wrong. There is even a fully functioning Health Club built into the premises! We absolutely guarantee that you will be thrilled with this firm if you are qualified! PLEASE note before you read further: This company is a publicly held, incredibly successful firm, BUT, because of certain clients, they do require the ability to secure a Secret Clearance. This means citizenship of you, and your direct family to Mother and Father, if they are still living. Because of this, the candidate pool becomes thin. So if you are qualified, AND can get clearance, you will be received with enthusiasm and given the 'red carpet' treatment, as they need engineers in a big way! In an effort to help with the massive growth they are experiencing, we need to find Engineers who fall into the areas of expertise listed below. The descriptions are intentionally brief, and this is because the amount of available jobs are more than you could read through in a single post. All jobs are new positions, not vacancies. Software Engineers: *Experience developing Real-Time, software intensive projects using Ada, C, C++, in a UNIX, NT, and/or VMS environment. *Requirements definition, preliminary/detailed design code/unit testing and software integration. *Familiarity with OO methodologies, signal processing, telecommunications, distributed systems, GUI builders, reusable software, relational data bases and automated test tools. *Looking for a BS/MS, CS or Math, or equivalent. Experience much more important than degree! DSP Engineers: *Lead, or be a part of, a multi-functional team working on digital/ DSP/communications subsystems utilizing state of the art design/analysis tools/techniques and modern packaging. Responsibilities may include: Participate in architectural and design trades, generate hardware and software specifications, simulate/evaluate DSP algorithm, design digital circuits used in standard and custom interfaces and micro-processor based designs, design high speed digital logic, develop/code DSP firmware, implement custom DSP hardware using PLD/FPGA, and test and integrate the hardware in the subsystem. *Languages: C or C++ in a UNIX environment, with knowledge of Windows NT a plus. Also, knowledge of high speed digital logic, Modem/PLL Datacom products, embedded control firmware, custom DSP hardware implementation, ASIC design and methodology a plus. Hardware Engineer: *Serve as Technical Leader for small to medium sized projects. Coordinate technical efforts of small engineering project teams. *Perform high level system design. Develop algorithms for key communication functions. Define architecture for state of the art communication products. *MSEE with emphasis on Communications theory and DSP. Minimum of 5 years of related experience. Experience with SPW, Xilinx, and Viewlogic design tools. Please also consider that we need Systems Engineers, Intelligence Engineers, a variety of Systems Administrators, and Directors also. The descriptions above are only general! There are multiple openings in every area, and the expertise varies from position to position, so please don't hesitate should you feel there might be a match! Again, this IS a fantastic company! You will not be wasting your time if you decide to respond, and ALL qualified candidates WILL be responded to very quickly. Thank you for making it this far, and we hope to hear from you soon! Contact us at: Hunter International Fax: (815)356-9225, or, cleaner@starnetinc.com Our thanks in advance, Dave Steiger...Article: 10881
I have some problems with the MAX+plus II sw.
I try to synthesise some Verilog code.
My first problem is that if the root module has a different name than
the file it is in, the compiler flags it as error and halts.
Is it a Verilog restriction unknown to me that filenames must match
module names they contain ?
In addition, if I have this simple (and mostly useless :-) Verilog code:
module test( q, c, e, s );
inout [7:0] q;
input c, e, s;
reg [7:0] l1, l2;
assign q = e ? ( s ? l1 : l2 ) : 8'bz;
always @ ( posedge c ) begin
if ( ! e ) begin
l2 <= l1;
l1 <= q;
end
end
endmodule
it compiles fine. However, if I change the assignment for q to the
following format:
assign q = ( e & s ) ? l1 :
( e & !s ) ? l2 : 8'bz;
which should be functionally equivalent (and indeed, Symlicity and Exemplar
happily accepts it as well as various simulators) I get error messages for
each bit in q:
Error: BIDIR pin 'q7' must be driven by TRI or OPNDRN buffer, but is driven
by primitive ':58'
Error: TRI or OPNDRN buffer ':50' can only drive logic (':60') if connected
to a BIDIR pin
for each bit in q.
Is there any particular reason to accept one format and refuse the other ?
I know that I can work it around, but it's still annoying (especially when
I have to retarget an older design).
An other interesting thing:
If I change the assignment to assign q = e ? ( sel ? l1 : l2 ) : 8'bz;
(which the tool accepts), define the wire sel and add a module
instantiation:
selgen u1( sel, e, s );
Now I define a most primitive selgen module:
module selgen( sel, ena, select );
output sel;
input ena, select;
assign sel = ena ? select : 0;
endmodule
it compile fine.
However, if I write the selgen module into a separate file, say test2.v
and put the statement `include "test2.v" at the end of the first file,
I get errors again:
Info: Analyzing included file "test2.v"
Info: Continuing analyzing source file "/home/zoltan/test.v"
Error: Line 24: File /home/zoltan/test.v: Verilog HDL syntax error:
component name "selgen" must be a module, task, function, or
block statement
This is strange and again, Leonardo or Symplicity and the simulators
do not have a problem with it, nor do I recall any Verilog restrictions
in relation to include files and what the can contain.
Could someone tell me if it's
- my and other tool vendors' lack of knowledge of Verilog subtleties, or
- restrictions by Altera which I didn't find in the docs, or
- bugs, err, I mean special features in the MAXplus-II ?
Thanks,
Zoltan
--
+------------------------------------------------------------------+
| To reach me write to zoltan in the domain of: bendor com au |
+--------------------------------+---------------------------------+
| Zoltan Kocsi | I don't believe in miracles |
| Bendor Research Pty. Ltd. | but I rely on them. |
+--------------------------------+---------------------------------+
Article: 10882I have written an I2C interface in software and considered doing it in hardware. It is a complicated interface no doubt. I didn't see any easy tricks for simplification. Simon ---------------------------------------------------------------------------------------------- "Steven K. Knapp" <sknapp@optimagic.com> wrote: >MEMEC Design Services (http://www.memecdesign.com) offers an FPGA-based core >for I squared C that they call "Two-Wire Serial Interface". There's more >information available at http://www.memecdesign.com/xf-twsi.htm. It >supports both master and slave transactions. > >----------------------------------------------------------- >Steven K. Knapp >OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" >E-mail: sknapp@optimagic.com > Web: http://www.optimagic.com >----------------------------------------------------------- > >Bryn Wolfe wrote in message <3590FED8.B6AFA96@hypercon.com>... >>Has anybody tried to implement an I squared C interface on an FPGA? I am >>trying to implement it in an HDL, say VHDL, but find that my logic is >>excessive for such a simple serial interface. I figure I'm missing some >>key insight into making the logic much simpler. >> >>If anybody has attempted this or knows where I might look for >>information on this subject, please help. >> >>-- >>Bryn Wolfe - Robotics Engineer >>Metrica TRAC Labs > > > > Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 10883
Marshall Industries, a Xilinx distributor in North America, offers a Xilinx Foundation Evaluation Kit. More details are available at 'http://www.marshall.com/dynamic/html/mfrs/xil/pages/found/fndeval.htm'. According to the page: "The Foundation Series Evaluation Kit also contains an ISP Starter Kit. The Kit includes a JTAG download cable and a XC9536 CPLD demo board. The Starter Kit allows you to do a complete CPLD design, including downloading your design onto the Xilinx XC9536 device." There's even an online request form at the bottom of the page. Also, you may be interested in the Xilinx Student Edition. More information availabel at 'http://www.optimagic.com/books.html'. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Andreas Kemper wrote in message <35921D7C.33A136B7@post.rwth-aachen.de>... >Hi, > >I'd like to program a XC9536 CPLD for hobby purpose without big >investments. >Can anyone give me a hint where I can get shareware or evalauation >software to generate the necessary bitstream for is-programming and a >hardware solution to program via the parallel port for example? > >Thanks, >Andreas > >PS: Please send a copy to me at andreas.kemper@post.rwth-aachen.deArticle: 10884
This is a multi-part message in MIME format. --------------99F8F8CA52B6FF0E2BC45F03 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I initially had troubles guiding under M1.4, but finally one day a Xilinx FAE was by, and showed the trick: In the Flow Engine: Select 'Options' In the Options Guide Design list: Select 'Custom' Browse to insert a 'Guide File', leave 'Mapping Guide File' blank. OK, OK. I generally leave 'Match Guide Design Exactly' unchecked as I'm not clear on what that means in M1.4. I was very familiar with APR, but haven't really read all the docs on PAR. At any rate, the above steps, coupled with any patches I may have installed from the Xilinx web site, have produced 4KE designs that will accept guides. Don't know about XL. Rickman wrote: > ems wrote: > > > > On Fri, 26 Jun 1998 12:07:51 GMT, timolmst@cyberramp.net wrote: > > > > >Have you tried using the design that worked as a guide file for making > > >the changes? This might help. > > > > good idea - except that i've never managed a successful guided design > > on a 4KE with foundation. the normal problem is a crash, but i seem to > > remember that there's a second problem as well. i think that there's > > now a patch for the crash; i'll give this a go if everything else > > fails. > > > > thanks > > > > evan > > I had the same crash result when I attempted to perform a guided design > on a 4013XL. Is this a known bug in M1.4? > > -- > > Rick Collins > > rickman@XYwriteme.com > > remove the XY to email me. --------------99F8F8CA52B6FF0E2BC45F03 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John L. Smith Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: John L. Smith n: Smith;John L. org: Visicom Imaging Products adr: 1 Burlington Woods;;;Burlington;MA;01803;USA email;internet: jsmith@visicom.com title: Principal Engineer tel;work: 781-221-6700 tel;fax: 781-221-6777 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------99F8F8CA52B6FF0E2BC45F03--Article: 10885
A lot of hot air has been vented about a clock-frequency doubler. Here is what I wrote 4 years ago, and it is still valid today ( see 1994 Xilinx data book, page 9-7 ): A 50% duty cycle signal can be doubled in frequency provided the resulting 2f clock can tolerate wide variations in duty cycle. The circuit below generates an output pulse in response to each transition on its input. The output rising edge is delayed one gate delay from the input transition. The output High time is the sum of the clock-to-Q delay, plus two gate delays, plus interconnect delays. This pulse will clock other flip-flops on the same die reliably.( assuming reasonable routing delays). Such asynchronous circuits are frowned upon by all true digital designers. Use this circuit only as a last resort. The input signal drives one side of a 2-input XNOR gate, the output of which is the double-frequency output. This output also clocks a flip-flop ( rising edge ). The Q output of this flip-flop is inverted and feeds its own D input. ( Toggle flip-flop ). The signal feeding the D-input also drives the second input of the XNOR gate mentioned in the beginning. I mainatin that this is a reliable circuit, albeit with a widely varying output pulse width. Peter Alfke, Xilinx ApplicationsArticle: 10886
On Fri, 26 Jun 1998 09:52:19 -0700, Peter Alfke <peter.alfke@xilinx.com> wrote: >simulator knows nothing about temperature, it just manipulates the worst >case ( i.e. hot and low-Vcc) speeds-file numbers. So, are you saying it >simulates ok, but the silicon does not work properly ? yes >At room temperature and nominal Vcc, or at hot and low Vcc ? the silicon works fine when frozen. it fails after a couple of minutes at room temperature (20C, no cooling, to be precise), at 5V +/- 2%, on one tested device. note that i'm *not* (yet) claiming that there's a problem with the simulator or the speed file. however, the failure is very specific, and i'm sure, as far as i can be, that the simulator can't reproduce it. i really wanted to confirm that the -1 speed file was no longer preliminary, and could be trusted, although no-one's commented specifically on this. i've got the version delivered with the F1.4 upgrade dated (i think) jan.'98. opinion seems to be divided as to whether the simulator in general can be trusted, insofar as any simulator can be. evan (ems@nospam.riverside-machines.com)Article: 10887
On Fri, 26 Jun 1998 20:19:56 -0400, Rickman <spamgoeshere2@yahoo.com> wrote: >ems wrote: >> >> On Fri, 26 Jun 1998 10:36:52 -0400, Ray Andraka >> <no_spam_randraka@ids.net> wrote: >> >> >I am not a big fan of doing timing analysis by simulation for this very >> >reason. It is too easy to miss something critical by not supplying the >> >correct timing in the simulation vectors >> >> true enough, but a static analysis doesn't get around this. > >By this, I assume that you mean the static timing analysis doesn't find >any problems? if you mean in this particular case then no, it didn't find any problems, but the clock frequency figures aren't any use anyway, because of the CE and multi-cycle issue. i have a large-ish number of constraints to cover these gray areas, but none of them failed. >When you say you have multiple clocks, are you interfacing data or >control signals between different clock domains? yes, but the domains are all derived from my main input clock, so i have complete control of the timing and there are no metastability issues (as long as the prop. delays are correctly controlled, of course). >You can tell the tools that the data path (or control path) is slower >than the CE path. There is a note on this in issue 28 of XCELL, the >Xilinx news/info/advertising "journal". The title is cryptically "Reduce >Compile Times". I guess they are suggesting that the use of distinct >timing constraints on data path and clock enable will allow the router >to complete in a shorter time, rather than just making a design >possible. True, but not my goal in life. I am concerned about "making it >work", most of the time. Anyway, the article should be on their web >site. You may need the title or issue number to find it. Or you could >try searching on "clock enable" or "multi-cycle". thanks - i'll look it up. i'm already individually constraining data and CE paths, but there may be something useful in it. >Have you checked the web site? I believe that I found some updated speed >files for some parts since the M1.4 release. i've checked, but the only updates appear to be for XL parts. the 4KE's seem not to have been updated since an XACT update in august last year. thanks evan (ems@nospam.riverside-machines.com)Article: 10888
On Fri, 26 Jun 1998 19:40:25 -0400, Rickman <spamgoeshere2@yahoo.com> wrote: >I had the same crash result when I attempted to perform a guided design >on a 4013XL. Is this a known bug in M1.4? yup, but apparently fixed. look up the sw updates, and they'll point you to a techdocs\***.htm (sorry, forgotten which one) which covers the patches and the reasons for them. one of them covers this problem, but i haven't tried it yet (or john's workaround). evan (ems@nospam.riverside-machines.com)Article: 10889
Hi We are currently running an embedded system with segmented Flash. This allows us to have a Boot code section and a Main code section. The Main code is the application. While the Boot code is a starting point from reset. It performs checks on the memory before jumping to the Main code. But it also allows us to download new Main code when a software upgrade needs to be performed. We have been having trouble fitting our Xilinx hex file into boot sector of the Flash. A 40k Spartan XCS20 file doesn't fit very easily into the 16k boot sector. Especially when the boot sector also contains other code mentioned above. Ideally we would like to keep the boot code (xilinx file included) entirely in the boot code - protecting it from accidental software flash erasures. Has anyone done this before? My plan was to write a very simple FPGA file (all we need for the boot code to run is the DRAM controller) and compress it. The compression scheme was simply counting the number of '1's between '0's in the Xilinx file to create a compressed file. Decompression is then simply clocking out 'n' '1's followed by a '0'. And it brings the 40k file down to about 5k. But I would like more compression! Ideally I would like to keep this simple, as the decompression needs to be written in assembler (until the Xilinx is downloaded, the device doesn't have enough RAM for C). The nature of these programmable devices is very repetitive, with repeated CLBs and stuff - so I was hoping that someone had already done some work targeted towards this architecture. Anyone got any ideas? SteveArticle: 10890
Hi people, we have nifty FPGA Downloader tool that works with any voltage of FPGA / EPLD I/O from 1.8 V to 5 V. It replace Altera ByteBlaster and ByteBlasterMV . Will serve you long time even when 1.8 V devices will come up. Please see us on http://www.jps.net/eugenef/index.htm First 100 customers will receive free digital tape less recorder. Sincerely, Eugene Fleisher NEF Design Inc. 408-446-1694 eugenef@jps.netArticle: 10891
--------------00BD00065D4BCFF7A80EE0D4 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi people, we have nifty FPGA Downloader tool that works with any voltage of FPGA / EPLD I/O from 1.8 V to 5 V. It replaces Altera ByteBlaster and ByteBlasterMV . Will serve you long time even when 1.8 V devices will come out. Please see us on http://www.jps.net/eugenef/index.htm First 100 customers will receive free digital tape less recorder (20 sec, 9 V battery) Sincerely, Eugene Fleisher NEF Design Inc. 408-446-1694 eugenef@jps.net --------------00BD00065D4BCFF7A80EE0D4 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> Hi people, <P>we have nifty FPGA Downloader tool that works with any voltage of FPGA / <BR>EPLD I/O from 1.8 V to 5 V. <P>It replaces Altera ByteBlaster and ByteBlasterMV . Will serve you long <BR>time even when 1.8 V devices will come out. <P><B>Please see us on <A HREF="http://www.jps.net/eugenef/index.htm">http://www.jps.net/eugenef/index.htm</A></B> <P>First 100 customers will receive free digital tape less recorder (20 sec, 9 V battery) <P>Sincerely, <P>Eugene Fleisher <P>NEF Design Inc. <P>408-446-1694 <BR>eugenef@jps.net <BR> <BR> <BR> <BR> </HTML> --------------00BD00065D4BCFF7A80EE0D4--Article: 10892
ems wrote: ...snip... > >When you say you have multiple clocks, are you interfacing data or > >control signals between different clock domains? > > yes, but the domains are all derived from my main input clock, > so i have complete control of the timing and there are no > metastability issues (as long as the prop. delays are correctly > controlled, of course). I'm not sure what you mean when you say "the domains are all derived from my main input clock". If you are using signals divided from your main clock as clock enables to other "domains", then you should be ok. If you are using divided clocks as actual clocks to separate parts of your design, then this is very different. The latter case is one of the few cases where you need to worry about minimum delay times internal to the chip. It sounds like you know as much about this stuff as myself, so I won't bother to go into an explanation of this clocking issue. But I am curious as to which of the two cases you are designing. And of course, if you would like any explanation, feel free to ask. -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10893
Given that your device runs when cold (internal paths and logic run faster), but not at room temp, here are SOME options: CAE/Vendor issues: 1) The speed files are not correct 2) Back annotating speed info did not work correctly 3) The simulator isn't using the speed info correctly 4) The device is faulty 5) Your design is relying on a path that the speed file doesn't cover Your issue: 6) Asynchronous logic 7) Paths that depend on N cycles taking N-1 cycles and logic can't handle occasional metastables 8) Timespec coverage is not complete 9) Multiple clock domains, using more than 1 clock signal rather than CE 10) External issue that depends on higher drive when device is cold. Let me write a little about (8) At the end of the trace report, it should indicate the percentage coverage of your time specs. It should be over 99%. (for some designs it is impossible to get 100% because of bugs in the way this coverage percentage is calculated). Your design should not rely on any default specs. you can run trace from the command line with the following command: ¦trce mychip.ncd mychip.pcf -v 100 -u -o mychip.twr >> mychip.log The -v says give verbose info on the worst 100 paths for each timespec. The report can be quite long. The -u says list unconstrained paths. These will be listed in the .twr file in a section titled: ========================================================= Timing constraint: Unconstrained path analysis 293 items analyzed, 0 timing errors detected. Minimum period is 13.289ns. Maximum delay is 19.354ns. --------------------------------------------------------- yada yada yada This section will be ommitted if ALL paths are covered by either specs you entered, or default specs. Following this heading it will list (verbosely) the worst 100 unconstrained paths. Go find them, and add tspecs to cover them. Re-netlist, PAR, trce. Repeat till this section disappears, or the paths are not constrainable (due to bugs in the SW. There are a few that affect this section, but they are REALLY rare.) At the end of the .twr file, you need to see something like: Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 40047 paths, 0 nets, and 22452 connections (100.0% coverage) Good luck. Philip Freidin In article <35969ebb.5128088@news.dial.pipex.com> ems@see_sig.com (ems) writes: > >the silicon works fine when frozen. it fails after a couple of >minutes at room temperature (20C, no cooling, to be precise), at 5V >+/- 2%, on one tested device. > >note that i'm *not* (yet) claiming that there's a problem with the >simulator or the speed file. however, the failure is very specific, >and i'm sure, as far as i can be, that the simulator can't reproduce >it. > >evan (ems@nospam.riverside-machines.com) >Article: 10894
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Article: 10895In <3596c0ed.1378542@news.netspace.net.au>, steve@burnet.edu.au (Steve) writes: I'm facing a situation identical to yours, except in my case, it's access to the serial port (needed to bootload the main application) that requires the Xilinx. I am looking at the same sort of run-length compression as you. I'm also considering just storing the Xilinx code outside of the boot sector, where space isn't so tight (the system has an alternate to flash for factory loading of the boot code). The last option would be to use GZIP compression. I tried it on the PC and got about a 98% compression of the target Xilinx file. The boot loader is written in C, so I could port the unzip. I would have to sell my bosses on it, though. --Gene >We are currently running an embedded system with segmented Flash. >This allows us to have a Boot code section and a Main code section. >The Main code is the application. While the Boot code is a starting >point from reset. It performs checks on the memory before jumping to >the Main code. But it also allows us to download new Main code when a >software upgrade needs to be performed. > >We have been having trouble fitting our Xilinx hex file into boot >sector of the Flash. A 40k Spartan XCS20 file doesn't fit very easily >into the 16k boot sector. Especially when the boot sector also >contains other code mentioned above. > >Ideally we would like to keep the boot code (xilinx file included) >entirely in the boot code - protecting it from accidental software >flash erasures. > >Has anyone done this before? > >My plan was to write a very simple FPGA file (all we need for the boot >code to run is the DRAM controller) and compress it. > >The compression scheme was simply counting the number of '1's between >'0's in the Xilinx file to create a compressed file. Decompression is >then simply clocking out 'n' '1's followed by a '0'. > >And it brings the 40k file down to about 5k. But I would like more >compression! > >Ideally I would like to keep this simple, as the decompression needs >to be written in assembler (until the Xilinx is downloaded, the device >doesn't have enough RAM for C).Article: 10896
> MEMEC Design Services (http://www.memecdesign.com) offers an FPGA-based core > for I squared C that they call "Two-Wire Serial Interface". There's more > information available at http://www.memecdesign.com/xf-twsi.htm. It > supports both master and slave transactions. The cost is quite prohibitive for such a simple piece of code. Austin Franklin darkroom@ix.netcom.comArticle: 10897
msimon@tefbbs.com wrote in article <3594f81a.2316187@news.megsinet.net>... > I have written an I2C interface in software and considered doing it > in hardware. It is a complicated interface no doubt. I didn't see any > easy tricks for simplification. It can be implemented in under 20 CLBs for a master interface. I don't believe that's all that complicated, so I am curious why you think it is (complicated that is)? Austin Franklin darkroom@ix.netcom.comArticle: 10898
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I'm a senior consultant from Sweden who attended to the 35th DAC. I have never been to DAC before so I wasn't prepared what to expect. I walked around the exhibitor's booths and talked to sales and technical people. All exhibitors really wanted you to listen to their presentation, and if you did, you were often given a gift (toy, t-shirt..). I realized that I had to sign up for any demo of beta or pre-releases of software at the booth in order to see some new stuff. So I signed up for a few, and also walked around the demo suites, and when I saw an interesting company, I stepped in and asked for a demo. The people at the demo suite then asked me questions to get a feeling for who I was. And then they allowed me in to the next demo. This worked for all companies, except for one: ALTERA. Before DAC, I had seen a press release that Altera was going to show the software that will come after MaxPlus2, and since I have been using MaxPlus2, I was interested in what they had improved. So I walked to their demo suite and stepped in and asked if I could see a demo. A man came towards me and and said 'NO It is only for special invited people' and then turned his back on me. I could do nothing but walk away. I'm still stunned about this attitude to an unknown customer; he didn't care to find out who I was or what I was doing. I might have been a customer who was going to buy thousands of their FPGAs, but they didn't care. If they had just asked who I was, and then said it is only for beta-site people and then asked me if I would like to become a beta-site, that would have been o.k. For crying out loud, he could have talked to me. If they had a good reason for not showing me the demo, I would have accepted it. But no, they didn't care. Then I thought it might be only this one guy with an attitude problem, so I walked to their booth again and asked the same question, and I was given the same answer and attitude. So, if Altera is ignoring me I will start to ignore Altera. My company is part of a group, which has 5000 employees, and we are the consulting company, with the largest number of technical consultants at Ericsson, the Swedish telecom giant. I have designed generic FIFO's, with independent read and write clocks. It is written in VHDL and has generic attributes for size and depth.I have also made a 2-D convolver, which is generic as well. These designs are given to Xilinx, and with my help we will build reference design and application notes, which will mean that these will be available free of charge. I have also SHARC DSP link receiver/transmitter and synthesizable conversion between IEEE Float and Std_Logic in VHDL design. I have also behavior models, which execute a pseudo-code for SHARC DSP and MC68376. All these models will be free of charge for use in all architectures, except Altera. If you need any of these models e-mail me, and state that you never will use these models in Altera designs. By the way my company is now producing IPCores, like a CANBus controller and Motor Control IPs. These cores will be available after this summer and be free of charge except for Altera designs. I will later post a message with the web-address. You may say that I'm acting like a 5-year old kid, and that may be true. I will ban Altera as long as I'm so disgusted with their attitude. I seldom get angry, but when I do I get real angry. Since I'm a consultant I will use Altera only if my client says so, and if the design really fits Altera. Otherwise I will look for alternative architectures. Göran Bilski -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
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