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I was reading the specs on the newm Altera devices. On of the items which caught my eye was the internal PLL. Will this be configured by a high level description language or via some switches in Maxplus II? If via HDL, would that make it harder to use other simulation tools in conjuction with Maxplus 2? Mike ScottArticle: 7501
Tim Forcer <tmf@ecs.soton.ac.uk.nojunk> wrote:
:David Collier warns users of AMD PALs:
[snip]
:>Basically, they [AMD] have added a "pull-up/down detector" to the IO pins. This
:>observes the I/O pins during power-on, and then engages a weak pull-up or
:>pull-down to hold the pin in the state seen. The consequence of this is
:>that the guaranteed leakage figures have gone from +/-10uA to +/-100uA.
:>We have a circuit which drives a Maxim watchdog/reset device from a PAL
:>output. The input is three-mode - high, low and floating, and floating
:>disables the watchdog. Of course the new PALs make an arbitrary choice at
:>power-on, and pull their outputs high or low. So we get an immediate
:>watchdog time-out. Wonderful.
:>
[snip]
:
:The "equivalent schematic" of for a PAL I/O shows a 100k pullup/down
:(although the change in current quoted by David Collier implies 50k
:rather than 100) being driven by a pin-sensing circuit and enabled by
:Vcc - so it is operative all the time, not just on power-up. The "fix"
:is therefore to add 180k (or lower) resistors to Vcc and Gnd, meaning
:that an IC change to get rid of resistors has actually increased the
:number needed.
[snip]
Alas, your remedy may well not work in David's application. The Maxim
watchdog is looking for a _floating_ input, not necessarily one
biassed to Vdd/2. It may still fail (worse, it will likely fail
_sometimes_, due to the wide tolerances of the on-chip resistors).
The tolerance spread quoted (50k - 100k) is well within the range to
be expected of on-chip resistors intended for non-critical
applications (eg pullups), so you and David are likely both right.
This of course makes it impractical to set the pin to Vdd/2 with a
single external resistor, unless you select on test (almost certainly
impractical). Depending on how the Maxim senses that _floating_ input,
an active drive to Vdd/2 might work (what happens when the PAL really
does drive that line?) but again, it's added complexity to something
that was meant to reduce it.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger daveb@opera.iinet.net.au
servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 7502My personal fantasy for several years has been a 6809 clocked at 100 to 300 MHz. Hell, it's so simple maybe you could cook it off at 600 MHz. I sure hope someone picks up production. EricArticle: 7503
In article <34214C96.5D39@xtra.co.nz>, jim granville <DesignTools@xtra.co.nz> wrote: >> We've asked Moto many times if they would license the patents they have >> on the 68xx family. So far they've said no... > > This is a feeding ground for lawyers, but I would have thought if a >supplier discontinues a device, that they also release any claims on >preventing users from making a clone. Nope, sorry, that might be justice, but it's not the law. :-) Only trademarks can actually lapse if not actively used. Patents, copyrights, and trade secrets remain in force... although disuse would weaken an infringement lawsuit some by undermining any claim of financial damage. (Caution, I'm not a lawyer... and the details of these laws keep changing. Consult an expert before doing anything rash.) -- The operating systems of the 1950s will be out | Henry Spencer next year from Microsoft. -- Mark Weiser | henry@zoo.toronto.eduArticle: 7504
On Tue, 16 Sep 1997 12:07:02 -0400, Eric Ryherd <"vauto@tiac.net"@tiac.net> wrote: >>We are redesigning a board with telecommunication stuff, that contains a >>6809 processor. >>The processor is being discontinued and we are looking for a way to >>avoid major SW-rework. >>Has anyone put this processor into an FPGA? >>Are there estimations how many resources in an FPGA it would take >>(Altera FPGAs)? >>It seems that none of the IP-companies offers such a core at the present >>time. > >We've asked Moto many times if they would license the patents they have >on >the 68xx family. So far they've said no... But if they are discontinuing >the 6809, I know of several other companies who may also be interested, >if we can get Moto to allow it... Please contact me and we can disuss >further... >-- >Eric Ryherd eric@vautomation.com >VAutomation Inc. Synthesizable VHDL and Verilog Cores >20 Trafalgar Sq. #443 http://www.vautomation.com >Nashua NH 03063 (603) 882-2282 FAX:882-1587 Sorry to see this part go - next in line to be discontinued... The 68000 and the PowerPC ! ;^} ( I hope not - its a shame to see technically superior parts loose out to the sh*t produced by the Great Satan Intel ) Does anybody know what volume levels a part has to fall below before a manufacturer decides to discontinue it ? Steven J. Ackerman, Consultant ACS, Sarasota, FL sja@gte.net http://www.acscontrol.comArticle: 7505
Are your CMOS circuits FCT/HCT/ACT type? If so, their inputs switch around 1.4V like TTL does, and a 2.4V is a garaunteed high. So the output from 3.3V device to a 5V TTL in should work. Note that by not pulling to the rail your VDD supply to the TTL compatible device will typically pull ~500uA per input in the level shifter circuit. If you are talking a smally # of lines, there are level translators circuits around. Nick Gent wrote: > > I know this subject has been covered here before, but I am still not sure of > one detail. > > Can a 3.3v xilinx chip (4000XL or 5200XL -series) safely drive 5v CMOS parts? > > The Oct '96 data book on page 6-2 suggests that "an external pull-up resistor > to 5v on each such input will assure a sufficiently high input voltage" (i.e. > > 3.5v). (However, it then warns that your 3.3v supply could be compromised by > all the currents flowing back through the ESD protection on the 3.3v drivers.) > > I have contacted our local Xilinx support, and they sent me an email suggesting > that we use TRISTATE outputs (drive low, hi-z for high). Are they implicitly > suggesting that there is a problem with a simple pull-up? > > Has anyone actually tried this for real? Do you get a good enough drive for > CMOS (with some noise margin)? > > Nick > ============================================================================ > Nick Gent > > Communications Measurements Division Email: nickg@sqf.hp.com > Hewlett-Packard Telephone: +44 131 331 7644 > South Queensferry EH30 9TG Fax: +44 131 331 7488 > Scotland > ============================================================================ -- ============================================================= Tim Tait No SPAM! Real Email: ttait at above domain ============================================================= And for you automated email spammers out there, here's the email addresses of the current board of the Federal Communications Commission: Chairman Reed Hundt: rhundt@fcc.gov Commissioner James Quello: jquello@fcc.gov Commissioner Susan Ness: sness@fcc.gov Commissioner Rachelle Chong: rchong@fcc.govArticle: 7506
[M.Vorbach] We built an emulator for an ASIC, that contains up to 100 pieces of Altera 10K100, so I would say, it was a big system. My experience is: Cluster your design as good as you can. Try to find groups and put them together in a FPGA. Be careful! This is one of the most important steps. Try to build external busses. If timing is not very hard you can multiplex signals at the bus and save lots of signals! Never trust the FPGA-tools. Fitting is really a big problem; which get harder as worster the FPGA utilization is. Good results can be expected up to 80% pin and 80% gate utilization. Remember: External pins depends from the fitting, be as flexible as possible. If you insert large busses, you can switch the position of the specific signals very easily and without problems. Do never use devices like zero-ohm-resistors or switches, jumpers or so on. Chaos will be the result. If possible, try early to fit the HDL on the FPGAs. There is no need to take the "final " code and netlist. Just alpha or beta versions give good fitting and pin estimations! If nothing helps insert devices from APTIX or ICUBE. This are so called crossbar switches, which are used and programmed FPGA-like (SRAM-cells). They provide programmable interconnects between lots of signals and the delay is still OK. The devices can be clustered together to get large interconnect arrays. Using this devices will result in a clean, electrically stable and easy to use PCB.Article: 7507
[M.Vorbach] Before you think about your HDL implementation, ask ALTERA if the devices are avaiable and which devices are on the market. We thought about the PLLs three months ago and had a bad surprise. I was reading the specs on the newm Altera devices. On of the items which > caught my eye was the internal PLL. Will this be configured by a high > level description language or via some switches in Maxplus II? > > If via HDL, would that make it harder to use other simulation tools in > conjuction with Maxplus 2? > [M.Vorbach] Pre-synthesis-simulation is a little bit tricky. After the synthesis you got all necessary data in an ALTERA output file, which is linked to your simulator. >Article: 7508
Motorola HAS already discontinued the 68000!
But I believe Hitachi still makes the 6809 called a 6309 (cmos
version). Tell me if I'm wrong.
snip....
>
>Sorry to see this part go - next in line to be discontinued...
>
>The 68000 and the PowerPC !
>
>;^}
>
>( I hope not - its a shame to see technically superior parts loose out
>to the sh*t produced by the Great Satan Intel )
>
>Does anybody know what volume levels a part has to fall below before a
>manufacturer decides to discontinue it ?
>
>Steven J. Ackerman, Consultant
>ACS, Sarasota, FL
>sja@gte.net
>http://www.acscontrol.com
Regards,
Aaron Quantz \^ ^/
)@ @(
+---------------------------oOO--(_)------------------------------------+
+ Mgr Software Development, Turret Control Systems +
+ HR Textron | Phone: (805) 253-5471 +
+ 25200 W. Rye Canyon Rd. | Fax: (805) 253-5962 +
+ Valencia, CA USA 91355-1265 | Email: aquantz@ibm.net +
+ Visit the Textron web site: http://www.textron.com +
+-----------------------------------Oooo--oOO---------------------------+
oooO ( )
( ) ) /
\ ( (_/
\_)
Article: 7509Eric Ryherd wrote: > > >We are redesigning a board with telecommunication stuff, that contains a > >6809 processor. > >The processor is being discontinued and we are looking for a way to > >avoid major SW-rework. > >Has anyone put this processor into an FPGA? > >Are there estimations how many resources in an FPGA it would take > >(Altera FPGAs)? > >It seems that none of the IP-companies offers such a core at the present > >time. > > We've asked Moto many times if they would license the patents they have > on > the 68xx family. So far they've said no... But if they are discontinuing > the 6809, I know of several other companies who may also be interested, > if we can get Moto to allow it... Please contact me and we can disuss > further... > -- > Eric Ryherd eric@vautomation.com > VAutomation Inc. Synthesizable VHDL and Verilog Cores > 20 Trafalgar Sq. #443 http://www.vautomation.com > Nashua NH 03063 (603) 882-2282 FAX:882-1587 This is a feeding ground for lawyers, but I would have thought if a supplier discontinues a device, that they also release any claims on preventing users from making a clone. Otherwise they are in a 'blocking' stance, in prevention of business. In fact, a good lawyer may be able to make the case for the original vendor PAYING for such developments, especially if the user can find any documents promising a long(er) life for said silicon. ( initial press releases, and road maps would be a good place to find many broken promises :-) Does anyone know of any test cases, of this type ? - jim.Article: 7510
I remember a while ago that there was a PIC microcontroller mode in VHDL or Verilog. Does anyone know where that model is ? TIA, Gareth Baron Email: gareth.baron@eng.efi.comArticle: 7511
Try, http://www.mindspring.com/~tcoonan/synthpic.html Hans. In article <01bcc449$ab2ad920$0913010a@gbaron-lt.corp.efi.com>, Gareth.Baron@eng.efi.com says... > >I remember a while ago that there was a PIC microcontroller mode in VHDL or >Verilog. Does anyone know where that model is ? > >TIA, > > >Gareth Baron >Email: gareth.baron@eng.efi.com >Article: 7512
-- Does anybody know where I could get a master or slave VME core?
--
...bruce
Article: 7513Eric W Braeden wrote: > > My personal fantasy for several years has been a 6809 > clocked at 100 to 300 MHz. Hell, it's so simple maybe you > could cook it off at 600 MHz. That's the beauty of Technology Independent Synthesizable Cores... in .18um CMOS at 2.8 V a 6809 core would EASILY run >100Mhz. Coupled with on-chip RAM (DRAM?) it would easily run 300Mhz! and you could include the rest of your system on the same chip all for $10! Best of all, no software changes required! Would the next gen .01um CMOS would clock at 1 terahertz??? (;-) I don't know, but as soon as the Synopsys libraries are available all you have to do is to rerun the synthesis with the new library to check it out! -- eric@ Eric Ryherd VAutomation Inc. vautomation 20 Trafalgar Sq. #443 Synthesizable VHDL and Verilog Cores .com Nashua NH 03063 (603)882-2282 FAX:(603)882-1587 http://www.vautomation.comArticle: 7514
Anyone have experience with these? We've been literally "Blowing" thru tubes of Xilinx 17256Ds with our XC40xx FPGA developments and are searching for a way to save a few bucks. What PROM burner is required to program them... I only have a Xilinx HW130 but would buy a new prom burner if the price is right... -- eric@ Eric Ryherd VAutomation Inc. vautomation 20 Trafalgar Sq. #443 Synthesizable VHDL and Verilog Cores .com Nashua NH 03063 (603)882-2282 FAX:(603)882-1587 http://www.vautomation.comArticle: 7515
Depending on how 'production worthy' your prototype needs to be and your budget, you might find Aptix' System Explorer MP4 board useful. It supports multiple FPGA devices connected together via _programmable_ interconnect. The signal pins of the various devices can be routed _after_ each of the FPGAs is routed. You can find more information at 'http://www.aptix.com/Products/mp4.html' -- Steven Knapp OptiMagic, Inc. E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.comArticle: 7516
A lot depends on your target technology, vendor, and preferred format. However, here's one that I came across: VME Slave from INICORE AG: 'http://www.inicore.com/vme_slav.htm' -- Steven Knapp OptiMagic, Inc. E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com bruce kidd <bruce.kidd@gecm.com> wrote in article <5vrmr3$eur@gcsin3.geccs.gecm.com>... | | -- Does anybody know where I could get a master or slave VME core? | -- | ...bruce | |Article: 7517
I've successfully used the 17C65 with Data I/0. BP microsystems (good value general purpose system) also supports them. Atmel also sells a little PC parallel port "configurator" board (see http://www.atmel.com/atmel/products/prod182.htm for data) Don't know the cost, but it can't be much. Might want to make sure it works with Windows NT (if you use NT). regards, tom Eric Ryherd wrote: > > Anyone have experience with these? > We've been literally "Blowing" thru tubes of Xilinx 17256Ds with > our XC40xx FPGA developments and are searching for a way to save > a few bucks. > > What PROM burner is required to program them... I only have a Xilinx > HW130 but would buy a new prom burner if the price is right... > > -- > eric@ Eric Ryherd VAutomation Inc. > vautomation 20 Trafalgar Sq. #443 Synthesizable VHDL and Verilog > Cores > .com Nashua NH 03063 > (603)882-2282 FAX:(603)882-1587 http://www.vautomation.comArticle: 7518
I would like to subscribe to the aforementioned newsgroups.
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 7519> Anyone have experience with these? We have used them on several projects and they work great! > What PROM burner is required to program them... I only have a Xilinx > HW130 but would buy a new prom burner if the price is right... Atmel sells a burner for about $100, but you might want to look into in-circuit re-programming. That is what we do, and it is really nice.Article: 7520
Speaking of the Atmel EEPROM. It works great but it defaults to having an active high RESET, whereas the Xilinx parts have an active low RESET. The data sheets on the ATMEL 17C65 say that there is a bit you can program in the EEPROM itself to invert the RESET pin so that it is effectively active low (like the Xilinx FPGA.) I got around this by hooking up the LDC_ (Low During Configuration) pin from the Xilinx FPGA to the EEPROM. However, I was curious (and I'm sure so is Eric) if anyone knows how to program that single bit on the ATMEL part. Thanks, John BTW: I also used the BP microsystems PROM burner. -- John ArchambeaultArticle: 7521
I am currently designing a project with Altera FLEX8000 8636A (84pin PLCC device, for that matter) - my hardware is already built around this device size and pinout but recently I heard some bad rumours about this device -- bad efficency / utilization / FLEX8000 is a failing Altera series... Is any of these true? Anyone have experience with these devices? Also - I am try to incorporate BCH error correction code (being used in a digital serial protocol) in my FLEX8000 EPLD and having real problem getting any material about the subject - any help/AHDL source/algorithm description will be appreciated. Thanks in advance. -- --== Ido Kleinman ==-- kleinn@erez.cc.biu.ac.ilArticle: 7522
I am currently designing a project with Altera FLEX8000 8636A EPLD (84pin PLCC device, for that matter) - my hardware is already built around this device size and pinout but recently I heard some bad rumours about this device -- bad efficency / utilization / FLEX8000 is a failing Altera series... Is any of these true? Anyone have experience with these devices? Also - I am try to incorporate BCH error correction code (being used in a digital serial protocol) in my FLEX8000 EPLD and having real problem getting any material about the subject - any help/AHDL source/algorithm description will be appreciated. Thanks in advance. -- --== Ido Kleinman ==-- kleinn@erez.cc.biu.ac.ilArticle: 7523
USA; Charlotte, NC; Electrical engineer; FPGA, DSP; 50 Mghtz Experience in embedded systems design using: FPGAs (Altera preferred), DSPs and PLDs; Systems level architecture; Sensitive high speed analog designs; and signal distribution. Control systems familiarity highly desirable. Please refer to JO# 2793RJS in your response. Richard Steinman Team Leader rjs@cmagroup.com IT & Software Solutions Team Career Marketing Associates http://www.cmagroup.com/IT.htmlArticle: 7524
In reply to several postings today.... Atmel sells a programming board (ATDH2200) that also supports ISP of Configurators for US$250 - about the cost of a tube of OTP EPROM parts :-) It's available from any of our US (or International) distributors. Of course you can use any industry standard programmer if you prefer. For mor information on Configurators visit our WEB site http://www.atmel.com/atmel/products/prod22.htm. Configurator **SAMPLES** are also available through this URL. Info. on setting the RESET polarity and ISP of Configurators is also available at this URL location. Martin Mason AT17Cxxx Atmel Corp. Eric Ryherd wrote in article >Anyone have experience with these? >We've been literally "Blowing" thru tubes of Xilinx 17256Ds with >our XC40xx FPGA developments and are searching for a way to save >a few bucks. > >What PROM burner is required to program them... I only have a Xilinx >HW130 but would buy a new prom burner if the price is right... >
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