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Hi
I tried to simulate this code under Modelsim 5.2 but the code does not
compile and it gives me an error message on the Type statement.
I also tried to synthesis it with Synopsys FPGA Express but also I got
the same error.
How can I use these tools to compile my code using the Type statement
or how can I make a synthesizable or simulatable memory core without
using the Type statement "is it a good idea to use array of registers?".
Thanks in advance
===============================================================================================
ENTITY dpmem IS
PORT (
clk : IN std_logic; -- write clock
reset : IN std_logic; -- System Reset
W_add : IN integer RANGE 0 TO 255; -- Write Address
R_add : IN integer RANGE 0 TO 255; -- Read Address
Data_In : IN std_logic_vector(7 DOWNTO 0); -- input data
Data_Out : OUT std_logic_vector(7 DOWNTO 0); -- Output Data
WR : IN std_logic; -- Write Enable
RE : IN std_logic); -- Read Enable
END dpmem;
ARCHITECTURE dpmem_v1 OF dpmem IS
BEGIN -- dpmem_v1
TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(7 DOWNTO
0);
-- Memory Type
SIGNAL data : data_array(0 TO 7); -- Local data
PROCESS (clk, reset)
VARIABLE result_data : std_logic_vector(7 DOWNTO 0); -- holds the
internal data of output data
BEGIN -- PROCESS
result_data := "ZZZZZZZZ"; -- Defualt value
-- activities triggered by asynchronous reset (active low)
IF reset = '0' THEN
result_data := "ZZZZZZZZ";
-- activities triggered by rising edge of clock
ELSIF clk'event AND clk = '1' THEN
IF RE = '1' THEN
result_data := data(R_add);
END IF;
IF WR = '1' THEN
data(W_add) := Data_In;
END IF;
END IF;
Data_OUT <= result_data;
END PROCESS;
END dpmem_v1;
Article: 16601On Sat, 29 May 1999 15:59:47 +0300, Jamil Khatib <khatib@ieee.org> wrote in article <374FE4C3.EFB69A09@ieee.org>: > I tried to simulate this code under Modelsim 5.2 but the code does > not compile and it gives me an error message on the Type statement. > I also tried to synthesis it with Synopsys FPGA Express but also I > got the same error. > How can I use these tools to compile my code using the Type > statement or how can I make a synthesizable or simulatable memory > core without using the Type statement "is it a good idea to use > array of registers?". The "type statement" is not a statement, it is a declaration. Exchanging the order of the lines > BEGIN -- dpmem_v1 and > TYPE data_array IS ... should fix your error. -- Paul Menchini | mench@mench.com |"The last thing I want to do is OrCAD | www.orcad.com | spread fear, uncertainty and doubt P.O. Box 71767 | 919-479-1670[v] | in the users' minds." Durham, NC 27722-1767 | 919-479-1671[f] | --Don Jones, MS's Y2K Product MgrArticle: 16602
ems@riverside-machines.com.NOSPAM wrote: > > On Fri, 28 May 1999 23:27:45 -0400, Rickman <spamgoeshere4@yahoo.com> > wrote: > >I maintain that this VHDL is really not an SR latch. It only looks like > >one on the surface. If you check every combination of state and every > >edge, you will see that a latch and an RS latch? (FF?) are not the same. > > i agree that the two models don't simulate in the same way if S and R > are removed simultaneously, but does it matter? is there a dictionary > definition of an SR? if there was, surely it couldn't include a > description of what should happen in this case, since this is an > implementation detail, and the real behaviour depends on the > gain-bandwidth product of the gates involved. > > evan I guess that is what I am saying. I am defining an SR "device" (I hate calling it a latch) as a pair of cross coupled gates, be they NANDs or NORs or others. That is how they were defined when I learned logic design. AFAIK, the warning about the simultaneous removal of S and R has always been a part of the definition as well. But at this point we seem to be splitting hairs. The bottom line is, he code produces something he doesn't like while it correctly matches the simulation (at a logic level). So change the code. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16603
ems@riverside-machines.com.NOSPAM wrote: > > On Fri, 28 May 1999 17:12:07 -0400, Craig Yarbrough > <hyarbr01@harris.com> wrote: > > >All, > > > >Does anyone know how or if it's possible to generate a GSR signal from > >within a Xilinx 4000/Virtex? > > > >- Craig > > this is straightforward - select your favourite startup component > (STARTUP/STARUP_VIRTEX/etc.), and connect your signal to the GSR port. > your signal (which can be a device input or an internal signal) then > drives the GSR net. watch out for the GSR net timing - there's a long > delay on release, which could cause you problems when starting > synchronous sections. there are situations in which it's better to > have your own reset net in the general purpose routing. > > if you're writing with an HDL then it may, or may not, do all this > automatically for you. this comes up every few weeks, so check > dejanews for specifics. > > evan If I could add my two cents worth. I struggled with the reset release problem on my last design. We started with an asynch reset which I felt worked ok since the external source was synced to the same clock. So on release I was OK on the timing problems. Because we had a noise problem on the board, we changed it to a synch reset. I believe we fixed the noise problem so I was considering converting it back to asynch. I read a lot of posts here and realized what I really needed was a combination of the two. The reset needs to be async when you have to immediately disable drivers or otherwise interrupt the state of a machine or output. But you can have problems synching the release, especially if you have multiple clock domains. The solution to that is to also use a sync reset. The async reset should cause a FF to assert a sync reset which can be removed either on the next clock edge or by software or other external stimulus. Each clock domain needs a separate reset FF working off of that clock. Then the circuit will come out of reset cleanly. If your reset FF is coming out of reset on the next clock edge, you may want to also apply the metastability issues (much of which I have learned here) to this FF and use two in cascade to reduce the likelyhood of this causing a problem. This almost sounds like I am making a parody of some of the more lengthly debated issues in this newsgroup, but I am completely serious. This type of reset circuit should work in almost every design you can come up with and is fairly simple. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16604
Jonathan Feifarek <feifarek@removethis.ieee.org> wrote: : I've been interested in Reconfigurable Computing in general, but know : very little about the area of Evolutionary Computation. I, for one, : would like to learn more. [...] : My question is this: if the mutations are truly random alterations in : the logic, doesn't the possibility of logic contention arise where two : output stages are driven to opposite states at the same time? A number of researchers in the area use FPGAs which are designed to try to avoid contention issues in all but the I/O stage - you can send a random bitstream to them without much fear that contention issues will arise. The Xilinx 6200 series is one family which exhibits this type of safety. : I've heard of damaged hardware from this - indeed, J-Bits comes with a : prominent warning to beware of it. To check each offspring for this : possibility sounds like it would be an enormous task for a reasonably : sized circuit. Whether or not this is the case depends on your approach. Consider Evolvaware: http://asd.bbn.com/evolvaware/index.htm These folks are effectively evolving VHDL. Given that they then wind up with a high level description of their circuit they can then apply the same techniques to avoid contention that human programmers employ. Alternatively there are techniques for insulating yourself from the hardware by employing a software layer between what you're evolving and the FPGA itself. This is the approach taken by those who're attempting to evolve "cellular neural nets" (neural nets implemented using cellular automata). Essentially the cellular automata is implemented in the programmable logic. Low-level reprogrammability may not even be strictly necessary if the design of the CA itself is fixed - ordinary VLSI slilcon could be employed, in principle. One of the most, notorious researchers employing this approach is Dr Hugo de Garis. Dr Hugo de Garis - Japan's "Brain Builder": http://www.hip.atr.co.jp/~degaris/ Other notable relevant web pages: Moshe Sipper: http://lslwww.epfl.ch/~moshes/ http://lslwww.epfl.ch/~moshes/firefly.html (his early FPGA board) Adrian Thompson's "evolvable hardware" list of researchers: http://www.cogs.susx.ac.uk/users/adrianth/EHW_groups.html Towards Evolvable Hardware - an introduction by Moshe Sipper: http://lslwww.epfl.ch/pages/events/seminar_09_95/ These links were mainly taken from http://www.alife.co.uk/links/hardware/ -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com Syntactic sugar causes cancer of the semi-colons.Article: 16605
On Fri, 28 May 1999, Stephen J. Byrne wrote: > I have implemented many RS flip-flops in the Actel A32200DX family of parts > without problems. However, they were synchronous flip-flops, not latches. > The description was much the same as yours with a synchronous clock and > asynchronous reset: > > sr: process(clk, rst_n) > begin > > if (rst_n = '0') then > tx_busy <= '0'; > elsif (clk'event and clk = '1') then > if (set_tx_busy = '1') then > tx_busy <= '1'; > elsif (clr_tx_busy = '1') then > tx_busy <= '0'; > end if; > end if; > > end process; > > It shouldn't surprise you that your code (below) would synthesize to a > latch as that's exactly what you specified. You've written a combinational > process where all possible input variations are not specified, therefore, a > latch is inferred. The synthesis tool won't make use of a DFF which is a > synchronous device for a non-synchronous process. I like your response because the implementation is simple and robust. It's more reasonable that the synthesizer should be able to control the setup and hold timing for the clock of the FF--ie skew. We generally expect all combinational signals to have some kind of uncertainty prior to setup to some kind of clock-- unless we are following a very structured timing schedule for asynchronous logic. It's unreasonable to expect the synthesizer to figure it out. In the implementation of another posting in this thread, other timing hazards are possible with x-coupled gates. It seems kind of risky to leave the timing up to the synthesizer. Even if you get the x-coupled gates in the edif, it seems a 50-50 chance that the latch would work. --alvin ########################################################### Alvin E. Toda aet@lava.net sr. engineer Phone: 1-808-455-1331 2-Sigma WEB: http://www.lava.net/~aet/2-sigma.html 1363-A Hoowali St. Pearl City, Hawaii, USAArticle: 16606
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Article: 16607This is a multi-part message in MIME format. --------------3F08E657EA0CBCC9838034DD Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi, what´s the RAW standards proposed at MIT?, it´s the first time I hear it, do you have more information about it? Thanks. lalitm@my-dejanews.com wrote: > Hi, > > I would like to know if there are any companies working on > reconfigurable chips adhering to RAW standards proposed at MIT. > Although there are many work on Reconfiguarble FPGA chips, I am not very > sure about any implementation of RAW architecture or any varient of that > currently. > > Any related information is welcome. > > Thanking in advance. > > Lalit > > --== Sent via Deja.com http://www.deja.com/ ==-- > ---Share what you know. Learn what you don't.--- --------------3F08E657EA0CBCC9838034DD Content-Type: text/x-vcard; charset=us-ascii; name="jmorenoz.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for José Antonio Moreno Zamora Content-Disposition: attachment; filename="jmorenoz.vcf" begin:vcard n:Moreno Zamora;José Antonio tel;cell:+34-617-281660 tel;fax:+34-927-257267 tel;home:+34-924-230593 tel;work:+34-927-257267 x-mozilla-html:TRUE url:http://atc.unex.es/joseanmo/ org:Universidad de Extremadura;Departamento de Informática version:2.1 email;internet:jmorenoz@nexo.es title:Profesor adr;quoted-printable:;;Escuela Polit=E9cnica=0D=0AAvda. Universidad, s/n;Cáceres;Cáceres;10071;Spain fn:José Antonio Moreno Zamora end:vcard --------------3F08E657EA0CBCC9838034DD--Article: 16608
We are getting ready to publish the next issue of EDA Vision on www.dacafe.com . If you or your company has an article you'd like published, please contact us as soon as possible. (editor1@ibsystems.com) Thanks much, David Heller Pres Internet Business Systems, Inc.Article: 16609
Want to network your cable modem ? Want to do it cheap and easy ? Check out http://multiuser.at/home.com no need to buy a second ip. tzdnjlhxulvsioosceopbrvkubwvemnldhbikesuqphriqymvunxqipxtmprsmhtjhcxfvmxyArticle: 16610
All: Please ignore this posting. Having severe problems connecting via my ISP. Need to double-check.Article: 16611
bmbhsvhumsddkmqqxcvdhwukloqovzpbrzlghssgzqdwxryxgndqrkyqexwssergvclqtfsfhlsyrjbfwkhrypiqwopsilofzlArticle: 16612
lpjwll@sssdfdf.org wrote: > bmbhsvhumsddkmqqxcvdhwukloqovzpbrzlghssgzqdwxryxgndqrkyqexwssergvclqtfsfhlsyrjbfwkhrypiqwopsilofzl How about "You're not going to understand this!" ? That makes a whole lotta sense. Exactly what was this person trying to communicate? That his cat can reach the keyboard? Mine can too!! (and types better) -Alan -- For a free weekly homeschooling newsletter, devotions, lesson plans, and more, visit http://www.THSresources.com. A member of the A+ Thematic Units Webring . Chat with me on ICQ #6913463 or AOL IM username flowoyab (bayowolf backwards) Remember: any excuse that starts with but(t) already has a crack in it. (Alan Hunter)Article: 16613
I used to use synopsys synthesis tool version 1998.02, and recently installed the same tool of version 1999.05. The problem is design_analyzer doesn't analyze any vhdl file. When I try to analyze a vhdl file, the result is design_analyzer > Reading in the Synopsys vhdl primitives. Error: Can't find primitives "sif_wildcard_eql" (HDL-3) What is this? Another problem : when I invoke design_analyzer, it doesn't parse correctly .dc_layers and .dc_name_rules included in .synopsys_dc.setup. Those files are generated while installation, and placed below "synopsys/admin/setup" directory. I have no idea what is wrong. Please somebody help me!Article: 16615
Hello, Does anyone out there have any good recommendations on books about FPGA which contains a good explanation of how FPGA works and its physical construction, LCA/LCB design analysis, programming circuit and logic etc.? Not the usual data sheets though. Thanks in advance. email: csoolan@dso.org.sgArticle: 16616
Rickman wrote: > ems@riverside-machines.com.NOSPAM wrote: > > > > On Fri, 28 May 1999 17:12:07 -0400, Craig Yarbrough > > <hyarbr01@harris.com> wrote: > > > > >All, > > > > > >Does anyone know how or if it's possible to generate a GSR signal from > > >within a Xilinx 4000/Virtex? > > > > > >- Craig > > > > this is straightforward - select your favourite startup component > > (STARTUP/STARUP_VIRTEX/etc.), and connect your signal to the GSR port. > > your signal (which can be a device input or an internal signal) then > > drives the GSR net. watch out for the GSR net timing - there's a long > > delay on release, which could cause you problems when starting > > synchronous sections. there are situations in which it's better to > > have your own reset net in the general purpose routing. > > > > if you're writing with an HDL then it may, or may not, do all this > > automatically for you. this comes up every few weeks, so check > > dejanews for specifics. > > > > evan > > If I could add my two cents worth. I struggled with the reset release > problem on my last design. We started with an asynch reset which I felt > worked ok since the external source was synced to the same clock. So on > release I was OK on the timing problems. > > Because we had a noise problem on the board, we changed it to a synch > reset. I believe we fixed the noise problem so I was considering > converting it back to asynch. I read a lot of posts here and realized > what I really needed was a combination of the two. > > The reset needs to be async when you have to immediately disable drivers > or otherwise interrupt the state of a machine or output. But you can > have problems synching the release, especially if you have multiple > clock domains. > > The solution to that is to also use a sync reset. The async reset should > cause a FF to assert a sync reset which can be removed either on the > next clock edge or by software or other external stimulus. Each clock > domain needs a separate reset FF working off of that clock. Then the > circuit will come out of reset cleanly. > What about a fully asynchronous reset with all your inputs (external inputs or internal inputs from a other clock domain) in an inactive state during the release of the reset? In such a case, the reset can be sync to the configuration clock. Do you thing this could be sufficient? > > If your reset FF is coming out of reset on the next clock edge, you may > want to also apply the metastability issues (much of which I have > learned here) to this FF and use two in cascade to reduce the likelyhood > of this causing a problem. > > This almost sounds like I am making a parody of some of the more > lengthly debated issues in this newsgroup, but I am completely serious. > This type of reset circuit should work in almost every design you can > come up with and is fairly simple. > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes (France) (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htmArticle: 16617
In article <37502151.CFCEA000@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > > But at this point we seem to be splitting hairs. The bottom line is, he > code produces something he doesn't like while it correctly matches the > simulation (at a logic level). > > So change the code. > >> Precisely. So, any suggestions on the code that will will give me a desirable implementation, namely a DFF whose (asynch) set and reset inputs are connected to my set and clear signals, whilst its clock and D inputs are effectively unused? regds Mike Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16618
Le mer Michel wrote: > > Rickman wrote: > > The reset needs to be async when you have to immediately disable drivers > > or otherwise interrupt the state of a machine or output. But you can > > have problems synching the release, especially if you have multiple > > clock domains. > > > > The solution to that is to also use a sync reset. The async reset should > > cause a FF to assert a sync reset which can be removed either on the > > next clock edge or by software or other external stimulus. Each clock > > domain needs a separate reset FF working off of that clock. Then the > > circuit will come out of reset cleanly. > > > > What about a fully asynchronous reset with all your inputs (external inputs > or internal inputs from a other clock domain) in an inactive state during > the release of the reset? > In such a case, the reset can be sync to the configuration clock. > Do you thing this could be sufficient? The issue is whether your state machines have pending state transitions. If this can be satisfied by keeping the inputs inactive, then that should work. But often there are initialization sequences on FSMs which start running as soon as you release Reset. This can be tricky to check for unless your design is small. If your machine starts off with a transition from 0000 state to 0011 state, then one FF might see the reset asserted while the other sees it released and you end up in 0010 or 0001. One hot encoding won't help. This would require a transition from 0001 to 0010 which still has two FF changing. Not to mention the metastability issues that can cause a problem even if you do transition to the correct state. The output may be unstable long enough that with the logic delays the FF that use this unstable (undefined) signal as an input will see different value. But if all FFs have inputs that will not cause a change in output, you should not have a problem. That is in essence what the added synchronous reset input does. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16619
micheal_thompson@my-deja.com wrote: > > In article <37502151.CFCEA000@yahoo.com>, > Rickman <spamgoeshere4@yahoo.com> wrote: > > > > But at this point we seem to be splitting hairs. The bottom line is, > he > > code produces something he doesn't like while it correctly matches the > > simulation (at a logic level). > > > > So change the code. > > > >> > Precisely. So, any suggestions on the code that will will give me a > desirable implementation, namely a DFF whose (asynch) set and reset > inputs are connected to my set and clear signals, whilst its clock and > D inputs are effectively unused? > regds > Mike > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. I don't understand why you need to use the DFF? Can't you just use a logic element as cross coupled gates? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16620
I am working on documentaion for my last design and I would like to include schematic pages in the document. I could just print them out and add the pages. But I was tring to add them electronically so that everything is in one file. I am writing this in Word 97 and using Xilinx Foundation 1.5i for the schematic capture. I was able to print to a PDF file, but Word won't accept that as a picture. I also tried printing Postscript to a file, but Word won't show that on the screen. It will only print it to a Postscript printer. Does anyone have an idea of how to do this? Are there any programs that will let me print the schematic to a picture file without a big loss of resolution? I found that I could cut and paste from Acrobat to Word. But the intermediate file format was a bit mapped file of some type and most of the text blurred a great deal. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16621
Company : Hall Kinion/RTP Website : http://www.hallkinion.com Job Title : FPGA Design Engineer - SYNTHESIS Location : Chapel Hill, NC Job Type : Full Time/Permanent ============================ HALL KINION/ Technical Recruiter-NEVER A FEE! Hall Kinion is the largest full-service tech recruiting firm in the Silicon Valleys of the world We work with top technical companies to offer the best of permanent and contract placements in North Carolina and across the United States and the U K Rapidly growing, state of the art company looking for FPGA Design Engineer with experience in the development of FPGA based digital devices using synthesis techniques. Requires extensive verilog design experience and experience synthesizing RTL based designs into FPGA. You must have contributed to a chip design that was reduced to working silicon. Experience with SYNOPSIS, VCS or other simulator, FPGA Express and FPGA vendor tool sets is also required. Plusses for the position would include experience with non-synthesized FPGA tools, processor design, PCI bus of SDRAM controllers and schematic capture tools and EDIF. Position is responsible for reflecting this company's DSP RTL into an FPGA implementation for high speed emulation of the ASIC design for both hardware verification and software development! Great growth opportunity and excellent compensation! Contact Information: Kelli Poe Hall Kinion/RTP 2525 Meridian Parkway, Suite 280 Durham, NC 27713 Email Address : kwp@hallkinion.com Phone: 800-365-3031 919-572-9999, x209 Fax No: 919-572-6550Article: 16622
On Mon, 31 May 1999 micheal_thompson@my-deja.com wrote: > Precisely. So, any suggestions on the code that will will give me a > desirable implementation, namely a DFF whose (asynch) set and reset > inputs are connected to my set and clear signals, whilst its clock and > D inputs are effectively unused? > regds > Mike It may not be possible to directly synthesize set/reset DFF with the FPGA if the circuits are not available. However, it is certainly possible to synthesize an asynchronous circuit from what is available that will perform the desired function. You may want to check if there are some libraries of such descriptions for the FPGA that you plan to use-- ie. pairs of resetable FF's or latches. In this thread, there is an example of a resetable DFF for example. --alvin ########################################################### Alvin E. Toda aet@lava.net sr. engineer Phone: 1-808-455-1331 2-Sigma WEB: http://www.lava.net/~aet/2-sigma.html 1363-A Hoowali St. Pearl City, Hawaii, USAArticle: 16623
Rick, You can print to a PDF (which tells me you probably have Acrobat exchange). Once you have the PDF file, open it with acrobat exchange, select the graphic (set the select graphic option in the tools menu). Now zoom way in before you copy it to the clipboard. You can then paste the image to your word file without it getting fuzzy. Apparently when you copy an acrobat image to the clipboard, it converts the image at the current zoom into a bit map. By zooming in, you get better quality images. No, I didn't find this written anywhere. I discovered it by accident when I was trying to do pretty much the same thing you are. Rickman wrote: > I am working on documentaion for my last design and I would like to > include schematic pages in the document. I could just print them out and > add the pages. But I was tring to add them electronically so that > everything is in one file. > > I am writing this in Word 97 and using Xilinx Foundation 1.5i for the > schematic capture. I was able to print to a PDF file, but Word won't > accept that as a picture. I also tried printing Postscript to a file, > but Word won't show that on the screen. It will only print it to a > Postscript printer. > > Does anyone have an idea of how to do this? Are there any programs that > will let me print the schematic to a picture file without a big loss of > resolution? I found that I could cut and paste from Acrobat to Word. But > the intermediate file format was a bit mapped file of some type and most > of the text blurred a great deal. > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16624
Just to clarify, change the zoom to 800% (the max) after selecting the graphic. Most likely, it will be bigger than your screen, but that is OK. Everything enclosed in the selection box, even if it is off the screen gets copied. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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