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Check out Xess at http://www.xess.com/FPGA/ho02000.html. They have a very small and very cheap development system for xilinx. Check the units out. -- Anthony Marchini Electronic Design Engineer American Locker Security Systems www.americanlocker.comArticle: 8226
I have a design in a 4010E with Viewlogic, and I wanted to rename a bus signal IRL31 to CODE by using a BUF between IRL31 and CODE. However, with this BUF the equation in which CODE is used, is not mapped correct in the device, although it does functional simulation ok. When I remove the BUF, my design works in simulation and on the board. I am sure I didn't overlook anything in the design, as it costed me two days to track down why the board was not working while the simulation was. Anyone experienced similar bugs in the mapper ? Should I stop trusting this mapper ? Thanks, BrunoArticle: 8227
I have not used Xilinx's tool before, but FYI, Altera is planning to support Verilog in its next Max+Plus II release (Q1 98?). Ying ying@csua.berkeley.edu In article <Pine.SOL.3.96.971129143328.12382A-100000@eesun3.tamu.edu>, Umesh Nair <nair@ee.tamu.edu> wrote: > >I would like to have your opinions on whether Altera's MaxplusII or the >Xilinx product -which is superior in what way? >I have used Altera's tool but not the one from Xilinx- one flaw I find is >that to use the Synopsis compiler for Verilog files; I need to have an >UNIX environment. I would like to have a comparison of these tools with >reference to following features: > >1. Programming PLD chips >2. Usability w.r.t Windows environment. >3. Usage of VHDL, Verilog,AHDL(Altera HDL)etc. >4. Timing analysis, Pin layouts, etc. > >thanks >Umesh > > -- ----------------------------------- http://www.csua.berkeley.edu/~yingArticle: 8228
Marc Heuler wrote: > Hm, when the flipflop is metastable, can it be recovered by > another clock pulse with valid setup/hold? Or is it on its > bad trip for an uncertain amount of time not accepting any > new input? The problem is, the length of time a register stays in the metastable state is dependent upon various factors, and isn't exactly deterministic. The delay of a register is basically Tco + Tmet, where Tmet is the additional wait time that the metastable state creates. Tmet could be anything from 0 to infinity, depending upon these factors. The equations show that it is a lot more likely that Tmet will be 1 ns than it will be 10 ns, and a lot more likely that Tmet will be 0.1 ns than it will be 1 ns. So having another register "recover" the first one's state by not violating setup and hold is a good idea, except that you can't always be certain that the first registers's metastability delay won't violate the second register's setup and hold unless you push the clock edge out a couple more nanoseconds (thus reducing the system's overall speed). The equations in my app note (Intel AP-336) describe the probability of a metastable occurance for a given set of conditions, so you may wish to look at that. -TBBArticle: 8229
There is a serious bug in the M1.3.7 mapper, with regard to the trimming of buffers (the buf symbol) and other reduced logic, when the destination of the signal has mapping control with FMAP symbols. A workaround is to attach the following attribute to the FMAP symbol: MAP=PUO This is OK if you can get at the FMAP. If the FMAP is inside a library macro (which is read only), then you will need to make a copy of the library macro, and then add the MAP=PUO attributes to your derived copy. Another approach would be to use the .NCF file (not the .UCF) file to add the attribute, but this is not trivial either. Your description of the bug you are seeing suggests that the above info may not be relevant to your problem, as the bug I am describing would not effect the logic of the design, just the performance and the number of CLBs used. In article <65ur5o$k06@miura.gent.bg.barco.com> "Bruno Fierens" <bruno.fierens@barco.com> writes: >I have a design in a 4010E with Viewlogic, and I wanted to >rename a bus signal IRL31 to CODE by using a BUF between >IRL31 and CODE. Nothing wrong here. This is the most common use of a buffer: renaming signals. >However, with this BUF the equation in which >CODE is used, is not mapped correct in the device, although it >does functional simulation ok. This is what I have also found, if the destination is covered by a FMAP >When I remove the BUF, my design >works in simulation and on the board. I am sure I didn't overlook >anything in the design, as it costed me two days to track down >why the board was not working while the simulation was. Only two days!!! You were lucky. >Anyone experienced similar bugs in the mapper ? >Should I stop trusting this mapper ? Since you are using XC4000E, you could use the older XactStep 5.2.1 / 6.0.1 software which I have found to be consistently better than M1 for this family. If you are using XC4000EX or XC4000XL, then you have to use M1, but then M1 seems to handle these families OK (except for the above described bug). >Thanks, >Bruno Good luck. PhilipArticle: 8230
CALL FOR PAPERS
1998 International Symposium on Physical Design (ISPD-98)
April 6-8, 1998, Embassy Suites Hotel, Monterey, CA
Sponsored by ACM SIGDA in cooperation with
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The International Symposium on Physical Design provides a forum to exchange
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highlight key new directions and leading-edge theoretical and experimental
contributions to the field. Accepted papers will be published by the ACM Press
in the Symposium proceedings. Topics of interest include but are not limited to:
Management of design data and constraints
Interactions with behavior-level synthesis flows
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Analysis and management of power dissipation
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Acceptance notification January 26, 1998
Camera-ready paper due February 23, 1998
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Alternatively, you may send ten (10) hardcopies of the paper to:
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To obtain information regarding the Symposium or to be added to the Symposium
mailing list, please send e-mail to ispd98@ee.iastate.edu. The ISPD web page
is at http://www.ee.iastate.edu/~ispd98
SYMPOSIUM ORGANIZATION:
General Chair: M. Sarrafzadeh (Northwestern)
Past Chair: A. Kahng (UCLA)
Steering Committee: J. Cohoon (Virginia), S. DasGupta (IBM),
M. Marek-Sadowska (UCSB), B. Preas (Xerox),
E. Yoffa (IBM)
Program Committee: M. Alexander (WA State) C.-K. Cheng (UCSD)
J. Cong (UCLA) W. Dai (UC Santa Cruz)
J. Fishburn (Lucent) D. D. Hill (Synopsys)
J. A. G. Jess (Eindhoven) L. Jones (Motorola)
S. Kang (Illinois) Y.-L. Lin (Tsing Hua)
M. Pedram (USC) R. Rutenbar (CMU)
C. Sechen (Washington) M. Wiesel (Intel)
D. F. Wong (Texas), Chair T. Yoshimura (NEC)
Publication Chair: D. D. Hill (Synopsys)
Panel Chair: N. Sherwani (Intel)
Local Chair: R.-S. Tsay (Axis Systems)
Publicity Chair: S. Sapatnekar (Minnesota)
Treasurer: S. Souvannavong
Article: 8231
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Article: 8232
In article <3482F613.525@data-io.com>, Tom Bowns <bowns@data-io.com> wrote:
>Marc Heuler wrote:
>The equations show that it is a lot more likely that Tmet will be 1 ns
>than it will be 10 ns, and a lot more likely that Tmet will be 0.1 ns
>than it will be 1 ns.
It is reasonable to model metastate decay like radioactive decay, so you
have a half-life specification and the likelyhood that the meta-state has
decayed increases exponentially with time, similar to an RC-circuit charge
curve.
>So having another register "recover" the first one's state by not
>violating setup and hold is a good idea, except that you can't always be
>certain that the first registers's metastability delay won't violate the
>second register's setup and hold unless you push the clock edge out a
>couple more nanoseconds (thus reducing the system's overall speed).
This is confused: setup and hold time don't matter at all. The width of the
capture window is the important quantity, and unfortunately it is usually
not specified and depends heavily on the nature of the flip-flop. It's
usually very short however (much much shorter than tsetup + thold, which are
as big as they are because of temperature variations). To get the second
flip-flop to also be in a meta-stable state requires that the first
flip-flop to transition within this small window and so is a very unlikely
event. Adding extra nanoseconds won't make any difference except for the
effect of changing where you are on the exponential decay probability curve.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 8233
Hello,
I am looking for PCI cores (FPGA or ASIC) and
HDL models (VHDL or Verilog) of the PCI bus.
Do you know where I can find information about that.
--
Best regards.
Stephane.
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Article: 8234I am trying to reconfigure a Altera MAX7000 via JTAG port through the ISA bus. Any help? Thank you, Curtis Lyson clyson@ontrack.comArticle: 8235
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Article: 8236Hello everybody, I'm having some problems with the XSI (Xilinx synopsys Interface). I have the Synopsys and XSI installed on a Sun Workstation but the XACT6 / Foundation Series is installed on a PC. As I don't have the license to use VHDL from Xilinx, I'm using the Synopsys tools to implement the "modules" of my design. The documentation describes the whole process of implementing designs in Synopsys and how to export the XNF file generated (using syn2xnf, etc...) to the Xilinx tools, so that one can place and route the design. But it assumes that the design is a top-level one, that is, it contains PADS and the signals are connected in some way to the external pins. In my case, I want to generate blocks (known as "macros") and place them in my schematic (Foundation Series) so that I can make the interconnections mannualy. I can successfully import the xnf generated by Synopsys and translated by the SYN2XNF from XSI into the schematic, but when I try to Place and Route something goes wrong and I receive dozens of warnings and PPR errors. Please, if someone can help me, do it ! Thanks, -- ////////////////////////////////////////////// // Rodrigo Cesar de Moraes Tavares // // e-mail: (mtavares@dcc.ufmg.br) // // Belo Horizonte - MG - Brasil // // Universidade Federal de Minas Gerais // //////////////////////////////////////////////Article: 8237
We are looking for somebody who can do a FPGA design that compresses images as seen on a PC screen, e.g. we want something that compresses exactely what you are seeing right now when looking at your screen and stores it somewhere in memory. That should be independent of graphics card used. Anybody out there? Carlo Reinhart XilinxArticle: 8238
I'm having a hard time with the UCF files. I created a UCF file with the pad constraints, e.g INST "FFTROE_N" LOC = "P127"; At the beginning, when implementing the design in the design manager, all the instances were found. After several times implementing the same design with the same UCF file, the design manager didn't find the signals anymore. I didn't modify the UCF file or the padnames in my design. What I tried now was using the EDIF netlist writer several times and bingo... after several times re-implementing and re- EDIF-netlist-writing, the design manager finally found the instances again. Anyone having similar problems and can shed some light on this ? Tnx in advance, KimArticle: 8239
Joseph H Allen <jhallen@world.std.com> wrote in article
<EKJr7v.4KI@world.std.com>...
> In article <3482F613.525@data-io.com>, Tom Bowns <bowns@data-io.com>
wrote:
> >Marc Heuler wrote:
>
<snip>
> >So having another register "recover" the first one's state by not
> >violating setup and hold is a good idea, except that you can't always be
> >certain that the first registers's metastability delay won't violate the
> >second register's setup and hold unless you push the clock edge out a
> >couple more nanoseconds (thus reducing the system's overall speed).
>
> This is confused: setup and hold time don't matter at all. The width of
the
> capture window is the important quantity, and unfortunately it is usually
> not specified and depends heavily on the nature of the flip-flop. It's
> usually very short however (much much shorter than tsetup + thold, which
are
> as big as they are because of temperature variations). To get the second
> flip-flop to also be in a meta-stable state requires that the first
> flip-flop to transition within this small window and so is a very
unlikely
> event. Adding extra nanoseconds won't make any difference except for the
> effect of changing where you are on the exponential decay probability
curve.
thanks for typing this up, joe, i just deleted almost exactly the same
text! the width of the 'window' is *MUCH* smaller than the setup and hold
times, which are generally designed so that any part that comes off of the
line, no matter what processing corner they hit, voltage variation,
temperature variation, etc., will pass. now, if my memory is correct, and
this goes back a while, here's the story. i think for 54lsxx flip-flops
the setup-hold window was like 20 nS or so - and the actual window where
metastability would hit was in the tens to perhaps a hundred or so
picoseconds. i'd have to dig in my basement for my articles on this,
perhaps someone has some good numbers handy. so, with a reasonably sized
setup time the probability of being 'not settled' is very low. and with a
second synchronizing flip-flop, the probability of system error is reduced
further by orders of magnitude and is really, really small and can be made
as small or smaller than the system reliability. of course, with the newer
processes and the flip-flops in fpgas, the 'tau' parameter is greatly
improved so failure rates get much lower, assuming you give asynchronous
signals equal settling time.
> --
> /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H.
Allen */
> int
a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
>
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+
q*2
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n","
#"[!a[q-1]]);}
-------------------------------------------------------------
rk
"there's nothing like real data to screw up a great theory"
- me (modified from original, slightly more colorful version)
--------------------------------------------------------------
Article: 8240Look it up in the Xilinx data book, page 13-43. The modern devices recover surprisingly fast from metastability, so the effective window that might create a 2 ns delay is a tiny fraction of a picosecond wide. If you have a 10 MHz clock clocking in data that changes about once per microsecond, you will induce a 2 ns extra delay statistically once per million years ( for the 2-year olf XC4005-3 ) But for a10-year oldXC3042-70 this extra 2 ns delay occurs about once per second. More than13 decimal orders of magnitude improvement in eight years ! We'll have to do some measurements to demonstrate further improvements, as we have gone from 0.8 to 0.5 to 0.35, and now to 0.25 micron technolgy in a matter of two or three years. Metastability is an interesting phenomenon, but it has lost some of its sting since the CMOS flip-flops have gotten so much better. It's just a matter of the gain-bandwidth product in the tiny feedback circuit in the master latch, an ideal parameter to improve with better technology. Everything else, including the sometimes long interconnect delays in modern circuits, is irrelevant Peter Alfke, Xilinx ApplicationsArticle: 8241
Some time ago I posted, asking why verilog was losing out to VHDL. I got a number of replies, some accusing me of trying to start a flame war. The answer I finally got was that VHDL was popular for FPGA designers, and verilog for ASIC designers. (The FPGA software that I knew of at the time supported VHDL and not verilog.) I would expect some people to do both FPGA and ASIC, and would want to use only one language. Though I still don't know why the University bookstore carries VHDL books, but verilog books are special order. -- glenArticle: 8242
Peter Alfke wrote in message <3484A59D.3576FB80@xilinx.com>... >If you have a 10 MHz clock clocking in data that changes about once per >microsecond, you will induce a 2 ns extra delay statistically once per >million years . . . . Yes, but it gets worse when your clocking at 100 MHz, and now we are moving to 300 MHz, so the problem comes back. >Metastability is an interesting phenomenon, but it has lost some of its >sting since the CMOS flip-flops have gotten so much better. But let us never forget . . . to remind new designers to beware. > It's just a matter of the gain-bandwidth product in the tiny feedback circuit >in the master latch, an ideal parameter to improve with better technology. >Everything else, including the sometimes long interconnect >delays in modern circuits, is irrelevant agreed, as long as the designer and/or synthesis does not construct flip-flops from gates. John Birkner, QuickLogicArticle: 8243
Their web site still seems active, but I get the impression that nobody quotes PREP results any more. Has PREP fallen out of favor, is it not representative, or am I just not paying enough attention? -- Pete FraserArticle: 8244
John Birkner (birkner@quicklogic.com) wrote: > Peter Alfke wrote in message <3484A59D.3576FB80@xilinx.com>... > >If you have a 10 MHz clock clocking in data that changes about once per > >microsecond, you will induce a 2 ns extra delay statistically once per > >million years . . . . > Yes, but it gets worse when your clocking at 100 MHz, > and now we are moving to 300 MHz, > so the problem comes back. I know that it is impossible to guarantee a legal value will be sampled, but is there anything that can be done to minimize the effects? Is it possible to design into your system a graceful recovery? Can you even recognize that your sampled value is in the metastable region? GREGArticle: 8245
--------------AEA5693ED2C135C41E4C4E9A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Adam Seychell schrieb: > Which manufacture of PGAs would make it possible for the hobbyist to > use this technology. Obviously the manufactures are mainly interested > in the big customers and so charge big bucks for their development > products. So far I've investigated Lattice, Altera & Xilinx and they > all have unrealistic prices for their design software. The cost of the > chips are relativly small ($10-$20 each). The cheapest design package > was around ($850 Australian). Maybe I haven't looked around enough, > but if anyone has managed to use re-programable PGAs for a home > project, then please direct me to a source. > > I am interested in devices capable of In System Programable and In > System Configerable. This has led me to the following products > > erase/program cycles > Lattice: ispLSI1000 series 1000 > Altera: FLEX6000 series infinite > Altera: MAX7000 series 100 > Xilinx: XC3000 series infinite > Philips: PZ5000 series 1000 > > > > Adam If you just want to play with reprogrammable logic then I'd recommend the Lattice isp1000 parts (they are good for real apps too). The design tool is free, at least for the smaller devices. If you need more ressourced there is only one free place&route tool available: the Motorola design system at http://www.design-net.com/fpga/fpga.html However there is no front end apart from the demo version of capilano (can't save). BUT: if you look at at http://home.t-online.de/home/akugel/mpa.htm you find some infos about my simulation and design entry project for the Motorola parts. It is not the latest version on the Web). The work is still not finished but will be useable hopefully by the end of this year. There is also a small prototyping PCB you can attach to an LPT port (FPGA with RAM, breadboard area). Device configuration and user access are done from a Win95 program. Beta testers and volunteers to complete the work are welcome. Andreas -- Andreas Kugel - University of Mannheim - Dept. of Computer Science V B6,26 - 68131 Mannheim - Germany Phone:+(49)621 292 1634 - Fax:+(49)621 292 5756 mailto:kugel@mp-sun1.informatik.uni-mannheim.de http://www-mp.informatik.uni-mannheim.de/groups/mass_par_1/parallelproc.html --------------AEA5693ED2C135C41E4C4E9A Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> <P>Adam Seychell schrieb: <BLOCKQUOTE TYPE=CITE> <TT>Which manufacture of PGAs would make it possible for the hobbyist to use this technology. Obviously the manufactures are mainly interested in the big customers and so charge big bucks for their development products. So far I've investigated Lattice, Altera & Xilinx and they all have unrealistic prices for their design software. The cost of the chips are relativly small ($10-$20 each). The cheapest design package was around ($850 Australian). Maybe I haven't looked around enough, but if anyone has managed to use re-programable PGAs for a home project, then please direct me to a source.</TT> <P><TT>I am interested in devices capable of In System Programable and In System Configerable. This has led me to the following products</TT> <P><TT> erase/program cycles</TT> <BR><TT> Lattice: ispLSI1000 series 1000</TT> <BR><TT> Altera: FLEX6000 series infinite</TT> <BR><TT> Altera: MAX7000 series 100</TT> <BR><TT> Xilinx: XC3000 series infinite</TT> <BR><TT> Philips: PZ5000 series 1000</TT> <BR> <BR> <P><TT>Adam</TT></BLOCKQUOTE> If you just want to play with reprogrammable logic then I'd recommend the Lattice isp1000 <BR>parts (they are good for real apps too). The design tool is free, at least for the smaller devices. <BR>If you need more ressourced there is only one free place&route tool available: the Motorola design <BR>system at <A HREF="http://www.design-net.com/fpga/fpga.html">http://www.design-net.com/fpga/fpga.html</A> <BR>However there is no front end apart from the demo version of capilano (can't save). <BR>BUT: if you look at at <A HREF="http://home.t-online.de/home/akugel/mpa.htm">http://home.t-online.de/home/akugel/mpa.htm</A> you find some infos about <BR>my simulation and design entry project for the Motorola parts. It is not the latest version on the Web). <BR>The work is still not finished but will be useable hopefully by the end of this year. <BR>There is also a small prototyping PCB you can attach to an LPT port (FPGA with RAM, breadboard area). <BR>Device configuration and user access are done from a Win95 program. <P>Beta testers and volunteers to complete the work are welcome. <BR> <P>Andreas <P>-- <BR>Andreas Kugel - University of Mannheim - Dept. of Computer Science V <BR>B6,26 - 68131 Mannheim - Germany <BR>Phone:+(49)621 292 1634 - Fax:+(49)621 292 5756 <BR><A HREF="mailto:kugel@mp-sun1.informatik.uni-mannheim.de">mailto:kugel@mp-sun1.informatik.uni-mannheim.de</A> <BR><A HREF="http://www-mp.informatik.uni-mannheim.de/groups/mass_par_1/parallelproc.html">http://www-mp.informatik.uni-mannheim.de/groups/mass_par_1/parallelproc.html</A> <BR> </HTML> --------------AEA5693ED2C135C41E4C4E9A--Article: 8246
On 3 Dec 1997, G. Herrmannsfeldt wrote: > Though I still don't know why the University bookstore carries VHDL > books, but verilog books are special order. Maybe because Verilog is so easy to learn that books are simply superfluous! :) It was just a joke, don't flame me! :) Mihai L.Article: 8247
In article <01bcfeea$75f00d80$c584accf@default>, "Richard B. Katz" <stellare_nospam@erols.com> writes: > i think for 54lsxx flip-flops > the setup-hold window was like 20 nS or so - and the actual window where > metastability would hit was in the tens to perhaps a hundred or so > picoseconds. It's unfortunately a bit more complex. The metastability window, or failure window, is usually calculated with this formula: w(tstab) = A * exp(-B*tstab) Where A and B are implementation/process specific constants and tstab is the time you want it to take for the flip-flop to stabilize. The length of the window w(tstab) varies extremly with the value of tstab. Example from one process I'm using today: w(10ns) = 4.8e-52 w(5ns) = 3.1e-31 w(2.5ns) = 7.7e-21 Kenny -- Kenny Ranerup Phone@work: +46 46 2701848 Axis Communications AB Phone@home: +46 46 139105 Scheelevägen 16 Fax@work: +46 46 136130 S-223 70 Lund, SWEDEN Email: kenny@axis.se http://www.axis.com/ http://hem1.passagen.se/kranerupArticle: 8248
It's fallen out of favour. Check out my article in the May 22, 1997 issue of EDN (also on www.ednmag.com, look in the archive) for the details.... >Their web site still seems active, but I get the impression >that nobody quotes PREP results any more. > >Has PREP fallen out of favor, is it not representative, >or am I just not paying enough attention? Brian Dipert Technical Editor EDN Magazine: The Design Magazine Of The Electronics Industry 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (916) 454-5101 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** Visit me at <http://members.aol.com/bdipert>Article: 8249
I'm trying to turn on the pullup or pulldown ressitors in an IO pad on a Xilinx 4000e series fpga. I've done this successfully in schematic capture but can't find out how to do it in VHDL. I'm using Leonardo as my VHDL compiler. Any help would be greatly appreciated. Thanks. Josh Potts University of Illinois
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