Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Wednesday, September 25, 2019 at 3:22:53 PM UTC-7, Rick C wrote:
> On Wednesday, September 25, 2019 at 5:53:38 PM UTC-4, Weng Tianxiang wrot=
e:
> > Hi,
> > In my opinion, using a 2-write port memory is a mature technique and it=
s implementation in any chip is never a secret. Hardware designers in HDL o=
ften use 2-write port memory in their applications.
> >=20
> > To relieve hardware designers from repeatedly writing complex code for =
a 2-write port memory, I suggest here for full HDL grammar spectrum to intr=
oduce a new keyword "if_2" and new "if_2" statement, specifying a new if st=
atement which has everything same as an if statement, but it specifies a se=
cond write to an array. Here is a code example on how to introduce such sta=
tement:
> >=20
> > p1: process(CLK) is
> > begin
> > if CLK'event and CLK =3D '1' then
> > if C1 then
> > An_Array(a) <=3D D1; -- it is first write to array An_Array
> > end if;
> >=20
> > -- "IF_2" is a new keyword which introduces a second write to an array =
in its full range, including all "else", "elsif" parts. And "if_2" keyword =
can only be used in a clocked process.
> >=20
> > if_2 C2 then
> > An_Array(b) <=3D D2; -- it is a second write to array An_Array
> > end if;
> > end if;
> > end process;
> >=20
> > If a 2nd write to an array does not need any condition, the statement c=
an be written as:
> >=20
> > if_2 '1' then
> > An_Array(b) <=3D D2; -- it is a second write without any conditio=
n
> > end if;
> >=20
> > Using the new suggested keyword "if_2" in HDL, everybody would like it,=
not having repeatedly to write a 2-write-port memory for different FPGA ch=
ips.
> >=20
> > Weng
>=20
> Can you give an example of the code this would replace??? I don't rememb=
er two port memory code being all that complex. =20
>=20
> --=20
>=20
> Rick C.
>=20
> - Get 2,000 miles of free Supercharging
> - Tesla referral code - https://ts.la/richard11209
For 2 writes on the same cycle to an array now you have to refer to a speci=
al library either from Xilink or Altera.=20
Even though referring=C2=A0a library is not difficult coding problem, but y=
our code has to change if you move chip provider from one to another.
With introduction of "if_2" concept you never have to refer to any library,=
and it would become normal and simple as addition of A and B!
Here is a more example:
p1: process(CLK) is
begin
if CLK'event and CLK =3D '1' then
if C1 thenAn_Array(a) <=3D D1; -- it is first write to array An_Array
if_2 C2 then
An_Array(b) <=3D D2; -- it is a second write to An_Array
end if;
end if;
end if;
end process;
Anywhere an if statement can be used an if_2 statement can be used!
With "if_2" introduction you don't have to remember any library from which =
company.
Article: 161451On Wednesday, September 25, 2019 at 11:16:40 PM UTC-4, Weng Tianxiang wrote= : > On Wednesday, September 25, 2019 at 3:22:53 PM UTC-7, Rick C wrote: > > On Wednesday, September 25, 2019 at 5:53:38 PM UTC-4, Weng Tianxiang wr= ote: > > > Hi, > > > In my opinion, using a 2-write port memory is a mature technique and = its implementation in any chip is never a secret. Hardware designers in HDL= often use 2-write port memory in their applications. > > >=20 > > > To relieve hardware designers from repeatedly writing complex code fo= r a 2-write port memory, I suggest here for full HDL grammar spectrum to in= troduce a new keyword "if_2" and new "if_2" statement, specifying a new if = statement which has everything same as an if statement, but it specifies a = second write to an array. Here is a code example on how to introduce such s= tatement: > > >=20 > > > p1: process(CLK) is > > > begin > > > if CLK'event and CLK =3D '1' then > > > if C1 then > > > An_Array(a) <=3D D1; -- it is first write to array An_Array > > > end if; > > >=20 > > > -- "IF_2" is a new keyword which introduces a second write to an arra= y in its full range, including all "else", "elsif" parts. And "if_2" keywor= d can only be used in a clocked process. > > >=20 > > > if_2 C2 then > > > An_Array(b) <=3D D2; -- it is a second write to array An_Array > > > end if; > > > end if; > > > end process; > > >=20 > > > If a 2nd write to an array does not need any condition, the statement= can be written as: > > >=20 > > > if_2 '1' then > > > An_Array(b) <=3D D2; -- it is a second write without any condit= ion > > > end if; > > >=20 > > > Using the new suggested keyword "if_2" in HDL, everybody would like i= t, not having repeatedly to write a 2-write-port memory for different FPGA = chips. > > >=20 > > > Weng > >=20 > > Can you give an example of the code this would replace??? I don't reme= mber two port memory code being all that complex. =20 > >=20 > > --=20 > >=20 > > Rick C. > >=20 > > - Get 2,000 miles of free Supercharging > > - Tesla referral code - https://ts.la/richard11209 >=20 > For 2 writes on the same cycle to an array now you have to refer to a spe= cial library either from Xilink or Altera.=20 I would suggest you spend more time researching this. I had no trouble fin= ding info on inferring dual write port RAMs with Xilinx tools.=20 http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/xst_v6s6.= pdf (page 250) > Even though referring=C2=A0a library is not difficult coding problem, but= your code has to change if you move chip provider from one to another. >=20 > With introduction of "if_2" concept you never have to refer to any librar= y, and it would become normal and simple as addition of A and B! >=20 > Here is a more example: > p1: process(CLK) is > begin > if CLK'event and CLK =3D '1' then > if C1 thenAn_Array(a) <=3D D1; -- it is first write to array An_Array > if_2 C2 then > An_Array(b) <=3D D2; -- it is a second write to An_Array > end if; > end if; > end if; > end process; >=20 > Anywhere an if statement can be used an if_2 statement can be used! >=20 > With "if_2" introduction you don't have to remember any library from whic= h company. I think you will find both a great deal of resistance since the general con= struct of VHDL is not to provide specific features in the language to speci= fy hardware, rather to describe behavior and let the tools infer appropriat= e hardware corresponding to the target technology. =20 I would also point out your code is not appropriate for a dual port RAM sin= ce the second port can only be written to when the first port is being writ= ten to. Shouldn't they both be independent as was the case in your other e= xamples in the other thread?=20 --=20 Rick C. + Get 2,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209Article: 161452
On Wednesday, September 25, 2019 at 9:30:11 PM UTC-7, Rick C wrote: > On Wednesday, September 25, 2019 at 11:16:40 PM UTC-4, Weng Tianxiang wro= te: > > On Wednesday, September 25, 2019 at 3:22:53 PM UTC-7, Rick C wrote: > > > On Wednesday, September 25, 2019 at 5:53:38 PM UTC-4, Weng Tianxiang = wrote: > > > > Hi, > > > > In my opinion, using a 2-write port memory is a mature technique an= d its implementation in any chip is never a secret. Hardware designers in H= DL often use 2-write port memory in their applications. > > > >=20 > > > > To relieve hardware designers from repeatedly writing complex code = for a 2-write port memory, I suggest here for full HDL grammar spectrum to = introduce a new keyword "if_2" and new "if_2" statement, specifying a new i= f statement which has everything same as an if statement, but it specifies = a second write to an array. Here is a code example on how to introduce such= statement: > > > >=20 > > > > p1: process(CLK) is > > > > begin > > > > if CLK'event and CLK =3D '1' then > > > > if C1 then > > > > An_Array(a) <=3D D1; -- it is first write to array An_Array > > > > end if; > > > >=20 > > > > -- "IF_2" is a new keyword which introduces a second write to an ar= ray in its full range, including all "else", "elsif" parts. And "if_2" keyw= ord can only be used in a clocked process. > > > >=20 > > > > if_2 C2 then > > > > An_Array(b) <=3D D2; -- it is a second write to array An_Arra= y > > > > end if; > > > > end if; > > > > end process; > > > >=20 > > > > If a 2nd write to an array does not need any condition, the stateme= nt can be written as: > > > >=20 > > > > if_2 '1' then > > > > An_Array(b) <=3D D2; -- it is a second write without any cond= ition > > > > end if; > > > >=20 > > > > Using the new suggested keyword "if_2" in HDL, everybody would like= it, not having repeatedly to write a 2-write-port memory for different FPG= A chips. > > > >=20 > > > > Weng > > >=20 > > > Can you give an example of the code this would replace??? I don't re= member two port memory code being all that complex. =20 > > >=20 > > > --=20 > > >=20 > > > Rick C. > > >=20 > > > - Get 2,000 miles of free Supercharging > > > - Tesla referral code - https://ts.la/richard11209 > >=20 > > For 2 writes on the same cycle to an array now you have to refer to a s= pecial library either from Xilink or Altera.=20 >=20 > I would suggest you spend more time researching this. I had no trouble f= inding info on inferring dual write port RAMs with Xilinx tools.=20 >=20 > http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/xst_v6s= 6.pdf (page 250) >=20 >=20 > > Even though referring=C2=A0a library is not difficult coding problem, b= ut your code has to change if you move chip provider from one to another. > >=20 > > With introduction of "if_2" concept you never have to refer to any libr= ary, and it would become normal and simple as addition of A and B! > >=20 > > Here is a more example: > > p1: process(CLK) is > > begin > > if CLK'event and CLK =3D '1' then > > if C1 thenAn_Array(a) <=3D D1; -- it is first write to array An_Arr= ay > > if_2 C2 then > > An_Array(b) <=3D D2; -- it is a second write to An_Array > > end if; > > end if; > > end if; > > end process; > >=20 > > Anywhere an if statement can be used an if_2 statement can be used! > >=20 > > With "if_2" introduction you don't have to remember any library from wh= ich company. >=20 > I think you will find both a great deal of resistance since the general c= onstruct of VHDL is not to provide specific features in the language to spe= cify hardware, rather to describe behavior and let the tools infer appropri= ate hardware corresponding to the target technology. =20 >=20 > I would also point out your code is not appropriate for a dual port RAM s= ince the second port can only be written to when the first port is being wr= itten to. Shouldn't they both be independent as was the case in your other= examples in the other thread?=20 >=20 > --=20 >=20 > Rick C. >=20 > + Get 2,000 miles of free Supercharging > + Tesla referral code - https://ts.la/richard11209 Rick, I just list a code snippet that suggests if statement and if_2 statement ca= n be mixed, not a code error.=20 WengArticle: 161453
On 25/09/2019 22:22, Weng Tianxiang wrote: > On Wednesday, September 25, 2019 at 12:34:13 PM UTC-7, KJ wrote: >> On Wednesday, September 25, 2019 at 2:07:45 PM UTC-4, Weng Tianxiang wrote: .. > p1: process(CLK) is > begin > if CLK'event and CLK = '1' then > if C1 then > An_Array(a) <= D1; > end if; > > -- "IF_2" is a new keyword which introduces a second write to an array in its full range, including all "else", "elsif" parts. And "if_2" keyword can only be used in a clocked process. > > if_2 C2 then > An_Array(b) <= D2; > end if; > end if; > end process; > > Using the new suggested keyword "if_2" in VHDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chip. > > In my design there are more than 10 arrays need 2-write port memory. > > Weng > Hi Weng, Give it up, your are flogging a dead horse, no new language constructs are requires as we already have the correct simulation and synthesis models for decades. If you have lots of dual port memories to connect use a Generate statement. Regards, Hans www.ht-lab.comArticle: 161454
On Wednesday, September 25, 2019 at 11:16:40 PM UTC-4, Weng Tianxiang wrote= : > On Wednesday, September 25, 2019 at 3:22:53 PM UTC-7, Rick C wrote: > > On Wednesday, September 25, 2019 at 5:53:38 PM UTC-4, Weng Tianxiang wr= ote: >=20 > For 2 writes on the same cycle to an array now you have to refer to a spe= cial library either from Xilink or Altera.=20 >=20 That is incorrect. Since this is your premise for your new if_2 statement,= and it is incorrect you should go back to rethinking the supposed problem. > Even though referring=C2=A0a library is not difficult coding problem, but= your code has to change if you move chip provider from one to another. >=20 No you don't. >=20 > Anywhere an if statement can be used an if_2 statement can be used! >=20 Not only that, but the if statement can be used whenever the if_2 statement= can be used, there is no need for if_2. > With "if_2" introduction you don't have to remember any library from whic= h company. No need to remember if_2 either. But don't worry, Google will remember. Kevin JenningsArticle: 161455
On Wednesday, September 25, 2019 at 5:22:34 PM UTC-4, Weng Tianxiang wrote: > On Wednesday, September 25, 2019 at 12:34:13 PM UTC-7, KJ wrote: > > On Wednesday, September 25, 2019 at 2:07:45 PM UTC-4, Weng Tianxiang wr= ote: >=20 > I prefer for VHDL grammar to introduce a new statement, specifying an if = statement is a second write to an array.=20 'I prefer' is not justification. One needs to provide objective, measurabl= e improvement. 'I prefer' doesn't do it. > Here is a code example on how to introduce such statement: Yet your example by one measure shows how your new method is worse. Rather= than simply typing 'if', now one types 'if_2'. How is that better? The s= ame simulation and synthesis results would occur but now any designer is ty= ping more to achieve the same...sort of unproductive don't you think? The = language gets more complex and produces no objective benefit to anyone...no= t the sort of change that benefits. >=20 > Using the new suggested keyword "if_2" in VHDL, everybody would like it, = not having repeatedly to write a 2-write-port memory for different FPGA chi= p. >=20 Everybody? How about anybody besides you? Who are these people that "repea= tedly to write a 2-write-port memory" rather than writing it once? Those p= eople need to learn how design should be done. > In my design there are more than 10 arrays need 2-write port memory. >=20 This statement simply demonstrates your total lack of ability in design. I= f you're writing the same thing 10 times you're doing it the wrong way. Kevin JenningsArticle: 161456
On Thursday, September 26, 2019 at 2:50:48 AM UTC-7, HT-Lab wrote: > On 25/09/2019 22:22, Weng Tianxiang wrote: > > On Wednesday, September 25, 2019 at 12:34:13 PM UTC-7, KJ wrote: > >> On Wednesday, September 25, 2019 at 2:07:45 PM UTC-4, Weng Tianxiang wrote: > .. > > p1: process(CLK) is > > begin > > if CLK'event and CLK = '1' then > > if C1 then > > An_Array(a) <= D1; > > end if; > > > > -- "IF_2" is a new keyword which introduces a second write to an array in its full range, including all "else", "elsif" parts. And "if_2" keyword can only be used in a clocked process. > > > > if_2 C2 then > > An_Array(b) <= D2; > > end if; > > end if; > > end process; > > > > Using the new suggested keyword "if_2" in VHDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chip. > > > > In my design there are more than 10 arrays need 2-write port memory. > > > > Weng > > > > Hi Weng, > > Give it up, your are flogging a dead horse, no new language constructs > are requires as we already have the correct simulation and synthesis > models for decades. > > If you have lots of dual port memories to connect use a Generate statement. > > Regards, > Hans > www.ht-lab.com Hans, Here is an excellent paper dealing with the situation: efficient multi-port memory with FPGA, http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf. I appreciate the paper very much. I know there is a solution to 2-write memory, but simple "if_2" is a simple solution to inferring to the method. WengArticle: 161457
On Thursday, September 26, 2019 at 9:36:46 AM UTC-4, Weng Tianxiang wrote: > On Thursday, September 26, 2019 at 2:50:48 AM UTC-7, HT-Lab wrote: > > On 25/09/2019 22:22, Weng Tianxiang wrote: > > > On Wednesday, September 25, 2019 at 12:34:13 PM UTC-7, KJ wrote: > > >> On Wednesday, September 25, 2019 at 2:07:45 PM UTC-4, Weng Tianxiang= wrote: > > .. > > > p1: process(CLK) is > > > begin > > > if CLK'event and CLK =3D '1' then > > > if C1 then > > > An_Array(a) <=3D D1; > > > end if; > > >=20 > > > -- "IF_2" is a new keyword which introduces a second write to an= array in its full range, including all "else", "elsif" parts. And "if_2" k= eyword can only be used in a clocked process. > > > =20 > > > if_2 C2 then > > > An_Array(b) <=3D D2; > > > end if; > > > end if; > > > end process; > > >=20 > > > Using the new suggested keyword "if_2" in VHDL, everybody would like = it, not having repeatedly to write a 2-write-port memory for different FPGA= chip. > > >=20 > > > In my design there are more than 10 arrays need 2-write port memory. > > >=20 > > > Weng > > >=20 > >=20 > > Hi Weng, > >=20 > > Give it up, your are flogging a dead horse, no new language constructs= =20 > > are requires as we already have the correct simulation and synthesis=20 > > models for decades. > >=20 > > If you have lots of dual port memories to connect use a Generate statem= ent. > >=20 > > Regards, > > Hans > > www.ht-lab.com >=20 > Hans, >=20 > Here is an excellent paper dealing with the situation: efficient multi-po= rt memory with FPGA, http://www.eecg.toronto.edu/~steffan/papers/laforest_f= pga10.pdf. >=20 > I appreciate the paper very much. I know there is a solution to 2-write m= emory, but simple "if_2" is a simple solution to inferring to the method. >=20 > Weng You have provided a keyword, "if_2" and a code example which is not logical= ly correct. I don't see how your keyword solves anything. First, you need= to define exactly what the keyword does, which I assume is the same as "if= ". Then you need to use examples which are logically correct. Then perhap= s you can explain why your new keyword accomplishes something that the exis= ting keyword doesn't do already.=20 It sure seems like you are trying to solve a problem that doesn't exist. C= ertainly your initial premise that dual write port RAMs must be instantiate= d is not correct. Dual write port RAMs can be inferred as shown in the inf= o I linked to in the other thread.=20 --=20 Rick C. + Get 2,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209Article: 161458
On 26/09/2019 14:36, Weng Tianxiang wrote: > On Thursday, September 26, 2019 at 2:50:48 AM UTC-7, HT-Lab wrote: >> On 25/09/2019 22:22, Weng Tianxiang wrote: .. >> >> Hi Weng, >> >> Give it up, your are flogging a dead horse, no new language constructs >> are requires as we already have the correct simulation and synthesis >> models for decades. >> >> If you have lots of dual port memories to connect use a Generate statement. >> >> Regards, >> Hans >> www.ht-lab.com > > Hans, > > Here is an excellent paper dealing with the situation: efficient multi-port memory with FPGA, http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf. > > I appreciate the paper very much. I know there is a solution to 2-write memory, but simple "if_2" is a simple solution to inferring to the method. > > Weng Hi Weng, Yes I know that paper quite well and have used the XOR variant in one of my x86 processors (4W8R). I had no problems implementing it, the standard method is simple and straightforward. As others have told you multi port memories are well established and understood in our community, there is no need for a special keyword. Regards, Hans www.ht-lab.comArticle: 161459
On Thursday, September 26, 2019 at 9:36:46 AM UTC-4, Weng Tianxiang wrote: >=20 > Here is an excellent paper dealing with the situation: efficient multi-po= rt memory with FPGA, http://www.eecg.toronto.edu/~steffan/papers/laforest_f= pga10.pdf. >=20 > I appreciate the paper very much. I know there is a solution to 2-write m= emory, but simple "if_2" is a simple solution to inferring to the method. >=20 If_2 is not the solution to inferring the method by LaForest and Steffan. = In a nutshell, what they describe is the bolded text in section 5 (LVT-Base= d Multiported memories) where it clearly says "Our approach comprises banks of replicated block RAMs where a mechanism of indirection...". They = are not claiming to implement something that implements the two write port = hardware description that you presented. There would still need to be code= written to implement the LVT approach in order to describe that LVT design= . Once that code is written, one would have a multi-port design that one c= ould reuse but it would use more logic/memory resources than just a memory. If you think the LVT based approach is worth using for your design, then wr= ite the code to implement an LVT based memory design. Trying to propose 'i= f_2' as being some way to implement LVT (or some other alternative approach= ) is quite naive on your part. Kevin JenningsArticle: 161460
Here is new definition for keyword "if_2", version 2.
It is developed based on many discussions after my first post: " New keywor=
d "if_2" is suggested for dealing with 2-write port memory."
New keyword "if_2" is used to put m-write and n-read memory module from chi=
p manufactures' toolbox behind HDL language so that with the new keyword "i=
f_2" introduction any m-write and n-read memory module would be fully speci=
fied in HDL with very simple coding and without special technique and knowl=
edge about memory module, or instantiated memory module needed for circuit =
designers. All related complex job is left to synthesizer' manufacturers.
If_2-statement ::=3D
[ if_2_label : ]
if_2 condition then
sequence_of_statements
{ elsif condition then
sequence_of_statements }
[ else
sequence_of_statements ]
end if [ if_2_label ] ;
1. Any assignment statement's target array in sequence_of_statements under =
an if-2 statement is an independent write to a memory that must be executed=
, not obeying statement sequence in a process, regardless how many writes t=
o the target array are coded before or after its appearance.
2. Any assignment statement's target non-array signal in sequence_of_statem=
ents under an if_2 statement obeys statement sequence in a process.
3. An if-statement under an if_2-statement is treated as an if_2-statement.
4. An if_2-statement can only exist within a clocked process.
Here is a code example to specify a 3-write and 2-read memory module:
p1: process(CLK) is
begin
if CLK'event and CLK =3D '1' then
if C1 then
An_Array(a) <=3D D1; -- it is first write to array An_Array
end if;
if_2 C2 then
An_Array(b) <=3D D2; -- it is the second write to array An_Array
end if;
if_2 C3 then
An_Array(c) <=3D D3; -- it is the third write to array An_Array
end if;
X <=3D An_Array(j); -- first read from array An_Array
Y <=3D An_Array(k); -- second read from array An_Array
end if;
end process;
Especial thanks to the creative response writers who mentioned keyword "if_=
3", who gave me the specification of Cyclone and has deep discussions with =
me, and Han from HDL-lab whose implementation of a 8-write and 8-read memor=
y for a CPU chip gave me deep impression long before the new idea is born.
Weng
Article: 161461On Thursday, September 26, 2019 at 11:42:35 PM UTC-4, Weng Tianxiang wrote: > Here is new definition for keyword "if_2", version 2. >=20 Same comments as with the first 'definition' which is that it provides no b= enefit to anyone that uses VHDL and it expands the keyword list of the stan= dard without providing any benefit. Good luck with that. Now that VHDL-20= 19 is near the end of the finish line, VHDL-2030 won't be far behind, that = will be your next opportunity. Each instance of 'if_2' in your example process can be replaced with today'= s 'if' and the example process works with every VHDL standard that has been= released to date. So, if 'if_2' ever became part of the standard, then an= yone who would use it is locking themselves into requiring use of a particu= lar standard when it is not needed. That is poor design practice. I guess= users will just have to muddle through by typing the exact same thing exce= pt for the needless '_2'. Kevin JenningsArticle: 161462
I download someone's key code from pastebin.com and copy it here for easy d= iscussion. He claims that the following code describes a 10-write and 10-re= ad memory module, but he admitted that a synthesizer does not run it well. architecture example of memtest is ... . shared variable memory : memory_t; -- !!! begin . . blks : for i in 0 to PORT_COUNT-1 generate . . . memport : process(clocks(i)) . . . begin . . . . . if rising_edge(clocks(i)) then . . . . . . . if stbs(i) =3D '1' then . . . . . . . . . memory(addrs(i)) :=3D writes(i); . . . . . . . end if; . . . . . . . reads(i) <=3D memory(addrs(i)); . . . . . end if; . . . end process; . . end generate; end architecture; Does it mean a 10-write and 10-read port memory module? I really don't understand what the code means, and how synthesizer executes= it, and hope some experts explain it to me further. As a fact, he says that "The fact that this probably wouldn't go so well wh= en you ran it comes down to the synthesizer not the language." That is abso= lutely not as good as you promised what you have describe it before: the me= thod to generate an n-write and m-read memory module is well established in= HDL grammar. If a well defined code based on a grammar cannot run well by = a synthesizer, can I believe what you say? If it is really a 10-port memory module, why a synthesizer does not do well= ? Thank you. WengArticle: 161463
On Friday, September 27, 2019 at 7:25:33 PM UTC-4, Weng Tianxiang wrote: > I download someone's key code from pastebin.com and copy it here for easy= discussion. He claims that the following code describes a 10-write and 10-= read memory module, but he admitted that a synthesizer does not run it well= . >=20 > architecture example of memtest is > ... > . shared variable memory : memory_t; -- !!! > begin > . . blks : for i in 0 to PORT_COUNT-1 generate > . . . memport : process(clocks(i)) > . . . begin > . . . . . if rising_edge(clocks(i)) then > . . . . . . . if stbs(i) =3D '1' then > . . . . . . . . . memory(addrs(i)) :=3D writes(i); > . . . . . . . end if; > . . . . . . . reads(i) <=3D memory(addrs(i)); > . . . . . end if; > . . . end process; > . . end generate; > end architecture; >=20 > Does it mean a 10-write and 10-read port memory module? >=20 > I really don't understand what the code means, and how synthesizer execut= es it, and hope some experts explain it to me further. >=20 > As a fact, he says that "The fact that this probably wouldn't go so well = when you ran it comes down to the synthesizer not the language." That is ab= solutely not as good as you promised what you have describe it before: the = method to generate an n-write and m-read memory module is well established = in HDL grammar. If a well defined code based on a grammar cannot run well b= y a synthesizer, can I believe what you say? >=20 > If it is really a 10-port memory module, why a synthesizer does not do we= ll? >=20 > Thank you. >=20 > Weng Yes, it describes a single memory with N ports where N is defined by PORT_C= OUNT. What part of the code do you find confusing?=20 There is no shortcoming in the language. This code describes the memory pr= operly. If a synthesizer can't synthesize this code for 10 ports that is a= problem with the synthesizer, not the language. I'm willing to bet you wi= ll have a hard time finding a library module for a 10 port memory. =20 If you don't understand the language enough to know this code describes an = N port memory, you really are not in a position to tell the rest of us how = the language should be changed to accommodate your lack of understanding. = =20 --=20 Rick C. - Get 2,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209Article: 161464
On Friday, September 27, 2019 at 5:05:55 PM UTC-7, Rick C wrote: > On Friday, September 27, 2019 at 7:25:33 PM UTC-4, Weng Tianxiang wrote: > > I download someone's key code from pastebin.com and copy it here for ea= sy discussion. He claims that the following code describes a 10-write and 1= 0-read memory module, but he admitted that a synthesizer does not run it we= ll. > >=20 > > architecture example of memtest is > > ... > > . shared variable memory : memory_t; -- !!! > > begin > > . . blks : for i in 0 to PORT_COUNT-1 generate > > . . . memport : process(clocks(i)) > > . . . begin > > . . . . . if rising_edge(clocks(i)) then > > . . . . . . . if stbs(i) =3D '1' then > > . . . . . . . . . memory(addrs(i)) :=3D writes(i); > > . . . . . . . end if; > > . . . . . . . reads(i) <=3D memory(addrs(i)); > > . . . . . end if; > > . . . end process; > > . . end generate; > > end architecture; > >=20 > > Does it mean a 10-write and 10-read port memory module? > >=20 > > I really don't understand what the code means, and how synthesizer exec= utes it, and hope some experts explain it to me further. > >=20 > > As a fact, he says that "The fact that this probably wouldn't go so wel= l when you ran it comes down to the synthesizer not the language." That is = absolutely not as good as you promised what you have describe it before: th= e method to generate an n-write and m-read memory module is well establishe= d in HDL grammar. If a well defined code based on a grammar cannot run well= by a synthesizer, can I believe what you say? > >=20 > > If it is really a 10-port memory module, why a synthesizer does not do = well? > >=20 > > Thank you. > >=20 > > Weng >=20 > Yes, it describes a single memory with N ports where N is defined by PORT= _COUNT. What part of the code do you find confusing?=20 >=20 > There is no shortcoming in the language. This code describes the memory = properly. If a synthesizer can't synthesize this code for 10 ports that is= a problem with the synthesizer, not the language. I'm willing to bet you = will have a hard time finding a library module for a 10 port memory. =20 >=20 > If you don't understand the language enough to know this code describes a= n N port memory, you really are not in a position to tell the rest of us ho= w the language should be changed to accommodate your lack of understanding.= =20 >=20 > --=20 >=20 > Rick C. >=20 > - Get 2,000 miles of free Supercharging > - Tesla referral code - https://ts.la/richard11209 Rick, I think your conclusion is made too earlier. Here is what the code author responses: The synthesizer doesn=E2=80=99t do well because any additional port to a me= mory makes it exponentially harder to implement. You can implement a multi-memory in 3 ways: real physical designed hard memory block. These are the dual-ported memorie= s of FPGAs flip-flops or latch based arrays. These are very area inefficient. weird architectures that use dual-ported memories to build memories with a = larger number of ports. That=E2=80=99s the paper that you linked too. It is= extremely area inefficient as well. In practice. designers avoid multi-ported memories like the plague because = they are very costly. It has nothing to do with language features. As shown= above: writing the RTL for a 10-ported memory is trivial. You don=E2=80=99= t need new keywords for it. For example: a 10 ported read/write memory would require on the order of 10= 0 RAMs using the paper that you linked to. That is why synthesis tools don=E2=80=99t infer them: you=E2=80=99d give de= signers a lot of rope to hang themselves with a feature for which there is = no demand. Rick, After seeing the code author's response do you have any new idea? WengArticle: 161465
On Friday, September 27, 2019 at 9:21:02 PM UTC-4, Weng Tianxiang wrote: > On Friday, September 27, 2019 at 5:05:55 PM UTC-7, Rick C wrote: > > On Friday, September 27, 2019 at 7:25:33 PM UTC-4, Weng Tianxiang wrote= : > > > I download someone's key code from pastebin.com and copy it here for = easy discussion. He claims that the following code describes a 10-write and= 10-read memory module, but he admitted that a synthesizer does not run it = well. > > >=20 > > > architecture example of memtest is > > > ... > > > . shared variable memory : memory_t; -- !!! > > > begin > > > . . blks : for i in 0 to PORT_COUNT-1 generate > > > . . . memport : process(clocks(i)) > > > . . . begin > > > . . . . . if rising_edge(clocks(i)) then > > > . . . . . . . if stbs(i) =3D '1' then > > > . . . . . . . . . memory(addrs(i)) :=3D writes(i); > > > . . . . . . . end if; > > > . . . . . . . reads(i) <=3D memory(addrs(i)); > > > . . . . . end if; > > > . . . end process; > > > . . end generate; > > > end architecture; > > >=20 > > > Does it mean a 10-write and 10-read port memory module? > > >=20 > > > I really don't understand what the code means, and how synthesizer ex= ecutes it, and hope some experts explain it to me further. > > >=20 > > > As a fact, he says that "The fact that this probably wouldn't go so w= ell when you ran it comes down to the synthesizer not the language." That i= s absolutely not as good as you promised what you have describe it before: = the method to generate an n-write and m-read memory module is well establis= hed in HDL grammar. If a well defined code based on a grammar cannot run we= ll by a synthesizer, can I believe what you say? > > >=20 > > > If it is really a 10-port memory module, why a synthesizer does not d= o well? > > >=20 > > > Thank you. > > >=20 > > > Weng > >=20 > > Yes, it describes a single memory with N ports where N is defined by PO= RT_COUNT. What part of the code do you find confusing?=20 > >=20 > > There is no shortcoming in the language. This code describes the memor= y properly. If a synthesizer can't synthesize this code for 10 ports that = is a problem with the synthesizer, not the language. I'm willing to bet yo= u will have a hard time finding a library module for a 10 port memory. =20 > >=20 > > If you don't understand the language enough to know this code describes= an N port memory, you really are not in a position to tell the rest of us = how the language should be changed to accommodate your lack of understandin= g. =20 > >=20 > > --=20 > >=20 > > Rick C. > >=20 > > - Get 2,000 miles of free Supercharging > > - Tesla referral code - https://ts.la/richard11209 >=20 > Rick, > I think your conclusion is made too earlier. >=20 > Here is what the code author responses: >=20 > The synthesizer doesn=E2=80=99t do well because any additional port to a = memory makes it exponentially harder to implement. >=20 > You can implement a multi-memory in 3 ways: >=20 > real physical designed hard memory block. These are the dual-ported memor= ies of FPGAs >=20 > flip-flops or latch based arrays. These are very area inefficient. >=20 > weird architectures that use dual-ported memories to build memories with = a larger number of ports. That=E2=80=99s the paper that you linked too. It = is extremely area inefficient as well. >=20 > In practice. designers avoid multi-ported memories like the plague becaus= e they are very costly. It has nothing to do with language features. As sho= wn above: writing the RTL for a 10-ported memory is trivial. You don=E2=80= =99t need new keywords for it. >=20 > For example: a 10 ported read/write memory would require on the order of = 100 RAMs using the paper that you linked to. >=20 > That is why synthesis tools don=E2=80=99t infer them: you=E2=80=99d give = designers a lot of rope to hang themselves with a feature for which there i= s no demand. >=20 > Rick, > After seeing the code author's response do you have any new idea? I'm not clear on what your points are. I don't see anything in this post t= hat contradicts anything I've said. What did I say that you are addressing= ?=20 BTW, it is hard to follow the conversation when you keep starting new threa= ds on the same topic.=20 --=20 Rick C. + Get 2,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209Article: 161466
On 28/09/2019 00:25, Weng Tianxiang wrote: > I download someone's key code from pastebin.com and copy it here for easy discussion. He claims that the following code describes a 10-write and 10-read memory module, but he admitted that a synthesizer does not run it well. > > architecture example of memtest is > ... > . shared variable memory : memory_t; -- !!! > begin > . . blks : for i in 0 to PORT_COUNT-1 generate > . . . memport : process(clocks(i)) > . . . begin > . . . . . if rising_edge(clocks(i)) then > . . . . . . . if stbs(i) = '1' then > . . . . . . . . . memory(addrs(i)) := writes(i); > . . . . . . . end if; > . . . . . . . reads(i) <= memory(addrs(i)); > . . . . . end if; > . . . end process; > . . end generate; > end architecture; > > Does it mean a 10-write and 10-read port memory module? > > I really don't understand what the code means, and how synthesizer executes it, and hope some experts explain it to me further. > > As a fact, he says that "The fact that this probably wouldn't go so well when you ran it comes down to the synthesizer not the language." That is absolutely not as good as you promised what you have describe it before: the method to generate an n-write and m-read memory module is well established in HDL grammar. If a well defined code based on a grammar cannot run well by a synthesizer, can I believe what you say? > > If it is really a 10-port memory module, why a synthesizer does not do well? Because there are no suitable primitives for the synthesis tool to map to. This is not the say the synthesis vendor couldn't infer a decuple (had to look this up) port memory block using existing techniques like templates, attributes, synthesis directive etc but I suspect the number of configurations would be too large for very little return. As many others have told you adding a new keyword to the language will not make this any easier! I would be interested to find out what circuit needs a true decuple port memory block. Processor register files and network controllers require a large number of read/write ports but I am sure it is not as high as 10. Regards, Hans www.ht-lab.com > > Thank you. > > Weng >Article: 161467
On Saturday, September 28, 2019 at 1:24:26 AM UTC-7, HT-Lab wrote: > On 28/09/2019 00:25, Weng Tianxiang wrote: > > I download someone's key code from pastebin.com and copy it here for ea= sy discussion. He claims that the following code describes a 10-write and 1= 0-read memory module, but he admitted that a synthesizer does not run it we= ll. > >=20 > > architecture example of memtest is > > ... > > . shared variable memory : memory_t; -- !!! > > begin > > . . blks : for i in 0 to PORT_COUNT-1 generate > > . . . memport : process(clocks(i)) > > . . . begin > > . . . . . if rising_edge(clocks(i)) then > > . . . . . . . if stbs(i) =3D '1' then > > . . . . . . . . . memory(addrs(i)) :=3D writes(i); > > . . . . . . . end if; > > . . . . . . . reads(i) <=3D memory(addrs(i)); > > . . . . . end if; > > . . . end process; > > . . end generate; > > end architecture; > >=20 > > Does it mean a 10-write and 10-read port memory module? > >=20 > > I really don't understand what the code means, and how synthesizer exec= utes it, and hope some experts explain it to me further. > >=20 > > As a fact, he says that "The fact that this probably wouldn't go so wel= l when you ran it comes down to the synthesizer not the language." That is = absolutely not as good as you promised what you have describe it before: th= e method to generate an n-write and m-read memory module is well establishe= d in HDL grammar. If a well defined code based on a grammar cannot run well= by a synthesizer, can I believe what you say? > >=20 > > If it is really a 10-port memory module, why a synthesizer does not do = well? >=20 > Because there are no suitable primitives for the synthesis tool to map=20 > to. This is not the say the synthesis vendor couldn't infer a decuple=20 > (had to look this up) port memory block using existing techniques like=20 > templates, attributes, synthesis directive etc but I suspect the number= =20 > of configurations would be too large for very little return. >=20 > As many others have told you adding a new keyword to the language will=20 > not make this any easier! >=20 > I would be interested to find out what circuit needs a true decuple port= =20 > memory block. Processor register files and network controllers require a= =20 > large number of read/write ports but I am sure it is not as high as 10. >=20 > Regards, > Hans > www.ht-lab.com >=20 >=20 > >=20 > > Thank you. > >=20 > > Weng > > Hi Hans, I remember that you mentioned that you implemented a 8*8 port memory module= using technique based on paper "Efficient Multi-Ported Memories for FPGAs"= .=20 Can you disclose more details and your experiences about your implementatio= n? And what is the best technique to design a CPU register file in your opi= nion? In my project, I need multiple 2-write and 2 read port memory, true dual po= rt memory does not meet my requirement. I estimate that I need 4 RAM with e= ach having 1-write and 1-read port.=20 Even though my project is still in logic design stage and there is no probl= em for me to simulate the logic, based on current logic design: an array ca= n be read n times and written m times: when multiple writing to an array in= a process I guess a simulator would only write any data at the written add= ress once it meets an assignment statement that would guarantee the last wr= ite is valid if their writing addresses are same.=20 The technique based on the paper needs n*m RAM blocks if each RAM block has= one write and one read port. What role may a dual port memory block play? = =20 Thank you. WengArticle: 161468
On Saturday, September 28, 2019 at 10:02:42 AM UTC-4, Weng Tianxiang wrote: > On Saturday, September 28, 2019 at 1:24:26 AM UTC-7, HT-Lab wrote: > > On 28/09/2019 00:25, Weng Tianxiang wrote: > > > I download someone's key code from pastebin.com and copy it here for = easy discussion. He claims that the following code describes a 10-write and= 10-read memory module, but he admitted that a synthesizer does not run it = well. > > >=20 > > > architecture example of memtest is > > > ... > > > . shared variable memory : memory_t; -- !!! > > > begin > > > . . blks : for i in 0 to PORT_COUNT-1 generate > > > . . . memport : process(clocks(i)) > > > . . . begin > > > . . . . . if rising_edge(clocks(i)) then > > > . . . . . . . if stbs(i) =3D '1' then > > > . . . . . . . . . memory(addrs(i)) :=3D writes(i); > > > . . . . . . . end if; > > > . . . . . . . reads(i) <=3D memory(addrs(i)); > > > . . . . . end if; > > > . . . end process; > > > . . end generate; > > > end architecture; > > >=20 > > > Does it mean a 10-write and 10-read port memory module? > > >=20 > > > I really don't understand what the code means, and how synthesizer ex= ecutes it, and hope some experts explain it to me further. > > >=20 > > > As a fact, he says that "The fact that this probably wouldn't go so w= ell when you ran it comes down to the synthesizer not the language." That i= s absolutely not as good as you promised what you have describe it before: = the method to generate an n-write and m-read memory module is well establis= hed in HDL grammar. If a well defined code based on a grammar cannot run we= ll by a synthesizer, can I believe what you say? > > >=20 > > > If it is really a 10-port memory module, why a synthesizer does not d= o well? > >=20 > > Because there are no suitable primitives for the synthesis tool to map= =20 > > to. This is not the say the synthesis vendor couldn't infer a decuple= =20 > > (had to look this up) port memory block using existing techniques like= =20 > > templates, attributes, synthesis directive etc but I suspect the number= =20 > > of configurations would be too large for very little return. > >=20 > > As many others have told you adding a new keyword to the language will= =20 > > not make this any easier! > >=20 > > I would be interested to find out what circuit needs a true decuple por= t=20 > > memory block. Processor register files and network controllers require = a=20 > > large number of read/write ports but I am sure it is not as high as 10. > >=20 > > Regards, > > Hans > > www.ht-lab.com > >=20 > >=20 > > >=20 > > > Thank you. > > >=20 > > > Weng > > > >=20 > Hi Hans, >=20 > I remember that you mentioned that you implemented a 8*8 port memory modu= le using technique based on paper "Efficient Multi-Ported Memories for FPGA= s".=20 >=20 > Can you disclose more details and your experiences about your implementat= ion? And what is the best technique to design a CPU register file in your o= pinion? >=20 > In my project, I need multiple 2-write and 2 read port memory, true dual = port memory does not meet my requirement. I estimate that I need 4 RAM with= each having 1-write and 1-read port.=20 >=20 > Even though my project is still in logic design stage and there is no pro= blem for me to simulate the logic, based on current logic design: an array = can be read n times and written m times: when multiple writing to an array = in a process I guess a simulator would only write any data at the written a= ddress once it meets an assignment statement that would guarantee the last = write is valid if their writing addresses are same.=20 >=20 > The technique based on the paper needs n*m RAM blocks if each RAM block h= as one write and one read port. What role may a dual port memory block play= ? =20 You think too much in terms of the HDL you have written. There is no way f= or the HDL to know the two addresses are equal, so the first/last thing doe= sn't enter into the matter. That is also why the suggested code to infer a= multiple write port memory is with a shared variable and separate processe= s. =20 Remember that an HDL is a hardware description language. Exactly what hard= ware are you trying to describe? That is, how do you expect the tools to i= mplement your multiple write port memory? =20 The fact that your code simulated means nothing if the code can't be synthe= sized to working hardware.=20 --=20 Rick C. -- Get 2,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209Article: 161469
On 28/09/2019 15:02, Weng Tianxiang wrote: > On Saturday, September 28, 2019 at 1:24:26 AM UTC-7, HT-Lab wrote: >> On 28/09/2019 00:25, Weng Tianxiang wrote: .. >>> > > Hi Hans, > > I remember that you mentioned that you implemented a 8*8 port memory module using technique based on paper "Efficient Multi-Ported Memories for FPGAs". Hi Weng, I actually used the XOR variant (not multipumped) to implement a 4W8R port. You can find the paper here: http://fpgacpu.ca/multiport/FPGA2012-LaForest-XOR-Paper.pdf and more papers on the main page: http://fpgacpu.ca/multiport/ > > Can you disclose more details and your experiences about your implementation? And what is the best technique to design a CPU register file in your opinion? That all depends on your design. In my case I could use the XOR variant as I have a pipelined design were I could latch the register file's read request early on in the pipeline and then in a later stage XOR with the new results for the write request. The XOR is the most area efficient but was the most complicated to add to my design (due to data hazards and the fact that each write request also needs a read request). > > In my project, I need multiple 2-write and 2 read port memory, true dual port memory does not meet my requirement. I estimate that I need 4 RAM with each having 1-write and 1-read port. In that case forget about LaForest Et.al paper and simple use one of the core wizards like Intel's MegaWizard, Xilinx's Coregen etc. You get 2W2R area/speed optimised design with lots of configurable options. > > Even though my project is still in logic design stage and there is no problem for me to simulate the logic, based on current logic design: an array can be read n times and written m times: when multiple writing to an array in a process I guess a simulator would only write any data at the written address once it meets an assignment statement that would guarantee the last write is valid if their writing addresses are same. The core wizards gives you the option what should happen if you read/write to the same address. > > The technique based on the paper needs n*m RAM blocks if each RAM block has one write and one read port. What role may a dual port memory block play? Not sure what you are asking, you need DPRAM's as the basic building block for a a multi-port design. If you have the time I would suggest to implement the various versions and see how they behave, I learned a lot from it. Good luck, Hans www.ht-lab.com > > Thank you. > > Weng >Article: 161470
On Saturday, September 28, 2019 at 9:29:54 AM UTC-7, HT-Lab wrote: > On 28/09/2019 15:02, Weng Tianxiang wrote: > > On Saturday, September 28, 2019 at 1:24:26 AM UTC-7, HT-Lab wrote: > >> On 28/09/2019 00:25, Weng Tianxiang wrote: > .. > >>> > >=20 > > Hi Hans, > >=20 > > I remember that you mentioned that you implemented a 8*8 port memory mo= dule using technique based on paper "Efficient Multi-Ported Memories for FP= GAs". >=20 > Hi Weng, >=20 > I actually used the XOR variant (not multipumped) to implement a 4W8R=20 > port. You can find the paper here: >=20 > http://fpgacpu.ca/multiport/FPGA2012-LaForest-XOR-Paper.pdf >=20 > and more papers on the main page: >=20 > http://fpgacpu.ca/multiport/ >=20 > >=20 > > Can you disclose more details and your experiences about your implement= ation? And what is the best technique to design a CPU register file in your= opinion? >=20 > That all depends on your design. In my case I could use the XOR variant= =20 > as I have a pipelined design were I could latch the register file's read= =20 > request early on in the pipeline and then in a later stage XOR with the= =20 > new results for the write request. The XOR is the most area efficient=20 > but was the most complicated to add to my design (due to data hazards=20 > and the fact that each write request also needs a read request). >=20 > >=20 > > In my project, I need multiple 2-write and 2 read port memory, true dua= l port memory does not meet my requirement. I estimate that I need 4 RAM wi= th each having 1-write and 1-read port. >=20 > In that case forget about LaForest Et.al paper and simple use one of the= =20 > core wizards like Intel's MegaWizard, Xilinx's Coregen etc. You get 2W2R= =20 > area/speed optimised design with lots of configurable options. >=20 > >=20 > > Even though my project is still in logic design stage and there is no p= roblem for me to simulate the logic, based on current logic design: an arra= y can be read n times and written m times: when multiple writing to an arra= y in a process I guess a simulator would only write any data at the written= address once it meets an assignment statement that would guarantee the las= t write is valid if their writing addresses are same. >=20 > The core wizards gives you the option what should happen if you=20 > read/write to the same address. >=20 > >=20 > > The technique based on the paper needs n*m RAM blocks if each RAM block= has one write and one read port. What role may a dual port memory block pl= ay? >=20 > Not sure what you are asking, you need DPRAM's as the basic building=20 > block for a a multi-port design. If you have the time I would suggest to= =20 > implement the various versions and see how they behave, I learned a lot= =20 > from it. >=20 > Good luck, > Hans > www.ht-lab.com >=20 >=20 > >=20 > > Thank you. > >=20 > > Weng > > Hans, Thank you very much for your help and sharing your experience with me, and = 2 links are valuable. I will spend time reading those specifications and pa= pers carefully. Because VHDL has means to generate a n*m port code, so my if_2 idea is mean= ingless and dead. I am sorry for your times spent on those related posts.Of= cause I learned a lot. Also thank Rick and JK for your time. WengArticle: 161471
On 28/09/2019 21:27, Weng Tianxiang wrote: > On Saturday, September 28, 2019 at 9:29:54 AM UTC-7, HT-Lab wrote: >> On 28/09/2019 15:02, Weng Tianxiang wrote: >>> On Saturday, September 28, 2019 at 1:24:26 AM UTC-7, HT-Lab wrote: >>>> On 28/09/2019 00:25, Weng Tianxiang wrote: >> .. >>>>> >>> >>> Hi Hans, >>> >>> I remember that you mentioned that you implemented a 8*8 port memory module using technique based on paper "Efficient Multi-Ported Memories for FPGAs". >> >> Hi Weng, >> >> I actually used the XOR variant (not multipumped) to implement a 4W8R >> port. You can find the paper here: >> >> http://fpgacpu.ca/multiport/FPGA2012-LaForest-XOR-Paper.pdf >> >> and more papers on the main page: >> >> http://fpgacpu.ca/multiport/ >> >>> >>> Can you disclose more details and your experiences about your implementation? And what is the best technique to design a CPU register file in your opinion? >> >> That all depends on your design. In my case I could use the XOR variant >> as I have a pipelined design were I could latch the register file's read >> request early on in the pipeline and then in a later stage XOR with the >> new results for the write request. The XOR is the most area efficient >> but was the most complicated to add to my design (due to data hazards >> and the fact that each write request also needs a read request). >> >>> >>> In my project, I need multiple 2-write and 2 read port memory, true dual port memory does not meet my requirement. I estimate that I need 4 RAM with each having 1-write and 1-read port. >> >> In that case forget about LaForest Et.al paper and simple use one of the >> core wizards like Intel's MegaWizard, Xilinx's Coregen etc. You get 2W2R >> area/speed optimised design with lots of configurable options. >> >>> >>> Even though my project is still in logic design stage and there is no problem for me to simulate the logic, based on current logic design: an array can be read n times and written m times: when multiple writing to an array in a process I guess a simulator would only write any data at the written address once it meets an assignment statement that would guarantee the last write is valid if their writing addresses are same. >> >> The core wizards gives you the option what should happen if you >> read/write to the same address. >> >>> >>> The technique based on the paper needs n*m RAM blocks if each RAM block has one write and one read port. What role may a dual port memory block play? >> >> Not sure what you are asking, you need DPRAM's as the basic building >> block for a a multi-port design. If you have the time I would suggest to >> implement the various versions and see how they behave, I learned a lot >> from it. >> >> Good luck, >> Hans >> www.ht-lab.com >> >> >>> >>> Thank you. >>> >>> Weng >>> > > Hans, > Thank you very much for your help and sharing your experience with me, and 2 links are valuable. I will spend time reading those specifications and papers carefully. > > Because VHDL has means to generate a n*m port code, so my if_2 idea is meaningless and dead. I am sorry for your times spent on those related posts.Of cause I learned a lot. No need to apologise, how many of us can say we have 4(?) granted US patents. Please continue to share your ideas and questions. Regards, Hans. www.ht-lab.comArticle: 161472
On Sunday, September 29, > No need to apologise, how many of us can say we have 4(?) granted US > patents. Please continue to share your ideas and questions. > > Regards, > Hans. > www.ht-lab.com Hans, Thank you for your experience, help and encouragement. Your 4*8 memory module and a 4 computer system are a great achievement!!! WengArticle: 161473
Respected members, I'm a 3rd-year undergrad, majoring on Electronics & Communication Engineering at IIEST Shibpur, India. I have been experimenting on my Artix-7 Basys-3 board since my 2nd-semester and got very fascinated in the field of digital architecture designing. Since then, I have been involved in a number of projects related to this field. It is my request that if any opportunities are available in industry or research institutes, could you please inform me (p.s. I have been trying for a very long time, and have been very unsuccessful in acquiring one). my CV: https://drive.google.com/open?id=1F9hk3c7jbCoaoAc6QFn6ezJR3gotne8s I apologize if anyone is inconvenienced by this post as spam.Article: 161474
On 3/18/2019 6:13 PM, gnuarm.deletethisbit@gmail.com wrote: > Most of us have implemented small processors for logic operations that don't need to happen at high speed. Simple CPUs can be built into an FPGA using a very small footprint much like the ALU blocks. There are stack based processors that are very small, smaller than even a few kB of memory. > > If they were easily programmable in something other than C would anyone be interested? Or is a C compiler mandatory even for processors running very small programs? > > I am picturing this not terribly unlike the sequencer I used many years ago on an I/O board for an array processor which had it's own assembler. It was very simple and easy to use, but very much not a high level language. This would have a language that was high level, just not C rather something extensible and simple to use and potentially interactive. > > Rick C. > Where do find the memory for the program and data? On the FPGA, external or floating on a cloud? Oldben
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z