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Hi If you get any useful hints please forward them to us. We have a similar problem on Windows 95 platform. Thanks Krishna Mohan Aztech Systems Limited Singapore Eric Holmberg wrote: > > Is anybody out there using the LP6-MPU programmer under NT 4.0 (or any verision for that matter). I > installed the card and have tried all 16 :~( IO Addresses to no avail. The configuration menu > refuses to accept my hardware... HELP!!! > > A direct email of *anything* would be appreciated. > > Thanks, > > Eric <ohms@vt.edu>Article: 4751
Unlike EPROMs, very few GALs share the same algorithms and programming voltages. On top of that, the AMD device has 64 fewer bits in it than a normal 16V8, because it lacks the user electronic signature, so your programmer may be rejecting it simply because of the block size mismatch. But I suspect it goes deeper. GAL programmers are supposed to get the device electronic signature and only program those devices which they **explicitly** support. Often, this is not the case, and you can get nearly-blown devices. However, with a decent programmer you will find it correctly rejecting e.g. a particular 16V8-10 when it does the same make's 16V8-15 - because the algorithm and/or the voltages are different. And you can never find out the details because the algorithms are secret and are disclosed to you only after an NDA and a lot of hassle, pretending to be a PLD programmer mfg. This makes it easy for PLD programmer vendors to wash their hands of algorithm bugs simply by claiming the algorithm has been changed since you bought it! I have had a lot of this. >I have been programming SGS GALS 16V8 for a long time using my old GAL >STARTER KIT. Now I need programming a PALCE16V8 from AMD but it refuses. >Does anybody know why? >Many thanx. >Francesco Iovine >fj@iol.it > Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 4752
Every day, we at Quote-A-Day e-mail an interesting quote to people on the Internet. The quotes are inspirational, witty and insightful. We don’t charge for this service and we hope you’ll want to be a part of it. If you would like to join our mailing, send e-mail to Subscribe2@Juno.com And put your name in the body of the message. Later, if you like, you can stop receiving this mailing by sending e-mail to Unsubscribe2@Juno.com (kjumsv)Article: 4753
scs@m4com.demon.co.uk (Steve Sutherland) wrote: >I would like to use a serial EEPROM to configure a XILINX fpga. ( >Master Serial Mode ), so I can have the possibility of re-writing the >configuration data in the field. > Has anyone had any success finding/using a compatible serial eeprom >? We have successfuly used this technique for 5 yearr in production. We use ONLY the XIlinx serial ROM. I think their latest offerings are EEPROM. AT&T offers a supposedly compatible device, but I donlt reccomend it. We have had some problems wityh their serial roms. They sometimes don;t respond properly on power up. Thus, your FPGA doesn;t get properly loaded. Not good!Article: 4754
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Advance Program
1997 ACM/SIGDA Fifth International Symposium on
Field-Programmable Gate Arrays (FPGA'97)
Sponsored by ACM SIGDA, with support from Altera, Xilinx, and Actel
Monterey Beach Hotel, Monterey, California
February 9-11, 1997
(Web page: http://www.ece.nwu.edu/~hauck/fpga97)
------------------------------------------------------------------------------
Welcome to the 1997 ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays (FPGA'97). This annual symposium is the premier forum for
presentation of advances in all areas related to FPGA technology, and
also provides a relaxed atmosphere for exchanging ideas and stimulating
discussions for future research and development in this exciting new field.
This year's symposium sees a strong increase of interest in FPGA
technology, with over 20% increase in paper submissions. The technical
program consists of 20 regular papers, 35 poster papers, an evening panel,
and an invited session. The technical papers present the latest results
on advances in FPGA architectures, new CAD algorithms and tools for FPGA
designs, and novel applications of FPGAs. The Monday evening panel
will debate whether reconfigurable computing is commercially viable.
The invited session on Tuesday morning addresses the challenges for
architecture development, CAD tools, and circuit design of
one million-gate FPGAs and beyond.
We hope that you find the symposium informative, stimulating, and enjoyable.
Carl Ebeling, General Chair
Jason Cong, Technical Program Chair
------------------------------------------------------------------------------
SYMPOSIUM PROGRAM
Sunday February 9, 1997
6:00pm Registration
7:00pm Welcoming Reception,
Monterey Beach Hotel, Monterey
Monday February 10, 1997
7:30am Continental Breakfast/Registration
8:20am Welcome and Opening Remarks
Session 1: FPGA Architectures
Session Chair: Rob Rutenbar, Carnegie Mellon Univ.
Time: 8:30 - 9:30am
1.1 "Architecture Issues and Solutions for a High-Capacity FPGA",
S. Trimberger, K. Duong, B. Conn, Xilinx, Inc.
1.2 "Memory-to-Memory Connection Structures in FPGAs with Embedded Memory
Arrays",
Steven J.E. Wilton, J. Rose, Z.G. Vranesic, University of Toronto
1.3 "Laser Correcting Defects to Create Transparent Routing for Large Area
FPGAs",
G.H. Chapman, B. Bufort, Simon Fraser University
Poster Session 1: Analysis and Design of New FPGA Architectures
Session Chair: Tim Southgate, Altera, Inc.
Time: 9:30 - 10:30am (including coffee break)
Session 2: FPGA Partitioning and Synthesis
Session Chair: Richard Rudell, Synopsys, Inc.
Time: 10:30 - 11:30am
2.1 "I/O and Performance Tradeoffs with the FunctionBus during Multi-FPGA
Partitioning",
F. Vahid, University of California, Riverside
2.2 "Partially-Dependent Functional Decomposition with Applications in FPGA
Synthesis and Mapping",
J. Cong, Y. Hwang, Univ. of California, Los Angeles
2.3 "General Modeling and Technology-Mapping Technique for LUT-based FPGAs",
A. Chowdhary, J.P. Hayes, University of Michigan
Poster Session 2: Logic Optimization for FPGAs
Session Chair: Martine Schlag, Univ. of California, Santa Cruz
Time: 11:30 - 12noon
Lunch: noon - 1:30pm
Session 3: Rapid Prototyping and Emulation
Session Chair: Carl Ebeling, Univ. of Washington
Time: 1:30 - 2:30pm
3.1 "The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System",
D.M. Lewis, D.R. Galloway, M. V. Ierssel, J. Rose, P. Chow,
University of Toronto
3.2 "Signal Processing at 250 MHz using High-Performance Pipelined FPGA's",
Brian Von Herzen, Rapid Prototypes, Inc.
3.3 "Module Generation of Complex Macros for Logic-Emulation Applications",
Wen-Jong Fang, Allen C.H. Wu, Duan-Ping Chen, Tsinghua University
Poster Session 3: Novel FPGA Applications
Session Chair: Brad Hutchings, Brigham Young Univ.
Time: 2:30 - 3:30pm (including coffee break)
Session 4: Reconfigurable Computing
Session Chair: Jonathan Rose, Univ. of Toronto
Time: 3:30 - 4:30pm
4.1 "Wormhole Run-time Reconfiguration",
R. Bittner, P. Athanas, Virginia Polytechnic Institute
4.2 "Improving Computational Efficiency Through Run-Time Constant
Propagation",
M.J. Wirthlin, B.L. Hutchings, Brigham Young University
4.3 "YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data
Processing",
A. Tsutsui, T. Miyazaki, NTT Optical Network System Lab.
Poster Session 4: Reconfigurable Systems
Session Chair: Scott Hauck, Northwestern Univ.
Time: 4:30 - 5:30pm
Dinner: 6:00 - 7:30pm
Evening Panel: Is reconfigurable computing commercially viable?
Moderator: Herman Schmit, Carnegie Mellon Univ.
Time: 7:30 - 9:00pm
Panelists:
Steve Casselman: President, Virtual Computer Corp.
Daryl Eigen: President, Metalithic Systems, Inc.
Robert Parker: Deputy Director, ITO, DARPA
Peter Athanas: Assistant Professor, Virginia Polytechnic Institute
Robert Colwell: Pentium Pro Architecture Manager, Intel Corp.
In this panel session, we will try to address the questions of whether
there will be a mass-market for FPGA-based computing solutions. Are
there large sets of applications whose performance requirements far
exceed that offered by microprocessors but which are only
occasionally executed? Where are these applications? Does the
ability to reconfigure during execution change the cost and
performance benefits of reconfigurable hardware significantly? What
are the key challenges to making reconfigurable computing a reality,
and what can PLD manufacturers, system houses, government, and
academia do to overcome these obstacles?
Session 5: FPGA Floorplanning and Routing
Session Chair: Dwight Hill, Synopsys, Inc.
Time: 8:30 - 9:30am
5.1 "Synthesis and Floorplanning for Large Hierarchical FPGAs",
H. Krupnova, C. Rabedaoro, G. Saucier, Institut National Polytechnique de
Grenoble/CSI
5.2 "Performance Driven Floorplanning for FPGA Based Designs",
J. Shi, Dinesh Bhatia, University of Cincinnati
5.3 "FPGA Routing and Routability Estimation Via Boolean Satisfiability",
R.G. Wood, R.A. Rutenbar, Carnegie Mellon University
Poster Session 5: High level Synthesis and Module Generation for FPGAs
Session Chair: Martin Wong, Univ. of Texas at Austin
Time: 9:30 - 10:30am (including coffee break)
Session 6 (Invited): Challenges for 1 Million-Gate FPGAs and Beyond
Session Chair: Jason Cong, Univ. of California, Los Angeles
Time: 10:30am - noon
Process technology advances tell us that the one million gate FPGA will soon
be here, and larger devices shortly after that. Current architectures
will not extend easily to this scale because of process characteristics and
because new opportunities are presented by the increase in available
transistors. In addition, such large FPGAs will also present significant
challenges to the computer-aided design tools and methods.
Two invited papers address these issues.
6.1 "Architectural and Physical Design Challenges for One Million Gate FPGAs
and Beyond",
Jonathan Rose, University of Toronto, Dwight Hill, Synopsys, Inc.
6.2. "Challenges in CAD for the One Million-Plus Gate FPGA",
Kurt Keutzer, Synopsys, Inc.
Lunch: noon - 1:30pm
Session 7: Studies of New FPGA Architectures
Session Chair: Steve Trimberger, Xilinx, Inc.
Time: 1:30 - 2:30pm
7.1 "A CMOS Continuous-time Field Programmable Analog Array",
C.A. Looby, C. Lyden, National Microelectronics Research Center
7.2 "Combinational Logic on Dynamically Reconfigurable FPGAs",
D. Chang, M. Marek-Sadowska, Univ. of California, Santa Barbara
7.3 "Generation of Synthetic Sequential Benchmark Circuit",
M. Hutton, J. Rose, D. Corneil, University of Toronto
Poster Session 6: FPGA Testing
Session Chair: Sinan Kaptanoglu, Actel, Inc.
Time: 2:30 - 3:30pm (including coffee break)
Session 8: Novel Design and Applications
Session Chair: Pak Chan, Univ. of California, Santa Cruz
Time: 3:30 - 4:10pm
8.1 "Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency
Independent of Counter Size",
A.F. Tenca, M. D. Ercegovac, Univ. of California, Los Angeles
8.2 "A FPGA-based Implementation of a Fault Tolerant Neural Architecture for
Photon Identification"
M. Alderight, E.L. Gummati, V. Piuri, G.R. Sechi, Consiglio Nazionale delle
Ricerche, Universita degli Studi di Milano, Politecnico di Milano
4:30pm Symposium Ends.
-------------------------------------------------------------------------------
Organizing Committee:
General Chair: Carl Ebeling, University of Washington
Program Chair: Jason Cong, UCLA
Publicity Chair: Scott Hauck, Northwestern University
Finance Chair: Jonathan Rose, University of Toronto
Local Chair: Pak Chan, UC Santa Cruz
Program Committee:
Michael Butts, Quickturn Pak Chan, UCSC
Jason Cong, UCLA Carl Ebeling, U. Washington
Masahiro Fujita, Fujitsu Labs Scott Hauck, Northwestern Univ.
Dwight Hill, Synopsys Brad Hutchings, BYU
Sinan Kaptanoglu, Actel David Lewis, U. Toronto
Jonathan Rose, U. Toronto Richard Rudell, Synopsys
Rob Rutenbar, CMU Gabriele Saucier, Imag
Martine Schlag, UCSC Tim Southgate, Altera
Steve Trimberger, Xilinx Martin Wong, UT Austin
Nam-Sung Woo, Lucent Technologies
-------------------------------------------------------------------------------
Hotel Information
FPGA'97 will be held at the Monterey Beach Hotel, 2600 Sand Dunes Dr.,
Monterey, CA 93940 USA. The phone number for room reservations is
1-800-242-8627 (from USA or Canada) or +1-408-394-3321 (fax: +1-408-393-1912).
Reservations must be made before January 10, 1997. Identify yourself with
the group: ACM/FPGA'97 to receive the special rates of US$75 single/double
for Gardenside and US$105 single/double for Oceanside (additional person
in the room is $10), plus applicable state and local taxes.
Reservations may be canceled or modified up to 72 hours prior to arrival
without a penalty. If the cancellation is made within 72 hours of arrival,
or you fail to show up, first nights room and tax will be charged. If a
modification is made within 72 hours of arrival (i.e., postpones arrival or
departs earlier than reserved) the actual nights of your stay will be charged
at the quoted rack rate for the room occupied.
Check-in time is 4:00 pm, and check-out time is 12:00 noon.
Directions by car: From San Jose (1.5 hours) or San Francisco Airport (2.5
hours) take Hwy 101 South to Hwy 156 West to Hwy 1 South. From Hwy 1 South,
take Seaside/Del Rey Oaks exit. The hotel is at this exit on the ocean side.
You can also fly directly to Monterey Airport, which is served by United,
American and other airlines with at least 8 flights per day.
Monterey Area
The Monterey Peninsula is famous for its many attractions and recreational
activities, such as John Steinbeck's famous Cannery Row and the Monterey Bay
Aquarium. Also, play one of 19 championship golf courses. Charter fishing
is available right at Firsherman's Wharf. Monterey is renowned worldwide for
its spectacular coastline, including Big Sur and the Seventeen Mile Drive.
Recreational activities, shopping opportunities and restaurants abound.
-------------------------------------------------------------------------------
Registration Information:
The Symposium registration fee includes a copy of the symposium proceedings,
a reception on Sunday evening, February 9, coffee breaks, lunch on both days,
and dinner on Monday evening, February 10.
First Name:_____________________Last Name:_________________________________
Title/Job Function:________________________________________________________
Company/Institution:_______________________________________________________
Address:___________________________________________________________________
City:___________________________State:_____________________________________
Postal Code:____________________Country:___________________________________
E-mail:_________________________ACM Member #:______________________________
Phone:__________________________Fax:_______________________________________
Circle Fee Before January 22, 1997 After January 22, 1997
ACM/SIGDA Member US$300 US$370
*Non-Member US$400 US$470
Student US$ 90 (does not include reception or banquet,
available for US$15 and US$55 respectively)
Guest Reception Tickets: # Tickets _____x US$15 = ______
Guest Banquet Tickets: # Tickets _____x US$55 = _______
Total Fees: _________________ (Make checks payable to ACM/FPGA'97)
Payment included (circle one): American Express MasterCard Visa Check
Credit Card # :_______________________ Expiration Date:________
Signature:______________________________________________________
Send Registration, including payment in full, to:
FPGA'97, Meeting Hall, Inc.,
571 Dunbar Hill Rd.,
Hamden, CT 06514 USA
Phone/fax: +1 203 287 9555
For registration information contact Debbie Hall via e-mail at
halldeb@aol.com. Cancellations must be in writing and received
by Meeting Hall, Inc. before January 22, 1997.
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
| Scott A. Hauck, Assistant Professor |
| Dept. of ECE Voice: (847) 467-1849 |
| Northwestern University FAX: (847) 467-4144 |
| 2145 Sheridan Road Email: hauck@ece.nwu.edu |
| Evanston, IL 60208 WWW: http://www.ece.nwu.edu/~hauck |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
Article: 4755In article <58mdps$6if$1@newshost.cyberramp.net>, timolmst@cyberramp.net wrote: We > use ONLY the XIlinx serial ROM. I think their latest offerings are > EEPROM. AT&T offers a supposedly compatible device, but I donlt > reccomend it. Let me clarify this issue: Xilinx serial PROMs offer the most reliable start-up on power-on, and they have a well-documented and supported way to adjust the RESET polarity, but the present Xilinx SPROMs are NOT electrically re-programmable. The present Xilinx devices use EPROM technolgy in a plastic package. Therefore there is no way to erase them. Xilinx suggests to use the download cable while debugging the configuration. We are well aware of the fact that some users prefer an electrically erasable SPROM, and I have often referrred users to the two manufacturers, AT&T and Atmel, offering EEPROM-based SPROMs that, at least superficially, are compatible with the Xilinx devices. There is plenty of anecdotal evidence that the AT&T devices have a different power-up characteristic, and many users have reported difficulties with unreliable start-up, a problem they NEVER encountered with Xilinx SPROMs. Be forewarned, or "caveat emptor". Atmel devices suffered from confusing documentation of the RESET polarity programming. Allegedly, this has been straightened out, but I have heared the "All Clear" signal once too often from the Atmel camp. If you have a problem with the Atmel devices, it will only be with the reset polarity. You may also want to stay away from 10 MHz CCLK rates that are supported by the XC4000 devices, but not by Atmel SPROMs. SPROMs are a tiny but crucial part of an FPGA-based design. The user deserves the best technology, features, and reliability. And the most honest information and support. I refuse to let marketing poison out of any camp confuse this issue. Peter Alfke, Xilinx ApplicationsArticle: 4756
x-no-archive: yes
I'm looking for VHDL examples on how to describe simple, synthesizable
multiply-accumulate functions for DSP applications. If anyone know of
such examples, please e-mail me the info. to danielrob@hotmail.com.
Thank-you,
--Dan
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 4757In article <850227870.10591.0@m4com.demon.co.uk>, scs@m4com.demon.co.uk says... > >I would like to use a serial EEPROM to configure a XILINX fpga. ( >Master Serial Mode ), so I can have the possibility of re-writing the >configuration data in the field. > > Has anyone had any success finding/using a compatible serial eeprom >? > >Any comments/suggestions welcome! > > >Steve Sutherland > >M4COM Ltd. >QED center >Treforest Est. >CF37 5YR >UK >scs@m4com.demon.co.uk > > Try contacting Micro Call Ltd - Thame (UK) they are fairly hot on XILINX stuff (& XICOR serial EE & compatible devices) Incidentally were you working in the Tewkesbury area around 1984 ish?Article: 4758
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Article: 4759this is only a test, john do you see this.Article: 4760
Atmel makes a line of serial EEPROMs that are pin-for-pin compatible with the Xilinx OTP parts. They can also be reprogrammed in-system, Atmel tech support can give you info on doing this. I've been using AT17C128's in some prototype designs; someone at my workplace mentioned that they'd seen some discussions in comp.arch.fpga regarding the reliability of the Atmel parts - I'm not sure whether they were referring to the number of programming cycles the devices can withstand or how long the EEPROM device retains its contents or perhaps something else-- but since I've missed that discussion I figured this would be a good time to stir it back up -- I wouldn't want to recommend a part that I haven't fully evaluated yet... They also mentioned that (I think) early AT17Cxxx parts may have had some kind of bug early on, but I think it had been fixed-- does anybody know more about this?? scs@m4com.demon.co.uk (Steve Sutherland) wrote: >I would like to use a serial EEPROM to configure a XILINX fpga. ( >Master Serial Mode ), so I can have the possibility of re-writing the >configuration data in the field. > > Has anyone had any success finding/using a compatible serial eeprom >? > >Any comments/suggestions welcome! > > >Steve Sutherland > >M4COM Ltd. >QED center >Treforest Est. >CF37 5YR >UK >scs@m4com.demon.co.uk > >Article: 4761
Kayvon Irani (kirani@cinenet.net) wrote: >Hi everyone: > Just wondering if anyone out there has first hand experience or cares to comment > on the use of ASICs and FPGAs in safety critical applications such as in > passanger airplanes. Are the FPGAs more prone to failure by their virtue of > being "programmable" and because they have unused dangling gates on the silicon? > Any one used any particular FPGAs on FAA certified equipment? > > Regards, > Kayvon Irani > Los Angeles, ca -- staff@acqsys.comArticle: 4762
I would like to know if there are any EERPOMS for replacement of Altera EPC1 and EPC1064. From some sketchy data, it looks like one can use the Atmel AT17C64 in place of the EPC1064. Any ideas? Thanks ----------------------------------------------------------------------------- Charles Stevens c.stevens@ieee.org => cstevens@iafrica.com Box 782094 Sandton. Tel/Fax: (+2711) 468 2311 South Africa, 2146. Cell: 083 255 4906Article: 4763
This is a multi-part message in MEME format. As computer architectures converge on the brain-mind architecture it is imperative to consider theories of the target architecture: /^^^^^^^^^^^\ Machine Perception Architecture /^^^^^^^^^^^\ /visual memory\ ________ semantic / auditory \ | /--------|-------\ / syntax \ memory |episodic memory| | | recog-|nition | \________/<-----------|-------------\ | | ___|___ | | |flush-vector | _______ | | | /image \ | ___V____V___ word-fetch | /stored \ | | | / percept \<--|-->/ conceptual \--------------|->/ phonemes\| | | \ engrams / | \ mini-grids / for thinking | \ of words/ | | \_______/ | \__________/ in language | \_______/ | http://www.newciv.org/Mentifex/ run periodic Mentifex Web search. http://www.complex.com.pl/~venom/science.html a waystation of AI.Article: 4764
Has anyone seen a FPGA implementation of an FFT? Thanks, -David davidb@visionics.comArticle: 4765
In article <32AC3050.4AD@wago.de>, symon.brewer@wago.de wrote: > Dear All, > I am configuring a XC4010E-4PQ160 in slave serial mode. etc This is strange behavior. What you describe should work. When you say "the first few bytes appear at the DOUT output", how many do appear? It should be the first 5 bytes, the header. After that, DOUT goes High, indicating that the bits being received are for this chip. DOUT only becomes active after the first chip in a daisy-chain has been filled completely. Can you capture the leading bits coming out of DOUT, and are they the same bits that you fed into DIN? Have you looked a the duty cycle and the rise and fall times of CCLK ? Anything strange, like glitches or "hick-ups" ? Peter Alfke, Xilinx ApplicationsArticle: 4766
In article <32AC67BB.18C2@esiee.fr>, Raphael BELLEC <bellecr@esiee.fr> wrote: > Dear everyone. > But I would like to know "in use" what is the real difference you can > make between an FPGA and a high density epld? EPLDs and CPLDs are derived from the PAL architecture and thus have an AND-OR logic structure ( with most of the programmability in the AND array ) feeding a flip-flop macrocell. That means less logic flexibility, but predictable delays, fewer flip-flops, but faster compile times than for FPGAs. Also, the technology used tends to have substantial static power consumption. FPGAs have a more flexible, finer-grained gate-array-like structure with a hierarchical interconnect structure. They have more flip-flops, but less predictable routing delays. Most use SRAM technology, and thus are dynamically reconfigurable, but some use antifuses, which make them One-Time-Programmable. The technology is static digital CMOS with almost zero static power consumption. Altera confuses the issue by calling their SRAM-based FPGA-like families "CPLDs" for peculiar, non-technical reasons. Peter Alfke, Xilinx ApplicationsArticle: 4767
David Badzinski wrote: > > Has anyone seen a FPGA implementation of an FFT? > > Thanks, > > -David > > davidb@visionics.com I've seen a couple papers on the subject. One was presented at SPIE's photonics east conference on reconfigurable computing. Another using CORDIC techniques was presented at FCCM '96. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 4768
Martin d'Anjou wrote: > ... > So I guess they don't fear putting them in critical apps... Is a black-box a critical application? I would consider the aircraft-control- apparatus a critical application, not the black-box that only records data. --Article: 4769
We tend to use antifuse parts (Actel) which are OTP rather than SRAM based parts. I'm fairly sure we would not be allowed to use SRAM parts in "flight-critical" applications. -- The opinions expressed are mine and do not necessarily reflect those of my employer. Alasdair Maclean, Development Engineer GEC Marconi Radar and Defence Systems, GNET: 709-5711; Tel: +44 (0)131-343-5711 Fax: +44 (0)131-343-5050 Email: <mailto:alasdair.maclean@gecm.com>Article: 4770
I have seen past requests on the NG for an inexpensive FPGA development system for XILINX parts. Some wishing to try XILINX have beenprevented to the high cost of the fitter router. Well now APS is shipping the full up FOUNDATION tools with the APS-X84 FPGA development board and a 5202 FPGA. As described below the entire kit sells for $359.00!! The anouncment is below APS has the APS-X84DK FPGA development kit which contains an IBM PC ISA FPGA TEST BOARD with a 5202 and XILINX VHDL compiler, schematic entry software, and ROUTING software. It also contains C code programs for the ISA board with VHDL examples. The VHDL compiler is part of the XILINX foundation software which is sent with the kit. It is limited to 250 designs, but other than that is fully functional. The whole kit is only $359.00 aaps@erols.com http://www.erols.com/aapsArticle: 4771
Alternatively, you can also have a look at Cypress ISR (In System Reprogrammable) devices. The VHDL Compiler Warp (which is pretty impressive!) can be purchased for a mere 32 pounds. To program these devices you have to buy a 62 pounds download cable which plugs into your parallel port. You can also program them with a microcontroller. Hans. http://www.cypress.com:80/cypress/prodgate/tool/cy3120.html In article <01bbe8e8$5dd7c8a0$31bea1ce@rick>, aaps@erols.com says... > >I have seen past requests on the NG for an inexpensive FPGA development >system for XILINX parts. Some wishing to try XILINX have beenprevented to >the high cost of the fitter router. Well now APS is shipping the full up >FOUNDATION tools with the APS-X84 FPGA development board and a 5202 FPGA. >As described below the entire kit sells for $359.00!! The anouncment is >below >Article: 4772
In article <58r4uo$94f@gcsin3.geccs.gecm.com>, Alasdair MacLean <alasdair.maclean@gecm.com> writes: |> |> We tend to use antifuse parts (Actel) which are OTP rather |> than SRAM based parts. I'm fairly sure we would not be allowed |> to use SRAM parts in "flight-critical" applications. |> |> -- |> The opinions expressed are mine and do not necessarily reflect |> those of my employer. |> |> Alasdair Maclean, Development Engineer |> GEC Marconi Radar and Defence Systems, |> GNET: 709-5711; Tel: +44 (0)131-343-5711 |> Fax: +44 (0)131-343-5050 |> Email: <mailto:alasdair.maclean@gecm.com> |> |> Keep in mind that I have no experience in the arena of 'flight critical' systems, FPGAs, and the ugly secrets of ASIC vendors. 'flight-critical' components are required to have detailed fault models used to evaluate the systems ability to 'operate' in the presents of faults. The system can be built of any kind of components, however, the system fault model is more accurate if it's component parts have accurate fault models. If the components are bult from Gate Array, Standard Cell, or Full Custom, parts the 'composition' of those parts can be readily determined and fault models created. That is the ASIC layout and macro cell function is know. These parts are also manufactured from the same masks for the life of the product so they don't change .... much. If the components are built from FPGAs, there is a significant portion of there composition that will be considered proprietary, and you will be required to sign lots-o-stuff, if you can even get that far. Also FPGAs are 'standard products', meaning they go through life cycles that are out of your control. The parts may be changed in significant ways in terms of the fault model. They may discontinue the part long before you are ready, which came happen with ASICs, but the last time buy should be much cheaper than if you had to buy several hundred thousand FPGAs. JohnArticle: 4773
cstevens@iafrica.com (Charles Stevens) wrote: >I would like to know if there are any EERPOMS for replacement of Altera >EPC1 and EPC1064. >From some sketchy data, it looks like one can use the Atmel AT17C64 in >place of the EPC1064. >Any ideas? >Thanks > I use an Atmel AT17C128 to config an EPF8820 instead of the Altera EPC1 or EPC1213. They are (IMHO) excellent. I recommend the Equinox Technologies (address below) MicroPro programmer to program them. It costs £125. The software for the AT17C series is still in beta but I can assure you it works fine. Try: www.demon.co.uk/equintec/ sales@equintec.demon.co.uk These my be out of date, Email me direct if they don't work. Cheers JulianArticle: 4774
I thought it might be of interest to some -- there is a tenure track computer engineering position currently being advertised for the Padnos School of Engineering at Grand Valley State University. You can find the advertisement in the December IEEE Spectrum, and also in a recent ASEE Prism. This will be of particular interest to those interested in practical teaching and research. If you want send me the information requested in the advert. by email I will forward it to the appropriate committee. hugh p.s. You can find out more about GVSU engineering at, http://www.engineer.gvsu.edu
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