Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, Can anyone tell me what the difference is between a course-grain netlist and a fine-grain netlist. eg what is a fine/course grain? What effect does synthesis, optimization have on this, and how can this effect the design process? Thanks, Phil.Article: 4601
Be a Beta Tester! http://www.trenet.com/btrArticle: 4602
In article <3291FDAB.611D@pa.msu.edu> Steve Gross <gross@pa.msu.edu> writes:
>I have a couple of questions about configuring a Xilinx XC4000-series
The rest of Steve's article is at the end of this message.
Steve, the problem you are having is that the done pin going high is
not the last thing that needs to happen before the chip is ready to
run. On page 2-30 of the 1994 data book (4-63 of the 1996 one) are the
diagrams that reveal the secrets (well some of them) as to why you
need to give the chip some extra clocks. As you can see, there is a 5
state shift register state machine that sequences the chip after an
internal signal (Full) goes high, together with a signal called
Length Count going high (This is the output of the length count
comparator that is checking the length count that was at the beginning
of the bitstream. on the far right there is an internal signal called
'finished' that is the real end of things. This state machine is advanced
by configuration clocks, and in the Asynchrous Peripheral Mode, this is
generated internaly, whenever you give the chip another byte of data.
If the length count is met, then the state machine starts up, and DONE
goes high at time C1 (from Q0), see page 2-29 / 4-61. Here's where things
are going wrong for you: If this happens near the end of shifting a
byte that you have loaded via Asynchrous Peripheral Mode, then the
remaining clocks needed to release I/O and the GSR don't happen because
there are no more data bits to be shifted. Loading the extra byte (I
usuall use an FF byte) gives the logic 8 extra clocks, which will be
enough to cycle the state machine to the finished state.
All the best
Philip Freidin
>device via Asynchrous Peripheral Mode. I have a design in which
>I configure an XC4013L in Asynch. Peripheral Mode over VME. The
>download appears to work (in the sense that ERR* never goes low, and
>DONE goes high at the appropriate time), but I am having a spot of
>confusion regarding the actual startup. Details:
>
>I am using NeoCAD (err...Xilinx) FPGA Foundry to create Motorola
>Exormacs format (S-Record) data which is read by a VME single-board
>computer which in turn writes the bitstream to the XC4013L device
>(which is located on a separate card, reachable from the SBC via VME).
>This data is 30995 bytes (247960 bits) long, which exactly matches
>the "PROM size" required for this device ('96 data book table 22,
>page 4-57). I write the data to the device using 30995 writes,
>checking RDY/BUSY* and ERR/INIT* as necessary. After the 30995th
>write, DONE goes high as expected, but the newly-configured device
>does not actually complete startup (all I/O pins are still 3-stated,
>I am using the "default" startup order, activate DONE first, then
>release internal GTS, then release internal GSR). I need to write
>one more byte of data to the device (a 30996th byte, it doesn't seem
>to matter what the byte contents are) to get the I/O's to activate.
>
>I wanted to understand why I needed this 30996th write (which didn't
>really make sense to me), so I started digging. The only funny
>thing I could find was that the "length count" field generated
>by NeoCAD (umm...Xilinx) bitgen, and placed in the bitstream,
>was NOT 247960 (as I had naively expected) but was actually 247958.
>Does this make sense? What does Xilinx MakeBits put in as a length
>count for a single 4013 device? Is this a known bitgen bug?
>
>One more thing. This 247958 value DOES work for a different 4013L
>(on the same board) which configures itself in Master Serial Mode,
>reading out of an XC17256 SPROM.
>
>Thanks in advance for any possible tips. Peter, do you have any
>insight?
>
>-Steve Gross gross@pa.msu.edu
Article: 4603In article <32915B1F.3D2D@icd.com.au> pnibbs@icd.com.au "P Nibbs" writes: "Hi, " "I have just started investigating designing using fpga's, cplds etc and "was wondering if there are any advantages at all in purchasing third "party software (ie viewlogic, mentor, cadence, veribest etc). " <snip> You will have to purchase the back-end place-and -route tool from the vendor(s) you wish to use; there is no longer any vendor- independent source of these tools since Xilinx bought NeoCAD. The disadvantage of using the vendor's own front-end toolset is that while they may work well for that vendor, they will encourage you to use proprietary libraries, which will mean that you cannot then migrate to another vendor, or compare implementation results with another vendor. The third-party tools will be more expensive, but offer the potential of vendor-independent design via standards such as LPM (Library of Parameterized Macros) and the use of HDLs. David PashleyArticle: 4604
timolmst@cyberramp.net wrote: >>As I understand it, I must use their tools (Max+Plus and XACT) to place >>and route, obtain timing etc). These tools seem to come with schematic >>capture, vhdl simulators, synthesis engines etc (a complete design >>environment?). >Xilinx tools don't COME WITH anything! You pay for all of it, >cafeteria style. The basic XACT system is just the "back-end" place >and route stuff. You have to buy your fornt-end design entry tool >seperate, at additional cost. With regard to VHDL synthesis: not all synthesizers are equally good at their job. In Altera's case I know of some restrictions regarding the synthesizable subset e.g. an assignment like "A <= (others => 'Z');" would synthesize with Synopsys but not with Altera. Also there may be differences with regard to area and speed of the synthesized design, but I didn't evaluate these tools thoroughly enough to make a statement about that. -StefanArticle: 4605
We are a small networking company looking for four designers for the design of an ASIC using VHDL and for design verification. The following qualifications are required: - Previous ASIC experience - VHDL - Synopsys synthesis - Design verification There are possibilities for permanent employment or as a consultant. PRINCIPALS ONLY! Fax your resume to (617)527-1325 or email to arnaud@ecla.comArticle: 4606
Hi, does anyone happen to know if PRO series is compatable with windows 95 ? I am running Procapture from the Xilinx PROflow task launcher and as soon as I select add component the system crashes. If you have managed to get PRO series working with win95 could you get in touch, please ? -- Gordon McGregor --------------------------------------------------------------------- Communications Division Email: g.mcgregor@eee.strath.ac.uk Electronic & Electrical Eng. Dept. http://drl4.eee.strath.ac.uk/~gmcg University of Strathclyde Tel: +44 (0)141 548 2250 Glasgow G1 1XW Fax: +44 (0)141 552 4968Article: 4607
Vincent Rowley wrote: > > Hi, > > We are looking for a VHDL code editor for Windows NT platform. > > All information is welcome. > > If you reply to the group, send also a copy to the address > vrowley@hexavision.com . > > Thanks, > > Vincent Rowley > > -- > ----------------------------------------------------------------------- > -- Vincent Rowley -- HexaVision Technologies Inc. -- > -- -- 2050 Rene-Levesque ouest -- > -- Email: vrowley@hexavision.com -- Bureau 101 -- > -- Tel: 418-686-5000 (233) -- Sainte-Foy, Quebec, Canada -- > -- Fax: 418-686-5043 -- G1V 2K8 -- > ----------------------------------------------------------------------- Hi Vincent, We use a product called Sledgehammer, which is an HDL addon to CodeWright. I have been quite satisfied as the editor is very easily customized - I feel that emulation with whatever the user is most familiar is an extremely important attribute. We only code Verilog here, but it color codes keywords from both HDL's as well as smart indenting, etc. and emulates Brief, VI, and Epsilon, as well as "Notebook" type editors. The company is VHDL Tech. Group @ 610-882-3130. They are probably on the web somewhere too! Hope this helps. Regards, Mike Harrison OIS Northville, MIArticle: 4608
"Micropipelines", Ivan Sutherland. In Communications of the ACM, 32(6):720-738, 1989. While I haven't looked exhaustively for the paper, there are nonetheless some interesting things on the web regarding the transition signalling and micropipelines. Here's some of what I found: http://docs.dcs.napier.ac.uk/DOCS/GET/bailey91b/document.html http://paradise.ucsd.edu/class/ece260c/Article: 4609
C A L L F O R P A P E R S
THE FIFTH ANNUAL
IEEE SYMPOSIUM ON CUSTOM COMPUTING MACHINES
Napa, California
April 16-18, 1997
http://www.fccm.org
PURPOSE: To bring together researchers to present recent work in the
use of Programmable Logic Devices as reconfigurable computing
elements. This symposium will focus primarily on the current
opportunities and problems in this new and evolving technology for
computing. Contributions are solicited on all aspects of custom
computing, including but not limited to:
Architecture of reconfigurable computing systems, including
coprocessors, attached processors, and hybrids.
Languages, compilation techniques, tools, and environments for
programming;
Application domains;
Prototyping for architecture emulation;
Use of custom computing in education.
SUBMISSIONS: Authors are invited to send submissions (4 copies, 10
pages maximum) by January 10, 1997, to Jeffrey Arnold. Notification
of acceptance will be sent in early March. Final papers will be due
on the first day of the symposium. After the Symposium a proceedings
will be published by the IEEE Computer Society Press.
Authors may also submit PostScript or Microsoft Word manuscripts by
FTP. For instruction on electronic submission, please see the Web
page or contact Jeffrey Arnold (jma@super.org).
SPONSORSHIP: The IEEE Computer Society and the Technical Committee on
Computer Architecture.
CO-CHAIRS:
Kenneth L. Pocek
Intel
Mail Stop RN6-18
2200 Mission College Boulevard
Santa Clara, California 95052
Voice: 408-765-6705 Fax: 408-765-5165
kenneth_pocek@ccm11.sc.intel.com
Jeffrey M. Arnold
10686 Mira Lago Terrace
San Diego, CA 92131
Voice: 619-547-9257 Fax: 619-547-9010
jma@super.org
PROGRAM COMMITTEE:
Peter Athanas, Virginia Tech.
Donald Bouldin, University of Tennessee, Knoxville
Duncan Buell, Center for Computing Sciences
Michael Butts, Quickturn Design Systems, Inc.
Pak Chan, Univ. California, Santa Cruz
Apostolos Dollas, Technical Univ. of Crete
Scott Hauck, Northwestern Univ.
Brad Hutchings, Brigham Young Univ.
Tom Kean, Xilinx, Inc. (U.K).
Phil Kuekes, HP Labs.
Wayne Luk, Imperial College
Mark Shand, Digital Equipment (Paris)
Satnam Singh, Univ. of Glasgow
Stephen Smith, Altera Corp.
Article: 4610
A while back one of my co-workers brought me an article he'd clipped
out of a magazine. Actel had a new part that would hold 20K gates
with 100% utilization... or so they claimed. At the time we were just
getting started on a small ASIC, about 14K gates. "Great", I said.
"We'll be able to create a prototype and use that one FPGA to test our
entire design." It was not to be. The problem was that the 20K gate
part would barely hold 10K 'real' gates.
This wasn't my first run-in with an FPGA company whose parts turned
out to be smaller in real life than advertised. Last year an ASIC
which we wanted to prototype in a Xilinx 4000 series part turned out
the same way. The FPGA industry has come a long way by learning from
the ASIC industry. Design methodologies are constantly improving and
support for HDLs gaining momentum. Can someone tell me why the FPGA
industry is having such a hard time learning to count?
David Gardner
--
David N. Gardner
ASIC Design Engineer Lowrance Electronics
david@lowrance.com 12000 E. Skelly Drive.
918 437-6881 x8583 Tulsa OK, 74128
-----------------------------------------------------------------------
This article was posted to Usenet via the Posting Service at Deja News:
http://www.dejanews.com/ [Search, Post, and Read Usenet News]
Article: 4611
MAKE MONEY BY DOING NOTHING!!
Take five minutes to read this and it WILL change your life.
The Internet has grown tremendously. It doubles in size every 4
months.
think about it. You see those 'Make.Money.Fast' posts more and more.
That's ... because it WORKS ! So I thought, all those new users might
make it work. And I decided to try it out, a few months ago. Besides,
whats $5.00, I spend more than that in the morning on my way to work
on coffee and cigs for the day. So I sent in my money and posted.
Everyone was calling it a scam, but there are SO many new users from
AOL, Netcom, etc. they will join in and make it work for you.
Well, two weeks later, I began recieving bucks in the mail! I
couldn't
believe it! Not just a little, I mean big bucks! At first only a few
hundred dollars, then a week later, a couple of thousand, then BOOM.
By
the end of the fourth week, I had recieved nearly $47,000.00. It came
from all over the world. And every bit of it perfectly legal and on
the
up and up. I've been able to pay off all my bills and still had enough
left over for a nice vacation for me and my family.
Not only does it work for me, it works for other folks as well.
Markus
Valppu says he made $57,883 in four weeks. Dave Manning claims he made
$53,664 in the same amount of time. Dan Shepstone says it was only
$17,000 for him. Do I know these folks? No, but when I read how they
say they did it, it made sense to me. Enough sense that I'm taking a
similar chance with $5 of my own bucks. Not a big chance, I admit--but
one with incredible potential, because $5 is all anyone ever invests
in
this system. Period. That's all Markus, Dave, or Dan invested, yet
their $5 netted them tens of thousands of dollars each, in a safe,
legal, completely legitimate way. Here's how it works in 3 easy steps:
STEP 1.
Invest your $5 by writing your name and address on five seperate pieces
of paper along with the words: "PLEASE ADD ME TO YOUR MAILING LIST."
(In
this way, you're not just sending a dollar to someone; you're paying
for
a legitimate service.) Fold a $1 bill, money order, or bank note inside
each paper, and mail them by standard U. S. Mail to the following five
addresses:
1- Natalie Jansen
Lancveldlaan 18
5671 CN Nuenen
Holland
2- Chad Collier
2785 Cold Springs Rd. #49
Placerville, CA 95667
3- Steve Boltinghouse
1009 Bird St.
Hannibal, MO 63401
4- Jeremy Bero
2021 M SW
Miami, OK 74354
5- Andrew Rieck
119 Wood Creek Dr.
Martinez, GA 30907
USA
STEP 2.
Now remove the top name from the list, and move the
other names up.This way, #5 becomes #4 and so on.
Put your name in as the fifth one on the list.
STEP 3.
Post the article to at least 250 newsgroups. There are at
least 19000 newsgroups at any given moment in time.
Try posting to as many newsgroups as you can. Remember
the more groups you post to, the more people will see your
article and send you cash!
STEP 4.
You are now in business for yourself, and should start seeing
returns within 7 to 14 days! Remember, the Internet is new
and huge. There is no way you can lose.
Now here is how and why this system works:
Out of every block of 250 posts I made, I got back 5 responses.
Yes, thats right,only 5. You make $5.00 in cash, not checks or
money orders, but real cash with your name at #5.
Each additional person who sent you $1.00 now also makes 250
additional postings with your name at #4, 1000 postings. On
average then, 50 people will send you $1.00 with your name at
#4,....$50.00 in your pocket!
Now these 50 new people will make 250 postings each with your
name at #3 or 10,000 postings. Average return, 500 people= $500.
They make 250 postings each with your name at #2= 100,000
postings=5000 returns at $1.00 each=$5,000.00 in cash!
Finally, 5,000 people make 250 postings each with your name at
#1 and you get a return of $60,000 before your name drops off
the list.And that's only if everyone down the line makes only 250
postings each! Your total income for this one cycle is $55,000.
From time to time when you see your name is no longer on the list,
you take the latest posting you can find and start all over again.
The end result depends on you. You must follow through
and repost this article everywhere you can think of.
The more postings you make, the more cash ends up in
your mailbox. It's too easy and too cheap to pass up!!!
So thats it. Pretty simple sounding stuff, huh? But believe me, it
works. There are millions of people surfing the net every day, all
day, all over the world. And 100,000 new people get on the net
every day. You know that, you've seen the stories in the paper.
So, my friend, read and follow the simple instructions and play
fair. Thats the key, and thats all there is to it. Print this out
right now so you can refer back to this article easily. Try to keep
an eye on all the postings you made to make sure everyone is
playing fairly. You know where your name should be.
If you're really not sure or still think this can't be for
real, then don't do it. But please print this article and pass it
along to someone you know who really needs the bucks, and see
what happens.
REMEMBER....HONESTY IS THE BEST POLICY.YOU DON'T
NEED TO CHEAT THE BASIC IDEA TO MAKE THE BUCKS!
GOOD LUCK TO ALL, AND PLEASE PLAY FAIR AND YOU WILL
WIN AND MAKE SOME REAL INSTANT FREE CASH!
*** By the way, if you try to deceive people by posting the messages
with your name in the list and not sending the bucks to the people
already included, you will not get much. I know someone who did this
and only got about $150 (and that's after two months). Then he sent
the 5 bills, people added him to their lists, and in 4-5 weeks he had
over $10,000!
TRY IT AND YOU'LL BE HAPPY!!! :o) !!!!!!!!!!
Article: 4612
david@lowrance.com wrote:
>
> A while back one of my co-workers brought me an article he'd clipped
> out of a magazine. Actel had a new part that would hold 20K gates
> with 100% utilization... or so they claimed. At the time we were just
> getting started on a small ASIC, about 14K gates. "Great", I said.
> "We'll be able to create a prototype and use that one FPGA to test our
> entire design." It was not to be. The problem was that the 20K gate
> part would barely hold 10K 'real' gates.
>
> This wasn't my first run-in with an FPGA company whose parts turned
> out to be smaller in real life than advertised. Last year an ASIC
> which we wanted to prototype in a Xilinx 4000 series part turned out
> the same way. The FPGA industry has come a long way by learning from
> the ASIC industry. Design methodologies are constantly improving and
> support for HDLs gaining momentum. Can someone tell me why the FPGA
> industry is having such a hard time learning to count?
The short answer is greed.
The longer answer is that there really is no good way to relate FPGA
features to ASIC nand gates. When the answer is undefined, the
marketing guys will always promote the most optimistic estimate. It
probably got started like this.
Marketing: How big is that new FPGA thing?
Engineering: Well, it has 400 4LUTS:DFFs and registers in the IO blocks.
Marketing: No, I mean how big is it?
Engineering: Well we have two design which just fit. One is from a 6K
ASIC and the other is from a 4K ASIC.
Marketing: (Lets see 6+4 = 10) OK, gotta go.
But seriously folks:
Can someone tell me what is a real gate?
FPGA feature metrics
-gates/DFF?
-gates/4LUT?
-gates/4SRAM?
-gates/carry_generator?
-gates/tristate_bus_line?
-gates/interconnect_switch?
Software metrics
-gates/16 bit operator?
-gates/line_of_code?
System metrics
-gates/unrouted_fpga
-gates/routed_fpga
-gates/fpga_at_10MHz
-gates/fpga_at_50MHz
-ASIC_gate/FPGA_gate
Financial metrics
- VHDL_gates/hr
- Schematic_gates/hr
- Debugged_gates/hr
- delivered_to_a_customer_and_used_gates/hr
- Gates/mm_silicon
- Gates/pin
- Gates/$
Just messing around while I wait for a 10K_gate_FPGA to route:
routing metric = 10K_gates/29min * 50%full= 10K gates/hr.
design metric = 2 days = 5k/16hrs = 300 gates/hr
debug metric = I wish I knew!
-
Brad
Article: 4613Vincent Rowley wrote: > > Hi, > > We are looking for a VHDL code editor for Windows NT platform. > > All information is welcome. > > If you reply to the group, send also a copy to the address > vrowley@hexavision.com . > > Thanks, > > Vincent Rowley > > -- > -----------------------------------------------------------------------> -- Vincent Rowley -- HexaVision Technologies Inc. -- > -- -- 2050 Rene-Levesque ouest -- > -- Email: vrowley@hexavision.com -- Bureau 101 -- > -- Tel: 418-686-5000 (233) -- Sainte-Foy, Quebec, Canada -- > -- Fax: 418-686-5043 -- G1V 2K8 -- > -----------------------------------------------------------------------I use Winedit, shareware available from : http://www.windowware.com Very usefull editor also includes VHDL code highlighting. I have written some macros to do compilation and error tracing for Modeltec and Viewsynthesis from within the editor, also VHDL templates and Automatic test bench generation. If you want these E-mail me at the following address: arvdwatt@csir.co.za Regards Rynier van der WattArticle: 4614
I am looking for a low cost FPGA test board which will run on an IBM PC and will take a X4010 or X5010 FPGA. I am on a low budget and can't afford thousands of dollars. Does anyone know of such a beast? I already have the XILINX routing software and synthesis tools. Thanks in advance, JimArticle: 4615
Has anyone made their own download cable for programming devices from an IBM PC parallel board? If so , (and it was successful) could you describe the circuit? Thanks in advance , Richard.Article: 4616
Hello and good day, I'm new to VHDL and even more so to Mentor Graphics tools. My question is: Will MG continue to support autologic II? Or, will they(MG) drop it all together since I here MG is now going to use EXEMPLAR's synthesis tools? As a side note, does anyone know when Xilinx xc4ke will be compatible with Mentor Graphics 8.5? (I'm not sure if b1 or b2?) TIA, --jfgArticle: 4617
Check out the VHDL Editor at http://www.vhdl.com.au Setanta ED is a VHDL aware editor offering: - syntax colouring - template expansion - Automatic TestBench Generation - Automatic model insertions (hundreds of free models available) - Automatic Error tracking A 45 day evaluation licence is available, at http://www.vhdl.com.au -John Maher Technical Director - VHDL System Solutions P/LArticle: 4618
Richard Staley (rjs@hep.ph.bham.ac.uk) wrote: : Has anyone made their own download cable for programming devices from an IBM PC : parallel board? : If so , (and it was successful) could you describe the circuit? : Thanks in advance , Richard. What's your problem exactly? Why not buy download cable from Lattice? If yuo are interested in ISP design, you are welcome to contact our UK's Lattice office for help. -- ****************************************************************************** * Wong Man Kit 黃文傑 * * Applications Engineer 工程師 * * Lattice Semiconductor Asia Ltd 萊迪思半導體有限公司 * * Rm 201, 72 Tat Chee Avenue, 香港九龍 * * HKITC, Kowloon, 達之路七十二號 * * Hong Kong 香港工業科技中心二零一室 * * (852)-2319-2929 (852)-2319-2929 * ****************************************************************************** * Email address * mankit_wong@latticesemi.com * 電郵地址 * * * 96kwong@alumni.ee.ust.hk * * * Home page * http://eelindc1.ee.ust.hk/~eekwong * 網頁 * ******************************************************************************Article: 4619
Gordon McGregor wrote: > > Hi, > does anyone happen to know if PRO series is compatable with > windows 95 ? I am running Procapture from the Xilinx PROflow > task launcher and as soon as I select add component the system > crashes. It's not compatible with win95. It's almost not compatible with win32s either. It sort of a dos program which tends to look like windows. I would call it PRObug. But that has changed with the new version of ViewLogic's products: WorkView office. If you are using Xilinx XACT 6.0.0 or 6.0.1 just stick to win3.11 and wait for the update of Xilinx XACT 1Q1997. This update should work with win95 and NT. If you already have ViewLogic Workview Office 7.2 you can go to win95 but the Xilinx Hardware Debugger probably won't work. (I heard of someone who told me that it didn't work with a screen saver and did without the screen saver.) > > If you have managed to get PRO series working with win95 could > you get in touch, please ? > You would have to use magic to do that. -- Rene Bakker P.S. Downgrading from Win95 back to win3.11 isn't fun. I have some experience -- ------------------------------------------------------------------------ | Rene Bakker | FOM Institute for Atomic and Molecular Physics | | Digital engineer | Electronica & Informatica | | | Kruislaan 407 | | | 1098 SJ Amsterdam | | | The Netherlands | | | | | | Tel: +31-(0)20-6081234 | | | Fax: +31-(0)20-6684106 | | | E-mail: rbakker@amolf.nl | ------------------------------------------------------------------------Article: 4620
In article <3293BB30.15B5@emf.net>,
Brad Taylor <blt@emf.net> wrote:
>
> The short answer is greed.
> The longer answer is that there really is no good way to relate FPGA
> features to ASIC nand gates. When the answer is undefined, the
> marketing guys will always promote the most optimistic estimate. It
> probably got started like this.
> Marketing: How big is that new FPGA thing?
> Engineering: Well, it has 400 4LUTS:DFFs and registers in the IO blocks.
> Marketing: No, I mean how big is it?
> Engineering: Well we have two design which just fit. One is from a 6K
> ASIC and the other is from a 4K ASIC.
> Marketing: (Lets see 6+4 = 10) OK, gotta go.
> But seriously folks:
> Can someone tell me what is a real gate?
> FPGA feature metrics
> -gates/DFF?
> -gates/4LUT?
> -gates/4SRAM?
> -gates/carry_generator?
> -gates/tristate_bus_line?
> -gates/interconnect_switch?
> Software metrics
> -gates/16 bit operator?
> -gates/line_of_code?
> System metrics
> -gates/unrouted_fpga
> -gates/routed_fpga
> -gates/fpga_at_10MHz
> -gates/fpga_at_50MHz
> -ASIC_gate/FPGA_gate
> Financial metrics
> - VHDL_gates/hr
> - Schematic_gates/hr
> - Debugged_gates/hr
> - delivered_to_a_customer_and_used_gates/hr
> - Gates/mm_silicon
> - Gates/pin
> - Gates/$
> Just messing around while I wait for a 10K_gate_FPGA to route:
> routing metric = 10K_gates/29min * 50%full= 10K gates/hr.
> design metric = 2 days = 5k/16hrs = 300 gates/hr
> debug metric = I wish I knew!
> -
> Brad
>
Your right. This can be a confusing problem and anybody who wants to
could come up with new ways of measuring their parts, new metrics that
give whatever appearance they wish. I do however think it is possible
to take a logical approach to this issue.
Paul Hardy, a Xilinx FAE, emailed me with his thoughts on the subject.
He included a link to a Xilinx app note which discusses how Xilinx
counts gates ( http://www.xilinx.com/xapp/xapp059.pdf ).
The first approach Xilinx took to calculating the Maximum Logic Gates
was to analyse the fundamental building block of their architecture,
the CLB, and determine how it relates to the logic gates of a typical
ASIC vendor. Here's what they came up with for a 4000 series part:
CLB Resource Gates
-----------------------------------
4-input LUT (2 per CLB) 1 to 9
3-input LUT 1 to 6
flip-flop (2 per CLB) 7 to 12
TOTAL 17 to 48
We can also look at other vendors this way too. For example, the
Actel 3200 family. These parts are based on a finer grained
architecture than the Xilinx 4000 series. The fundamental block
of the 3200 series part is a Logic Module:
LM Resource Gates
-----------------------------------
AND 2
OR 2
4 input mux 7
flip flop (in half of LMs) 7 to 12
TOTAL 14.5 to 17
These numbers give us an idea of what is possible (with the perfect
design). The obvious problem though is that there is no such thing as a
perfect design. In the real world we'll never have a design that
uses every element of every FPGA logic block. These numbers can still
be very useful however for comparing different FPGA structures.
But the original question still stands. If I have a design that takes
X number of ASIC NAND gates then how do I know what FPGAs it will fit
into. I think the only way to determine this is through empirical
data. If we were to take a variety of designs of known size (in terms
of ASIC NAND gates) and route them into an FPGA then we could determine
a real-life number representing the average number of gates per logic
module. This would truely be useful. And by the way Xilinx claims to
have done this. According to that app note I mentioned previously
Xilinx claims they can get an average of 26 gates per CLB. In my
experience the actual number is _much_ lower, on the order of 10. And
yes this means that my design which utilized a 4010 maxed out at about
4K gates... significantly lower than Xilnix's minimum number of 7K.
I should note that buried in the Actel documentation is a table that
gives "Average Gates Per Module". According to this table a 3200 series
part will hold about 4.8 gates per module. This is very close to what
I've seen which was about 4.5. But for the 3200 series part they claim
holds 20K gates if you calculate its size using the 4.8 number from
their own documentation you only get about 12K.
I want to encourage everyone to post a reply to this message, including
vender FAEs or reps. I want to hear about the experiances of others and
to know what kinds of utilization other designers have seen with Xilinx,
Actel, or any other FPGA.
David Gardner
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 4621david@lowrance.com wrote: >A while back one of my co-workers brought me an article he'd clipped >out of a magazine. Actel had a new part that would hold 20K gates >with 100% utilization... or so they claimed. At the time we were just >getting started on a small ASIC, about 14K gates. "Great", I said. >"We'll be able to create a prototype and use that one FPGA to test our >entire design." It was not to be. The problem was that the 20K gate >part would barely hold 10K 'real' gates. > > Couldn't something like the PREP benchmarks (http://www.prep.org) be used to compare FPGA's? I'm just starting to look into this but it appears that they have several standard designs with synthesis results for several parts from a number of vendors. Wouldn't a comparison of the synthesis results of several parts using the same tool set give an indication of the effective size of the part for the type of design indicated by the benchmark?Article: 4622
In article <32937289.4E25@best.com>, Michael Baxter <mbaxter@best.com> wrote: > "Micropipelines", Ivan Sutherland. In Communications of the ACM, > 32(6):720-738, 1989. > > While I haven't looked exhaustively for the paper, there are nonetheless > some interesting things on the web regarding the transition signalling > and micropipelines. Here's some of what I found: > > http://docs.dcs.napier.ac.uk/DOCS/GET/bailey91b/document.html > > http://paradise.ucsd.edu/class/ece260c/ For those interested in asynchronous circuits in general, as well as some of the issues involved in mapping asynchronous logic to FPGAs, take a look at http://www.ece.nwu.edu/~hauck/asynch.html . This page includes copies of my 1995 Proceedings of the IEEE Survey of Asynchronous Design Methodologies (including micropipelines), as well as a paper on Montage, the first FPGA specifically designed for asynchronous circuits. Also, Eric Brunvand has done a lot of work on mapping asynchronous circuits onto Actel FPGAs. He doesn't seem to have his papers online, but the proper references are off his homepage (http://www.cs.utah.edu/~elb/home.html). Scott +-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+ | Scott A. Hauck, Assistant Professor | | Dept. of ECE Voice: (847) 467-1849 | | Northwestern University FAX: (847) 467-4144 | | 2145 Sheridan Road Email: hauck@ece.nwu.edu | | Evanston, IL 60208 WWW: http://www.ece.nwu.edu/~hauck | +-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+Article: 4623
I know this is an FPGA newsgroup, so I post here because a) I don't know where else to, and b) I figure there would be a great concentration of EEs in this group. Anyway, here is my question: Are there any formulas in electronics that incorporate the ratio of threshold voltages (Vto) between p-channel and n-channel devices? Specifically, (Vtp/Vtn), or (Vtn/Vtp). The reason I ask is that I am doing a sensitivity study in which I increase Vtp by 0.1V while at the same time decrease Vtn by 0.1V, and I want some way to correlate these two parameters. I just blindly thought of Vtp/Vtn but couldn't think of why that is a good formula. For that matter, are there any useful equations at all that use both Vtn AND Vtp in them in any way? I know that if I only vary either Vtn OR Vtp that I could use the percent difference, but what about varying two relatively independent variables such as these? Thanks, John -- John Rinck rinck@actel.com Web: http://www.wp.com/RINCK/ (for the Silicon Valley Apartment Guide) ---------------------------------------------------------------Article: 4624
Richard Staley wrote: > > Has anyone made their own download cable for programming devices from an IBM PC > parallel board? > If so , (and it was successful) could you describe the circuit? > > Thanks in advance , Richard. Actually, LAttice documents this cable in their, databook and ISP Manual. It is really quite simple and should be no problem to build.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z