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SKE is a small high-tech company providing technical services to clients such as NASA and the Air Force Research Labs. We are currently seeking an experienced Electronics Engineer to work on exciting DoD research project. The following qualifications apply: - BSEE or MSEE - 5+ years of digital electronics experience - FPGA - U.S. citizen or permanent resident required Qualified candidate please forward your resume to: Larry Li S&K Electronics 1016 Hercules Houston, TX 77058 e-mail: larryli@ghg.netArticle: 15176
Richard Guerin wrote in message <36E5F289.1AE1A793@home.com>... >Sounds like a fun project ... not familiar with the Instruction Set >Architecture ... can it be pipelined ? Indeed a pipeline approach may be used if we want. However, It seems that my first reaction to my assignment was too desperate. After talking with my professor about the instruction set, the microcomputer and other details, it seems that the toughest part of this project will focus on the ALU. The instructions are to remain relatively simple so most likely I'll stay away from utilizing any type of parallel processing. Who knows though, if things go well I just might shoot for extra credit! Thanks for the input to everyone who replied! Adios, Michael SharplesArticle: 15177
Hey! Steven! you are great! this is exactly what I've been looking for!!!! Thanxs a lot!!! Steven K. Knapp <sknapp@optimagic.com> wrote in article <7c5tvr$sos@sjx-ixn9.ix.netcom.com>... > You can find a FAQ on programmable logic on The Programmable Logic Jump > Station at http://www.optimagic.com/faq.html. > > ----------------------------------------------------------- > Steven K. Knapp > OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" > E-mail: sknapp@optimagic.com > Web: http://www.optimagic.com > ----------------------------------------------------------- > > Eci User wrote in message > <01be6ad2$c2f0f400$ef26ea93@pc-iosi.ecitele.com>... > >Please, can somebody tell me where to find any FAQ abot fpga's? > >Thanxs. > > >Article: 15178
This is a multi-part message in MIME format. --------------986E46546601AF6BACAF397E Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hello to ALL, Did anybody use the EPIC editor from Xilinx Foundation to modify the place and route of a proyect? I'd like to modify a proyect using the Epic editor, only to change the CLB configuration or/and change the internal pads, normally I can do that, but when I run again the compiler, it gives me the old result, it means, it doesn't modify the circuit as I asked. I'll waiting you coments. Thank you. Andres David --------------986E46546601AF6BACAF397E Content-Type: text/x-vcard; charset=us-ascii; name="garcia.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Andres David Garcia Garcia Content-Disposition: attachment; filename="garcia.vcf" begin:vcard n:Garcia Garcia;Andres David tel;pager:http://www-elec.enst.fr/~garcia/index.html tel;fax:(33-1)45-80-40-36 tel;home:(33-1)-44-16-18-90 tel;work:(33-1)-45-81-78-03 x-mozilla-html:TRUE org:Ecole Nationale Superieure des Telecommunications;Communications et Electronique version:2.1 email;internet:garcia@elec.enst.fr title:PhD Student on Electronics and Communications adr;quoted-printable:;;46, rue Barrault=0D=0A;Paris;;75634;France fn:PhD Student end:vcard --------------986E46546601AF6BACAF397E--Article: 15179
In article <36E6AF0C.649866D1@xilinx.com>, Peter Alfke <peter@xilinx.com> writes: > > Look-up table (LUT) is another word for a ROM ( read-only >memory) with n address lines and a single output. n is So then, is a RAM an E^2LUT? ;-)) -- Regards, Brent Hayhoe. Nortel Networks, Tel: +44 (0)1279-402937 Harlow Laboratories, London Road, Fax: +44 (0)1279-439636 Harlow, Essex, CM17 9NA, U.K. Email: hayhoe@nortelnetworks.comArticle: 15180
Is there any way to print AHDL code from Max+plus2 in color? Any utility to do that? TIA. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15181
I'm not familiar with the Virtex parts, however... We use XC9500XL, for which Xilinx recommends: "If free running clocks are delivered into the ISP CPLD, it may be necessary to disconnect or disable their entry into the CPLD while programming" Did you check the Virtex litterature for similar recommendations ? -Arve mark wrote: > > I've got a weird one I can't see to figure out. I have two XC300 Virtex > parts on my board which are being programmed in Master serial mode (ie. > first one is in master serial mode and the second is in slave serial mode). > When I disable my 50 MHz system clock (this clock has nothing to do with > the programming ... only required for operation ... it is connected to > one of the GCLK pins) the parts program every time. But, when the 50 MHz > clock is running the parts will not program. I'm convinced this is not a > noise / interference type of problem ... my board has solid power and > ground planes and decoupling is quite generous. I'm starting to suspect > something weird in the Virtex part itself. Has anyone seen any similar > problems with the Virtex parts? > > Thanks, > mark > > More Info ... The 50 MHz clock is comming from a 5V clock driver IC ... > The Vccio of the Virtex parts are connected to 3.3V which should provide 5V > tolerence ... in playing around I have inserted a low value resistor (50 > ohms) in series with the clock line between the buffer and the Virtex ... > with this setup the parts will program part of the time with the clock > runningArticle: 15182
September 28-30, 1999
Kossiakoff Conference Center
The Johns Hopkins University- Applied Physics Laboratory
Laurel, Maryland
The 2nd annual Military and Aerospace Applications of Programmable
Devices and Technologies International Conference will address
devices, technologies, usage, reliability, fault tolerance,
radiation susceptibility, and applications of programmable devices
and adaptive computing systems in military and aerospace systems.
The program will consist of oral and poster technical presentations
and industrial exhibits. This international conference is open to US
and foreign participation and is unclassified. There will be one
classified session at the secret level, for U.S. citizens only. For
additional conference information, please see Programmable
Technologies Web Site (http://rk.gsfc.nasa.gov).
Abstracts are being solicited in all aspects of the use of programmable
elements, devices, and systems for military and aerospace applications.
These include: PALs, FPGAs, PROMs, Programmable Substrates, FPIC,
Programmable Analog Circuits, adaptive computing systems and related
technologies.
Topics include (but are not limited to) the following:
- System on a Chip
- Advanced Devices, Technologies, and Software and Their Impact on
Critical System Reliability
- Programmable Technologies and State-of-the-Art Devices and
Programmable Elements
- Adaptive Computing Systems
- Evolvable Hardware
- Radiation Effects, Device Reliability and Element Characteristics
- Device Architecture, Performance, and Capabilities
- Applications and Novel Techniques for Military and Spaceflight
Circuits.
- Use of COTS Devices in the Military and Spaceflight Environment
- Testing and Analysis Techniques
- Software Tools for Design/Analysis - HDLs, Synthesis, and
Intellectual Property
- Advanced Packaging including Known-Good-Die, MCMs, and chip-scale
packaging.
The conference is sponsored by:
- NASA/GSFC
- JHU/Applied Physics Laboratory
- NSA
- NASA Radiation Effects Program
- Military & Aerospace Programmable Logic Users Group
- American Institute of Aeronautics and Astronautics
For more information see http://rk.gsfc.nasa.gov or contact:
Richard Katz
NASA
rich.katz@gsfc.nasa.gov
Tel: (301) 286-9705
Alan W. Hunsberger
NSA
awhunsb@afterlife.ncsc.mil
Tel: (301) 688-0245
Ann Garrison Darrin
JHU/APL
ann.darrin@jhuapl.edu
Tel: (240) 228-4952
Abstracts should be approximately 2 pages long and are due June 11,
1999. Please send abstracts to maplug@pop700.gsfc.nasa.gov.
Include first author information (name, affiliation, phone number,
and email address) and whether an open or classified presentation
is desired. If you can not submit an unclassified abstract, please
contact Al Hunsberger.
Industrial exhibit reservations should be sent to
maplug@pop700.gsfc.nasa.gov and should include company name and
contact information (name, phone and email).
------------------------------------------------------------------
MAPLD 99 Program
Military and Aerospace Applications of Programmable Devices and
Technologies Conference
Welcome
Rich Katz - NASA Goddard Space Flight Center
Dr. Stamatios Krimigis - Head, Space Department
Johns Hopkins University/Applied Physics Lab
Technical Sessions:
I. Military & Aerospace Applications
Session Chair: Marty Fraeman - JHU/APL
Invited Speaker: Dr. Ralph McNutt - JHU/APL
II. Devices, Elements, and Technologies
Session Chair: Rich Katz - NASA Goddard Space Flight Center
Invited Speaker: John McCollum - Actel Corp.
III. Radiation Environments and Effects
Session Chair: Ken LaBel - NASA Goddard Space Flight Center
Invited Speaker: Rich Katz - NASA GSFC
"FPGAs in Space Environment and Design Techniques"
IV. Adaptive Computing
Session Chair: John McHenry - National Security Agency
Invited Speaker: Brad Hutchings - Brigham Young University
V. SoC, Synthesis, and IP
Session Chair: Hans Tiggeler - University of Surrey, UK
Invited Speaker: To be announced.
VI. Classified Session
Session Chair: Al Hunsberger - National Security Agency
Invited Speaker: Mark Dunham and TBA - Los Alamos National Labs
VII. Poster Session
Session Chair: Christina Gorsky - SGT, Inc.
Dinner Speaker (Tuesday Evening)
Dr. Don DeVoe, University of Maryland at College Park
"Micro Electro Mechanical Systems (MEMS)"
Panel Session: (Wednesday Evening)
"Architecture, Technologies and Design Methodologies for 2005
and Beyond"
Panel Moderator: Ann Garrison Darrin - JHU/APL
---------------------------------------------------
Technical Committee
===================
Ray Andraka - The Andraka Group
Neil Bergmann - Queensland University of Tech, Australia
Ben Cohen - Hughes Aircraft/Raytheon
Lew Cohn - Defense Threat Reduction Agency
Marco Figueiredo - SGT, Inc.
Marty Fraeman - JHU/Applied Physics Lab
Ann Garrison Darrin - JHU/Applied Physics Lab
Creigh Gordon - Air Force Research Lab/VSSE
Christina Gorsky - SGT, Inc.
Al Hunsberger - National Security Agency
Brad Hutchings - Brigham Young University
Richard B. Katz - NASA GSFC
Ralph Kohler - Air Force Research Laboratory
Ken LaBel - NASA GSFC
John McHenry - National Security Agency
Robert Reed - NASA GSFC
Michael Regula - Dornier Satellitensysteme GmbH
Frank R. Stott - Jet Propulsion Laboratory
Hans Tiggeler - University of Surrey, UK
Tanya Vladimirova - University of Surrey, UK
Article: 15183If I understand you correctly, you want changes that you make in EPIC to automatically be reflected in your input design. EPIC is just a low-level editor, and there is no way to feed changes, (especially logic changes) back to your schematic or HDL file. It's sort of like editing the assembler output of a compiler and expecting it to update your C code to relect the changes - a difficult problem. For placement and pinouts, you could look into using the floorplanner and constraint editor. Or, read up on constraint (.cst) file usage and create your own. For now, I prefer to put all my timing & placement constraints on the schematics - self-documenting, no 'extra' files to get lost or out of sync. I just use EPIC to verify that things got placed and routed as I had requested. The floorplanner is useful here, too. regards, Tom Burgess Andres David Garcia Garcia wrote: > > Hello to ALL, > > Did anybody use the EPIC editor from Xilinx Foundation to modify the place > and route of a proyect? > > I'd like to modify a proyect using the Epic editor, only to change the CLB > configuration or/and > change the internal pads, normally I can do that, but when I run again the > compiler, it gives me the > old result, it means, it doesn't modify the circuit as I asked. > > I'll waiting you coments. Thank you. > > Andres David >Article: 15184
Peter Alfke <peter@xilinx.com> writes:
> The presentations will be given by experienced Field
> Applications Engineers. I will assist in Germany and Sweden,
> my old stomping grounds. We will describe parts and
> solutions that you can buy and use today, no vaporware here.
Would love to go, but there isn't any seminar in Sweden on the page
you supplied. What gives?
Homann
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 15185I am creating a low-level FPGA design using Xilinx EPIC. Great program, but nowhere can I find any documentation on the syntax for the LUT equations. Essentially, if you highlight a logic slice in a CLB, pick editblock, pick a LUT (by clicking on the check box market "LUT" on the logic element), then click attr (for attibutes), you get a dialog box with "LUT Equations". Great, that's just what I need, but a few syntax guesses all errored out. I called Xilinx tech support - they said they would find out (didn't know immediately over the phone) - and I have not heard back from them since. No phone, no voice mail, no e-mail. I also called up one of our local distribution reps - he again said he would try to find me the right person, but when I called him today, he hemmed and hawed, said he was having difficulty tracking down someone who could help, said he would try looking through old manuals, faxed me a sheet, and it did not help. So I'm still stopped. So, very simply put, What is the correct syntax for entering LUT equations for Virtex parts in the dialog box for that purpose in Xilinx EPIC 1.5? Any help would be MUCH appreciated. TIA, Alex Rast arast@inficom.comArticle: 15186
Here is what I know that works: parenthesis () can be used to show the order of operations: ~ implements a NOT fuction + implements an OR function * implements an AND function @ implements a XOR function So if I wanted to create equation ((A and S) or (B and ~S)) for the F function generator I would do the following. first connect the A, B and S nets to the input pins for the F function generator. For example connect pin F1 to net A, pin F2 to B and pin F3 to S. Set the equation: F= (F1*F3)+(F2*~F3) Cheers, Tom Branca Xilinx ApplicationsArticle: 15187
Magnus Homann wrote: > Would love to go, but there isn't any seminar in Sweden on > the page > you supplied. What gives? > April 20, in Kista. Contact Dipcom or Xilinx Sweden.Hälsningar PeterArticle: 15188
FPGA Downloader for Altera FPGA/EPLD - ONLY $75.00 Works with any voltage from the target board 1.8 V - 5.5 V Replaces Altera ByteBlaster and ByteBlaster MV downloader You will never need another downloader Please visit us at: http://welcome.to/nefdesign.com Sincerely, NEF Design, Inc. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15189
I am interested in processor design, and I would like to know what I need to get started. I do not want to spend too much money.Article: 15190
Hi,
I am trying to map a design on a PAMette board that has four 4010e LCAs.
My design uses all four LCAs and runs under static mode. I have a few
questions:
1. I have a global reset in my VHDL code. I used a STARTUP block to
instantiate the GSR signal. Where should I put this GSR signals?
Currently I am using ring[0] as a GSR signal. But I guess there is an
error in my code (attached below) because all the internal FFs in LCAs
are all 0s no matter how many cycles I run.
2. What is meaning of the option -g GSRInactive:C3 in bitgen? Does this
influence anything on the GSR?
3. when you write "PamDownloadBitstream(pam, &drc_pam, 30);"
Does this function also set the user clock to be 33MHz as well?
Thanks!
-- Zhen
49. /* using ring[0] to initiate a reset */
50. userport = &(PAMREGS(pam)->link);
51. *userport = 0; PamFlush();
52. // enable ring[0], disable ring[1]
53. PAMREGS(pam)->decode = (PAMREGS(pam)->decode & ~PPAMRING_ENABLES)
| (0x1 << 8);
54. // force write
55. PamFlush();
56. // Set a '1' on ring[0]
57. PAMREGS(pam)->dwnld1 = (PAMREGS(pam)->dwnld1 & ~PPAMRINGS) | 0x1
<< 8;
58. // force write
59. PamFlush();
60. // Set a '0' on ring[0]
61. PAMREGS(pam)->dwnld1 = (PAMREGS(pam)->dwnld1 & ~PPAMRINGS) | 0x0
<< 8;
62. PamFlush();
Article: 15191Me too, bit what about So. Cal?? Bob Peter Alfke wrote in message <36E85567.D0A02958@xilinx.com>... >Magnus Homann wrote: > >> Would love to go, but there isn't any seminar in Sweden on >> the page >> you supplied. What gives? >> > >April 20, in Kista. Contact Dipcom or Xilinx >Sweden.Hälsningar >Peter > >Article: 15192
Hi!
----------
> From: Jim <jok@erols.com>
> To: Kuznetsov Dmitry <dkuzn@orc.ru>
> Subject: Re: Startup issues with 24c04 eeprom and I2C interface
> Date: 11 MAR 1999 a. 4:56
>
> Dear Kuznetsov Dmitry,
>
> Yes, the part can get reset in this manner. Since I am designing
> an ASIC I have no specification to cause a situation of 'interuption
> in protocol.' All of the operations the ASIC performs are graceful.
> Power up is no-man's land in terms of gates and/or firmware. But,
> givne that the start condition seems to be defined with some
> thought of power up in mind, I think that power up will not
> cause a problem with eeprom.
>
> I may add suspenders if I have silicon and time. You just never know.
I wants to warn on one serious problem.
To Call Attention that SerialEEPROM has no an external signal of reset,
but ASIC has a similar external signal (reset - configuration). And all
this under stable and excellent power. As A Result can have a situation,
when ASIC will be reconfigurated the external signal without the concerns
about SerialEEPROM and does not be able to begin a correct work with her.
This danger is peculiar to parts without the forced reset and under
minimum powers, sufficient for continuing their capacity to work.
For instance, under temporary worsenning a quality of power. Monitor of
power will produce the full system reset, except 24c04 eeprom.
For preventing this danger it is necessary completely to delete a power.
But this sometimes impossible do.
This problem has different solutions.
1) Following to recommendations a vendor of parts for deciding this
situations of 'interuption in protocol'. This is do by the host by
programme methods.
2) Independent test by means of the hardware model (as an addenda to the
first point) for the study of announcing an part in different possible
situations..
3) Using the elements with the hardware unset, for instance, family 93x.
Bye!
Kuznetsov Dmitry, Moscow <> Mailto: dkuzn@orc.ru
HomePage <><> http://www.orc.ru/~dkuzn/index.htm
Alias http://attend.to/dkuzn
Article: 15193In the stage of pre-layout, how can I estimate the wiring effect? The module I made is reported to have about 34,000 area and 14,000 nets by Synopsys DesignCompiler. The net area is yet 0, and wire load was not considered as delay factor. How does massive wiring affect the chip area and speed? Does Synopsys provide good method for estimating them?Article: 15194
>
> An other way is to map and place my_logiblox alone into a chip big enough
> to accept the future full design. Then add your modification and set the
> "copy guide (map and flooplanner) to clipboard".
>
Some more informations :
There are 2 ways to set the guide file :
1 : design implement
copy guide/floorplan to clipboard. The PAR can change a quite big part
of the design, even with minor input modifications
2 : design
set guide file
with or without "match guide design exactly". The PAR will keep
remaining CLBs at their locations but you will have warnings for
modifications.
You have to choose.
Michel Le Mer
Gerpi sa (Xilinx Xpert)
3, rue du Bosphore
Alma city
35000 Rennes
France
(02 99 51 17 18)
http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm
Article: 15195Bob Bauman wrote: > Me too, bit what about So. Cal?? > Thanks for the interest.Keep looking. Some of our sales offices are a bit slow in posting. Sorry. Peter AlfkeArticle: 15196
Luis de Funes wrote: > Peter Alfke ha scritto And there > >also is no glitch when you change two address lines more > or > >less simultaneously if - and only if - all four address > >combinations generate the same output. > >I get that question quite often > > > >Peter Alfke, Xilinx Applications > > > > Dear Peter, > That "only if" is a surprise for me. > For example, we have this function > > out = (a XOR b XOR c) AND d > > When d=0, I tought the out is ALWAYS 0, wathever > occours to the inputs a b c. > You say instead that in these conditions the out > might have glitches ? > > Luis, there is of course NO glitch. You misunderstood me: When I said "all four address combinations" I meant all the four addresses you get from the permutations of the two lines that are changing. In your example, you can change a,b,andc as much as you want and in any order, all the eight permutations still give you a 0 out. Thinking more about it, the situation is actually even better: Assuming two inputs change: There will be no glitch if all the THREE potential new address combinations generate the same result, which is allowed to be different from the original ooutput. For three lines changing "simultaneously", no glitch if the seven potentially new addresses all give the same result. The user can, of course, also avoid some potential glitches by controlling the sequence in which the inputs change. Peter Alfke, Xilinx ApplicationsArticle: 15197
Luis de Funes wrote: > Peter Alfke ha scritto And there > >also is no glitch when you change two address lines more > or > >less simultaneously if - and only if - all four address > >combinations generate the same output. > >I get that question quite often > > > >Peter Alfke, Xilinx Applications > > > > Dear Peter, > That "only if" is a surprise for me. > For example, we have this function > > out = (a XOR b XOR c) AND d > > When d=0, I tought the out is ALWAYS 0, wathever > occours to the inputs a b c. > You say instead that in these conditions the out > might have glitches ? > > Luis, there is of course NO glitch. You misunderstood me: When I said "all four address combinations" I meant all the four addresses you get from the permutations of the two lines that are changing. In your example, you can change a,b,andc as much as you want and in any order, all the eight permutations still give you a 0 out. Thinking more about it, the situation is actually even better: Assuming two inputs change: There will be no glitch if all the THREE potential new address combinations generate the same result, which is allowed to be different from the original ooutput. For three lines changing "simultaneously", no glitch if the seven potentially new addresses all give the same result. The user can, of course, also avoid some potential glitches by controlling the sequence in which the inputs change. Peter Alfke, Xilinx ApplicationsArticle: 15198
Luis de Funes wrote: > Peter Alfke ha scritto And there > >also is no glitch when you change two address lines more > or > >less simultaneously if - and only if - all four address > >combinations generate the same output. > >I get that question quite often > > > >Peter Alfke, Xilinx Applications > > > > Dear Peter, > That "only if" is a surprise for me. > For example, we have this function > > out = (a XOR b XOR c) AND d > > When d=0, I tought the out is ALWAYS 0, wathever > occours to the inputs a b c. > You say instead that in these conditions the out > might have glitches ? > > Luis, there is of course NO glitch. You misunderstood me: When I said "all four address combinations" I meant all the four addresses you get from the permutations of the two lines that are changing. In your example, you can change a,b,andc as much as you want and in any order, all the eight permutations still give you a 0 out. Thinking more about it, the situation is actually even better: Assuming two inputs change: There will be no glitch if all the THREE potential new address combinations generate the same result, which is allowed to be different from the original ooutput. For three lines changing "simultaneously", no glitch if the seven potentially new addresses all give the same result. The user can, of course, also avoid some potential glitches by controlling the sequence in which the inputs change. Peter Alfke, Xilinx ApplicationsArticle: 15199
Hi. I need to introduce a 40-50 ns delay in the line clock of the fpga (the clock will be in the 5-8MHz range). how can i do it?? I thought in feeding back the clock in a new pin and delaying with a cap, but, i suppose this delay can be do with internal logic also. Thanks. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
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