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I had not realized that iob attribute I used was a different attribute. Apparently, the buffer_type set to none seems to be working! Thanks a lot, Brian!!!Article: 149301
On Oct 14, 6:12=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > Amal <akhailt...@gmail.com> writes: > > Can you not do the same thing with planAhead? =A0It has many netlist > > searching and display features. > > You may well be able to now - Planahead didn't exist when I first > wrote FPGAOptim :) > > But, how long does planahead take to update a netlist? =A0Many tens of > seconds in my experience on a 80% full S3ADSP3400 EDK design, vs about > 5 secs for FPGAOptim. =A0Admittedly, I haven't tried Planahead 12.x > yet... > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.co.uk/capabilities/39-electronic-hardware Great. I am sure it's a great tool and you did a great job. I just wanted to know what exactly it offers. -- AmalArticle: 149302
On Thu, 14 Oct 2010 18:41:07 -0400, "MM" <mbmsv@yahoo.com> wrote: >I had not realized that iob attribute I used was a different attribute. >Apparently, the buffer_type set to none seems to be working! > >Thanks a lot, Brian!!! > Lost in a maze of twisty little attributes, all alike. At least you weren't trying to fight all the optimisation stages,and trying to find the appropriate combination of attributes "keep", "preserve_signal", "don't_optimise", and "equivalent_register_removal=no"... - Brian (whose longer-lived code sometimes looks like a graveyard of dead attributes....)Article: 149303
Hi, i have two newbie questions: is it possible to use differential pin as single ended pin? is it possible to implement SPI in any IO pin? thansArticle: 149304
Hi Eryer, Simple answers: Yes and yes. On Fri, 15 Oct 2010 03:21:16 -0700 (PDT), eryer <idkfaidkfaidkfa@gmail.com> wrote: >Hi, >i have two newbie questions: >is it possible to use differential pin as single ended pin? >is it possible to implement SPI in any IO pin? >thansArticle: 149305
Hi MM, I haven't been able to find your previous posts. In your attempt to disable the IOB insertion on the IP Core, did you try to modify the .mhs file in XPS, by assigning BUFFER_TYPE=NONE on the port giving you problems? Regards, Kim P. On Thu, 14 Oct 2010 17:41:20 -0400, "MM" <mbmsv@yahoo.com> wrote: >This is a more generic question following up my previous question on >translation failing because of the IOBs instantiated in one of the EDK >cores. I was wondering if there is a way (short of hacking the core) to >either disable IOB instantiation in EDK altogether or vice-versa to disable >IOB instantiation in ISE, but only for those pins, which already have IOBs >instantiated by EDK. I tried implementing the latter idea by assigning >synthesis iob attribute for these pins and setting it to FALSE, but got an >INTERNAL_ERROR in XST... I can't believe there is no simple solution... In >the past ISE somehow managed to figure this out. I also vaguely remember >that at some point long ago I had a similar problem and did something with >some of the cores, but can't remember what... In any case latest MPMC core >has these IOB instantiations scattered through many files and hacking them >all doesn't appear to be a nice solution. > >Any ideas will be highly appreciated! > >/Mikhail >Article: 149306
On 15 Ott, 12:42, Kim Povlsen <k...@rtldesign.dk> wrote: > Hi Eryer, > > Simple answers: > Yes and yes. > > On Fri, 15 Oct 2010 03:21:16 -0700 (PDT), eryer > > <idkfaidkfaid...@gmail.com> wrote: > >Hi, > >i have two newbie questions: > >is it possible to use differential pin as single ended pin? > >is it possible to implement SPI in any IO pin? > >thans Thanks for your answers.... from xilix ise, where can i find SPI logicore?I don't find it...Article: 149307
On Thu, 14 Oct 2010 18:41:07 -0400, "MM" <mbmsv@yahoo.com> wrote: >I had not realized that iob attribute I used was a different attribute. >Apparently, the buffer_type set to none seems to be working! > >Thanks a lot, Brian!!! I strongly recommend going back to the Answer Record you found, giving feedback that it no longer works with ISE12, and outlining what worked instead. Despite the warnings the feedback system gives you, sometimes Xilinx do listen, and if they update the Answer Record, the information will be useful to others. - BrianArticle: 149308
On Oct 15, 7:25=A0am, eryer <idkfaidkfaid...@gmail.com> wrote: > On 15 Ott, 12:42, Kim Povlsen <k...@rtldesign.dk> wrote: > > > Hi Eryer, > > > Simple answers: > > Yes and yes. > > > On Fri, 15 Oct 2010 03:21:16 -0700 (PDT), eryer > > > <idkfaidkfaid...@gmail.com> wrote: > > >Hi, > > >i have two newbie questions: > > >is it possible to use differential pin as single ended pin? > > >is it possible to implement SPI in any IO pin? > > >thans > > Thanks for your answers.... > from xilix ise, where can i find SPI logicore?I don't find it... I thought the only SPI "core" is the one for Microblaze which would be in the EDK rather than ISE. Also if you want to use SPI to configure the FPGA as well as using it to access a flash memory after configuration, you need to use the pins as described in the Configuration User Guide. SPI itself is a fairly simple protocol, so normally people just write their own interface if using a SPI device other than device configuration or use with an embedded processor. Generally the data sheet for the SPI-connected device will show you the required protocol. Regards, GaborArticle: 149309
On Oct 14, 6:07=A0pm, "MM" <mb...@yahoo.com> wrote: > > I don't have the exact answer, but after looking at > >http://www.xilinx.com/support/answers/37204.htm > > my next move would be to find the 12.x Constraints Guide (cgd.pdf) and > > look up > > the =A0"buffer_type" attribute - is there a "none" value for it? > > > Then try adding > > > attribute buffer_type: string; > > attribute buffer_type of my_sig: signal is "none"; > > > to all the relevant signals - if you can suppress XST's desire to inser= t > > buffers > > on these specific signals you should be good. > > I tried this: > > attribute =A0iob: =A0 =A0string; > > attribute =A0iob =A0of Ddr_Ck_N =A0: signal =A0is =A0"FALSE"; > attribute =A0iob =A0of Ddr_Ck_P =A0: signal =A0is =A0"FALSE"; > attribute =A0iob =A0of Ddr_A =A0 =A0: signal =A0is =A0"FALSE"; > attribute =A0iob =A0of Ddr_D =A0 =A0: signal =A0is =A0"FALSE"; > > It results in an internal error in XST :( > > /Mikhail Yeah, the iob attribute just says whether or not to place an instance in the IOB block vs. using some fabric resource. Generally this is applied to flip-flops only. So telling it not to place a pad net in an IOB would not have good results. Regards, GaborArticle: 149310
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:tpegb654veim0lpmar5aut1bgus5v9cfb3@4ax.com... > > I strongly recommend going back to the Answer Record you found, giving > feedback > that it no longer works with ISE12, and outlining what worked instead. > It turns out I was wrong and it does work. Shame on me... I was adding search path to ngbuild instead of XST... /MikhailArticle: 149311
"Kim Povlsen" <kim@rtldesign.dk> wrote in message news:9fcgb6dk3277dks6sahi1f9gggsih4n5ai@4ax.com... > > In your attempt to disable the IOB insertion on the IP Core, did you > try to modify the .mhs file in XPS, by assigning BUFFER_TYPE=NONE on > the port giving you problems? > I didn't know you could do this in the .mhs file... Thank you for the suggestion. But it turns out that I don't need to do this at all. See the following thread: "ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages." Thanks, /MikhailArticle: 149312
Hi, i need to create a M-LVDS nwtwork running at 50-100Mbps. As i could not find any driver that could be placed to run that multdrop network (any protocol and datalink designed with small and size variable packet (Max 256 bytes) would be suitable) i designed one myself on a FPGA. On the on the uC/DSP side there is a 8/16 bits parallel interface and at the M-LVDS the clock is recovered with oversampling the data (using the rise and fall edge and a second clock with 90 degree phase as described in this paper: http://www.date-conference.com/proceedings/PAPERS/2010/DATE10/PDFFILES/IP2_04.PDF . The fisrt questions is: Is possible to implement such oversampling on a CPLD? Does CPLDs got any kind of PLL or something like that? Second: Do you think CPLDs are going to stay on the market for a long time? Or they are going to disapear and there will be just FPGAs? Third: This device must got a real small footprint. The best i found was a EP1C3 of Altera, but any one knows how long is going to take until this device is discontinued? Any sugestion of using a CPLD or FPGA for this design, or sugestions of any small fottprint (no BGA) FPGA of Altera or Xilinx (i got the download cable of both and dont want to get a new one). Thank you! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149313
On Oct 15, 11:30=A0am, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Hi, i need to create a M-LVDS nwtwork running at 50-100Mbps. As i could n= ot > find any driver that could be placed to run that multdrop network (any > protocol and datalink designed with small and size variable packet (Max 2= 56 > bytes) would be suitable) i designed one myself on a FPGA. On the on the > uC/DSP side there is a 8/16 bits parallel interface and at the M-LVDS the > clock is recovered with oversampling the data (using the rise and fall ed= ge > and a second clock with 90 degree phase as described in this paper:http:/= /www.date-conference.com/proceedings/PAPERS/2010/DATE10/PDFFILE... > . > > The fisrt questions is: Is possible to implement such oversampling on a > CPLD? Does CPLDs got any kind of PLL or something like that? > I see another problem... can you find a CPLD with LVDS I/O? > Second: Do you think CPLDs are going to stay on the market for a long tim= e? > Or they are going to disapear and there will be just FPGAs? > CPLD's still have a place in the market with no end in sight. Anything that needs a bit of glue logic that comes up running on power-up can use one. > Third: This device must got a real small footprint. The best i found was = a > EP1C3 of Altera, but any one knows how long is going to take until this > device is discontinued? > > Any sugestion of using a CPLD or FPGA for this design, or sugestions of a= ny > small fottprint (no BGA) FPGA of Altera or Xilinx (i got the download cab= le > of both and dont want to get a new one). > > Thank you! =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com You might find some cross-over "CPLD's" that are really FPGA's with another name like the Lattice MachXO series. Some of these (the larger ones) have PLL and LVDS I/O. However I'm not sure about smaller packages. Don't discount other IC vendors because you already own a cable. A cable is cheap compared to a missed market opportunity. Regards, GaborArticle: 149314
I dont really need LVDS as i am using an external tranceiver. Most of FPGAs LVDS ports cant drive a MLVDS bus. Not enough current. The MachXO is more expensive than a Cayclone and the smallest footprint is the same. But the best point is no need of external flash. I am not totally disconsidering other vendors, but i strongly prefer one that i got some experience and tools. Thank you! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149315
Another mistery in ISE12.3. I am getting a bunch of errors during MAP phase,
which all look like this:
------------------
ERROR:Pack:2811 - Directed packing was unable to obey the user design
constraints (LOC=R29) which requires the combination of the symbols
listed
below to be packed into a single IOB component.
The directed pack was not possible because: More than one pad symbol.
The symbols involved are:
BUF symbol "Ddr_A_11_OBUF" (Output Signal = Ddr_A<11>)
PAD symbol "Ddr_A<11>" (Pad Signal = Ddr_A<11>)
PAD symbol "Phy2_Mdio" (Pad Signal = Phy2_Mdio)
The problem is that R29 was indeed in the past assigned to Phy2_Mdio, but it
is commented out in the .ucf file I searched through the whole project and I
can't find where it is getting this from... I deleted all files I could
imagine could have this information. I cleaned the project several times...
All to no avail...
Where else can Xilinx store pad location constraints?
Thanks,
/Mikhail
Article: 149316On Oct 15, 2:56=A0pm, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > I dont really need LVDS as i am using an external tranceiver. Most of FPG= As > LVDS ports cant drive a MLVDS bus. Not enough current. The MachXO is more > expensive than a Cayclone and the smallest footprint is the same. But the > best point is no need of external flash. I am not totally disconsidering > other vendors, but i strongly prefer one that i got some experience and > tools. > > Thank you! =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I'm a long time Xilinx-user and found that the Lattice tools and architecture are similar enough that there was not a big learning curve. If you don't need LVDS, then the only other showstopper in a CPLD is how many flip-flops you have in the design. FPGA's are much richer in fabric flip-flops for a given size of part. Still I don't remember seeing PLL's in a real CPLD. Can you do it with a separate PLL part? You can get some PLL's intended for cleaning up clock jitter that have very good spec's in a small TSSOP or QFN package. Then if you don't need more flip-flops than are reasonable in a CPLD you can again find very small QFN parts. Any reason you don't want to consider BGA packages? Regards, GaborArticle: 149317
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_imple= ment_fpga_design.htm "The Translate process merges all of the input netlists and design constraints and outputs a Xilinx Native Generic Database (NGD) file, which describes the logical design reduced to Xilinx primitives. See the following table for details. " translate=3Dngdbuild ie ngdbuild reads the UCF file and outputs the constraints in the .ngd file. You need to rerun ngdbuild. --steve On Oct 15, 4:13=A0pm, "MM" <mb...@yahoo.com> wrote: > Another mistery in ISE12.3. I am getting a bunch of errors during MAP pha= se, > which all look like this: > > ------------------ > ERROR:Pack:2811 - Directed packing was unable to obey the user design > =A0 =A0constraints (LOC=3DR29) which requires the combination of the symb= ols > listed > =A0 =A0below to be packed into a single IOB component. > > =A0 =A0The directed pack was not possible because: More than one pad symb= ol. > =A0 =A0The symbols involved are: > =A0 =A0 BUF symbol "Ddr_A_11_OBUF" (Output Signal =3D Ddr_A<11>) > =A0 =A0 PAD symbol "Ddr_A<11>" (Pad Signal =3D Ddr_A<11>) > =A0 =A0 PAD symbol "Phy2_Mdio" (Pad Signal =3D Phy2_Mdio) > > The problem is that R29 was indeed in the past assigned to Phy2_Mdio, but= it > is commented out in the .ucf file I searched through the whole project an= d I > can't find where it is getting this from... I deleted all files I could > imagine could have this information. I cleaned the project several times.= .. > All to no avail... > > Where else can Xilinx store pad location constraints? > > Thanks, > /MikhailArticle: 149318
Vipul, this is a pretty standard and common problem in FPGAs. You can't independently synchronize a bunch of control signals when crossing clock domains. They'll all cross individually OK, but there's no guarantee that they'll all end up in the same clock phase on the other side, especially if the destination domain is faster than the source domain. You need to have a send/receive handshake that consists of a single signal, synchronized in both directions. The control signals that need to cross are flopped directly in the receiving domain without any synchronizers. The handshake signal is double flop synchronized and used as an enable on the flops that receive the control signals. By the time the double flopped sync signals make it through to the flop enable, the other control signals are stable and can be safely latched. An async FIFO is another possibility. Do a search on clock domain crossing and you'll come up with plenty of answers. --steve On Oct 13, 1:48=A0am, jas <thejaspr...@gmail.com> wrote: > Hi Everyone, > > I am designing a system where I am interfacing a Motorolla processor > in my system for read and write data. This processor is on the board > where my fpga will interact with it. The processor is the master mode > always and the salave is my interface design and the fpga. > > The motoroll Processor will have LBC Local bus controller signals > will > be comunicating to my interface inside the FPGA. > > The processor can run at configurable clock of 33 MHz to 133 MHz. The > address bus is 24 Bits and tye data bus is 32 bits. > > I have to design an interface where the control signals from the > processor to my interface will be > > 1. LALE Used for latching address and making is two distict phases as > data and address phase. The LALE when HIgh is an Address phase and > when Address is low it is Data phase. =A0(From processor =A0to Design ) > 2. LWE it is a read and write signal single bit active low. (From > processor =A0to Design ) > 3. LOE Output enable active low =A0(From processor =A0to Design ) > 4. LCS is active low signal from processor to my interface. It is > used > for selecting the chip/slave chip select > 5. LA address 24 bits ( From processor =A0to Design ) > 6. LAD data 32 bits =A0(Bidirectional) > > I am thinking about runing my design at 300 Mhx 3X then the processor > LBC clock . The LBC clock is not coming from the processor to my > interface in fpga . So in my Interface i dont have the reference > clock > from the processor and all the above mentioned signals are from > Processor to my design except LAD which is bidirectional . > > I am using 2 flop synchronisers for the control signals and MUX-Latch > model for data latching and synchronization across the cock domain . > > My Confusion is that when we have multiple control signal passing the > clock =A0domain . Can we synchronize with 2 flops all the control > signals. > > Shall we use some glue logic to make sure we pass and synchronise > only > one control signal across the domain and later use this synchronous > signal value to select the mux-latch of other control signals that > are > input to a latch and sampled when we get the synchronized signal. > > In the scenario like this has anyone used multiple control signals to > pass the clock domain throgh individual 2 flop synchronizers for each > control lines. > > I am using 3X clock in the destination clock domain and has ample > time > to sample the signal in the interface block. > > Any suggestion ideas will be highly appreciated > > Thanks > > VipulArticle: 149319
On Oct 15, 5:35=A0pm, steve ravet <steve.ra...@gmail.com> wrote: > http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c... > > "The Translate process merges all of the input netlists and design > constraints and outputs a Xilinx Native Generic Database (NGD) file, > which describes the logical design reduced to Xilinx primitives. See > the following table for details. " > > translate=3Dngdbuild > > ie ngdbuild reads the UCF file and outputs the constraints in the .ngd > file. =A0You need to rerun ngdbuild. > > --steve > > On Oct 15, 4:13=A0pm, "MM" <mb...@yahoo.com> wrote: > > > Another mistery in ISE12.3. I am getting a bunch of errors during MAP p= hase, > > which all look like this: > > > ------------------ > > ERROR:Pack:2811 - Directed packing was unable to obey the user design > > =A0 =A0constraints (LOC=3DR29) which requires the combination of the sy= mbols > > listed > > =A0 =A0below to be packed into a single IOB component. > > > =A0 =A0The directed pack was not possible because: More than one pad sy= mbol. > > =A0 =A0The symbols involved are: > > =A0 =A0 BUF symbol "Ddr_A_11_OBUF" (Output Signal =3D Ddr_A<11>) > > =A0 =A0 PAD symbol "Ddr_A<11>" (Pad Signal =3D Ddr_A<11>) > > =A0 =A0 PAD symbol "Phy2_Mdio" (Pad Signal =3D Phy2_Mdio) > > > The problem is that R29 was indeed in the past assigned to Phy2_Mdio, b= ut it > > is commented out in the .ucf file I searched through the whole project = and I > > can't find where it is getting this from... I deleted all files I could > > imagine could have this information. I cleaned the project several time= s... > > All to no avail... > > > Where else can Xilinx store pad location constraints? > > > Thanks, > > /Mikhail The standard answer to all of this kind of horse-s**t is to "cleanup project files" which forces the tools to re-run everything. I found in some versions that "cleanup project files" did not clean enough and I had to remove the <projectname>_xdb folder in the project directory to really clean out everything. I think 12.2 does a better job of cleanup, but I wish Xilinx could just figure out that trying to save us a few seconds on every run by not compiling EVERYTHING ends up costing hours of debugging the tools. Regards, GaborArticle: 149320
"Gabor" <gabor@alacron.com> wrote in message news:cdfbe883-cd35-4406-be45-f6434ef6fe74@c10g2000yqh.googlegroups.com... > The standard answer to all of this kind of horse-s**t is to "cleanup > project files" > which forces the tools to re-run everything. I found in some versions > that > "cleanup project files" did not clean enough and I had to remove the > <projectname>_xdb folder in the project directory to really clean out > everything. Well I did all of that and I am still getting the same errors! /MikhailArticle: 149321
On 10/15/2010 3:43 PM, MM wrote: > "Gabor"<gabor@alacron.com> wrote in message > news:cdfbe883-cd35-4406-be45-f6434ef6fe74@c10g2000yqh.googlegroups.com... > >> The standard answer to all of this kind of horse-s**t is to "cleanup >> project files" >> which forces the tools to re-run everything. I found in some versions >> that >> "cleanup project files" did not clean enough and I had to remove the >> <projectname>_xdb folder in the project directory to really clean out >> everything. > > Well I did all of that and I am still getting the same errors! > > /Mikhail > > Possibly it's in one of your source files? Recursive grep the whole damn project looking for "R29", see if anything turns up. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 149322
Good advice. If the bus logic works like a typical async memory interface, he doesn't need to resync everything for metastability. There are either one or two timing control strobes depending on the details of the signals or how you wish to use them. You may be able to use either LALE or LCS as the single timing control or you may want to use LWE and LOE as a mutually exclusive pair of timing control strobes. Pick which way you want to do this based on the details of the timing from the CPU. Sync the timing control to your FPGA clock domain and detect the appropriate edge. Use this as a register enable for grabbing the address and data (on writes). The LOE will be used to enable the output drivers onto the LAD bus for reads. This is not a complex design, but how you do it depends on the details of the bus protocol and timing specs. It may be that you don't need to register the address/data or any of the other control signals at all. Rick On Oct 15, 5:48=A0pm, steve ravet <steve.ra...@gmail.com> wrote: > Vipul, this is a pretty standard and common problem in FPGAs. =A0You > can't independently synchronize a bunch of control signals when > crossing clock domains. =A0They'll all cross individually OK, but > there's no guarantee that they'll all end up in the same clock phase > on the other side, especially if the destination domain is faster than > the source domain. =A0You need to have a send/receive handshake that > consists of a single signal, synchronized in both directions. > > The control signals that need to cross are flopped directly in the > receiving domain without any synchronizers. =A0The handshake signal is > double flop synchronized and used as an enable on the flops that > receive the control signals. =A0By the time the double flopped sync > signals make it through to the flop enable, the other control signals > are stable and can be safely latched. > > An async FIFO is another possibility. > > Do a search on clock domain crossing and you'll come up with plenty of > answers. > > --steve > > On Oct 13, 1:48=A0am, jas <thejaspr...@gmail.com> wrote: > > > Hi Everyone, > > > I am designing a system where I am interfacing a Motorolla processor > > in my system for read and write data. This processor is on the board > > where my fpga will interact with it. The processor is the master mode > > always and the salave is my interface design and the fpga. > > > The motoroll Processor will have LBC Local bus controller signals > > will > > be comunicating to my interface inside the FPGA. > > > The processor can run at configurable clock of 33 MHz to 133 MHz. The > > address bus is 24 Bits and tye data bus is 32 bits. > > > I have to design an interface where the control signals from the > > processor to my interface will be > > > 1. LALE Used for latching address and making is two distict phases as > > data and address phase. The LALE when HIgh is an Address phase and > > when Address is low it is Data phase. =A0(From processor =A0to Design ) > > 2. LWE it is a read and write signal single bit active low. (From > > processor =A0to Design ) > > 3. LOE Output enable active low =A0(From processor =A0to Design ) > > 4. LCS is active low signal from processor to my interface. It is > > used > > for selecting the chip/slave chip select > > 5. LA address 24 bits ( From processor =A0to Design ) > > 6. LAD data 32 bits =A0(Bidirectional) > > > I am thinking about runing my design at 300 Mhx 3X then the processor > > LBC clock . The LBC clock is not coming from the processor to my > > interface in fpga . So in my Interface i dont have the reference > > clock > > from the processor and all the above mentioned signals are from > > Processor to my design except LAD which is bidirectional . > > > I am using 2 flop synchronisers for the control signals and MUX-Latch > > model for data latching and synchronization across the cock domain . > > > My Confusion is that when we have multiple control signal passing the > > clock =A0domain . Can we synchronize with 2 flops all the control > > signals. > > > Shall we use some glue logic to make sure we pass and synchronise > > only > > one control signal across the domain and later use this synchronous > > signal value to select the mux-latch of other control signals that > > are > > input to a latch and sampled when we get the synchronized signal. > > > In the scenario like this has anyone used multiple control signals to > > pass the clock domain throgh individual 2 flop synchronizers for each > > control lines. > > > I am using 3X clock in the destination clock domain and has ample > > time > > to sample the signal in the interface block. > > > Any suggestion ideas will be highly appreciated > > > Thanks > > > Vipul > >Article: 149323
rickman skrev: > On Oct 9, 12:55 pm, Ulf Samuelsson <u...@notvalid.atmel.com> wrote: >> Peter Alfke skrev: >> >>> On Oct 4, 7:27 pm, rickman <gnu...@gmail.com> wrote: >>>> Rick >>>> PS I use the computer format for dates 20101004 or preferred 101004, >>>> at least in my code. >>> Rick, your sequence is also the official method used in Sweden. >> Yes, but it is actually an International Standard (ISO 8601). >> You would normally write "2010-10-04" for readability. >> "10-10-04" risk wraparound problems. > > Not in my lifetime! Six digits works just fine for my needs. I don't > expect any of my code to survive for 90 more years either. It is also a matter of clarity. 101010 is clearly 10 October 2010. What is 111210? Is it: Dec 11, 2010 ? Dec 10, 2012 ? The standard is there to remove such abiguity. 2010-11-12 is clear. (Noone is using YYYY-DD-MM) > > >> All Swedish citizens (and Companies) get a personal number: >> "YYMMDD-XXXX" where YYMMDD is birthdate, and XXXX makes >> the number unique. >> >> We have elderly people that get advertisement for baby stuff >> after they reach 100+, since year is only two numbers. > > Depending on the dental care in Sweden they may be ready for baby food > again. ;-) > > >> The system copes with that, since your number changes to >> "YYMMDD+XXXX" once you'r past 100, but it is rarely used >> and many/most applications does not allow >> you to feed in the "+" sign. > > So their systems have a "negative" attitude towards age? > No, just ignorance. > RickArticle: 149324
On Oct 15, 11:48=A0pm, steve ravet <steve.ra...@gmail.com> wrote: > Vipul, this is a pretty standard and common problem in FPGAs. =A0You > can't independently synchronize a bunch of control signals when > crossing clock domains. =A0They'll all cross individually OK, but > there's no guarantee that they'll all end up in the same clock phase > on the other side, especially if the destination domain is faster than > the source domain. =A0You need to have a send/receive handshake that > consists of a single signal, synchronized in both directions. > > The control signals that need to cross are flopped directly in the > receiving domain without any synchronizers. =A0The handshake signal is > double flop synchronized and used as an enable on the flops that > receive the control signals. =A0By the time the double flopped sync > signals make it through to the flop enable, the other control signals > are stable and can be safely latched. > > An async FIFO is another possibility. > > Do a search on clock domain crossing and you'll come up with plenty of > answers. > > --steve > > On Oct 13, 1:48=A0am, jas <thejaspr...@gmail.com> wrote: > > > Hi Everyone, > > > I am designing a system where I am interfacing a Motorolla processor > > in my system for read and write data. This processor is on the board > > where my fpga will interact with it. The processor is the master mode > > always and the salave is my interface design and the fpga. > > > The motoroll Processor will have LBC Local bus controller signals > > will > > be comunicating to my interface inside the FPGA. > > > The processor can run at configurable clock of 33 MHz to 133 MHz. The > > address bus is 24 Bits and tye data bus is 32 bits. > > > I have to design an interface where the control signals from the > > processor to my interface will be > > > 1. LALE Used for latching address and making is two distict phases as > > data and address phase. The LALE when HIgh is an Address phase and > > when Address is low it is Data phase. =A0(From processor =A0to Design ) > > 2. LWE it is a read and write signal single bit active low. (From > > processor =A0to Design ) > > 3. LOE Output enable active low =A0(From processor =A0to Design ) > > 4. LCS is active low signal from processor to my interface. It is > > used > > for selecting the chip/slave chip select > > 5. LA address 24 bits ( From processor =A0to Design ) > > 6. LAD data 32 bits =A0(Bidirectional) > > > I am thinking about runing my design at 300 Mhx 3X then the processor > > LBC clock . The LBC clock is not coming from the processor to my > > interface in fpga . So in my Interface i dont have the reference > > clock > > from the processor and all the above mentioned signals are from > > Processor to my design except LAD which is bidirectional . > > > I am using 2 flop synchronisers for the control signals and MUX-Latch > > model for data latching and synchronization across the cock domain . > > > My Confusion is that when we have multiple control signal passing the > > clock =A0domain . Can we synchronize with 2 flops all the control > > signals. > > > Shall we use some glue logic to make sure we pass and synchronise > > only > > one control signal across the domain and later use this synchronous > > signal value to select the mux-latch of other control signals that > > are > > input to a latch and sampled when we get the synchronized signal. > > > In the scenario like this has anyone used multiple control signals to > > pass the clock domain throgh individual 2 flop synchronizers for each > > control lines. > > > I am using 3X clock in the destination clock domain and has ample > > time > > to sample the signal in the interface block. > > > Any suggestion ideas will be highly appreciated > > > Thanks > > > Vipul Hi Rick /Steve Thanks for your reply. The processor might send continuous data and i don't have the control for the processor. In handshake mechanism the processor might have to see my response then send the next data. Rick you are right that we can use LOE for read case to latch data in the LAD bus. All signals are mutually exclusive and it is typically like a async memory interface. I have googled but did dot get any good relevant text on this that talk about async memory interface . All talk about CDC issues and control and data bus synchronization. I am looking for some thing on async memory interface or something that is async and have to be synchronized at the interface to be used by other logic in the design. I will look into it the way you both have advised. Thanks Vipul
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