Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Is there anyone out there who uses an mcALLPROG, the universal programmer that appeared as a project in the now (sadly) non-existant German magazine 'mc' back in 1988? It was marketed by a company (HAMIS) from Braunschweig? I bought 2 of the things back then. The company have since disappeared and since my last update is 8 years old I have trouble programming nearly all 16V8 GAL types (except ST and Lattice). Does anyone know what happened to the company (HAMIS)? If they don't exist any more, can anyone please send me a newer version of the PC software and the EPROM hex file. My email is: cardware@eunet.yu Thanks a lot, ViktorArticle: 6801
Peter <z80@dserve.com> wrote in article <33bed6b4.85681393@news.netcomuk.co.uk>... > > I would also add that one should avoid doing low-power designs, i.e. > ones where one is gating clocks to parts of the circuit to reduce > dynamic Icc. > > With the older XC3000 parts one could do this OK, just by assigning > e.g. a long-line to the clock. But the present-day versions are not > only much faster but also have a different distribution of delays > within the device, and this just does not work. > > I have concluded that the only way is what Xilinx nowadays recommend, > i.e. use the global clock for *every* D-type, and use clock-enables. > But this makes it draw a lot of current than would be the case > otherwise. > > for a general reply (not xilinx-specific) how about using techniques such as clocking flops on opposite edges, using latches w/ multi-phase non-overlapping clocks, use ripple counters instead of synchronous ones where applicable, etc. i do this all the time for micropower designs. driving the clock networks in fpga's tends to get a bit expensive. also, some architecutres permit driving the low skew clocks from logic so you can shut it down when you don't need it or for a bit more power you can drive the logic-generated clock off chip and then on through dedicated pins. note that some architectures don't permit low power structures like ripple counters. rkArticle: 6802
Peter Alfke <peter@xilinx.com> wrote in article <33B3F9CA.3829@xilinx.com>... > Here comes the unambiguous answer from Xilinx Applications: > <snip> > Xilinx XC4000XL and XC5200XL pins have a circuit structure that > eliminates the classical clamp diode between pin and Vcc. The pin can > thus be driven as High as 5.5 V irrespective of the actual supply > voltage on the receiving input. These devices are, therefore, > unconditionally 5-V tolerant, and the user can ignore all interface > precautions. These devices achieve their excellent ESD protection ( > several thousand volts ) by means of a patented diode-transistor > structure that does not rely on Vcc. " finally! been bugging vendors for years for this feature. and i keep on ordering cd4050b's for down level shifting and power isolation;. just ordered another batch last week and eventually they'll probably stop making these antique parts (which are slooooooow). also note the chip express guys have some nice interface circuits on their cx family which i'm starting to look at real seriously. <snip snip> > I am happy to report that we solved this ( admittedly knotty ) problem > in the best possible way for the user. You can intermix XC4000XL and > XC5200XL freely with 5-V logic, and you don't even have to worry about > power sequencing. > > ( Well, the 5-V inputs should have "TTL-like thresholds".) if i read this correctly (and it is a bit late) 5-v circuits that receive a signal from the xl series devices must have ttl-compatible thresholds; this implies a vih of 2.0 and along with that comes the vil of 0.8. so, this has two implications: 1. the delta-icc current, per input, of the receiving device must be added to the power consumption of the card. from my ti ac logic book, this is a max of 1 mA/input (max) with Vin @ 3.4 volts. from my ti hc logic book, this is a max of 3 mA/input (max) with Vin @ 2.4 volts. unfortunately this power consumption can add up if there are a lot of pins (and todays fpga's have a ton) and this energy usage does no useful work. for micropower designs, it would be nice to have the input stage tolerant of 5v levels (and this looks to be well done), have the core run @ 3.3 volts, and have the output stage output either 3.3 or 5 volt CMOS levels. any comments? the chip express cx series does this, i beleive; are there other families that have this capability? 2. the vil of 0.8 that comes with the ttl thresholds really hurts the system noise margin quite a bit from cmos levels. and fighting the logic '0' noise levels on old ttl systems was never any fun. > > I hope this clarifies the confusion. > > Peter Alfke, Xilinx Applications interesting topic, rkArticle: 6803
In some fast digital scopes they increase the vertical resolution of
repetitive signals by sampling at random different times during each period,
and "filling in" more holes on the screen as time goes on. Thus if you have
an ADC with a 2GHz bandwidth but only a 100MHz sample rate and low sample
jitter, you can still effectively sample at 2GHz.
So my question is... how do they accurately time these "random" samples? Are
they sythesized (perhaps with a counter or shift register running at 2GHz),
are they timed (with a counter running at 2GHz and use some other method of
generating random clocks for the ADC), or do they use delay lines with
selected taps or timing vernier chips?
Does anyone know? Are there chips that I can buy which accept a trigger
input and which generate these timing pulses available? Do they use
discrete ECL? Do they have custom chips?
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 6804
Andrew DeWeerd <deweerd@mindspring.com> wrote in comp.arch.embedded:
AD> Schlumberger (France-based) or Gemplus (???-based).
Gemplus is french, too. However, the GPM496, GPM896 cards are the worst to
program for I've ever seen.
Siemens is another big one in that market. I would prefer a Siemens card
over a Gemplus every day.
Then there are the simple I2C EEPROM cards which should be available from
various manufacturers. They're just a usual I2C EEPROM like a 24C08 embedded
in a plastic card. Of course, they don't know anything about security...
Olav (who doesn't work for Siemens)
--
Olav "Mac" Wölfelschneider wosch@rbg.informatik.th-darmstadt.de
PGP fingerprint = 065F66B32AAD7D2DB719673C95A79DAF
But let your communication be Yea, yea; nay, nay: -- Matthew 5:37
for whatsoever is more than these cometh of evil. on computers
Article: 6805Hi I've just started using FPGAs (XC6200) for my research and I would appreciate any advice on the following problem. I'm working with simple and regular designs but require complete control over place and route. So it seems better (and cheaper) to work at (or close to) the EDIF level rather than use an expensive HDL or schematic tool. So is there any place where I can get info on the EDIF subset understood by Xilinx tools, esp. XACT 6000? Please send an email copy while replying. Thanks in advance.Article: 6806
I can't exactly comment on the use of the board, since I haven't done anything with it yet, but I can say that APS do look after their customers; I'm in the UK and hence Xilinx have an attitude problem with me purchasing one of APS's all in kits and registering it; however Richard has worked to resolve the problem. The board is well made, half size PC, double side, silk screen printed, one patch, documentation is good (including schematics), and there is a disk with stuff on it. There are jumpers and sockets for things you are likely to want to do, and it been plugged into a PC so I guess it's tested! I'm a happy customer. One of those engineers Richard mentions just taking their first real poke at FPGA, for own product purposes. Currently just trying to get my head around being able to draw a state diagram and have it made magically into silicon... In article <33AA8D39.23B6@erols.com> aaps@erols.com writes: > Marinos J. Yannikos wrote: > > > > Is the APS-X84 kit as good as it looks on http://www.erols.com/aaps/ ? > > I'd like to experiment a bit with various algorithms and this looks as if > > it would suffice, while the price does not hurt much. However, since I'm > > new to FPGAs, I'm not at all sure I can tell. Any comments would be much > > appreciated. > > > > Thanks, > > -nino > Marinos, > > I am not at all unbiased but we have sold dozens of these kits in the > last several months, and gotten only rave reviews. I have never gotten > even one complaint, (except that at one point we ran out and had a > delivery delay of about 2 weeks). The kits are just as they seem --a > great value-- We are in the midst of developing low cost SRAM, FIFO and > AD/DA modules which plug in to the top of the X84 boards connectors, and > allow for various scenarios to be tried with the board. We are proud to > have sold our X84 products to Universities and large conpanies like ITT, > 3M, Texas Instruments, and Hewlett Packard. But the bulk of our kits > have been sold to individual engineers who are new to FPGAs, or are > either starting thier own side business or want unrestricted access to > their own kits. APS is committed to supporting these kits with tech > notes and low cost support modules to encourage and promote FPGA > coding. > Hopefully some who are avid readers of this newsgroup will chime in and > give you a more unbiased view. Feel free to contact me with any > questions you have concering these kits. > > > Richard Schwarz, President > > Associated Professional Systems(APS) -- ----------------------------------------+------------------------------------ David Buckley of Electric Solutions Ltd | Email: dbuckley@esl.tex.com Services to the Computing,Electronics | and Entertainment industries. | Calling from South London, in the UK | -----------------------------------------------------------------------------Article: 6807
Yes, it can be done. But it requires one to spend time on clever structures where glitches due to skew don't matter (e.g. Gray code counters) rather than on the job itself. There should be *local* clock nets. In the past, long lines worked fine, and in fact were recommended by X. engineers, but definitely not any more. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 6808
In article <33b7dcd4.6054265@news.idx.com.au>, TJ <hellotwt@twt.aust.com> writes >I would like to implement a security entry/logging functions using >smart cards or any other memory cards. I would also like to design the >reader using microcontroller. >Are these cards expensive? Can I get them in Australia? Do Smart Card >manufacturers publish data sheets on how to interface them? > >THANKS IN ADAVANCE > > try http://www.aks.com they do a smart card development kit. I have no conection or info on the company other than having seen their ad in a magazine. /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ \/\/\/\/\/\ Chris Hills,Tamworth Staffs /\/\/\/\/\/ /\/\/\/\/\/\/\/\/\ B77 5PG England /\/\/\/\/\/\/\/\ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/Article: 6809
Dear Internet user, If you are paying for your Internet services then you have not heard about 1stFamily. We have a marketing method that guarantees you will not have to pay one dollar to access the Internet. * You will never again have a busy signal ! * You will always have the fastest access you have ever seen ! * Residual income for the rest of your life ! * and much much more. This opportunity is for YOU to take advantage of ! Do you wish to continue the rest of your life paying $19.95/month to access the Internet when you can access it for free with speed and reliability that exceeds the other competitors ??? We did not think so. That is why our company is the best and fastest growing of it's kind and will soon compete with AT&T and MCI and all the big companies in providing Internet Service. For complete information please mailto:ASE1000@1stfamily.com and type "More Info" in the subject box. You will receive our webpage address where you can get enrolled in seconds !! _______________________________________________________ «¤»¥«¤»§«¤»¥«¤»§«¤»¥«¤»§«¤»¥«¤»§«¤»¥«¤»§«¤»¥«¤»§«¤»¥«¤» ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ Ray (Sponsor ID# SAF5197) Stop Paying for Internet Access http://members.aol.com/upline mailto:ase1000@1stfamily.com _______________________________________________________ «¤»¥«¤»§«¤»¥«¤»§«¤»¥«¤»§«¤»¥«¤»§«¤»¥«¤»§«¤»¥«¤»§«¤»¥«¤» ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯Article: 6810
Try this page for more details: http://www.embedded-solutions.ltd.uk/ProdApp/handelc.htm ----------- Tony Williams Philips Research LabsArticle: 6811
In article <33b7dcd4.6054265@news.idx.com.au>, hellotwt@twt.aust.com (TJ) says: > >I would like to implement a security entry/logging functions using >smart cards or any other memory cards. I would also like to design the >reader using microcontroller. >Are these cards expensive? Can I get them in Australia? Do Smart Card >manufacturers publish data sheets on how to interface them? UTIMACO is a leading supplier of smart card readers in Europe. The Cardman-II hooks up to a V.24 (==RS232) port of about any computer, there are software drivers for DOS, OS/2, Win 3.11, Win 95, Win NT, UNIX workstations and so on. Cardman-II does not need an additional power supply and reads/writes synchronous cards (==eeprom cards) as well as asynchronous cards (==processor cards). Cardman Compact fits into a PCMCIA slot and is software compatible to the Cardman-II. UTIMACO is also able to supply modified OEM versions of these smart card readers, depending on quantity. From Australia, your best contact would probably be UTIMACO United Kingdom. Send me an email if you need the telephone number. Gregor Glawitsch | Tel: ++43 (0)732 655 755 - 33 Utimaco Safe Concept GmbH | Fax: ++43 (0)732 655 755 - 5 Europaplatz 6 | email (office): Gregor.Glawitsch@utimaco.co.at A-4020 Linz, Austria | email (home) : Gregor.Glawitsch@magnet.at Disclaimer: Just an engineer, not speaking for the company.Article: 6812
Robert M. M=FCnch wrote: > = > > -----Original Message----- > > From: hunterbp@magellan.Colorado.EDU (Brian P Hunter) > > Subject: Verilog Simulation and Synthesis for FPGA Devices > > > > These are the vendors I'm looking at right now: > > Synario with FPGA Express > > VeriBest with FPGA Express (from right here in Boulder!) > > ViewLogic's ViewDraw, VCS, and FPGA Express > > > > Can anyone here sway me in the right direction? Thanks in advance! > > > > > [Robert M. M=FCnch] Yes, don't use Veribest! Their programs are a > collection of bugs! Nothing works! We tried the synthesis and their > optimizer is real good -> you won't get any signal in the result if you= > are lucky and the program doens't crash your machine! Try Synopsis FPGA= > Express and VCS. Aren't You mixing things now? VeriBest's synthesis part IS Synopsys's FPGA Express, which You are recommending. As far as I know people are using it quite succesfully for FPGA synthesis. We are using front-end and simulation tools from VB together with Synopsys Design Compiler and I would say that they don't contain more bugs than any other piece of EDA software I've seen. Of course I also would like to see a totally bug-free one, but ... Regards, Veli-Matti Karppinen -- = *************************************************************************= ** ** ** Veli-Matti Karppinen Internet: ventti@fincitec.fi ** ** Fincitec Oy ** ** P.B. 11 tel. +358-16-221490 ** ** FIN-94601 KEMI,FINLAND fax. +358-16-221561 ** ** ** *************************************************************************=Article: 6813
In article <ECIqFs.16J@world.std.com>, jhallen@world.std.com (Joseph H Allen) says:
>
>
>In some fast digital scopes they increase the vertical resolution of
>repetitive signals by sampling at random different times during each period,
>and "filling in" more holes on the screen as time goes on. Thus if you have
>an ADC with a 2GHz bandwidth but only a 100MHz sample rate and low sample
>jitter, you can still effectively sample at 2GHz.
>
>So my question is... how do they accurately time these "random" samples? Are
>they sythesized (perhaps with a counter or shift register running at 2GHz),
>are they timed (with a counter running at 2GHz and use some other method of
>generating random clocks for the ADC), or do they use delay lines with
>selected taps or timing vernier chips?
I believe Hewlett-Packard described their system in the Hewlett-Packard
Journal, many years ago. Contact HP and see if you can get a reprint.
>Does anyone know? Are there chips that I can buy which accept a trigger
>input and which generate these timing pulses available? Do they use
>discrete ECL? Do they have custom chips?
I don't know of any timing chips which would really do the whole job
that you are asking for. The Analog Device AD9500 and AD9501 are
effectively digitally programmable monostables which might serve as a
beginning, and the Motorola MC100E195/6 are digitally programmable
delay lines with a range of 2nsec.
The oscilloscope manufacturers definitely use their own custom chips -
TriQuint was originally the Tektronix in-house chip source. When designing
such systems, there are real advantages to using balanced signals
and current-steering logic for interconects, so there is a preference
for ECL over TTL and CMOS in the vicinity of the input.
I've done a similar sort of system, with systematically interleaved
sampling, for a stroboscopic electron microscope. We use a mixture
of Gigabit Logic GaAs and 100k ECL with a small admixture of discrete
components. E-mail me if you want more details.
Bill Sloman (sloman@sci.kun.nl) | Precision analog design
TZ/Electronics, Science Faculty, | Fast analog design and layout
Nijmegen University, The Netherlands | Very fast digital design/layout
| e-mail for rates and conditions.
Article: 6814TJ wrote: > > I would like to implement a security entry/logging functions using > smart cards or any other memory cards. I would also like to design the > reader using microcontroller. > Are these cards expensive? Can I get them in Australia? Do Smart Card > manufacturers publish data sheets on how to interface them? > > THANKS IN ADAVANCE There are about a half dozen different smartcard interface protocols out there, all using the same connector. I did a universal smart coard controller in a xilinx 3042-7 along with a keyboard controller and a barcode reader interface a few years back. Basically, I reloaded the xilinx with a smartcard specific program after running a test to determine what flavor smartcard was inserted. I do remember Gem and Seimens as two of the card suppliers. There were others, but I don't remember their names now. Each of the smartcards has datasheets similar to IC datasheets associated with them. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 6815
Hi, I have been doing a Xilinx XC4013E PCI design using the PCI Logicore. I have been doing the design as a mixed schematic/VHDL design. Most of my memory elements and FIFOs internal to the FPGA are done in the Xilinx/Viewlogic schematic models and I create the controls to these using VHDL. I have been functionally simulating my VHDL using the Viewlogic Fusion/Speedwave VHDL functional simulator. I have functionally simulated my design and it seems to be working quite well. I have compiled my VHDL using Exemplar/Galileo and created an XNF file for each of my VHDL logic blocks. I then use the XACT tool to create a WIR file which is used to create the Viewlogic VSM file. Anyway, my problem is that it seems that the Xilinx XNF2WIR is not converting the XNF file verbatim. For example: Given a 32 bit input address bus, I want to strip off the bottom 16 address bits and pad the upper 16 bits with '0'. My code looks something like: out_addr(31 downto 0) <= "0000000000000000" & in_addr(15 downto 0); XNF to wire doesn't show the uppper address bits getting set to anything and the simulator sets the value as 'X'. Knowing this, I have a real tough time believing anything else XNF2WIR generates. I guess I am looking for a little advice on how to handle the mixed logic design. Does anybody fully trust the functional simulator to generate the same logic as the gate level synthesis. I know in an ideal world it shouldn't matter, but the world is hardly perfect. Does anybody know of a switch in XNF2WIR that may fix this, or do I just wait for the M1 tool to be installed in our tool suite here. Thanks, RJL -- Rod Leiting Rockwell International 400 Collins Rd. NE Cedar Rapids, IA 52498 mailto:rjleitin@collins.rockwell.com The opinions voiced are the opinions of the author and not Rockwell.Article: 6816
"Richard B. Katz" <stellere@erols.com> wrote:
> finally! been bugging vendors for years for this feature. and i keep on
> ordering cd4050b's for down level shifting and power isolation
You could also try quickswitch chips for level shifting. These have
almost no delay, and come in wide bus versions.
See
http://www.qualitysemi.com/ftp/lit_ftp/app_note/an11.pdf
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 6817Regi$ter Online!'s "Design-YOURware" is a programming proposal and creativity tool allowing you to design the specific type of software you need and want. The total package of "Design-YOURware" is summed up as a group of programming proposals presented to programmers and attracting bids for the compilation of your creations. Within this package, you'll find 27 separate programming proposals containing all the components you may ever want in a program with options to add your own ideas. All coding and/or programming is performed by the software developer who replies with an appropriate bid, and signs a private "work-for-hire" contract with you (sample included). After you have edited and saved the proposal to read as you want it to, copy and paste it into your email program or newsgroup program to send it to where you will attract bids (areas listed in file) and prepare your "work-for-hire" contract (sample included) while you wait for responses. Requires a Rich Text Format Editor and Unzipping Program. Download Design-YOURware @ http://registerline.com/yourware.htm or email yourware@registerline.com!Article: 6818
Problem solved. Bad solder joint. Peter Alfke, Xilinx ApplicationsArticle: 6819
yeah, it's a pain. and a lot of the design tools don't work any more (synchronous counters, state machines, etc.). note that the atmel at6000 series has column clocks - that's their 'resolution.' unfortunately, you can't build a lot of simple, low-power structures like ripple counters out of it. the actels, which i use mostly, let's you make lots of high-skew clocks. in some of their 3200dx models, they give you 4 extra quadrant clocks which are low-skew, so you don't have to drive the whole chip. rk. Peter <z80@dserve.com> wrote in article <33b7aeb5.41363347@news.netcomuk.co.uk>... > > Yes, it can be done. But it requires one to spend time on clever > structures where glitches due to skew don't matter (e.g. Gray code > counters) rather than on the job itself. > > There should be *local* clock nets. In the past, long lines worked > fine, and in fact were recommended by X. engineers, but definitely not > any more. > > > Peter. > > Return address is invalid to help stop junk mail. > E-mail replies to z80@digiserve.com. >Article: 6820
one favorite i left off before is using johnson twisted ring counters and using appropriate combinations of taps for glitchless state machine decodes. rk _______________________________________ Peter <z80@dserve.com> wrote in article <33b7aeb5.41363347@news.netcomuk.co.uk>... > > Yes, it can be done. But it requires one to spend time on clever > structures where glitches due to skew don't matter (e.g. Gray code > counters) rather than on the job itself. > > There should be *local* clock nets. In the past, long lines worked > fine, and in fact were recommended by X. engineers, but definitely not > any more. > > > Peter. > > Return address is invalid to help stop junk mail. > E-mail replies to z80@digiserve.com. >Article: 6821
I have a few links to VHDL tutorials at 'http://www.optimagic.com/tutorials.html' and to various related newsgroups at 'http://www.optimagic.com/newsgroups.html'. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com Stephen D. Scott <sds@cardinal.cs.wustl.edu> wrote in article <5otuk6$4h8@cardinal.cs.wustl.edu>... | Gianpaolo Scassellati wrote: | >Hi there, | > | > I am learning VHDL but I have some troubles. In particular, I | >need to know where I can find a online manual on the net, and if there | >are any specific newsgroups on VHDL. | > | >Bye. | > Gianpaolo | | http://server.vhdl.org/viuf/ is the home of the VHDL International | Users' Forum and has lots of good information, including an extensive | FAQ with a list of VHDL books. http://www.erols.com/aaps/x84lab/ has a | VHDL tutorial, but I haven't tried it myself so I cannot vouch for it. | Finally, try the newsgroup comp.lang.vhdl. | | Stephen | | -- | Stephen D. Scott sds@cs.wustl.edu | Department of Computer Science 535 Jolley Hall | Washington University, Campus Box 1045 phone: (314) 935-4425 | One Brookings Drive fax: (314) 935-7302 | St. Louis, MO 63130-4899 URL: http://www.cs.wustl.edu/~sds/ |Article: 6822
There is a fairly comprehensive list of FPGA boards and reconfigurable computing systems at 'http://www.optimagic.com/boards.html'. Most of the boards listed are for Xilinx FPGAs but there are a few Altera boards in there, too. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com Steve Martindell <a840272@# Replace this line with your news domain> wrote in article <5os2ed$kk6@hammerhead.dadd.ti.com>... | I'm looking for a board that would have a Xilinx or Altera FPGA(either | soldered or socketed) with all the FPGA I/O pins brought out to a | connector(s). A board like this would allow me to quickly protype | designs without having to send out to a board-shop. Does anyone | know of a company that makes a product like this? | | thanks, | Steve Martindell | s-martindell@ti.com |Article: 6823
Have you thought about using a PIC 16C84 ? These are made in wafer card form as well as the dil chip, which is the same size as a standard smartcard. These can be easily reprogrammed, and should have enough enough memory for your application, plus the program can be code protected in the chip for security. Just a thought, Gareth Downes-Powell -- ****************************************************************** * PIC 16C84 Infosite * * http://ds.dial.pipex.com/mecsystems/ * * Suppliers of PIC 16C84 Chips, and PIC Development Boards * * Home to the EVERYDAY PRACTICAL ELECTRONICS PIC MIRROR SITE !!! * * 16C84 / 16F84 Programmer on Sale NOW !!! * ******************************************************************Article: 6824
Has anyone used the Xilinx 95xx series parts? If so, what is the tool flow...ie. what programs do you run to get it to make a downloadable design.... I am using Viewlogic WVOffice as the front end.... I assume I have to run wir2xnf...but what then? I am running these tools under NT 4.0.... Any input would be appreciated... Austin Franklin darkroom@ix.netcom.com remove the number from the reply address to reply directly...
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z