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In article <3746937c.1197113@nntp.netcomuk.co.uk>, Stuart Clubb <s_clubb@NOSPAMnetcomuk.co.uk> writes <snip> >Closer examination and interpolation of Synopsys financial figures >from '98 reveals that their revenue stream is probably now close to >being 45% maintenance. Synthesis and associated product accounts for >45-50% of total revenue so the SEAT sales of Synthesis AND "Design >creation" products might soon account for less than a quarter of >revenue. Take a look at the Synopsys line card and there are quite a >few products that could be termed "design creation". With a seat of DC >costing some 100K, the actual number of DC seats being sold might not >be as impressive as the headline revenue figure might suggest. > >I heard a rumour that Synopsys sales people are no longer remunerated >on DC sales as their job is to "sell-up" on the back of the headline >product. Could be just a rumour though... >Cheers >Stuart >An employee of Saros Technology: >Model Technology, Exemplar Logic, TransEDA, Renoir. >www.saros.co.uk Sounds like you're just back from one of those Mentor sales meetings. I don't know whether what you say is true w.r.t. Synopsys, but it occurs to me that you could substitute "Mentor" for "Synopsys" in all of the above. DavidArticle: 16476
Jim Kipps <jkipps@viewlogic.com> writes:
> Evan-
>
> Thank you for mentioning other features of 3.1 in a good light, but I
> stand behind my
> statement that FPGA Express is competitive with regard to language.
>
> Synplify and Leonardo both support broader subsets of VHDL and Verilog,
> but only
> FPGA Express (and FPGA Compiler II) is fully Design Compiler compatible.
What you are saying is basically that Synplify and Leonardo have
better language support, but the FPGA Express is the only one that
have the same "features" as Design Compiler, and that is what counts.
Wow, what an argument...
Homann
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 16477>I'm keen on learning the real reasons behind >the apparent Windows orientation of the EDA industry. Because nearly everybody has a PC running windoze. There is also nothing much wrong with NT4, reliability-wise. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 16478
On Tue, 25 May 1999 09:18:42 +0100, David Pashley <David@edasource.com> wrote: <snip> >Sounds like you're just back from one of those Mentor sales meetings. Never been invited, so I wouldn't know :-) >I don't know whether what you say is true w.r.t. Synopsys, but it occurs >to me that you could substitute "Mentor" for "Synopsys" in all of the >above. As I work for an independent distributor (ie, NOT owned by Mentor) and do not explicitly represent Mentor Graphics per-se, that's hard for me to accurately gauge. I am only involved with the HDL side of their tools, which is Renoir/MTI/Exemplar as stand-alone business units of Mentor. I know nothing of the vast plethora of other tools addressing different areas. However, you are probably right though, The same could also probably be said of Cadence's EDA revenue and any other long-established EDA company (if there is such a thing). My point was that in a well established (with limited access) market, the term *competitive* does not necessarily mean the same measurement metrics are applicable. Cheers Stuart An employee of Saros Technology: Model Technology, Exemplar Logic, TransEDA, Renoir. www.saros.co.ukArticle: 16479
Jonathan Feifarek <feifarek@ieee.org> wrote: : Tim Tyler wrote: :> While I'm all in favour of a portable, universal means of describing :> algorithms that enables them to be implemented efficiently on parallel :> hardware, unfortunately, Java doesn't look /remotely/ like what I :> envisage. : I agree, though there seems to be enough work using this as a start : (J-Bits and JHDL are written in Java -- plus check out this cool : product-in-process: http://www.lavalogic.com/products.html ) [...] "Forge compiler technology is part of the LavaLogic Forge Series of Hardware Development Tools. It automatically compiles Java source code into efficient Verilog-HDL files compatible with industry-standard RTL synthesis and simulation tools." : [...] that I find it hard to ignore. I'm not recommending people /ignore/ it. I should think that Java and programmable logic make a better match than a good number of existing C based tools. However, if using a serial language to target a parallel machine, Java appears to have a number of features which make the process of hardware compilation harder than it would otherwise be, as it was not designed with this sort of parallelism in mind. Java objects can have static members. Java's concurrency paradigm is almost entirely thread-based. These sorts of thing make implementation on shared-memory atchitectures [bleurgh] look attractive and implementation on fine-grained parallel architectures unnecessarily messy. AIUI, more functional approaches would help. Erricson's open-source Erlang (http://www.erlang.org/white_paper.html) is an example of a message-based concurrent language. IIRC, this actually has a compiler which can traget FPGAs. TAOS's Elate (http://www.tao-group.com/) - though not terribly functional - is another such concurrent-from-the-ground-up approach. To me the whole notion of using smart compilation to target (largely) serial code at parallel architectures just seems like a way of mobilising the vast quantities of legacy serial code on parallel machines. It's on a par with pipelines, "EPIC" and other attempts to squeeze parallelism out of a serial stream of instructions. I think programmers targetting parallel machines should target their code for such machines if they want good performance. This will generally mean designing something like circuitry rather than making a serial recipe. :> I envisage something like a "rubber circuit" which 'stretches' to fit :> the characteristics of the target hardware, while retaining the relevant :> inter-component distances and ratios, for purposes of retaining correct :> synchronous operation. : This sounds like an interesting concept, but I'm not sure I follow. I'm not sure what more to say - the idea is still an embryonic one. The design would not know what hardware it would be implemented on, though it would assume that it was capable of significant parallelism - as it's not really possible in general to write algorithms which are completely neutral with respect to such a fundamental architectural feature. In a number of respects my idea sounds similar to the icon-oriented scheme of yours - in that it would represent the connections between the components in a visual schematic way, rather than in a textual format. Textual formats (and HDLs) are best suited to designing serial programs where the serial nature of the spoken work matches the serial nature of the algorithm being expressed. When designing something parallel it makes sense to try and get away from a description in a form which is inherently serial due to its being based on words and symbols, and go for a more visual representation, where possible. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com Magnet: Windows cleaner.Article: 16480
Zoltan Kocsi wrote: ...snip... > Since the first scenario doesn't sound very plausible and the second > is rather malicious, I'm keen on learning the real reasons behind > the apparent Windows orientation of the EDA industry. > > Zoltan Perhaps there is a third choice which simply has to do with marketing and cost. If I had the choice of selling one system to say 40% of the market or increasing my market share to, say 45%, by selling two systems and doubling my development costs, I think I would choose the one platform approach. My guess is that in the last 3 years or so, the vendors are seeing that customers who at one time were Unit die-hards, are now willing to use Windows. I would also expect that a lot of potential Windows customers would not be willing to go to Unix. Whenever the vendors are asked about Linux versions of their software, they say they will do it when the customer demand is there. The bottom line is that they will sell what customers are most likely to buy. I would also point out that Unix development is more expensive. The machines cost more, the software costs more, and perhaps the developers cost more (not sure about this last one). -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16481
Jonathan Feifarek wrote: > Michael, > In a way, you do own the processor with a Reconfigurable Computer, > because the degree of parallelism possible. > In theory, if one process (thread) need more logic than is available, > the logic allotted to that process can be reconfigured to perform the > rest of the thread without affecting the context of the other threads. > Or "idle" threads could be pre-empted to free logic for the "active" > thread (after saving the internal state of the replaced logic). > In practice the switching times depend on the hardware (usually FPGAs). > Standard FPGAs require the entire configuration to be loaded (serially > to boot) - a growing problem as the number of configuration bits > increase with larger components. Some FPGAs (notably Atmel, the defunct > Xilinx 5000, 6000 series, and now the Xilinx Virtex series) allow > partial reconfigurability, which usually reduces switching times. > On-chip storage of configuration data which can be loaded in a single > clock cycle was the original topic of discussion for this newsgroup > thread. There was earlier reference to some DARPA funded research aimed > at this goal. > There is a Reconfigurable Computing chip just announced by NEC which > apparently can store multiple configurations and switch between them. > Check out this link: http://www.edtn.com/story/OEG19990215S0004 . > Maybe the switching time problem has finally been solved. > Jonathan I have worked in software enough to know what a process is. It is an execution with its own memory and program counter. But I am not familiar with what a thread it. You seem to be using them interchangablly. The software people I have spoken to in the past, have indicated that a thread is not quite the same as a process. For example, they say that a process can have many threads. But I have never been able to get a clear definition. Can you explain the difference? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16482
Rickman wrote: > I have worked in software enough to know what a process is. It is an > execution with its own memory and program counter. But I am not familiar > with what a thread it. You seem to be using them interchangablly. The > software people I have spoken to in the past, have indicated that a > thread is not quite the same as a process. For example, they say that a > process can have many threads. But I have never been able to get a clear > definition. > > Can you explain the difference? Short answer: A thread is an execution with its own program counter and stack (and registers) that shares memory with other threads. Long answer: You can be in between as well, for instance having memory partially shared and partially private. This allows you to combine the overhead of managing separate address spaces with the difficulty of creating robust programs with unrestricted access to shared memory. As a finishing touch, make sure the shared portion of memory is writable and contains critical operating system functions - and you have the worlds most popular OS. P.S. Our current President is also very popular. -- Stuart D. Gathman <stuart@bmsi.com> Business Management Systems Inc. Phone: 703 591-0911 Fax: 703 591-6154 "Microsoft is the QWERTY of Operating Systems" - SDG "Confutatis maledictis, flammis acribus addictis" - background song for a Microsoft sponsored "Where do you want to go from here?" commercial. (HINT: Find a translation of the "Dies Irae".)Article: 16483
Rickman wrote: > > I have worked in software enough to know what a process is. It is an > execution with its own memory and program counter. But I am not familiar > with what a thread it. You seem to be using them interchangablly. The > software people I have spoken to in the past, have indicated that a > thread is not quite the same as a process. For example, they say that a > process can have many threads. But I have never been able to get a clear > definition. > > Can you explain the difference? > Rick, I did use the terms process and thread interchangeably to describe my concept of a reconfigurable architecture, but they are not strictly the same thing. I am no Java expert, but here is one definition I came across at the following web site (http://aidu.cs.nthu.edu.tw/javadoc/java/threads/definition.html): "Some texts use either the name lightweight process instead of thread. A thread is similar to a real process in that a thread and a running program are both a single sequential flow of control. However, a thread is considered lightweight because it runs within the context of a full-blown program and takes advantage of the resources allocated for that program and the program's environment. As a sequential flow of control, a thread must carve out some of its own resources within a running program (it must have its own execution stack and program counter for example). The code running within the thread only works within that context. Thus, other texts use execution context as a synonym for thread." Jonathan -- Jonathan F. Feifarek Consulting and design Programmable logic solutionsArticle: 16484
Jonathan Feifarek <feifarek@ieee.org> wrote: > > I picture some sort of icon oriented language similar to the Khoros > glyphs or the Labview environment. The designer may even use icon > layout schemes to effectively floorplan. That's too romantic. Surely today's automatic layout and synthesis algorithms eliminate the need for interaction. --== Sent via Deja.com http://www.deja.com/ ==-- ---Share what you know. Learn what you don't.---Article: 16485
Dear username, The LUT in the XC3000 families is implemented as a 16 x 1 PROM. It can therefore implement any function of 4 (or fewer) signals, and is not limited to AND-OR or AND-NOR type compositions. i.e a 2 input XOR and a 2 input XNOR feeding into a 2 input NAND is just as legal as a 4 input OR with a random set of inverters on its inputs. Programming the ROM is done as part of the configuration bitstream. You cant change the contents of a XC3000 LUT without reconfiguring the whole device. On the XC4000 families, the LUTs can be setup as RAMs, so you can change them on the fly, but they still implement any function of 4 signals. Philip Freidin In article <374A4C32.6E3C@dso.org.sg> username@dso.org.sg writes: >Does anyone know how the LUT is implemented or can be changed in the >XC3000 ? For example, I want to implement a Boolean equation, how do >I know if it is implemented thru a AND-OR or AND-NOR type of LUT? >Please advise. >email: csoolan@dso.org.sgArticle: 16486
rolandpj@bigfoot.com wrote: > > [JIT:] why not do the same thing, but right down to the hardware, > rather than down to machine code. What you need, however, is a > general compiler from a high-level language (Java bytecode?) to > fpga gates. Which function or aspect of JVM operation would most benefit from reconfigurable hardware? --== Sent via Deja.com http://www.deja.com/ ==-- ---Share what you know. Learn what you don't.---Article: 16487
Hi all,
I am trying to synthsise a design with Xilinx Foundations F1.5, with
some inputs and outputs. I have a constraint file to locate every
signal in a pin, but I get the error message:
ERROR:baste:263 - The LOC constraint "P68" (a IOB location) is not valid
for
symbol "linea_lect.PAD" (pad signal=linea_lect), which is being
mapped to the
following site types:
CLKIOB
My signal is fixed at PIN 68, a normal IOB, but the synthesis tool map
the signal to a clock, and I don't know why.
Anyone has any idea?
Thanks to all for reading my message and sorry for my english.
Article: 16488
Jean-Francois Richard wrote:
>
> I did an algorithm in C language and I want to do
> the implementation on a FPGA. The algorithm is on
> floating points and I would like to
> transfert that on fixed points.
>
> Any good software that do the conversion AUTOMATICALY ?
> Do they calculate the quantization error ?
There are only two addresses for this:
Frontier Design at www.frontierd.com and C level or something...(dunno
their website)
There main focus is exactly that: transition from
floating point to fixed point (especially for DSP). They have a fixed
point library
called ARTlibrary.
So you just replace your floating point declarations like
float x;
by
fxp<10,4> x;
and recompile and link. start out with a fixed point that is certainly
to wide.
You get statistics about bit use. Then run a worst case simulation
that needs the biggest word width and let the statistics tool report
on how many bits are redundant + quantisation error!
Frontiers 'ARTbuilder' product can convert your fixedpoint
implementation
to Verilog and VHDL. It's cool!
There is a free download option for ARTlibrary which is limited in
some way.
Full option ARTlibrary costs 1000 USD.
ARTBuilder doesn't seem to be downloadable. I don't know its price,
but it's shipping.
best regards,
Peter
--
======================================================================
Peter Sels === Easics ===
ASIC Design Engineer === VHDL-based ASIC design services ===
mailto:peter@easics.be ===================================
Tel: +32-16-395 605 Interleuvenlaan 86, B-3001 Leuven, BELGIUM
Fax: +32-16-395 619 http://www.easics.com/peter/
Article: 16489Hi there I am a Student in Berlin,Germany and looking for a job at a firm to work in the fild of embedded systems. I have some expiriences with the MCU-8051 family and the ispLSI-family fom Lattice. I have also some knowleg in Programming in C/C++, Electronic engineering and digital systems. A Job in California (San Francisco) would be nice but could be anywere in the USA. Frank Scherler scherler@tfh-berlin.deArticle: 16490
Tim, I believe we are in violent agreement! My reference "that I find it hard to ignore [Java]" refers to my preconceived notion that there will be a complete paradigm shift in this field, and hence my own temptation to disregard the emerging "bridging" technologies. Applying Java to reconfigurable computing seems to me more of the "paradigm drift" that Steve Casselman mentioned. Tim Tyler wrote: > > To me the whole notion of using smart compilation to target (largely) > serial code at parallel architectures just seems like a way of mobilising > the vast quantities of legacy serial code on parallel machines. It's > on a par with pipelines, "EPIC" and other attempts to squeeze parallelism > out of a serial stream of instructions. I agree. It's a noble and challenging goal to think that existing software might be translated to a flexible hardware platform and have orders of magnitude increase in performance. But I don't see it happening with unqualified success. As you (Tim Tyler) said: > > I think programmers targetting parallel machines should target their code > for such machines if they want good performance. This will generally > mean designing something like circuitry rather than making a serial recipe. > [...] > When designing something parallel it makes sense to try and get away from > a description in a form which is inherently serial due to its being based > on words and symbols, and go for a more visual representation, where > possible. Serial programming statements are a good match for a classical architecture in which instructions are operated serially, one at a time. Early parallel processing consisted of multiple classical computers operating at the same time, so extending this approach made sense. In an FPGA based machine, massive parallelism in time is not only possible, but is a better model for how things really operate. Not only can one group of hardware can be used to perform multiple tasks, but through reconfigurability, one task can also be performed by sequentially executing in the same hardware. This adds a new dimension of capability and complexity. In addition to this difference, the underlying physical structure of an FPGA is (currently) two dimensional. If this fact is ignored or too greatly abstracted, performance suffers greatly or fails altogether. This implies that a way of expressing the design in more dimensions would make it easier for a designer to create a more optimal system. The Khoros work I mentioned ( http://www.khoral.com/core.html ) takes a graphical approach at a system level, and maintains a library of reusable software. I saw a poster that they presented at FCCM '99 about applying their icon oriented methodology to reconfigurable computers. It allows concepts such as concurrency and time sequencing to be represented in a form which can be more easily visualized. Jonathan -- Jonathan F. Feifarek Consulting and design Programmable logic solutionsArticle: 16491
Hi there I am a Student in Berlin,Germany and looking for a job at a firm to work in the fild of embedded systems. I have some expiriences with the MCU-8051 family and the ispLSI-family fom Lattice. I have also some knowleg in Programming in C/C++, Electronic engineering and digital systems. A Job in California (San Francisco) would be nice but could be anywere in the USA. Frank Scherler scherler@tfh-berlin.de I forgot: isīt only for a six month internship.Article: 16492
Jean-Francois Richard wrote: > > I did an algorithm in C language and I want to do > the implementation on a FPGA. The algorithm is on > floating points and I would like to > transfert that on fixed points. > > Any good software that do the conversion AUTOMATICALY ? > Do they calculate the quantization error ? http://www.eetimes.com/story/OEG19990309S0030 gives pointers to the two relevant companies doing this. Peter -- ====================================================================== Peter Sels === Easics === ASIC Design Engineer === VHDL-based ASIC design services === mailto:peter@easics.be =================================== Tel: +32-16-395 605 Interleuvenlaan 86, B-3001 Leuven, BELGIUM Fax: +32-16-395 619 http://www.easics.com/peter/Article: 16493
>I'm designing a ISA and PCI card.However,I need a testbench to generate
>all signals.Thank for any info.
I've used Synopsys' models ( PCI and others but not ISA ) and
think they are terrific. Also known as LMC (Logic Modeling Comp; was
purchased by Synopsys a few years back ).
Pavel Zivny, Tek
( no connection to Synopsy but as a satisfied user. Speaking for self not
for Tek. )
Article: 16494I just thought of one SMALL problem... I don not believe Virtex supports 5V PCI??? Austin Austin Franklin <austin@dark9room.com> wrote in article <01bea62b$225d0a80$207079c0@drt1>... > The problem I have with that, is it locks me into THE interface THEY > provide for the back end. > > The pins are used for the back end interface anyway, so why not just > connect them to the PCI bus. Also, the PCI interface is supposedly only > supposed to take up a few 10s of thousands of gates MAX, and that's hardly > anything to worry about in a 300k-800k gate part. If it is, someone is > doing something wrong. > > Austin > > > Ray Andraka <randraka@ids.net> wrote in article > <3748AE04.BF8B2490@ids.net>... > > Austin, > > > > Unless it is a board for something going into production, I'd rather have > the > > PCI in a separate part so that I can get use of the entire virtex part, > and so > > I don't have to worry about how the PCI interface is going to affect the > > floorplanning for my stuff. I only use these type of boards in one-off > > designs and as prototyping platforms. For the most part, they are way > too > > expensive to use in a product that is going to be produced and sold in > any > > kind of quantity. > > > > Austin Franklin wrote: > > > > > Why don't you guys have the PCI interface in the Xilinx? > > > > > > Malachy Devlin <m.devlin@nallatech.com> wrote in article > > > <B4000FE0503ED211864100104B4C66C30972A9@CONTEXT>... > > > > Nallatech has been supplying a Virtex development platform since > > > > February. This is a 32bit 33Mhz PCI card with a 300K - 800K Virtex > > > > device and 2 individual banks of 2MBytes 100Mhz ZBT SRAM. > > > > The PCI card, called the Ballynuey, handles all the PCI issues and > comes > > > > with a pre-configured Spartan that handles the PCI interfacing and > data > > > > buffering between the Virtex and the PC application. PCI drivers, > Virtex > > > > debug tool, FPGA configuration and Application API are included with > the > > > > card. > > > > Additionally the card includes 4 DIME modules for expansion and > custom > > > > I/O. Currently there are modules for Image Capture and Display, a > Dual > > > > XCV1000 module (yes over 2Million gates!) and various other I/O > modules > > > > (e.g. LVDS) with more in the pipeline. The modules can provide over > > > > 2Gbytes/sec bandwidth and has over 200 I/O connections. > > > > > > > > Configuration of the on-board Virtex is configured dynamically over > the > > > > PCI using the tools provided with the card (and is much faster than > > > > Xchecker!) If additional DIME modules are placed on the card their > FPGAs > > > > are also individually configurable via PCI. > > > > > > > > > > > > Check out the web site for more details and new developments soon to > be > > > > announced at http://www.nallatech.com/ > > > > > > > > > > > > Malachy Devlin > > > > Nallatech Ltd > > > > m.devlin@nallatech.com > > > > > > > > > > > > > -----Original Message----- > > > > > From: alfred fuchs [mailto:alfred.fuchs@siemens.at] > > > > > Posted At: 12 May 1999 19:09 > > > > > Posted To: fpga > > > > > Conversation: Virtex based PCI cards > > > > > Subject: Re: Virtex based PCI cards > > > > > > > > > > > > > > > I've just finished the design of a CompactPCI board (6U) with > > > > > one Virtex1000 > > > > > and two synchronous SRAM-modules (2Mx72). It mainly uses > > > > > rear-panel-I/O > > > > > (more than 100 signals) and is therefore open for various > > > > > applications. The > > > > > PCI-IF is a PLX9054, the FPGA is configured by the PCI-master. > > > > > Pricing is TBD, but we tend to be expensive. > > > > > > > > > > Alfred Fuchs > > > > > Siemens Austria > > > > > PSE PRO LMS2 > > > > > +43/1/1707-34113 > > > > > > > > > > Atif Zafar schrieb: > > > > > > > > > > > Hello: > > > > > > > > > > > > Does anyone know of any development boards (PCI) that > > > > > use the Virtex > > > > > > FPGA? I am interested in a board with preferably several > > > > > XV800 or XV1000 > > > > > > devices along with RAM for prototyping a custom graphics > pipeline. I > > > > > > have heard of the PCI Pamette board, but to my knowledge > > > > > this does not > > > > > > have Virtex silicon. Thanks for any info. > > > > > > > > > > > > Atif Zafar > > > > > > Regenstrief Institute > > > > > > Zafar_A@regenstrief.iupui.edu > > > > > > > > > > > > > > > > > > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka > > > > > > >Article: 16495
In article <3748ABE4.E8E4610D@ids.net>, Ray Andraka <randraka@ids.net> wrote:
>I don't think so, Tim.
>
>The only way to create a schmitt trigger function in a PLD without schmitt
>trigger inputs is to use up an additional pin as an output to provide feedback
>to a resistive divider. The other option you have is to add a schmitt trigger
>chip between the input and your PLD.
You could also use two input pins for that particular signal;
then make one to have a lower treshold than the other.
( e.g. by programming their input cells to a different treshold, or
puting a res. divider in front of one of them ... this will depend
on the technology at hand )
Then you connect the lower-treshold signal to a RESET_ of a latch,
and you connect the higher-treshold signal to a SET . (note the polarities .)
You'll probably want to make the latch yourself (out of the FPGA's gates)
for this, but that depends on the rouatability of the RESET and SET
of the latch cells. Also make sure that the latch does the_right_thing
when both RESET and SET are asserted ( as they will be on either pos
or neg edge, depending on prop delays ).
I don't claim that this is better than Ray's method, it's just that
you can do it all inside. Your milleage _will_ vary :-)
>> I created a Schmitt trigger once on a Lattice CPLD, using schematic entry.
>> You can do it with a 2-input NAND and an inverter.
I agree with Ray, short of some tri-state magic I would not dare to even
think about the above sounds like perhaps Tim mis-remembers it - ?
Pavel Zivny
speaking for self, not for Tek .
Article: 16496Some tools are too smart for their own good! ;-) Seriously, some synthesis tools will take a signal that drives the clock of a flip-flop or latch and automatically assign it to a BUFG, whether or not you want it. You may be able to force it NOT to; check the on-line help for your synthesis tool (FPGA Express?) or with tech support. I have been using FPGA Express to synthesize, and not everything works as advertised (at least on the comman line); however, I have generally been able to coerce it to do what I want. You should see in your xnf or edif file if a BUFG (BUFGLS, ...) was inserted. If so, and your signal comes directly from a pin, you have to assign that signal to the appropriate IOB type: e.g., CLKIOB. If your tool can be explicity told to do things the way you want, you may want to insert some dummy logic that functions as a buffer, but in a way that the synthesis tool won't recognize (such as ANDing with a signal that is always a logic 1 when the circuit is operating.) Jason T. Wright "Expressing my opinions." On Tue, 25 May 1999 18:38:48 +0200, Tximo <jgracia@disca.upv.es> wrote: >Hi all, > >I am trying to synthsise a design with Xilinx Foundations F1.5, with >some inputs and outputs. I have a constraint file to locate every >signal in a pin, but I get the error message: > >ERROR:baste:263 - The LOC constraint "P68" (a IOB location) is not valid >for > symbol "linea_lect.PAD" (pad signal=linea_lect), which is being >mapped to the > following site types: > CLKIOB > >My signal is fixed at PIN 68, a normal IOB, but the synthesis tool map >the signal to a clock, and I don't know why. > >Anyone has any idea? > >Thanks to all for reading my message and sorry for my english. >Article: 16497
Of course there is already a XILINX FPGA PC104 board available from APS (APS-X240) at http://www.associatedpro.com It can take up to a 4085 240 pin QFP (with VIRTEX coming) and has provisions for on board 256Kby 8 SRAM, 232 transceiver, prom and osc socket, and can take xchecker, JTAG cable for download, or can be controlled from ISA bus via a PC104 controller or optional ISA carrier board. The board can be used used stand alone and can take a UART core for control. My customers find these boards useful indeed, and it saves them alot of design time. They can use the boards over and over to test algorithms. Many actually use them in their own products. You can currently purchase the XILINX Base kits with VHDL and router and JTAG cable with an APS-X240 board with a 240 pin SPARTAN FPGA for under $1000.00. Rickman wrote: > This is not intended to be an advertisement, so forgive me if it sounds > like one. But I would like to get the opinion of the engineers in the > newsgroup about a new board that we are designing. > > This board will have a PC/104 interface and form factor. It will contain > a TMS320C30 processor running at 40 MIPS (80 MHz). It will contain 256 > (or maybe 512) Kwords of SRAM and 2 MB of Flash. It will also use an > FPGA for the logic on the card. > > This is where I would like your opinion. The main function of the FPGA > will be to interface the various components of the board such as the two > I/O modules, the PC/104 bus and the DSP. But I can very easily, and > without much added cost, make this FPGA much larger than what is needed > to provide these basic functions. So the rest of the FPGA could be used > for user designated functions. > > Is this a useful feature for a DSP board? Has anyone designed custom > FPGA circuitry on a commercial board like this before? What is your > opinion as to the marketabililty of this feature? > > I appreciate your answers. Please post here or email me at the address > below. > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 16498
Some tools are too smart for their own good! ;-) Seriously, some synthesis tools will take a signal that drives the clock of a flip-flop or latch and automatically assign it to a BUFG, whether or not you want it. You may be able to force it NOT to; check the on-line help for your synthesis tool (FPGA Express?) or with tech support. I have been using FPGA Express to synthesize, and not everything works as advertised (at least on the command line); however, I have generally been able to coerce it to do what I want. You should see in your xnf or edif file if a BUFG (BUFGLS, ...) was inserted. If so, and your signal comes directly from a pin, you have to assign that signal to the appropriate IOB type: e.g., CLKIOB. If your tool can't be explicity told to do things the way you want, you may want to insert some dummy logic that functions as a buffer, but in a way that the synthesis tool won't recognize (such as ANDing with a signal that is always a logic 1 when the circuit is operating.) Jason T. Wright "Expressing my opinions." On Tue, 25 May 1999 18:38:48 +0200, Tximo <jgracia@disca.upv.es> wrote: >Hi all, > >I am trying to synthsise a design with Xilinx Foundations F1.5, with >some inputs and outputs. I have a constraint file to locate every >signal in a pin, but I get the error message: > >ERROR:baste:263 - The LOC constraint "P68" (a IOB location) is not valid >for > symbol "linea_lect.PAD" (pad signal=linea_lect), which is being >mapped to the > following site types: > CLKIOB > >My signal is fixed at PIN 68, a normal IOB, but the synthesis tool map >the signal to a clock, and I don't know why. > >Anyone has any idea? > >Thanks to all for reading my message and sorry for my english. >Article: 16499
Hello, I'm in the position of laying out a board with the data flow in the FPGA more or less known, but with the algorithms yet to be thought out (to be honest). Looking at the Virtex data sheet, I see Cin (carry in) coming in from the bottom and C-out (carry out) coming out the top. Does this actually correspond to the geometry of the chip ie are the carry lines going from the bottom of the chip to the top? I read somewhere that data busses should be connected to the row pins. Does all this mean that the data bus pins should be placed in ascending order along the side of the chip with D0 (LSB) at the bottom and the MSB at the top? Thanks very much, David Langmann david@dalanco.com
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