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"Jonathan Bromley" <spam@oxfordbromley.plus.com> wrote in message news:d375c296-7ed3-4d21-a33f-fcd6c8169934@z20g2000yqe.googlegroups.com... On Feb 16, 9:03 am, Vips <thevipulsi...@gmail.com> wrote: > I am designing a system where I have to transfer a control pulse > signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in > 100 MHz domain. How to "Stretch" the pulse in the slow domain to get > it sampled. Use it to enable a toggle flip-flop in the 100MHz domain. Then you have a step-edge that you can resample in your 12MHz clock domain. Obviously this won't work if the 100MHz pulse happens more often than about 6MHz, because you'll need at least two samples in the 12MHz domain to resynchronize and detect the edge (probably three, for comfort and simplicity). If that's the case then you may need to mess around with Gray counters. (Actually the toggle FF is a degenerate case of a Gray counter, with just one bit.) If the 100MHz and 12.5MHz clocks are in fact synchronous (e.g. using a DCM) then the same toggle-to-stretch technique works well, but the resynchronization problem is slightly different - details depend on exactly how the two clocks are related. It's often simpler just to assume that they are unrelated, to save yourself the bother of worrying about those details. Jonathan Bromley Jeez! Is this was thinking in HDL does for you? See my other post! PhilArticle: 150851
On 02/16/2011 08:08 AM, stephen.craven@gmail.com wrote: > All, > > I am teaching an intro digital logic lab. In past semesters I used the > final assignments to introduce students to structural Verilog netlists > using Spartan 3E boards. > > As the class size has outgrown my Spartan boards and I feel that a > modern FPGA is overkill for the simple circuits they are building, I > am looking for a different solution and would appreciate your > suggestions. > > My goals: > (1) A cheap reprogrammable PLD / FPGA (~$10 or less), > (2) A DIP package suitable for use in a breadboard, and > (3) A simple tool suite that supports an HDL (preferably Verilog). > > Are these mutually exclusive desires? I am willing to tolerate an > expensive programmer. Just a thought: I recently had a conversation with the son of a friend of mine. He was taking a logic class, and had some questions about how to do things. He remarked that this was his second class, and that the first ended up being more about how to shoe-horn logic into teeny little devices rather than learning the language. Knowing how to shoe-horn logic into small spaces is an essential skill, but I think it's something you want to impose on people _after_ you've given them a chance to play in a _big_ sand box. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 150852
On Feb 16, 9:49=A0pm, Jay <jpt03...@engr.uconn.edu> wrote: > Bryan <bryan.fletc...@avnet.com> wrote: > >> You could use the $39 USB JTAG cable from Digilent, I'm thinking of > >> getting one. It isn't supported by Impact, but Digilent supplies their > >> own Adept software for it. > > > The Digilent Cables can, in fact, support iMPACT, ChipScope, and SDK > > Debugging using a 3rd-party cable plug-in that Digilent provides. > > There are a few extra steps involved to get it set up, but it does > > work. =A0Since the $39 cable is USB Full-speed, you might want to > > consider the $47.95 High-Speed version. > > > Also, it looks like Digilent has a Xilinx-authorized replica of the > > Platform Cable USB-II since Digilent participates in the Xilinx > > University Program. =A0The non-Academic price is $129. > > > Bryan > > I've been using the XUP cable for a few months now, and I have no > complaints. A bit pricy, but I wanted a cable that works with impact unde= r > Linux. I got the academic price, though. Thanks all for your suggestions. Am considering ordering one for Digilent.Article: 150853
On 2/16/2011 5:11 PM, Phil Jessop wrote: > "Jonathan Bromley"<spam@oxfordbromley.plus.com> wrote in message > news:d375c296-7ed3-4d21-a33f-fcd6c8169934@z20g2000yqe.googlegroups.com... > On Feb 16, 9:03 am, Vips<thevipulsi...@gmail.com> wrote: > >> I am designing a system where I have to transfer a control pulse >> signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in >> 100 MHz domain. How to "Stretch" the pulse in the slow domain to get >> it sampled. > > Use it to enable a toggle flip-flop in the 100MHz domain. > Then you have a step-edge that you can resample in > your 12MHz clock domain. > > Obviously this won't work if the 100MHz pulse happens > more often than about 6MHz, because you'll need at least > two samples in the 12MHz domain to resynchronize and > detect the edge (probably three, for comfort and simplicity). > If that's the case then you may need to mess around with > Gray counters. (Actually the toggle FF is a degenerate > case of a Gray counter, with just one bit.) > > If the 100MHz and 12.5MHz clocks are in fact synchronous > (e.g. using a DCM) then the same toggle-to-stretch > technique works well, but the resynchronization problem > is slightly different - details depend on exactly how the > two clocks are related. It's often simpler just to assume > that they are unrelated, to save yourself the bother of > worrying about those details. > > Jonathan Bromley > > > Jeez! Is this was thinking in HDL does for you? > See my other post! > > Phil > > Nope, this is was [sic] thinking in terms of a newsgroup post does for you. Next year, when that link to your lovely picture has gone dead, your archived post will be useless. HTH, Syms.Article: 150854
Hi Cyrille, Here's a basic start. I need to add more to it, which I will try to do over the next few days. Thanks, Symon. http://projects.embetel.com/documents/111Article: 150855
On Feb 17, 5:08=A0am, "stephen.cra...@gmail.com" <stephen.cra...@gmail.com> wrote: > All, > > I am teaching an intro digital logic lab. In past semesters I used the > final assignments to introduce students to structural Verilog netlists > using Spartan 3E boards. > > As the class size has outgrown my Spartan boards and I feel that a > modern FPGA is overkill for the simple circuits they are building, I > am looking for a different solution and would appreciate your > suggestions. > > My goals: > (1) A cheap reprogrammable PLD / FPGA (~$10 or less), > (2) A DIP package suitable for use in a breadboard, and > (3) A simple tool suite that supports an HDL (preferably Verilog). > > Are these mutually exclusive desires? I am willing to tolerate an > expensive programmer. DIP is the most constraining of these conditions, The largest DIP CPLD I know of is the Atmel ATF2500C (DIP40, Digikey $6.25+), which has 48 Macrocells (24 buried, 24 pins) It has smaller siblings ATF750CL(20MC DIP24), and the ATF22V10 (10MC DIP24), and even ATF16V8(8MC DIP20) All of these need a Programmer, (eg EETools ChipMAX 2) If you can tolerate PLCC, Digikey have ATF1508ASVL-20JU84 Simplest tool suite is Atmel-CUPL, very fast and works from a TextEditor, which can also generate Test vectors. These append to the JED file, and run in the programmer after device pgm. Thus students can do functional sim, and also verify actual chip operation, before they get to the breadboard. hth -jgArticle: 150856
I think you can miss a pulse with your circuit if you go metastable on the output of the slow FF. With the T FF (or with pulse stretching) on the fast side followed by some FFs and an edge detect on the slow side, you can put in as many FFs as you like on the slow side to deal with metastability. ChrisArticle: 150857
Tim Wescott <tim@seemywebsite.com> wrote: (snip) > Just a thought: > I recently had a conversation with the son of a friend of mine. He was > taking a logic class, and had some questions about how to do things. He > remarked that this was his second class, and that the first ended up > being more about how to shoe-horn logic into teeny little devices rather > than learning the language. Is that a quarter, semester, or year class? > Knowing how to shoe-horn logic into small spaces is an essential skill, > but I think it's something you want to impose on people _after_ you've > given them a chance to play in a _big_ sand box. Is there something in between? I do believe that students need to learn to think in terms of logic, as distinct from (serial) software. Thinking about combining gates and FF's to make working logic is a good starting point. Seeing how inefficiently you can do it (in a large sand box) doesn't seem to me to be the right direction. (It isn't good in software, either.) I believe also that logic minimization is still a little more important than software optimization. Digital logic and FPGAs are needed when something needs to be faster than it can be done in software (such as on a microcontroller). In addition, it is easier to start learning logic minimization on smaller systems, and build up to larger ones. -- glenArticle: 150858
stephen.craven@gmail.com <stephen.craven@gmail.com> wrote: > I am teaching an intro digital logic lab. In past semesters I used the > final assignments to introduce students to structural Verilog netlists > using Spartan 3E boards. > As the class size has outgrown my Spartan boards and I feel that a > modern FPGA is overkill for the simple circuits they are building, I > am looking for a different solution and would appreciate your > suggestions. (snip of constraints) What I would like to see is a board designed around a smaller FPGA, specifically for introductory classroom use. It used to be that a digital clock was a favorite introductory project, though maybe not any more. Still, a board with resources to do that wouldn't be a bad start for an introductory class. Some time ago, I thought about a board that could be used in introductory classes for a digital clock (or something else with LED display and simple inputs), and later classes to do (what I believe is misnamed) SDR. (Software defined radio.) That is, with a minimal amount of external hardware needed, such that one could build the rest in the FPGA. (Antenna input, RF amplifier, ADC, DAC, audio amplifier, speaker.) If produced in large enough quanitities, it should be affordable for each student to buy one, and that would allow for economy of scale. -- glenArticle: 150859
On 02/16/2011 10:18 AM, Symon wrote: > Hi Cyrille, > Here's a basic start. I need to add more to it, which I will try to do > over the next few days. > Thanks, Symon. > > http://projects.embetel.com/documents/111 Did you mean to post that to this group? -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 150860
>My goals: >(1) A cheap reprogrammable PLD / FPGA (~$10 or less), >(2) A DIP package suitable for use in a breadboard, and >(3) A simple tool suite that supports an HDL (preferably Verilog). > >Are these mutually exclusive desires? I am willing to tolerate an >expensive programmer. I can't quite figure out what you are trying to do. If you are OK with an expensive programmer, I'd look for boards that included a USB programmer. The interesting stuff may be close to $10 over an expensive programmer. That doesn't get you a DIP package. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 150861
On Feb 15, 4:13=A0am, "RCIngham" > > Why has it taken you so long to work this out? > Amen! BIG NEWS! All counters are FSMs. Not all FSMs are counters. Do we need a dissertation to tell us this? Really? AndyArticle: 150862
Hal Murray <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote: >>My goals: >>(1) A cheap reprogrammable PLD / FPGA (~$10 or less), >>(2) A DIP package suitable for use in a breadboard, and >>(3) A simple tool suite that supports an HDL (preferably Verilog). >>Are these mutually exclusive desires? I am willing to tolerate an >>expensive programmer. > I can't quite figure out what you are trying to do. > If you are OK with an expensive programmer, I'd look for > boards that included a USB programmer. The interesting > stuff may be close to $10 over an expensive programmer. I thought the idea of expensive programmer was that only one was needed, even for a large number of boards. (Though that causes a bottleneck in the classroom.) -- glenArticle: 150863
Not _exactly_ like what you were asking for, but the Actel Igloo Nano Starter kit, or the Igloo Icicle Evaluation board might get you going. I don't know if Actel has educational discount programs. AndyArticle: 150864
"stephen.craven@gmail.com" <stephen.craven@gmail.com> wrote: >All, > >I am teaching an intro digital logic lab. In past semesters I used the >final assignments to introduce students to structural Verilog netlists >using Spartan 3E boards. > >As the class size has outgrown my Spartan boards and I feel that a >modern FPGA is overkill for the simple circuits they are building, I >am looking for a different solution and would appreciate your >suggestions. > >My goals: >(1) A cheap reprogrammable PLD / FPGA (~$10 or less), >(2) A DIP package suitable for use in a breadboard, and >(3) A simple tool suite that supports an HDL (preferably Verilog). Did you look into the X9500 series for Xilinx? They cost a few dollars in single quantities. You can use a PLCC socket which is very breadboard friendly. You can use Xilinx ISE tools and your favourite HDL. Programming can be done using Xilinx's standard parallel or USB cable. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 150865
I would like to clarify that it was IBM that defined the legacy parallel po= rt addresses. It was they that designed the first PCs and laid down the ori= ginal standards as to what has become known to be PC legacy stuff. It was n= ot Intel and it was more like 30 years ago! -- mkarasArticle: 150866
On Wed, 16 Feb 2011 10:08:17 -0800 (PST), jack <postbox4jack@gmail.com> wrote: >On Feb 16, 9:49 pm, Jay <jpt03...@engr.uconn.edu> wrote: >> Bryan <bryan.fletc...@avnet.com> wrote: >> >> You could use the $39 USB JTAG cable from Digilent, I'm thinking of >> >> getting one. It isn't supported by Impact, but Digilent supplies their >> >> own Adept software for it. >> >> > The Digilent Cables can, in fact, support iMPACT, ChipScope, and SDK >> > Debugging using a 3rd-party cable plug-in that Digilent provides. >> > There are a few extra steps involved to get it set up, but it does >> > work. Since the $39 cable is USB Full-speed, you might want to >> > consider the $47.95 High-Speed version. >> >> > Also, it looks like Digilent has a Xilinx-authorized replica of the >> > Platform Cable USB-II since Digilent participates in the Xilinx >> > University Program. The non-Academic price is $129. >> >> > Bryan >> I tried to order the Digilent cable and they told me that since I wasn't a student, they could not sell me one. Period. That was about a year ago. I'm in the US if that makes any difference. boB >> I've been using the XUP cable for a few months now, and I have no >> complaints. A bit pricy, but I wanted a cable that works with impact under >> Linux. I got the academic price, though. > >Thanks all for your suggestions. Am considering ordering one for >Digilent.Article: 150867
On Feb 17, 5:12=A0am, boB wrote: > On Wed, 16 Feb 2011 10:08:17 -0800 (PST), jack > > > > <postbox4j...@gmail.com> wrote: > >On Feb 16, 9:49 pm, Jay <jpt03...@engr.uconn.edu> wrote: > >> Bryan <bryan.fletc...@avnet.com> wrote: > >> >> You could use the $39 USB JTAG cable from Digilent, I'm thinking of > >> >> getting one. It isn't supported by Impact, but Digilent supplies th= eir > >> >> own Adept software for it. > > >> > The Digilent Cables can, in fact, support iMPACT, ChipScope, and SDK > >> > Debugging using a 3rd-party cable plug-in that Digilent provides. > >> > There are a few extra steps involved to get it set up, but it does > >> > work. Since the $39 cable is USB Full-speed, you might want to > >> > consider the $47.95 High-Speed version. > > >> > Also, it looks like Digilent has a Xilinx-authorized replica of the > >> > Platform Cable USB-II since Digilent participates in the Xilinx > >> > University Program. The non-Academic price is $129. > > >> > Bryan > > I tried to order the Digilent cable and they told me that since I > wasn't a student, they could not sell me one. =A0Period. That was about > a year ago. > > I'm in the US if that makes any difference. > > boB > > >> I've been using the XUP cable for a few months now, and I have no > >> complaints. A bit pricy, but I wanted a cable that works with impact u= nder > >> Linux. I got the academic price, though. > > >Thanks all for your suggestions. Am considering ordering one for > >Digilent. I'd forgotten that I actually had one that I ordered some time ago from Trenz, Digilent's German distributor, and stashed away. Unfortunately, I can't get it to work with my Digilent Spartan 3 board, using both the Adept 2 software or Impact. I emailed Digillent about the problem a couple of days ago, and haven't had a reply, despite the acknowledgement claiming that they respond in 24 hours. I don't recommend that you order one. LeonArticle: 150868
On 2/16/2011 4:54 PM, Andy wrote: > On Feb 15, 4:13 am, "RCIngham"> >> Why has it taken you so long to work this out? >> > Amen! > > BIG NEWS! All counters are FSMs. Not all FSMs are counters. > > Do we need a dissertation to tell us this? Really? > Apologies, I just "sensed" that was not clear to every one. But I am glad I was wrong. Amen! > AndyArticle: 150869
Hi all,
I have a very simple problem but I do not get my head around what is
going wrong. Essentially, the whole thing works fine when simulating it,
however, having it in hardware gives me the wrong result. Basically I
have two ctrl signals that determine the behaviour of the entity:
GET (ctrl = "00000000") sets register tx to input of op1
SH1_L (ctrl = "00000001") outputs (op1 << 1) or register tx
shifts register tx to the right by 31 bits
(tx >> 31)
library ieee;
use ieee.std_logic_1164.all;
entity test is
port
(
op1 : in std_logic_vector(31 downto 0); -- Input operand
ctrl : in std_logic_vector(7 downto 0); -- Control signal
clk : in std_logic; -- clock
res : out std_logic_vector(31 downto 0) -- Result
);
end;
architecture rtl of test is
type res_sel_type is (GET, SH1_L);
constant Z : std_logic_vector(31 downto 0) := (others => '0');
signal res_sel : res_sel_type;
signal load : std_logic := '0';
signal shl : std_logic := '0';
signal tx : std_logic_vector(31 downto 0) := (others => '0');
signal inp1 : std_logic_vector(31 downto 0) := (others => '0');
begin
dec_op: process (ctrl, op1)
begin
res_sel <= GET;
load <= '0';
shl <= '0';
inp1 <= ( others => '0');
case ctrl is
-- store operand
when "00000000" =>
inp1 <= op1;
load <= '1';
res_sel <= GET;
-- 1-bit left-shift with carry
when "00000001" =>
inp1 <= op1;
shl <= '1';
res_sel <= SH1_L;
when others =>
-- Leave default values
end case;
end process;
-- Selection of output
sel_out: process (res_sel, inp1)
begin
case res_sel is
when GET => NULL;
when SH1_L =>
res <= ( inp1(30 downto 0) & '0' ) or tx;
when others =>
res <= (others => '0');
end case;
end process;
sync: process(clk)
begin
if clk'event and clk = '1' then
if load = '1' then
tx <= op1;
elsif shl = '1' then
tx <= Z(30 downto 0) & op1(31);
end if;
end if;
end process;
end rtl;
TESTPROGRAM
GET 0
SH1_L 0xfedcba90 exp. output: 0xfdb97520 act. output = 0xfdb97521
SH1_L 0x7654321f exp. output: 0xeca8643f act. output = 0xeca8643e
SH1_L 0x71234567 exp. output: 0xe2468ace act. output = 0xe2468ace
As you can see, the last bit is wrong for some reason. I must have
something wrong with the timing, so that the register tx is first
written before it is acutally used in the computation of the output.
Anyone an idea how to solve this problem?
Many thanks!
Article: 150870Patrick wrote: > -- Selection of output > sel_out: process (res_sel, inp1) > begin > > case res_sel is > > when GET => NULL; > > when SH1_L => > res <= ( inp1(30 downto 0) & '0' ) or tx; > > when others => > res <= (others => '0'); > > end case; > > end process; You should put "tx" on the sensitivity list. Best regardsArticle: 150871
> You should put "tx" on the sensitivity list. Thanks, I tried that, but the result was unfortunately the same. Any other ideas what could have gone wrong? thanks!Article: 150872
On Feb 17, 7:06=A0pm, Patrick <Patr...@hotmail.com> wrote: > > You should put "tx" on the sensitivity list. > > Thanks, I tried that, but the result was unfortunately the same. Any > other ideas what could have gone wrong? > > thanks! Look carefully at all synthesis / map / par warnings. The above case with 'tx' should have been highlighted in one of them. There might be something else that is going wrong. As an alternative, can you output intermediate signal also, and see what their state is? Should help you zero in on the problem...Article: 150873
>> After some study and a lot of discussions with colleagues and friends I
>> would like to pin down the reasons why I have always believed that a
>> finite state machine (FSM) _is not_ a counter and at the same time try
>> to explain why a counter is a very special FSM (hope the thread will not
>> be too hot!).
This is indeed a job for the python argument clinic:
http://www.youtube.com/watch?v=teMlv3ripSM
-- Mike Treseler
Article: 150874
On 17 Feb., 18:59, Patrick <Patr...@hotmail.com> wrote:
> Hi all,
>
> I have a very simple problem but I do not get my head around what is
> going wrong. Essentially, the whole thing works fine when simulating it,
> however, having it in hardware gives me the wrong result. Basically I
> have two ctrl signals that determine the behaviour of the entity:
>
> =A0 GET =A0 (ctrl =3D "00000000") sets register tx to input of op1
> =A0 SH1_L (ctrl =3D "00000001") outputs (op1 << 1) or register tx
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shifts register t=
x to the right by 31 bits
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(tx >> 31)
[..]
> Anyone an idea how to solve this problem?
First about your obvious part of the problem:
> case res_sel is
>
> when GET =3D> NULL;
This leads to instatiation of a latch, this latch will likely store
the wrong value when you hope to have the output settle to the final
result.
In fact latch at the FF output (with little logic between) may lead to
unintended race-conditions.
Second your code and the solution to the described problem is
difficult to read and understand.
how about spending two registers for tx and the output and using only
one process to manage all?
if rising_edge(clk) then
case ctrl is
when GET =3D> tx <=3D op1;
when SH1_L =3D> tx <=3D (0 =3D> op1(31), others =3D> '0'); -- seems quit=
e
silly, really needed?
res <=3D (op1(30 downto 0) & '0') or tx;
when others =3D> null; -- or is res needed to be all 0?
end case;
regards Thomas
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