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I think you will find that Cadence are probably using FPGAs, or something very like FPGAs, within their box if it's the product I am thinking of. What they do, and you don't see, is the partitioning of your design onto the target hardware platform. If you do use either our boards, or DINI, there is partitioning software availavle from Auspey and Synopsis(Synplicity) to split designs. This probably a little more hands on than the Cadence way but massively less than a manual partitioning would be. As to speed you are unlikely to get the same speed in a FPGA based board acting as a simulator but the same goes for the Cadence offering. However co-FPGA hardware simulation like this is massively better than purely software only simulation it terms of the number of operational cycles that can be simulated. It does fill a big gap between the software only simulation and a very expensive ASIC cut. It also does not have the timescales that go with an ASIC cut and can shorten your project timescales. In Merrick1 we do have some scaling advantantages over the Cadence offering. One of the founding principals of the Merrick family platform is the ability to scale in a sensible way. The I/O structures of Merrick1 can support something like 0.5-1 terrabit/s of data and that can be connected to a second, or more, Merrick1s. Conceptually we can build either linear arrays like a pipeline, or a flat regular NxN, or even a blend of these. The limit is up to you. For the alternate use of Merrick as a High Performance Computing (HPC) engine we are looking at arrays of up to 10,000 boards and that's not a hard limit in what we can. The heat problem, and the little power station, you need for this particular supercomputer are much more of the problem for this design. As to value for money I'm sure you could have several of our Merrick1 platforms for the price of the competition. This platform can even be customised, within a normal delivery timescale, for specific customer applications which I don't think many of compeditors can offer. We also have other members of this family coming that expand the ideas even more. John Adair Enterpoint Ltd. - Home of Merrick1. The ASIC Prototyping Platform. On 19 Aug, 21:39, Test01 <cpan...@yahoo.com> wrote: > My company is intertested in doing emulation of complex CISC > superscaler processor using FPGAs. =A0Currently we are not using the > FPGA technology but instead using Cadence technology. =A0I would like to > hear your views on this. =A0What are the pros and cons of using the FPGA > technology? =A0Also if I want to go with the FPGA technology then what > are the options? > > Thanks.Article: 142601
> Interesting... I had a single example of an 250E turn itself into a > space heater a few weeks back while working on code for loading it > from an embedded processor. =A0It had previously worked flawlessly, as > did the replacement. =A0Perhaps there are certain invalid bit streams > that will introduce enough internal "shorts" to kill it? Im not suprised. I feel only xilinx could achieve a hardware failure thru code. Ive designed with a lot of xilinx devices, and use a lot of devices with work. They have been great. But its not like that anymore.It all began with their idiot "inputs only" on banks, then quadrant "global" clocks, then weird power allocations. All their devices have short falls now. We have put our spartan 6 products on hold for a while, but are moving ahead with arria and Cyclone III's. Not a good sign. But devices not working as advertised is the worst. After this last horrible ordeal i feel i have changed camps.Article: 142602
Hi Antii, Yep, i used too program direct as welll. But with the ease of using a bridge to a standard interfcae such as SPI or BPI, i dont think I ever want to go back to that method. Its just so easy to provide a new level of support to your customers without have pages of inxtructions or esoteric programming equipment. Xilinx wont fix the bug. If the bug wasnt that bad, they would have already. The 250E is toast. > Hi Steve, > > i almost always used own JTAG-SPI bypass soft cores and own PC host > software for SPI flash programming > (before the feature was added to impact) > > as I see the impact solution is still a problem. eh it would be so > much better if xilinx would supply source > code of the spi indirect cores... but they do not :( > > Antti- Hide quoted text - > > - Show quoted text -Article: 142603
Hello, Test01 <cpandya@yahoo.com> writes: > Also if I want to go with the FPGA technology then what > are the options? too add another board to the list of already listed, there is the ML509 board from Xilinx - evaluation plattform for OpenSparc. Afaik, due to space constraints, it just emulates one of the Niagara cores (But we have here also a Bee with 4 Virtex5 - there were more possible). FlorianArticle: 142604
On Aug 20, 10:55=A0am, Steve <srk...@gmail.com> wrote: > Hi Antii, > > Yep, i used too program direct as welll. But with the ease of using a > bridge to a standard interfcae such as SPI or BPI, i dont think I ever > want to go back to that method. Its just so easy to provide a new > level of support to your customers without have pages of inxtructions > or esoteric programming equipment. Xilinx wont fix the bug. If the bug > wasnt that bad, they would have already. The 250E is toast. > > > > > Hi Steve, > > > i almost always used own JTAG-SPI bypass soft cores and own PC host > > software for SPI flash programming > > (before the feature was added to impact) > > > as I see the impact solution is still a problem. eh it would be so > > much better if xilinx would supply source > > code of the spi indirect cores... but they do not :( > > > Antti- Hide quoted text - > > > - Show quoted text -- Hide quoted text - > > - Show quoted text - I did NOT program SPI-direct :) I programed SPI indirect using my own JTAG IP cores and pc side software AnttiArticle: 142605
Hi, I need to convert my fpga based designs to make an asic.I am entering into this area first time so i wanted to know the design issues, tools, vendors who provide this service and cost aspects for this process. If you can help me in this regard then I will be really thankful. Thanks in advance, ShrutiArticle: 142606
Hi, I compile my Quartus project with TCL and the way I add my files to the project is like this: set_global_assignment -name VERILOG_FILE ../code_gen/example1.v set_global_assignment -name VERILOG_FILE ../code_gen/example2.v set_global_assignment -name VERILOG_FILE ../code_gen/examplex.v This is working fine. Is ist possible to add multiple files to my design like: set_global_assignment -name VERILOG_FILE ../code_gen/*.v The * wildcard isn't working. I get the error message: Error (10002): Can't open VHDL or Verilog HDL file "C:/.../code_gen/*.v" I didn't find anything how to fix that in the web or in the handbook. Does anybody has a solution? Kind regardsArticle: 142607
Hi Shruti, I work for a design services company who does a lot of this type of work. Feel free to drop me an e-mail. Briefly: Main design issues will be replacing FPGA primitives & IP with ASIC equivalents (if any), then optimising for power (if necessary) and DFT additions & modifications. The main providers of ASIC tools are Cadence, Synopsys, Magma and Mentor. These are very expensive. Costs will vary widely depending upon the complexity of your design, the target process and volume, so I'd need a few more details of your design to give you a reasonable answer. Cheers, JonArticle: 142608
"Niieg" <stefan.nagel@kit.edu> wrote in message
news:Y8CdnWtnQaeI2xDXnZ2dnUVZ_j-dnZ2d@giganews.com...
> Hi,
> I compile my Quartus project with TCL and the way I add my files to the
> project is like this:
> set_global_assignment -name VERILOG_FILE ../code_gen/example1.v
> set_global_assignment -name VERILOG_FILE ../code_gen/example2.v
> set_global_assignment -name VERILOG_FILE ../code_gen/examplex.v
>
> This is working fine. Is ist possible to add multiple files to my design
> like:
> set_global_assignment -name VERILOG_FILE ../code_gen/*.v
>
> The * wildcard isn't working. I get the error message:
> Error (10002): Can't open VHDL or Verilog HDL file "C:/.../code_gen/*.v"
>
> I didn't find anything how to fix that in the web or in the handbook. Does
> anybody has a solution?
>
> Kind regards
>
Perhaps a bit of good old Tcl will work?
set strlist [glob *.v]
foreach strfile $strlist {
puts "set_global_assignment -name VERILOG_FILE $strfile"
}
Hans
www.ht-lab.com
Article: 142609
"Niieg" <stefan.nagel@kit.edu> writes:
> This is working fine. Is ist possible to add multiple files to my design
> like:
> set_global_assignment -name VERILOG_FILE ../code_gen/*.v
You can iterate over all the filenames and add them in a loop:
foreach filename [glob ../code_gen/*.v] {
set_global_assignment -name VERILOG_FILE $filename
}
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Article: 142610On Wed, 19 Aug 2009 15:58:51 -0700 (PDT), Peter Alfke <peter@xilinx.com> wrote: >On Aug 18, 11:15 pm, "sdaau" <s...@imi.aau.dk> wrote: >> (excuse if this is a double post - I tried to send this same message viahttp://www.fpgacentral.com/group/newsgroup/fpga/but it seems it doesn't >> send to comp.arch.fpga - so I'm trying again viahttp://www.fpgarelated.com/usenet/fpga.php) >> >> Hi all, >> >> I am just starting to learn about FPGA's, and as I found one schematic >> which I think I can read: >> >> The Xilinx Spartan - II Evaluation Boardhttp://www.fpga.synth.net/evalboards/files/fes2_user.pdf >> >> .. so, I'd basically like to rebuild this board for learning purposes. >> >> The problem is that it uses a programmable oscillator "EPSON’s MG-7010SA >> selectable-output PLL crystal oscillator", which has been discontinued: >> >> http://www.epsontoyocom.co.jp/english/discon/discon_osc.html >> >> .. and thus I cannot find it anywhere anymore (although I do get some >> hits with some russian sites). >> >> What I like about this chip, is that the frequency can be controlled via >> dip switches, as is done in fes2_user.pdf - which means, I don't have to >> worry about setting frequency through resistors or capacitors (and thus >> worrying about their value tolerances); nor about setting it through SPI or >> similar digital interfaces. >> >> I have been trying to look for alternatives to this chip, but without any >> success. Would any in the community have an idea if something similar to >> that chip currently exists for purchase? (btw I'd prefer RS Components or >> Farnell as suppliers). If there is no such chip manufactured anymore, what >> would be, in your opinion, the next best thing to use with the >> fes2_user.pdf Spartan-2 board? >> >> Thanks in advance for any answers... >> >> Cheers !! > >If you don't need the "rock-stable" frequency of a crystal oscillator, >you can use 3 pins of the FPGA, 2 resistors and one capacitor, and >build a surprisingly stable adjustable oscillator (google "Xilinx six >easy pieces") > >More importantly, do not start fresh with an obsolete design, go for >Spartan 3. > >Even more importantly: When you design and make your own multi-layer >pc board, you will struggle with, and hopefully learn many things, >like signal integrity, soldering of surface-mount components etc. You >need to master that before you even start designing the logic inside >the FPGA. > >My advice: Buy a ready-made, populated and tested board for $50 to >150, and save yourself a lot of grief and time. >Then you can concentrate on the real job. Always minimize the number >of unknown obstacles... >Peter Alfke, Xilinx Applications. Peter! I finally got someone to accept an order for S6s! Thanks! JohnArticle: 142611
Hi Antii, Wow, I missed that bit - ive been so used to info not being what I wanted to read, that I totally over looked the fact you had written your own! Dangling that carrot in front of me is too much, so Would it be ok if I could have a copy?? Thanks, Steve > > Hi Antii, > > > Yep, i used too program direct as welll. But with the ease of using a > > bridge to a standard interfcae such as SPI or BPI, i dont think I ever > > want to go back to that method. Its just so easy to provide a new > > level of support to your customers without have pages of inxtructions > > or esoteric programming equipment. Xilinx wont fix the bug. If the bug > > wasnt that bad, they would have already. The 250E is toast. > > > > Hi Steve, > > > > i almost always used own JTAG-SPI bypass soft cores and own PC host > > > software for SPI flash programming > > > (before the feature was added to impact) > > > > as I see the impact solution is still a problem. eh it would be so > > > much better if xilinx would supply source > > > code of the spi indirect cores... but they do not :( > > > > Antti- Hide quoted text - > > > > - Show quoted text -- Hide quoted text - > > > - Show quoted text - > > I did NOT program SPI-direct :) > > I programed SPI indirect using my own JTAG IP cores and pc side > software > > Antti- Hide quoted text - > > - Show quoted text -Article: 142612
> > I did NOT program SPI-direct :) > > I programed SPI indirect using my own JTAG IP cores and pc side > software > From the time it takes impact to "indirectly" program a 500E even when it works it appears that they use JTAG to toggle the FPGA's pins so that it communicates with the EEPROM. At the same time Xilinx has an app note with a Picoblaze doing the flashing that works just fine but requires another serial channel. I wonder what stops them from creating a "UART" via the JTAG "user" instruction and use that. So I ended up creating a core that read the bits from a memory card and programs the flash in a few seconds. P.S. I'm the other person on Steve's project. His "we" was not royal. -Alex.Article: 142613
Hi Rick, This is what I like about vectors. You can generally force an implementation with the code and reduce the quirks that a given synthesis tool subjects you to. Cheers, JimArticle: 142614
Alex Freed <alex_news@mirrow.com> writes: > requires another serial channel. I wonder what stops them from > creating a "UART" via the JTAG "user" instruction and use that. So I I've been using the JTAG user module to program various attached devices for many years. Should not be a problem, but of course the vendors would probably like you to use their device specific IP. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 142615
On Aug 21, 4:08=A0am, Alex Freed <alex_n...@mirrow.com> wrote: > > I did NOT program SPI-direct :) > > > I programed SPI indirect using my own JTAG IP cores and pc side > > software > > =A0From the time it takes impact to "indirectly" program a 500E even when > it works it appears that they use JTAG to toggle the FPGA's pins so that > it communicates with the EEPROM. At the same time Xilinx has an app note > with a Picoblaze doing the flashing that works just fine but requires > another serial channel. I wonder what stops them from creating a "UART" > via the JTAG "user" instruction and use that. So I ended up creating a > core that read the bits from a memory card and programs the flash in a > few seconds. > > P.S. I'm the other person on Steve's project. His "we" was not royal. > > -Alex. the BSCAN can almost directly be bypassed to IO for SPI indirect i used hower a very small core for this hm, if i recall i had intermediate sync protocol what i called SSP (sync serial protocol) what is essentially spi without select :) so i had BSCAN-SSP and SSP-SPI modules the beaty of that is that it is really simple to convert SPI flash programming data to say SVF and play back that SVF to the FPGA JTAG and the spi chips gets accessed i did not use svf/jam (but own software), however using svf/jam would be easy too, then you can use vendor tools to access the jtag interface (impact, quartus programmer, whatever) funny.. I am just now thinking about putting live into that project http://groups.google.com/group/antti-brain/files?hl=3Den U2TOOL jpeg ist current development photo of the hardware gadget it is already working as USB Blaster and I was able to use Actel SVF converted to jam, and Altera commandline jam player to program an ProAsic3 :) I wonted to test with Stratix board, but i thas the +- in the 9V jack reversed :( I had for some years another nice application, FPGA freqeuncy meter it used LPT based JTAG cable and measured frequency (without the need of any known clocks connected to FPGA), with usb cables that isnt possible, well with U2TOOL it will be again.. so it makes fun to develop it. i can dig up my JTAG-SPI ip cores.. the approuch was rather nice (specially because of easy svf/jam programming) AnttiArticle: 142616
On Aug 21, 4:06=A0am, Steve <srk...@gmail.com> wrote: > Hi Antii, > > Wow, I missed that bit - ive been so used to info not being what I > wanted to read, that I totally over looked the fact you had written > your own! > Dangling that carrot in front of me is too much, so > > Would it be ok if I could have a copy?? > > Thanks, > Steve > > > > > > Hi Antii, > > > > Yep, i used too program direct as welll. But with the ease of using a > > > bridge to a standard interfcae such as SPI or BPI, i dont think I eve= r > > > want to go back to that method. Its just so easy to provide a new > > > level of support to your customers without have pages of inxtructions > > > or esoteric programming equipment. Xilinx wont fix the bug. If the bu= g > > > wasnt that bad, they would have already. The 250E is toast. > > > > > Hi Steve, > > > > > i almost always used own JTAG-SPI bypass soft cores and own PC host > > > > software for SPI flash programming > > > > (before the feature was added to impact) > > > > > as I see the impact solution is still a problem. eh it would be so > > > > much better if xilinx would supply source > > > > code of the spi indirect cores... but they do not :( > > > > > Antti- Hide quoted text - > > > > > - Show quoted text -- Hide quoted text - > > > > - Show quoted text - > > > I did NOT program SPI-direct :) > > > I programed SPI indirect using my own JTAG IP cores and pc side > > software > > > Antti- Hide quoted text - > > > - Show quoted text -- Hide quoted text - > > - Show quoted text - i posted to the brain :) AnttiArticle: 142617
Hi,..I want to make an FM broadcast receiver using Lyrtech SFF SDR Kit,..it has RF module, data conversion module and signal processing module having vertex 4 FPGA and a DSP chip, ...I am using Matlab/Simulink and System Generator to make my models,..Can anybody help me with it that what exactly i should be doing for making my receiver ,.... Secondly i have an FRS model with this kit ,..i have made some ammendments to make it work as an FM broadcast receiver but it has some sections which i have failed to understand.. I can provide the details with snapshots if anybody is willing to help.. :( UmairArticle: 142618
On Aug 20, 11:02=A0pm, JimLewis <J...@SynthWorks.com> wrote: > This is what I like about vectors. =A0You can generally force an > implementation with the code and reduce the quirks that a given > synthesis tool subjects you to. Only if you are willing to constrain the code to keep certain terms from being optimized away. The same synthesis tool, on the same target, generally applies the same sets of "back end" (technology mapping) optimizations regardless of what data type was used in the RTL, since by the time those optimizations are applied, everything is a vector of bits. The operations, defined by the data types, give certain hints & constraints based on behavior, but the back end is still free to accept those hints or offer something it thinks is better (so long as it implements the prescribed behavior, at the boundaries of interest). And in my observations, when Synplify has abandoned the explicit, traditional carry implied by the RTL, the circuit it came up with was faster and/or smaller. I learned to quit wasting my time second guessing the synthesis tool's chosen implementation, as long as it met performance and resource constraints. I still use the subtract and compare condition only because it is easy enough to write and understand, and consistently gives equal or better results than a simple pre-subtraction compare to zero. I actually prefer some of the attributes of integer arithmetic that have flowed into the IEEE fixed point vector types (e.g. length expansion to cover the potential range of the results). Unfortunately, the subtraction of unsigned operands still returns an unsigned result. Arithmetically, that is not always the case. Like integer operations, you specify the arithmetic operation with the fixed point expression, and control the data path width by assigning it to objects of a specific type/subtype with whatever "resizing" operation is required. You could probably code this whole exercise in fixed point more easily than in unsigned. AndyArticle: 142619
On Aug 21, 4:15=A0pm, "aliumair926" <aliumair...@hotmail.com> wrote: > Hi,..I want to make an FM broadcast receiver using Lyrtech SFF SDR Kit,..= it > has RF module, data conversion module and signal processing module having > vertex 4 FPGA and a DSP chip, ...I am using Matlab/Simulink and System > Generator to make my models,..Can anybody help me with it that what exact= ly > i should be doing for making my receiver ,.... > > Secondly i have an FRS model with this kit ,..i have made some ammendment= s > to make it work as an FM broadcast receiver but it has some sections whic= h > i have failed to understand.. I can provide the details with snapshots if > anybody is willing to help.. :( > > Umair Oh this is easy, here is task list todo: 1) configure the radio front end (DDS/LO frequency) 2) change the bandwith to 20mhz 3) change the channel lookup table 4) take out the squelch 5) adjust the demodulator (FRS is narrow band FM, so you need change for broadcast FM) to implement steps 1..5 you have many options: option a * do it over THIS weekend (or withing 2 days next week if you cant access the tools over the weekend) * collect your diploma * finish uni * get a job * be happy option b * do try it for the next 3 months * go nuts * do not get a job * be happy option c * do try it for the next 3 months * give up * quit uni * get a job * be happy option d * quit uni TODAY * get a job * be happy as you see there are many ways to the happiness. it's all up to you. **** it's seems that Lyrtech is giving the SFF SDR to the universities at real discount prices! and the student dont even know that there are two Virtex chips in the SFF SDR kit one in the base unit, one in the ADAC module.. so Umair, now YOU know, but can you answer me with which on those two V4 chips do you want to work? the one on the main unit, or the one in ADAC? do you know? do you know why? what is the other one for? what is the TI DSP doing on the main board? i really wonder how Lyrtech can expect students of today todo anything useful with the SFR kit within a few weeks time they have for the task. it seems the students who are given the SFF units have absolute 0 prior knowledge of FPGA's and tools. Antti PS does the red led on ADAC board blink?Article: 142620
On Wed, 19 Aug 2009 13:39:24 -0700 (PDT), Test01 <cpandya@yahoo.com> wrote: >My company is intertested in doing emulation of complex CISC >superscaler processor using FPGAs. Currently we are not using the >FPGA technology but instead using Cadence technology. I would like to >hear your views on this. What are the pros and cons of using the FPGA >technology? Also if I want to go with the FPGA technology then what >are the options? > >Thanks. Assuming you're talking about Palladium, for your application FPGA emulation maybe a good option. Palladium is a nice product which has very fast compile times and was able to fit a design which was very problematic because of extremely high routing density (a fully parallel LDPC decoder). The issue with this product is that its maximum frequency is limited to around 4MHz no matter what you do. If, on the other hand, one has an x64 processor which is designed to run at very high speeds careful attention has already been paid to all speed paths so timing such a design on a recent (V5, V6 etc.) at no more than 100 times speed loss should be possible so I'd say you should be able to get at least 30 MHz out of your emulation. The issues with using FPGA emulation, though, are not trivial. The main ones are partitioning, synthesis/p&r times and mapping your design to RTL which the FPGA synthesis tool can understand. But because you're already using an emulation technology already you must have models for all your cells so that may not be that big a problem. Partitioning maybe an issue though there are some software solutions which sort of work already but you still may have to do some manual work which is not necessary in a Palladium solution. So overall I think FPGA emulation has good potential for you in terms of speed but comes with some challenges in terms of synthesis/p&r round-trip delay and partitioning. It would also be a lot cheaper. I'd start with Synplicity (ney Synopsys) tools with some high end HAPS hardware for feasibility and see where that gets you. If you were in Silicon Valley I'd offer you my services but I really don't like commuting to Austin. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 142621
On Aug 16, 5:51=A0am, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > YES, there is no need to point to the "usual suspects" > unless there is a real feeling, i have missed something obvious. > I've been working on a new `Free Software' soft core, but backwards. The gcc/binutils/gdb/simulator ports are already in the upstream FSF repositories. I also have a qemu port and uClinux has just started to boot on the simulator. I have barely started the verilog coding, but I hope to have a first pass done in a few weeks. The toolchain already has some advanced features that are not available in most GNU ports, such as the ability to do reverse debugging (step backwards in time). It's a 32-bit load/store architecture. Most instructions are 16-bits, but it also has 48-bit instructions for dealing with 32-bit immediate values. I think this is fair trade-off that should result in compact code. The ISA was designed specifically to be an excellent target for GCC, although it still need tweaking (I've blogged all the details). In any case, it's called moxie, and I've been blogging about the entire adventure here: http://www.moxielogic.org/blog (and the original blog archive here: http://spindazzle.org/ggx). There's also a wiki and all of the tools/firmware/OS (and soon HDL) code is easily downloadable and buildable from a git repository (see the wiki here http://www.moxielogic.org/wiki). I'm new to HDLs and FPGAs (and just found this newsgroup!). I'd appreciate any help/feedback/comments as I go. Thanks! Anthony GreenArticle: 142622
On Aug 22, 7:58=A0am, green <atgree...@gmail.com> wrote: > On Aug 16, 5:51=A0am, "Antti.Luk...@googlemail.com" > > <antti.luk...@googlemail.com> wrote: > > YES, there is no need to point to the "usual suspects" > > unless there is a real feeling, i have missed something obvious. > > I've been working on a new `Free Software' soft core, but backwards. > The gcc/binutils/gdb/simulator ports are already in the upstream FSF > repositories. =A0I also have a qemu port and uClinux has just started to > boot on the simulator. =A0I have barely started the verilog coding, but > I hope to have a first pass done in a few weeks. > > The toolchain already has some advanced features that are not > available in most GNU ports, such as the ability to do reverse > debugging (step backwards in time). > > It's a 32-bit load/store architecture. =A0Most instructions are 16-bits, > but it also has 48-bit instructions for dealing with 32-bit immediate > values. =A0I think this is fair trade-off that should result in compact > code. =A0The ISA was designed specifically to be an excellent target for > GCC, although it still need tweaking (I've blogged all the details). > > In any case, it's called moxie, and I've been blogging about the > entire adventure here:http://www.moxielogic.org/blog(and the > original blog archive here:http://spindazzle.org/ggx). =A0There's also > a wiki and all of the tools/firmware/OS (and soon HDL) code is easily > downloadable and buildable from a git repository (see the wiki herehttp:/= /www.moxielogic.org/wiki). > > I'm new to HDLs and FPGAs (and just found this newsgroup!). =A0I'd > appreciate any help/feedback/comments as I go. =A0Thanks! > > Anthony Green Hi Anthony you are "in" the report now, and hopefully there will be HDL too BTW, I did first time boot uClinux for microblaze in my own simulator not on real FPGA AnttiArticle: 142623
Thank you Hans & Petter for your help,
it's working fine now.
Regards
Stefan
>"Niieg" <stefan.nagel@kit.edu> writes:
>
>> This is working fine. Is ist possible to add multiple files to my
design
>> like:
>> set_global_assignment -name VERILOG_FILE ../code_gen/*.v
>
>You can iterate over all the filenames and add them in a loop:
>
>foreach filename [glob ../code_gen/*.v] {
> set_global_assignment -name VERILOG_FILE $filename
>}
>
>
>Petter
>
>--
>A: Because it messes up the order in which people normally read text.
>Q: Why is top-posting such a bad thing?
>A: Top-posting.
>Q: What is the most annoying thing on usenet and in e-mail?
>
Article: 142624Hi, Has anyone here thought of an idea to make an fpga io to be serdes capable, that said, capable of connecting to standards like, PCIe,SATA et. al. for chip to chip connection (i.e not on cable). What could be the components inside the fpga? Any ideas? -Morp
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