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On Apr 25, 10:24=A0am, Pete Fraser <pfra...@covad.net> wrote: > Ed McGettigan wrote: > > > There have been a couple of times were the wrong compact flash card > > was included with the kit as part of the final assembly step. > > > Can you please confirm the full kit name that you ordered (should > > start with EK- or DK-) and the part # (should begin with 108) on the > > bag that the CF card came in so that I can try to figure out what > > happened? > > Unfortunately I threw the packing away. > I think it was the right CF though. > The memory stick that came with the system contains > UG668 (v3.0), which is consistent with the CF. > > The printed documentation is UG730 (v1.1) and discusses > the video demo. It also mentions software version 12.1. > Perhaps they enclosed the wrong printed material. > > Strangely enough UG668 and UG730 both have the title: > "Getting Started with the Virtex-6 FPGA ML605 > Embedded Kit". > > The video demo would be of more interest to me, > but perhaps it's not compatible with 13.1? > I went back through the archives, but couldn't find > it with the 12.1 release. I'm not sure where it is. > > Is there anywhere on the web site that gives a > summary of the various demos that run on the ML605 > platform, and where to find them? > > I'm really looking forward to the video demo that > I saw at x-tech, but I understand that won't be > available for a month or so. > > Thanks > > Pete Did you buy the EK-V6-ML605-G (base) or the DK-V6-EMBD-G-XP1 (embedded processing) kit? Most of the reference designs can be found at: http://www.xilinx.com/ml605 Ed McGettigan -- Xilinx Inc.Article: 151601
Ed McGettigan wrote: > > Did you buy the EK-V6-ML605-G (base) or the DK-V6-EMBD-G-XP1 (embedded > processing) kit? Embedded processing kit. > > Most of the reference designs can be found at: > http://www.xilinx.com/ml605 That's where I had been looking. I can't find the video demo that's referenced in the printed documentation though... The printed docs talk about ISE 12.1, so I assumed the video demo would at least be in the 12.1 archive, but it's not there. The "Hardware and Demo Setup Guide" points me to www.xilinx.com/v6embkit for more information, but that seems to be a dead link. Thanks PeteArticle: 151602
>>Hi, >>I am using spartan3 xc3s4000 custom board in my design interfaced with a >>national PHY DP83865, xilinx 12.3 for synthesis and implementation and >i'm >>facing a strange problem. I run the same RTL on two boards and it behaves >>differently on both of them. Has anyone faced this issue before ? Does >>anyone know why it's happening ? > >Do you know that both boards are built correctly? >Could it be a board hardware fault? >Does either board behave 'correctly'? > > >--------------------------------------- >Posted through http://www.FPGARelated.com Yes, the boards are built correctly i suppose. I haven't been able to find the fault so far. I have changed the timing constraints, as tight as they can get, and as loose as they can get, still no success. The RTL works smoothly on one board, and my packets are transferred fine. Whereas same RTL doesn't give the same behavior on other 3 boards. It is basically a Gigabit MAC RTL i have written. What happens on other boards is that packets are transferred smoothly and after a minute or so, they start dropping. Had it been buffer overflow issue, it should have occurred on the 1st board as well since i have tested the first board with full load. I changed the PHYs today, but to no avail. I am clueless now. Any pointers will be of great help. And about timing constraints, i have done many iterations and almost all of them work on the FIRST board and fail to deliver same performance on other boards. Kindly help me out. Thanks.. Regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151603
On Apr 26, 12:45=A0am, Gabor <ga...@szakacs.invalid> wrote: > I often see people, especially hobbyists looking for inexpensive > boards with a lot of non-dedicated I/O. =A0These new boards from > Lattice are pretty basic (no on-board RAM) but have a lot of > break-out pins for projects that just need a lot of I/O on > 0.1" centers for prototyping. > > Usually Lattice releases boards like this at a "kicker" price > and then quietly raises the price later, so you may want > to grab one while it's still $29.99 > > MachXO 2280 Breakout Board Evaluation Kit: > > http://www.latticesemi.com/products/developmenthardware/breakoutboard... > > -- Gabor > > PS - I'm not connected to Lattice in any way. =A0Just saw this on > an e-mail and thought it might be of interest. Or, you could wait for the MachXO2 breakout ;) - and I see they now have this real, at $29. http://www.latticesemi.com/products/developmenthardware/developmentkits/mac= hxo2picokit.cfm -jgArticle: 151604
Gabor <gabor@szakacs.invalid> wrote: >I often see people, especially hobbyists looking for inexpensive >boards with a lot of non-dedicated I/O. These new boards from >Lattice are pretty basic (no on-board RAM) but have a lot of >break-out pins for projects that just need a lot of I/O on >0.1" centers for prototyping. > >Usually Lattice releases boards like this at a "kicker" price >and then quietly raises the price later, so you may want >to grab one while it's still $29.99 > >MachXO 2280 Breakout Board Evaluation Kit: > >http://www.latticesemi.com/products/developmenthardware/breakoutboardevalkits.cfm > >-- Gabor > >PS - I'm not connected to Lattice in any way. Just saw this on >an e-mail and thought it might be of interest. Looks nice. I have another CRT to LCD screen conversion project coming up. Any word on the software provided by Lattice? The last time I attempted to use their software must be about 15 years ago. Synario Abel HDL IIRC. OTOH maybe I just stick with Xilinx. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 151605
On Apr 25, 7:44=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > Gabor <ga...@szakacs.invalid> wrote: > >I often see people, especially hobbyists looking for inexpensive > >boards with a lot of non-dedicated I/O. =A0These new boards from > >Lattice are pretty basic (no on-board RAM) but have a lot of > >break-out pins for projects that just need a lot of I/O on > >0.1" centers for prototyping. > > >Usually Lattice releases boards like this at a "kicker" price > >and then quietly raises the price later, so you may want > >to grab one while it's still $29.99 > > >MachXO 2280 Breakout Board Evaluation Kit: > > >http://www.latticesemi.com/products/developmenthardware/breakoutboard... > > >-- Gabor > > >PS - I'm not connected to Lattice in any way. =A0Just saw this on > >an e-mail and thought it might be of interest. > > Looks nice. I have another CRT to LCD screen conversion project coming > up. > Any word on the software provided by Lattice? The last time I > attempted to use their software must be about 15 years ago. Synario > Abel HDL IIRC. OTOH maybe I just stick with Xilinx. I use their software in a design I have in production and I don't find any issues with it really. I'm still using a two year old copy and they have updated to the later rev of VHDL which I don't have. The synthesis tool is Synplify and the simulator is Aldec ActiveHDL. I ordered the software with Modelsim and before they shipped it their agreement for Modelsim ran out and they switched to Aldec. I about threw a fit because I had the impression ActiveHDL was an inferior product and they did a bait and switch on me. But once I calmed down and used the SW it was pretty good. In fact, I have less trouble with ActiveHDL than I did with Modelsim. Modelsim had a memory leak or something that would crash it after some hours of being up. That was what, 2002 or so? I assume they eventually fixed that, no? RickArticle: 151606
On Apr 25, 12:39=A0pm, Pete Fraser <pfra...@covad.net> wrote: > Ed McGettigan wrote: > > > Did you buy the EK-V6-ML605-G (base) or the DK-V6-EMBD-G-XP1 (embedded > > processing) kit? > > Embedded processing kit. > > > > > Most of the reference designs can be found at: > >http://www.xilinx.com/ml605 > > That's where I had been looking. > I can't find the video demo that's referenced > in the printed documentation though... > > The printed docs talk about ISE 12.1, so I assumed > the video demo would at least be in the 12.1 archive, > but it's not there. > > The "Hardware and Demo Setup Guide" points me > towww.xilinx.com/v6embkitfor more information, > but that seems to be a dead link. > > Thanks > > Pete Ok, so the CF card image matches the kit that you bought, but maybe the printed documentation was wrong. There are several broken links with the xilinx.com site wide update last week. I will try to get this one fixed. In the mean while you can use this link: http://www.xilinx.com/products/boards-and-kits/DK-V6-EMBD-G.htm Ed McGettigan -- Xilinx Inc.Article: 151607
On Mon, 25 Apr 2011 15:26:25 -0500, salimbaba wrote: >>>Hi, >>>I am using spartan3 xc3s4000 custom board in my design interfaced with >>>a national PHY DP83865, xilinx 12.3 for synthesis and implementation >>>and >>i'm >>>facing a strange problem. I run the same RTL on two boards and it > behaves >>>differently on both of them. Has anyone faced this issue before ? Does >>>anyone know why it's happening ? >> >>Do you know that both boards are built correctly? Could it be a board >>hardware fault? >>Does either board behave 'correctly'? >> >> >>--------------------------------------- Posted through >>http://www.FPGARelated.com > > > Yes, the boards are built correctly i suppose. I haven't been able to > find the fault so far. I have changed the timing constraints, as tight > as they can get, and as loose as they can get, still no success. The RTL > works smoothly on one board, and my packets are transferred fine. > Whereas same RTL doesn't give the same behavior on other 3 boards. It is > basically a Gigabit MAC RTL i have written. > > What happens on other boards is that packets are transferred smoothly > and after a minute or so, they start dropping. Had it been buffer > overflow issue, it should have occurred on the 1st board as well since i > have tested the first board with full load. > > I changed the PHYs today, but to no avail. I am clueless now. Any > pointers will be of great help. > > And about timing constraints, i have done many iterations and almost all > of them work on the FIRST board and fail to deliver same performance on > other boards. > > Kindly help me out. > Thanks.. A Gb Ethernet MAC/PCS/PHY combination is likely to involve clock domain crossings. The PHYs negotiate with their link partner to decide on one end as being the master clock. The MACs, OTOH, will usually be clocked by the local source. There will be typically a few (+/-200 in the worst case) ppm difference between the clocks. This will be compensated for by either adding or deleting words of interframe gap. IIRC this happens in the PCS. The boards are supposedly identical, but the clock frequencies will be slightly different. I suggest looking for a bug in your rate adaptation circuit. Alternatively, you could add frequency counters to your design (that measure the PHY clock w.r.t. the local clock) and see if the direction of clock error correlates with the errors you see). Regards, AllanArticle: 151608
On Apr 25, 1:26=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >>Hi, > >>I am using spartan3 xc3s4000 custom board in my design interfaced with = a > >>national PHY DP83865, xilinx 12.3 for synthesis and implementation and > >i'm > >>facing a strange problem. I run the same RTL on two boards and it > behaves > >>differently on both of them. Has anyone faced this issue before ? Does > >>anyone know why it's happening ? > > >Do you know that both boards are built correctly? > >Could it be a board hardware fault? > >Does either board behave 'correctly'? > > >--------------------------------------- =A0 =A0 =A0 =A0 =A0 =A0 > >Posted throughhttp://www.FPGARelated.com > > Yes, the boards are built correctly i suppose. I haven't been able to fin= d > the fault so far. I have changed the timing constraints, as tight as they > can get, and as loose as they can get, still no success. The RTL works > smoothly on one board, and my packets are transferred fine. Whereas same > RTL doesn't give the same behavior on other 3 boards. It is basically a > Gigabit MAC RTL i have written. > > What happens on other boards is that packets are transferred smoothly and > after a minute or so, they start dropping. Had it been buffer overflow > issue, it should have occurred on the 1st board as well since i have test= ed > the first board with full load. > > I changed the PHYs today, but to no avail. I am clueless now. Any pointer= s > will be of great help. > > And about timing constraints, i have done many iterations and almost all = of > them work on the FIRST board and fail to deliver same performance on othe= r > boards. > > Kindly help me out. > Thanks.. > > Regards > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com- Hide quoted text - > > - Show quoted text - It could be due to PPM differences between the clock sources on your boards where the two that are exhibiting a problem are either faster or slower than the one that works well generating overruns or underruns. If your code isn't sending idles or recognizing idles and removing them this could be a problem. Or it could be due to two other issues that I described earlier that you haven't mentioned addressing: - Data transfers between asynchronous clocks without synchronization - Latches in the design due to HDL errors Ed McGettigan -- Xilinx Inc.Article: 151609
"Gabor" <gabor@szakacs.invalid> wrote in message news:ip3qdf$62j$1@dont-email.me... > MachXO 2280 Breakout Board Evaluation Kit: > > http://www.latticesemi.com/products/developmenthardware/breakoutboardevalkits.cfm I am about to place an order on 99$ Versa kit. What do You think about that?Article: 151610
Hello, I am working on a project which involve interfacing with Ethernet, USB, SATA and couple of other chips (mostly high performance audio/ video decoders and HDMI transmitters). In addition, the system needs enough computing resources for audio/video processing. (either through dedicated H/W realized in the FPGA or through software). My plan is to have a resourceful FPGA and have a softprocessor (like OpenRisc) on it for controlling purposes and use the rest of the resources for Ethernet/USB and other ipcores (Ex:I2C) and probably for H/W realizations needed for audio/video processing. As i have not worked on a H/W project of this scale, i thought of taking some advice from more experienced engineers on this. Assuming that i also want to reduce the cost as much as possible, what Xilinx FPGA device family would be the rational choice here? Would a vertex device with an embedded PowerPC processor be a rational choice? Will there be any royalties involved in using the power PC and EDK/Platform Studio in this situation? Thank you.Article: 151611
Forgot to mention that the Linux need to be run on top of the processor (softprocessor or PowerPC).Article: 151612
<snip> > ActiveHDL than I did with Modelsim. Modelsim had a memory leak or > something that would crash it after some hours of being up. That was > what, 2002 or so? I assume they eventually fixed that, no? > > Rick I don't know if it has been fixed? I currently have a similar issue with SE-64bit it gobbles up > 10GB of RAM memory and brings our system to its knees. But I am also using some VPI modules that I need to double check, MTI might get lucky and it could be another issue. ChrisArticle: 151613
On Apr 26, 1:19=A0am, Manusha <manusha1...@gmail.com> wrote: > Hello, > > I am working on a project which involve interfacing with Ethernet, > USB, SATA and couple of other chips (mostly high performance audio/ > video decoders and HDMI transmitters). In addition, the system needs > enough computing resources for audio/video processing. (either through > dedicated H/W realized in the FPGA or through software). My plan is to > have a resourceful FPGA and have a softprocessor (like OpenRisc) on it > for controlling purposes and use the rest of the resources for > Ethernet/USB and other ipcores (Ex:I2C) and probably for H/W > realizations needed for audio/video processing. As i have not worked > on a H/W project of this scale, i thought of taking some advice from > more experienced engineers on this. > > Assuming that i also want to reduce the cost as much as possible, what > Xilinx FPGA device family would be the rational choice here? > Would a vertex device with an embedded PowerPC processor be a rational > choice? Will there be any royalties involved in using the power PC and > EDK/Platform Studio in this situation? > > Thank you. It sounds to me like something like a Texas Instruments DM8168 would be a better fit.Article: 151614
Manusha <manusha1980@gmail.com> wrote: >Hello, > >I am working on a project which involve interfacing with Ethernet, >USB, SATA and couple of other chips (mostly high performance audio/ >video decoders and HDMI transmitters). In addition, the system needs >enough computing resources for audio/video processing. (either through >dedicated H/W realized in the FPGA or through software). My plan is to >have a resourceful FPGA and have a softprocessor (like OpenRisc) on it >for controlling purposes and use the rest of the resources for >Ethernet/USB and other ipcores (Ex:I2C) and probably for H/W >realizations needed for audio/video processing. As i have not worked >on a H/W project of this scale, i thought of taking some advice from >more experienced engineers on this. I'd look into a Cortex device like Freescale's IMX51, Samsung's S5PV2xx or TI's omap (or whatever they call it these days) first. A major problem with TI's Cortex solutions is that they have no power solution in a chip which is routable (unless you want to route traces 60um wide). -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 151615
On Apr 26, 2:19=A0am, Manusha <manusha1...@gmail.com> wrote: > Ethernet, USB, SATA .. audio/video decoders.. HDMI transmitters > ... > Assuming that i also want to reduce the cost as much as possible, what > Xilinx FPGA device family would be the rational choice here? Always consider "the right tool for the job". A chip that is specifically designed for a job is a magnitude more (cost-, power-, and else) efficient at it, compared to a different chip that is not. Using a FPGA gives you flexibility and sometimes an edge on time-to- market, but it does not escape this basic rule. An FPGA is reasonable for everything, and excels at nothing. Reading your list of requirements, I recommend you look into the chips/ chipsets from ultraportables to laptops. Everything above a modern smartphone SoC offers the power you ask for, and if you renounce SATA then even the smartphone SoC is good. Best regards MarcArticle: 151616
On Mar 31, 2:20=A0pm, Tobias Baumann <tobias.baum...@elpra.de> wrote: > I did it. I hope there's someone who can help. Here's the link: > > http://forums.xilinx.com/t5/Embedded-Processing/Microblaze-prorgam-be... I'd check the stack size in the linker script. I saw similar behaviour (strange hangups which appear deterministically but change when some lines are commented out) when the stack size was around 0x300 and the program tried to use much more. - Andris -Article: 151617
I would not use a Virtex if you design is cost sensitive unless it is simply a one off. In that case it is a design effort versus material cost question. On processors the PowerPC in Virtex is a bit of a dead end. It isn't appearing in Virtex-6 as far as I know and ARM appears in the next generation. No royalities for the embedded PowerPC but you do pay in other ways for this feature. MicroBlaze, and equivalents, are fairly good processors especially when you can add FPGA hardware acceleration features to increase performance. Interfaces like USB, Ethernet and SATA are often better in external chips for cost as we have done in our Hollybush2 http://enterpoint.co.uk/oem_industrial/hollybush2.html, Drigmorn3 http://enterpoint.co.uk/drigmorn/drigmorn3.html and Drigmorn4 http://enterpoint.co.uk/drigmorn/drigmorn4.html boards but it is not always such a simple decision. On our Raggedstone2 development board http://enterpoint.co.uk/raggedstone/r= aggedstone2.html we added SATA connectors to the product simply to use spare high speed transceivers that were left over after we used 1 lane for our PCIe interface. The Spartan-6 LXT FPGA that is on that product can natively support SATA signalling over these high speed signal interfaces. Adding a controller core from an IP vendor can then be worthwhile when you have already paid for the high speed interface capability. All of this does highly depend on numbers that you end up making the product in. John Adair Enterpoint Ltd. On Apr 26, 7:19=A0am, Manusha <manusha1...@gmail.com> wrote: > Hello, > > I am working on a project which involve interfacing with Ethernet, > USB, SATA and couple of other chips (mostly high performance audio/ > video decoders and HDMI transmitters). In addition, the system needs > enough computing resources for audio/video processing. (either through > dedicated H/W realized in the FPGA or through software). My plan is to > have a resourceful FPGA and have a softprocessor (like OpenRisc) on it > for controlling purposes and use the rest of the resources for > Ethernet/USB and other ipcores (Ex:I2C) and probably for H/W > realizations needed for audio/video processing. As i have not worked > on a H/W project of this scale, i thought of taking some advice from > more experienced engineers on this. > > Assuming that i also want to reduce the cost as much as possible, what > Xilinx FPGA device family would be the rational choice here? > Would a vertex device with an embedded PowerPC processor be a rational > choice? Will there be any royalties involved in using the power PC and > EDK/Platform Studio in this situation? > > Thank you.Article: 151618
Hello Everybody,
I am a verification trainee at a company and i am verifying a
design made in VHDL through a Systemverilog testbench.There are some
paramters used in the design and I want to force these parameters through
the test-bench,I cannot use any of the scripting languages,is there any
other way to force these parameters through the test bench??
I have used defparam but no use.
Regards
Ritesh
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 151619hi all, i have a doubt regarding no.of slices in xlinx what are slices? what are LUT? in xilinx 1)the no.of slice constant in every version or does it vary? 2)can the area of an architecture be decreased if we say no.of slices are decreased. is this type of approach is correct? or 3) how can we say a area of architecture is decreased? 4)i am implementing project which is having the no.of slices in order of hundreds. where as the previous technique implemented have the no.of slices in order of thousands from this can we conclude that the area is decreased. please kindly answer. my mail id: marysowji.99@gmail.com --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151620
On Apr 26, 10:07=A0pm, "mary" <marysowji.99@n_o_s_p_a_m.gmail.com> wrote: > hi all, > > i have a doubt regarding no.of slices in xlinx > > what are slices? > what are LUT? in xilinx > > 1)the no.of slice constant in every version or does it vary? > > 2)can the area of an architecture be decreased if we say no.of slices are > decreased. > is this type of approach is correct? > or > 3) how can we say a area of architecture is decreased? > > 4)i am implementing project which is having the no.of slices in order of > hundreds. > where as the previous technique implemented have the no.of slices in orde= r > of thousands from =A0this can we conclude that the area is decreased. A LUT is a "look up table" and are how an FPGA implements combinatorial logic. For all practical purposes it is a block of memory with the logic inputs used as the address and the data output used as the logic output. The memory contents defines that logic function implemented. Is that what you are asking? For a long time all LUTs in Xilinx parts had four inputs although they did some funky things with multiplexers to allow two or even four of the four input LUTS to be combined into five and even six input LUTS. In some of the newer parts in the high end logic families they provide six input LUTS. This is partly because the parts are getting so large that, like the CPUs in PCs they are having trouble finding ways to use the larger number of transistors. So they are making the LUTs larger. A slice is just a grouping of LUTs and FFs and some connective structure into the repeated unit of the FPGA. The number of LUTs and FFs vary with family. Originally LUTs had two LUTs and two FFs. According to the manual "Each Virtex-6 FPGA slice contains four LUTs and eight flip-flops", but they also use the term "Logic Cells" which is not a countable entity in a part, it is a marketing number like "gates". Using the number of slices used is not a good metric for the size of a design because if one LUT is used, the slice is counted as used. Better to count the number of LUTs and FF used. You can have 100% slice utilization and still fit more into a chip. But when 100% of the LUTs and FFs are used, you will be hard pressed to add anything to that design! RickArticle: 151621
Thanks all for the valuable advices. It seems like there are good alternatives to a vertex/powerPC based system. @AMDyer: I am pretty impressed with the TI Davinci DSP's. Did not go to details, but seems like it has pretty much i am looking for. I will evaluate this option seriously. @John: I agree, The vertex devices cost pretty much. For example, the one i am planning to use costs around $120 and it has a powerPC core. But my question is, are there any alternatives at a lesser cost? Would a low cost device give me the computing power i need? (I am sure i need significant amount of computing power for real time video processing). @Marc: Any suggestions where to look for such chips? /MArticle: 151622
On 27 Apr., 04:06, "rittu" <rittu16@n_o_s_p_a_m.gmail.com> wrote: > Hello Everybody, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 I am a verification trainee at a company and = i am verifying a > design made in VHDL through a Systemverilog testbench.There are some > paramters used in the design and I want to force these parameters through > the test-bench,I cannot use any of the scripting languages,is there any > other way to force these parameters through the test bench?? > > I have used defparam but no use. > > Regards > Ritesh > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Hi Ritesh. are the design parameters in the VHDL files set with "generic"s? If so it should be simple to use verilog "parameter" statements at the DUT instantiation to set these values in your testbench. Have a nice simulation EilertArticle: 151623
>hi all, > > >i have a doubt regarding no.of slices in xlinx > >what are slices? >what are LUT? in xilinx > >1)the no.of slice constant in every version or does it vary? > >2)can the area of an architecture be decreased if we say no.of slices are >decreased. >is this type of approach is correct? >or >3) how can we say a area of architecture is decreased? > >4)i am implementing project which is having the no.of slices in order of >hundreds. >where as the previous technique implemented have the no.of slices in order >of thousands from this can we conclude that the area is decreased. > > >please kindly answer. > Watch and learn: http://www.xilinx.com/training/fpga/virtex-6-slice-and-io-resources-video.htm --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151624
> Me and some engineers run an FPGA prototyping company. "poet_neel@yahoo." Doesn't inspire confidence. I'll stick with EBV. Nial.
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