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On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote: > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT reference cloc= k > > pins were normal I/Os that had extra dedicated routing to the MGTs. > > > Are you using a Xilinx board? =A0If so which one is it? > > > What are the IO location constraints that you are using for the output > > and input paths? > > > Ed McGettigan > > -- > > Xilinx Inc. > > Hello, > I am using the Virtex II Pro development board for my project. > I am pasting all the IO constraints written to the ucf file. > The signals to take out and then feed in are "inp_for_TI_chip" and > "op_from_TI_chip" respectively. > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25; > #LEFT P/B > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > #EXTERNAL_CLOCK_P > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25; > #EXTERNAL_CLOCK_N > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS25; > #MGT_TXP > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D > FAST | DRIVE =3D 8 ; > #MGT_TXN > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D LVCMOS25 | SLEW= =3D > FAST | DRIVE =3D 8 ; > #J5-11 > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS25 | SLEW =3D= FAST > | DRIVE =3D 8 ; > #J5-15 > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | SLEW =3D FAS= T | > DRIVE =3D 8 ; > #J6-27 > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | SLEW =3D FAST= | > DRIVE =3D 8 ; > #J6-35 > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D F= AST | > DRIVE =3D 8 ; > #J5-31 > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D F= AST | > DRIVE =3D 8 ; > #J5-39 > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SLOW | > DRIVE =3D 12 ; > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SLOW | > DRIVE =3D 12 ; > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SLOW | > DRIVE =3D 12 ; > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SLOW | > DRIVE =3D 12 ; > > Thanks, > Pratap The UCF file constraints have regular IO location assignments to A7 and A6 which are the MGT TXP/TXN pins. These locations are not valid for anything other than MGT TXP/TXN pins and your original post indicated that you had changed these to other locations and it worked. I'm confused. What exactly is your question or problem? Ed McGettigan -- Xilinx Inc.Article: 151351
On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be used > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT reference cl= ock > > > pins were normal I/Os that had extra dedicated routing to the MGTs. > > > > Are you using a Xilinx board? =A0If so which one is it? > > > > What are the IO location constraints that you are using for the outpu= t > > > and input paths? > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > Hello, > > I am using the Virtex II Pro development board for my project. > > I am pasting all the IO constraints written to the ucf file. > > The signals to take out and then feed in are "inp_for_TI_chip" and > > "op_from_TI_chip" respectively. > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25; > > #LEFT P/B > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > > #EXTERNAL_CLOCK_P > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25; > > #EXTERNAL_CLOCK_N > > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS25; > > #MGT_TXP > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D > > FAST | DRIVE =3D 8 ; > > #MGT_TXN > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D LVCMOS25 | SL= EW =3D > > FAST | DRIVE =3D 8 ; > > #J5-11 > > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D FAST > > | DRIVE =3D 8 ; > > #J5-15 > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | SLEW =3D F= AST | > > DRIVE =3D 8 ; > > #J6-27 > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | SLEW =3D FA= ST | > > DRIVE =3D 8 ; > > #J6-35 > > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D= FAST | > > DRIVE =3D 8 ; > > #J5-31 > > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D= FAST | > > DRIVE =3D 8 ; > > #J5-39 > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SLOW= | > > DRIVE =3D 12 ; > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SLOW= | > > DRIVE =3D 12 ; > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SLOW= | > > DRIVE =3D 12 ; > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SLOW= | > > DRIVE =3D 12 ; > > > Thanks, > > Pratap > > The UCF file constraints have regular IO location assignments to A7 > and A6 which are the MGT TXP/TXN pins. =A0These locations are not valid > for anything other than MGT TXP/TXN pins and your original post > indicated that you had changed these to other locations and it worked. > > I'm confused. =A0What exactly is your question or problem? > > Ed McGettigan > -- > Xilinx Inc. Yes, This is the ucf file that is not working. The ucf file that ensures that there is toggling at all the signal ports is as follows. NET "op_from_TI_chip" LOC =3D "F16" | IOSTANDARD =3D LVCMOS25; #MGT_CLK_P NET "inp_for_TI_chip" LOC =3D "G16" | IOSTANDARD =3D LVCMOS25 | SLEW =3D FAST | DRIVE =3D 8 ; #MGT_CLK_N My exact problem is in understanding why in the case when I connect the pins intended to be interfaced with the other chip to F16 and G16(The externally non-accessible ports on board) , I get the signals at the output port. If I connect those two signals to any other pin, it doesn't seem to work. I hope the problem is clear now. Thanks, PratapArticle: 151352
i want "fpga express 3.6" setup program. i have "ftp://ftp.xilinx.com/ pub/swhelp/M3.1i_updates/fpgaexp35.exe" update files. i want setup program. thanks.Article: 151353
On Mar 26, 8:41=A0pm, Pratap <pratap.i...@gmail.com> wrote: > On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be us= ed > > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT reference = clock > > > > pins were normal I/Os that had extra dedicated routing to the MGTs. > > > > > Are you using a Xilinx board? =A0If so which one is it? > > > > > What are the IO location constraints that you are using for the out= put > > > > and input paths? > > > > > Ed McGettigan > > > > -- > > > > Xilinx Inc. > > > > Hello, > > > I am using the Virtex II Pro development board for my project. > > > I am pasting all the IO constraints written to the ucf file. > > > The signals to take out and then feed in are "inp_for_TI_chip" and > > > "op_from_TI_chip" respectively. > > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25; > > > #LEFT P/B > > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > > > #EXTERNAL_CLOCK_P > > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25; > > > #EXTERNAL_CLOCK_N > > > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS25; > > > #MGT_TXP > > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS25 | SLE= W =3D > > > FAST | DRIVE =3D 8 ; > > > #MGT_TXN > > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D LVCMOS25 | = SLEW =3D > > > FAST | DRIVE =3D 8 ; > > > #J5-11 > > > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS25 | SLEW= =3D FAST > > > | DRIVE =3D 8 ; > > > #J5-15 > > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | SLEW =3D= FAST | > > > DRIVE =3D 8 ; > > > #J6-27 > > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | SLEW =3D = FAST | > > > DRIVE =3D 8 ; > > > #J6-35 > > > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D FAST | > > > DRIVE =3D 8 ; > > > #J5-31 > > > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D FAST | > > > DRIVE =3D 8 ; > > > #J5-39 > > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SL= OW | > > > DRIVE =3D 12 ; > > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SL= OW | > > > DRIVE =3D 12 ; > > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SL= OW | > > > DRIVE =3D 12 ; > > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLEW =3D SL= OW | > > > DRIVE =3D 12 ; > > > > Thanks, > > > Pratap > > > The UCF file constraints have regular IO location assignments to A7 > > and A6 which are the MGT TXP/TXN pins. =A0These locations are not valid > > for anything other than MGT TXP/TXN pins and your original post > > indicated that you had changed these to other locations and it worked. > > > I'm confused. =A0What exactly is your question or problem? > > > Ed McGettigan > > -- > > Xilinx Inc. > > Yes, > This is the ucf file that is not working. The ucf file that ensures > that there is toggling at all the signal ports is as follows. > > NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D LVCMOS25; > #MGT_CLK_P > > NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D > FAST | DRIVE =3D 8 ; > #MGT_CLK_N > > My exact problem is in understanding why in the case when I connect > the pins intended to be interfaced with the other chip to F16 and > G16(The externally non-accessible ports on board) , I get the signals > at the output port. If I connect those two signals to any other =A0pin, > it doesn't seem to work. > I hope the problem is clear now. > > Thanks, > Pratap- Hide quoted text - > > - Show quoted text - Sorry, it still isn't very clear and you still haven't identified which exact board you are using (vendor and model). As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for anything other that the MGT. For this device pins F16 and G16 are regular IO and also MGT reference clock input pins so they can be used for inputs or outputs. > If I connect those two signals to any other pin, > it doesn't seem to work. It isn't clear what you mean by any other pin and what doesn't work. Ed McGettigan -- Xilinx Inc.Article: 151354
On Sun, 27 Mar 2011 08:42:30 -0700 (PDT), electrocoder <electrocoder@gmail.com> wrote: >i want "fpga express 3.6" setup program. i have "ftp://ftp.xilinx.com/ >pub/swhelp/M3.1i_updates/fpgaexp35.exe" update files. i want setup >program. thanks. FPGA Express has been very dead and very unsupported for a very long time. If you have a client who's insisting on its use, tell the client they will have to find you an installation and a licence. Otherwise, pick one of the available alternatives. What can FPGA Express do for you that XST can't? -- Jonathan BromleyArticle: 151355
On Mar 27, 9:39=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Mar 26, 8:41=A0pm, Pratap <pratap.i...@gmail.com> wrote: > > > > > On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be = used > > > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT referenc= e clock > > > > > pins were normal I/Os that had extra dedicated routing to the MGT= s. > > > > > > Are you using a Xilinx board? =A0If so which one is it? > > > > > > What are the IO location constraints that you are using for the o= utput > > > > > and input paths? > > > > > > Ed McGettigan > > > > > -- > > > > > Xilinx Inc. > > > > > Hello, > > > > I am using the Virtex II Pro development board for my project. > > > > I am pasting all the IO constraints written to the ucf file. > > > > The signals to take out and then feed in are "inp_for_TI_chip" and > > > > "op_from_TI_chip" respectively. > > > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25; > > > > #LEFT P/B > > > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > > > > #EXTERNAL_CLOCK_P > > > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25; > > > > #EXTERNAL_CLOCK_N > > > > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS25; > > > > #MGT_TXP > > > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS25 | S= LEW =3D > > > > FAST | DRIVE =3D 8 ; > > > > #MGT_TXN > > > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D LVCMOS25 = | SLEW =3D > > > > FAST | DRIVE =3D 8 ; > > > > #J5-11 > > > > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS25 | SL= EW =3D FAST > > > > | DRIVE =3D 8 ; > > > > #J5-15 > > > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D FAST | > > > > DRIVE =3D 8 ; > > > > #J6-27 > > > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D FAST | > > > > DRIVE =3D 8 ; > > > > #J6-35 > > > > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 | SLEW= =3D FAST | > > > > DRIVE =3D 8 ; > > > > #J5-31 > > > > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 | SLEW= =3D FAST | > > > > DRIVE =3D 8 ; > > > > #J5-39 > > > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLEW =3D = SLOW | > > > > DRIVE =3D 12 ; > > > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D = SLOW | > > > > DRIVE =3D 12 ; > > > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLEW =3D = SLOW | > > > > DRIVE =3D 12 ; > > > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLEW =3D = SLOW | > > > > DRIVE =3D 12 ; > > > > > Thanks, > > > > Pratap > > > > The UCF file constraints have regular IO location assignments to A7 > > > and A6 which are the MGT TXP/TXN pins. =A0These locations are not val= id > > > for anything other than MGT TXP/TXN pins and your original post > > > indicated that you had changed these to other locations and it worked= . > > > > I'm confused. =A0What exactly is your question or problem? > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > Yes, > > This is the ucf file that is not working. The ucf file that ensures > > that there is toggling at all the signal ports is as follows. > > > NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D LVCMOS25; > > #MGT_CLK_P > > > NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D LVCMOS25 | SLEW= =3D > > FAST | DRIVE =3D 8 ; > > #MGT_CLK_N > > > My exact problem is in understanding why in the case when I connect > > the pins intended to be interfaced with the other chip to F16 and > > G16(The externally non-accessible ports on board) , I get the signals > > at the output port. If I connect those two signals to any other =A0pin, > > it doesn't seem to work. > > I hope the problem is clear now. > > > Thanks, > > Pratap- Hide quoted text - > > > - Show quoted text - > > Sorry, it still isn't very clear and you still haven't identified > which exact board you are using (vendor and model). > > As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for > anything other that the MGT. =A0For this device pins F16 and G16 are > regular IO and also MGT reference clock input pins so they can be used > for inputs or outputs. > > > If I connect those two signals to any other =A0pin, > > it doesn't seem to work. > > It isn't clear what you mean by any other pin and what doesn't work. > > Ed McGettigan > -- > Xilinx Inc. OK. Let me rephrase the problem. All I want is, I want to take a signal out of the Xilinx Virtex II Pro board which is fed to the FPGA pin "G15" (EXT_CLK_N). If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA through the pin "F15" (EXT_CLK_P), it works absolutely fine. But when I use both the pins F15 and G15 for two different input signals, and want to take a delayed version of the signal fed to "G15", by routing it through any of the pins in the connector series located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I want to stimulate another chip with this delayed signal coming from FPGA. The P&R completes without any problem when I use the Pin J37-A14 or any other pin, but when I am checking the signal at that pin by connecting an oscilloscope probe there, I don't see any signal there. This is what I mean by, things don't work. Is is there any issue in taking out the signals connected to F15 or G15 once I use both of those pins as inputs? If yes, why so and what is the way around? I hope the question is more straight forward now and thanks for the patience shown in understanding the issue. Thanks, PratapArticle: 151356
On Mar 27, 9:39=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Mar 26, 8:41=A0pm, Pratap <pratap.i...@gmail.com> wrote: > > > > > On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only be = used > > > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT referenc= e clock > > > > > pins were normal I/Os that had extra dedicated routing to the MGT= s. > > > > > > Are you using a Xilinx board? =A0If so which one is it? > > > > > > What are the IO location constraints that you are using for the o= utput > > > > > and input paths? > > > > > > Ed McGettigan > > > > > -- > > > > > Xilinx Inc. > > > > > Hello, > > > > I am using the Virtex II Pro development board for my project. > > > > I am pasting all the IO constraints written to the ucf file. > > > > The signals to take out and then feed in are "inp_for_TI_chip" and > > > > "op_from_TI_chip" respectively. > > > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25; > > > > #LEFT P/B > > > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > > > > #EXTERNAL_CLOCK_P > > > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25; > > > > #EXTERNAL_CLOCK_N > > > > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS25; > > > > #MGT_TXP > > > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS25 | S= LEW =3D > > > > FAST | DRIVE =3D 8 ; > > > > #MGT_TXN > > > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D LVCMOS25 = | SLEW =3D > > > > FAST | DRIVE =3D 8 ; > > > > #J5-11 > > > > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS25 | SL= EW =3D FAST > > > > | DRIVE =3D 8 ; > > > > #J5-15 > > > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D FAST | > > > > DRIVE =3D 8 ; > > > > #J6-27 > > > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D FAST | > > > > DRIVE =3D 8 ; > > > > #J6-35 > > > > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 | SLEW= =3D FAST | > > > > DRIVE =3D 8 ; > > > > #J5-31 > > > > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 | SLEW= =3D FAST | > > > > DRIVE =3D 8 ; > > > > #J5-39 > > > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLEW =3D = SLOW | > > > > DRIVE =3D 12 ; > > > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLEW =3D = SLOW | > > > > DRIVE =3D 12 ; > > > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLEW =3D = SLOW | > > > > DRIVE =3D 12 ; > > > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLEW =3D = SLOW | > > > > DRIVE =3D 12 ; > > > > > Thanks, > > > > Pratap > > > > The UCF file constraints have regular IO location assignments to A7 > > > and A6 which are the MGT TXP/TXN pins. =A0These locations are not val= id > > > for anything other than MGT TXP/TXN pins and your original post > > > indicated that you had changed these to other locations and it worked= . > > > > I'm confused. =A0What exactly is your question or problem? > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > Yes, > > This is the ucf file that is not working. The ucf file that ensures > > that there is toggling at all the signal ports is as follows. > > > NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D LVCMOS25; > > #MGT_CLK_P > > > NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D LVCMOS25 | SLEW= =3D > > FAST | DRIVE =3D 8 ; > > #MGT_CLK_N > > > My exact problem is in understanding why in the case when I connect > > the pins intended to be interfaced with the other chip to F16 and > > G16(The externally non-accessible ports on board) , I get the signals > > at the output port. If I connect those two signals to any other =A0pin, > > it doesn't seem to work. > > I hope the problem is clear now. > > > Thanks, > > Pratap- Hide quoted text - > > > - Show quoted text - > > Sorry, it still isn't very clear and you still haven't identified > which exact board you are using (vendor and model). > > As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for > anything other that the MGT. =A0For this device pins F16 and G16 are > regular IO and also MGT reference clock input pins so they can be used > for inputs or outputs. > > > If I connect those two signals to any other =A0pin, > > it doesn't seem to work. > > It isn't clear what you mean by any other pin and what doesn't work. > > Ed McGettigan > -- > Xilinx Inc. OK. Let me rephrase the problem. All I want is, I want to take a signal out of the Xilinx Virtex II Pro board which is fed to the FPGA pin "G15" (EXT_CLK_N). If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA through the pin "F15" (EXT_CLK_P), it works absolutely fine. But when I use both the pins F15 and G15 for two different input signals, and want to take a delayed version of the signal fed to "G15", by routing it through any of the pins in the connector series located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I want to stimulate another chip with this delayed signal coming from FPGA. The P&R completes without any problem when I use the Pin J37-A14 or any other pin, but when I am checking the signal at that pin by connecting an oscilloscope probe there, I don't see any signal there. This is what I mean by, things don't work. Is is there any issue in taking out the signals connected to F15 or G15 once I use both of those pins as inputs? If yes, why so and what is the way around? I hope the question is more straight forward now and thanks for the patience shown in understanding the issue. Thanks, PratapArticle: 151357
On Mar 27, 9:57=A0am, Pratap <pratap.i...@gmail.com> wrote: > On Mar 27, 9:39=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Mar 26, 8:41=A0pm, Pratap <pratap.i...@gmail.com> wrote: > > > > On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only b= e used > > > > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT refere= nce clock > > > > > > pins were normal I/Os that had extra dedicated routing to the M= GTs. > > > > > > > Are you using a Xilinx board? =A0If so which one is it? > > > > > > > What are the IO location constraints that you are using for the= output > > > > > > and input paths? > > > > > > > Ed McGettigan > > > > > > -- > > > > > > Xilinx Inc. > > > > > > Hello, > > > > > I am using the Virtex II Pro development board for my project. > > > > > I am pasting all the IO constraints written to the ucf file. > > > > > The signals to take out and then feed in are "inp_for_TI_chip" an= d > > > > > "op_from_TI_chip" respectively. > > > > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25; > > > > > #LEFT P/B > > > > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > > > > > #EXTERNAL_CLOCK_P > > > > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25; > > > > > #EXTERNAL_CLOCK_N > > > > > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS25; > > > > > #MGT_TXP > > > > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS25 |= SLEW =3D > > > > > FAST | DRIVE =3D 8 ; > > > > > #MGT_TXN > > > > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D LVCMOS2= 5 | SLEW =3D > > > > > FAST | DRIVE =3D 8 ; > > > > > #J5-11 > > > > > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS25 | = SLEW =3D FAST > > > > > | DRIVE =3D 8 ; > > > > > #J5-15 > > > > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | SLEW= =3D FAST | > > > > > DRIVE =3D 8 ; > > > > > #J6-27 > > > > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D FAST | > > > > > DRIVE =3D 8 ; > > > > > #J6-35 > > > > > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 | SL= EW =3D FAST | > > > > > DRIVE =3D 8 ; > > > > > #J5-31 > > > > > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 | SL= EW =3D FAST | > > > > > DRIVE =3D 8 ; > > > > > #J5-39 > > > > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D SLOW | > > > > > DRIVE =3D 12 ; > > > > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D SLOW | > > > > > DRIVE =3D 12 ; > > > > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D SLOW | > > > > > DRIVE =3D 12 ; > > > > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D SLOW | > > > > > DRIVE =3D 12 ; > > > > > > Thanks, > > > > > Pratap > > > > > The UCF file constraints have regular IO location assignments to A7 > > > > and A6 which are the MGT TXP/TXN pins. =A0These locations are not v= alid > > > > for anything other than MGT TXP/TXN pins and your original post > > > > indicated that you had changed these to other locations and it work= ed. > > > > > I'm confused. =A0What exactly is your question or problem? > > > > > Ed McGettigan > > > > -- > > > > Xilinx Inc. > > > > Yes, > > > This is the ucf file that is not working. The ucf file that ensures > > > that there is toggling at all the signal ports is as follows. > > > > NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D LVCMOS25; > > > #MGT_CLK_P > > > > NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D LVCMOS25 | SL= EW =3D > > > FAST | DRIVE =3D 8 ; > > > #MGT_CLK_N > > > > My exact problem is in understanding why in the case when I connect > > > the pins intended to be interfaced with the other chip to F16 and > > > G16(The externally non-accessible ports on board) , I get the signals > > > at the output port. If I connect those two signals to any other =A0pi= n, > > > it doesn't seem to work. > > > I hope the problem is clear now. > > > > Thanks, > > > Pratap- Hide quoted text - > > > > - Show quoted text - > > > Sorry, it still isn't very clear and you still haven't identified > > which exact board you are using (vendor and model). > > > As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used for > > anything other that the MGT. =A0For this device pins F16 and G16 are > > regular IO and also MGT reference clock input pins so they can be used > > for inputs or outputs. > > > > If I connect those two signals to any other =A0pin, > > > it doesn't seem to work. > > > It isn't clear what you mean by any other pin and what doesn't work. > > > Ed McGettigan > > -- > > Xilinx Inc. > > OK. > Let me rephrase the problem. > All I want is, I want to take a signal out of the Xilinx Virtex II Pro > board which is fed to the FPGA pin "G15" (EXT_CLK_N). > If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA > through the pin "F15" (EXT_CLK_P), it works absolutely fine. > But when I use both the pins F15 and G15 for two different input > signals, and want to take a delayed version of the signal fed to > "G15", by routing it through any of the pins in the connector series > located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I > want to stimulate another chip with this delayed signal coming from > FPGA. The P&R completes without any problem when I use the Pin J37-A14 > or any other pin, but when I am checking the signal at that pin by > connecting an oscilloscope probe there, I don't see any signal there. > This is what I mean by, things don't work. Is is there any issue in > taking out the signals connected to F15 or G15 once I use both of > those pins as inputs? If yes, why so and what is the way around? > I hope the question is more straight forward now and thanks for the > patience shown in understanding the issue. > Thanks, > Pratap- Hide quoted text - > > - Show quoted text - Pratap, You still haven't said what board you are using. who made the board and what is the model name? This is very important information. Ed McGettigan -- Xilinx Inc.Article: 151358
On Mar 27, 7:39=A0pm, Jonathan Bromley <s...@oxfordbromley.plus.com> wrote: > On Sun, 27 Mar 2011 08:42:30 -0700 (PDT), electrocoder > > <electroco...@gmail.com> wrote: > >i want "fpga express 3.6" setup program. i have "ftp://ftp.xilinx.com/ > >pub/swhelp/M3.1i_updates/fpgaexp35.exe" update files. i want setup > >program. thanks. > > FPGA Express has been very dead and very unsupported for > a very long time. =A0If you have a client who's insisting > on its use, tell the client they will have to find you > an installation and a licence. =A0Otherwise, pick one of > the available alternatives. =A0What can FPGA Express do > for you that XST can't? > -- > Jonathan Bromley I found update files. I want setup program. Unfortunately not found alternatives . Update files in Xilinx ftp for please : ftp://ftp.xilinx.com/pub/swhelp/M3= .1i_updates/Article: 151359
On Mar 28, 2:25=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Mar 27, 9:57=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > On Mar 27, 9:39=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Mar 26, 8:41=A0pm, Pratap <pratap.i...@gmail.com> wrote: > > > > > On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrot= e: > > > > > > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can only= be used > > > > > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT refe= rence clock > > > > > > > pins were normal I/Os that had extra dedicated routing to the= MGTs. > > > > > > > > Are you using a Xilinx board? =A0If so which one is it? > > > > > > > > What are the IO location constraints that you are using for t= he output > > > > > > > and input paths? > > > > > > > > Ed McGettigan > > > > > > > -- > > > > > > > Xilinx Inc. > > > > > > > Hello, > > > > > > I am using the Virtex II Pro development board for my project. > > > > > > I am pasting all the IO constraints written to the ucf file. > > > > > > The signals to take out and then feed in are "inp_for_TI_chip" = and > > > > > > "op_from_TI_chip" respectively. > > > > > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25; > > > > > > #LEFT P/B > > > > > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > > > > > > #EXTERNAL_CLOCK_P > > > > > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25; > > > > > > #EXTERNAL_CLOCK_N > > > > > > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS25= ; > > > > > > #MGT_TXP > > > > > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS25= | SLEW =3D > > > > > > FAST | DRIVE =3D 8 ; > > > > > > #MGT_TXN > > > > > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D LVCMO= S25 | SLEW =3D > > > > > > FAST | DRIVE =3D 8 ; > > > > > > #J5-11 > > > > > > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS25 = | SLEW =3D FAST > > > > > > | DRIVE =3D 8 ; > > > > > > #J5-15 > > > > > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | SL= EW =3D FAST | > > > > > > DRIVE =3D 8 ; > > > > > > #J6-27 > > > > > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | SLE= W =3D FAST | > > > > > > DRIVE =3D 8 ; > > > > > > #J6-35 > > > > > > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 | = SLEW =3D FAST | > > > > > > DRIVE =3D 8 ; > > > > > > #J5-31 > > > > > > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 | = SLEW =3D FAST | > > > > > > DRIVE =3D 8 ; > > > > > > #J5-39 > > > > > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D SLOW | > > > > > > DRIVE =3D 12 ; > > > > > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D SLOW | > > > > > > DRIVE =3D 12 ; > > > > > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D SLOW | > > > > > > DRIVE =3D 12 ; > > > > > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLEW = =3D SLOW | > > > > > > DRIVE =3D 12 ; > > > > > > > Thanks, > > > > > > Pratap > > > > > > The UCF file constraints have regular IO location assignments to = A7 > > > > > and A6 which are the MGT TXP/TXN pins. =A0These locations are not= valid > > > > > for anything other than MGT TXP/TXN pins and your original post > > > > > indicated that you had changed these to other locations and it wo= rked. > > > > > > I'm confused. =A0What exactly is your question or problem? > > > > > > Ed McGettigan > > > > > -- > > > > > Xilinx Inc. > > > > > Yes, > > > > This is the ucf file that is not working. The ucf file that ensures > > > > that there is toggling at all the signal ports is as follows. > > > > > NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D LVCMOS25; > > > > #MGT_CLK_P > > > > > NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D LVCMOS25 | = SLEW =3D > > > > FAST | DRIVE =3D 8 ; > > > > #MGT_CLK_N > > > > > My exact problem is in understanding why in the case when I connect > > > > the pins intended to be interfaced with the other chip to F16 and > > > > G16(The externally non-accessible ports on board) , I get the signa= ls > > > > at the output port. If I connect those two signals to any other =A0= pin, > > > > it doesn't seem to work. > > > > I hope the problem is clear now. > > > > > Thanks, > > > > Pratap- Hide quoted text - > > > > > - Show quoted text - > > > > Sorry, it still isn't very clear and you still haven't identified > > > which exact board you are using (vendor and model). > > > > As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used fo= r > > > anything other that the MGT. =A0For this device pins F16 and G16 are > > > regular IO and also MGT reference clock input pins so they can be use= d > > > for inputs or outputs. > > > > > If I connect those two signals to any other =A0pin, > > > > it doesn't seem to work. > > > > It isn't clear what you mean by any other pin and what doesn't work. > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > OK. > > Let me rephrase the problem. > > All I want is, I want to take a signal out of the Xilinx Virtex II Pro > > board which is fed to the FPGA pin "G15" (EXT_CLK_N). > > If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA > > through the pin "F15" (EXT_CLK_P), it works absolutely fine. > > But when I use both the pins F15 and G15 for two different input > > signals, and want to take a delayed version of the signal fed to > > "G15", by routing it through any of the pins in the connector series > > located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I > > want to stimulate another chip with this delayed signal coming from > > FPGA. The P&R completes without any problem when I use the Pin J37-A14 > > or any other pin, but when I am checking the signal at that pin by > > connecting an oscilloscope probe there, I don't see any signal there. > > This is what I mean by, things don't work. Is is there any issue in > > taking out the signals connected to F15 or G15 once I use both of > > those pins as inputs? If yes, why so and what is the way around? > > I hope the question is more straight forward now and thanks for the > > patience shown in understanding the issue. > > Thanks, > > Pratap- Hide quoted text - > > > - Show quoted text - > > Pratap, > > You still haven't said what board you are using. who made the board > and what is the model name? =A0This is very important information. > > Ed McGettigan > -- > Xilinx Inc. Sorry, Actually, it never struck to my mind that there are other varieties of Xilinx Virtex-II Pro. Here is the Target Device name: "Virtex-II Pro XC2VP30-7ff896" Product link: http://www.xilinx.com/products/devkits/XUPV2P.htm Image: http://www.xilinx.com/products/devkits/XUPV2P-image.htm Thanks, PratapArticle: 151360
On Mar 27, 3:21=A0pm, electrocoder <electroco...@gmail.com> wrote: > On Mar 27, 7:39=A0pm, Jonathan Bromley <s...@oxfordbromley.plus.com> > wrote: > > > On Sun, 27 Mar 2011 08:42:30 -0700 (PDT), electrocoder > > > <electroco...@gmail.com> wrote: > > >i want "fpga express 3.6" setup program. i have "ftp://ftp.xilinx.com/ > > >pub/swhelp/M3.1i_updates/fpgaexp35.exe" update files. i want setup > > >program. thanks. > > > FPGA Express has been very dead and very unsupported for > > a very long time. =A0If you have a client who's insisting > > on its use, tell the client they will have to find you > > an installation and a licence. =A0Otherwise, pick one of > > the available alternatives. =A0What can FPGA Express do > > for you that XST can't? > > -- > > Jonathan Bromley > > I found update files. I want setup program. Unfortunately not found > alternatives . > Update files in Xilinx ftp =A0for please :ftp://ftp.xilinx.com/pub/swhelp= /M3.1i_updates/ The OEM agreement that Xilinx had with Synopsys ended back in 2000 with the ISE 4.1i. After this point in time Xilinx would not be able to provide to software or license keys to be able to enable it to work. Support for existing users would still have been provided for a period of 1 year. It is unclear why you want to use the very old FPGA Express synthesizer instead of the XST synthesizer in the current ISE software. Ed McGettigan -- Xilinx Inc.Article: 151361
On Mar 27, 3:23=A0pm, Pratap <pratap.i...@gmail.com> wrote: > On Mar 28, 2:25=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Mar 27, 9:57=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > On Mar 27, 9:39=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > On Mar 26, 8:41=A0pm, Pratap <pratap.i...@gmail.com> wrote: > > > > > > On Mar 27, 6:39=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wr= ote: > > > > > > > On Mar 26, 7:53=A0am, Pratap <pratap.i...@gmail.com> wrote: > > > > > > > > > The MGT TXP/TXN/RXP/RXN pins are dedicated pins that can on= ly be used > > > > > > > > by the MGTs. =A0In the Virtex-II Pro FPGA family the MGT re= ference clock > > > > > > > > pins were normal I/Os that had extra dedicated routing to t= he MGTs. > > > > > > > > > Are you using a Xilinx board? =A0If so which one is it? > > > > > > > > > What are the IO location constraints that you are using for= the output > > > > > > > > and input paths? > > > > > > > > > Ed McGettigan > > > > > > > > -- > > > > > > > > Xilinx Inc. > > > > > > > > Hello, > > > > > > > I am using the Virtex II Pro development board for my project= . > > > > > > > I am pasting all the IO constraints written to the ucf file. > > > > > > > The signals to take out and then feed in are "inp_for_TI_chip= " and > > > > > > > "op_from_TI_chip" respectively. > > > > > > > > NET "reset_in" LOC =3D "AH1" | IOSTANDARD =3D LVCMOS25; > > > > > > > #LEFT P/B > > > > > > > > NET "clk_in" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > > > > > > > #EXTERNAL_CLOCK_P > > > > > > > > NET "samp_clk" LOC =3D "F15" | IOSTANDARD =3D LVCMOS25; > > > > > > > #EXTERNAL_CLOCK_N > > > > > > > > NET "op_from_TI_chip" =A0LOC =3D "A6" | IOSTANDARD =3D LVCMOS= 25; > > > > > > > #MGT_TXP > > > > > > > > NET "inp_for_TI_chip" =A0LOC =3D "A7" | IOSTANDARD =3D LVCMOS= 25 | SLEW =3D > > > > > > > FAST | DRIVE =3D 8 ; > > > > > > > #MGT_TXN > > > > > > > > NET "ti_delay_chip_cntl" =A0LOC =3D "R9" | IOSTANDARD =3D LVC= MOS25 | SLEW =3D > > > > > > > FAST | DRIVE =3D 8 ; > > > > > > > #J5-11 > > > > > > > > NET "dir_fine_delay" =A0LOC =3D "P1" | IOSTANDARD =3D LVCMOS2= 5 | SLEW =3D FAST > > > > > > > | DRIVE =3D 8 ; > > > > > > > #J5-15 > > > > > > > > NET "board_in1" =A0LOC =3D "AB1" | IOSTANDARD =3D LVCMOS25 | = SLEW =3D FAST | > > > > > > > DRIVE =3D 8 ; > > > > > > > #J6-27 > > > > > > > > NET "board_in2" =A0LOC =3D "W8" | IOSTANDARD =3D LVCMOS25 | S= LEW =3D FAST | > > > > > > > DRIVE =3D 8 ; > > > > > > > #J6-35 > > > > > > > > NET "cleaned_clk1" =A0LOC =3D "R3" | IOSTANDARD =3D LVCMOS25 = | SLEW =3D FAST | > > > > > > > DRIVE =3D 8 ; > > > > > > > #J5-31 > > > > > > > > NET "cleaned_clk2" =A0LOC =3D "U3" | IOSTANDARD =3D LVCMOS25 = | SLEW =3D FAST | > > > > > > > DRIVE =3D 8 ; > > > > > > > #J5-39 > > > > > > > > NET "status(3)" LOC =3D "AC4" | IOSTANDARD =3D LVCMOS25 | SLE= W =3D SLOW | > > > > > > > DRIVE =3D 12 ; > > > > > > > NET "status(2)" LOC =3D "AC3" | IOSTANDARD =3D LVCMOS25 | SLE= W =3D SLOW | > > > > > > > DRIVE =3D 12 ; > > > > > > > NET "status(1)" LOC =3D "AA6" | IOSTANDARD =3D LVCMOS25 | SLE= W =3D SLOW | > > > > > > > DRIVE =3D 12 ; > > > > > > > NET "status(0)" LOC =3D "AA5" | IOSTANDARD =3D LVCMOS25 | SLE= W =3D SLOW | > > > > > > > DRIVE =3D 12 ; > > > > > > > > Thanks, > > > > > > > Pratap > > > > > > > The UCF file constraints have regular IO location assignments t= o A7 > > > > > > and A6 which are the MGT TXP/TXN pins. =A0These locations are n= ot valid > > > > > > for anything other than MGT TXP/TXN pins and your original post > > > > > > indicated that you had changed these to other locations and it = worked. > > > > > > > I'm confused. =A0What exactly is your question or problem? > > > > > > > Ed McGettigan > > > > > > -- > > > > > > Xilinx Inc. > > > > > > Yes, > > > > > This is the ucf file that is not working. The ucf file that ensur= es > > > > > that there is toggling at all the signal ports is as follows. > > > > > > NET "op_from_TI_chip" =A0LOC =3D "F16" | IOSTANDARD =3D LVCMOS25; > > > > > #MGT_CLK_P > > > > > > NET "inp_for_TI_chip" =A0LOC =3D "G16" | IOSTANDARD =3D LVCMOS25 = | SLEW =3D > > > > > FAST | DRIVE =3D 8 ; > > > > > #MGT_CLK_N > > > > > > My exact problem is in understanding why in the case when I conne= ct > > > > > the pins intended to be interfaced with the other chip to F16 and > > > > > G16(The externally non-accessible ports on board) , I get the sig= nals > > > > > at the output port. If I connect those two signals to any other = =A0pin, > > > > > it doesn't seem to work. > > > > > I hope the problem is clear now. > > > > > > Thanks, > > > > > Pratap- Hide quoted text - > > > > > > - Show quoted text - > > > > > Sorry, it still isn't very clear and you still haven't identified > > > > which exact board you are using (vendor and model). > > > > > As I said twice already, the MGT TXP/TXN pins A6/A7 cannot be used = for > > > > anything other that the MGT. =A0For this device pins F16 and G16 ar= e > > > > regular IO and also MGT reference clock input pins so they can be u= sed > > > > for inputs or outputs. > > > > > > If I connect those two signals to any other =A0pin, > > > > > it doesn't seem to work. > > > > > It isn't clear what you mean by any other pin and what doesn't work= . > > > > > Ed McGettigan > > > > -- > > > > Xilinx Inc. > > > > OK. > > > Let me rephrase the problem. > > > All I want is, I want to take a signal out of the Xilinx Virtex II Pr= o > > > board which is fed to the FPGA pin "G15" (EXT_CLK_N). > > > If I give a signal to "G15" (EXT_CLK_N) and take it out of FPGA > > > through the pin "F15" (EXT_CLK_P), it works absolutely fine. > > > But when I use both the pins F15 and G15 for two different input > > > signals, and want to take a delayed version of the signal fed to > > > "G15", by routing it through any of the pins in the connector series > > > located on J5 or J6 or J37(Eg AC6 on J37-A14), it doesn't come out. I > > > want to stimulate another chip with this delayed signal coming from > > > FPGA. The P&R completes without any problem when I use the Pin J37-A1= 4 > > > or any other pin, but when I am checking the signal at that pin by > > > connecting an oscilloscope probe there, I don't see any signal there. > > > This is what I mean by, things don't work. Is is there any issue in > > > taking out the signals connected to F15 or G15 once I use both of > > > those pins as inputs? If yes, why so and what is the way around? > > > I hope the question is more straight forward now and thanks for the > > > patience shown in understanding the issue. > > > Thanks, > > > Pratap- Hide quoted text - > > > > - Show quoted text - > > > Pratap, > > > You still haven't said what board you are using. who made the board > > and what is the model name? =A0This is very important information. > > > Ed McGettigan > > -- > > Xilinx Inc. > > Sorry, > Actually, it never struck to my mind that there are other varieties of > Xilinx Virtex-II Pro. > Here is the Target Device name: "Virtex-II Pro XC2VP30-7ff896" > Product link:http://www.xilinx.com/products/devkits/XUPV2P.htm > Image:http://www.xilinx.com/products/devkits/XUPV2P-image.htm > Thanks, > Pratap- Hide quoted text - > > - Show quoted text - Virtex-II Pro is a FPGA family which is collection different device sizes and package options with a common architecture. Boards that use FPGAs are each unique implementations with a fixed set of features that the FPGA design most conform to or it won't work. The Xilinx XUP2VP board and your IO constraints have a couple of problems: 1) G15/F15 are connected on the board with a 100 ohm termination resistor When you said that you "gave" a signal to G15 and "took" it from F15 the 100 ohm resistor provided a pass through of the signal and the FPGA did not need to be involved. It isn't clear what is actually happening on your setup. If the input did resolve to a 0/1 in the FPGA then the output should drive the same value a few nanosconds later. This would lead to some contention during this period and the output waveform would not be clean. Your oscilloscope may be filtering this out due to the short duration. 2) The VCCO for the banks that you are using are 3.3V Bank 1 (F16/G16) and bank 3 (AC6) both have VCCO levels of 3.3V, but your UCF file has defined these IOs as LVCMOS25. The output should still be working, but without the correct drive strengths and levels. The input functionality will depend on the voltage that is present on the pin. It may resolve or it may not. You haven't said anything about the actual device that you are trying to interface with so I don't know what levels it is expecting and putting out. If the levels are correct then nothing will work. There is the possibilities that you have are not probing the correct pin on the connector. I would suggest that you try outputting the system clock to the desired pin to verify that you are probing/ connecting the right pin. Ed McGettigan -- Xilinx Inc.Article: 151362
On Mar 23, 6:23=A0pm, John McCaskill <jhmccask...@gmail.com> wrote: > On Mar 23, 4:16=A0pm, DaMunky89 <shwankymu...@gmail.com> wrote: > > > > > Currently, when trying to download the bitstream to this SP605 board, > > I get the following error: > > > FPGA configuration encountered errors. > > Program FPGA failed > > =A0 =A0ERROR: Connection to Board Failed > > Failed to Open JTAG Cable > > =A0 =A0 Check the following: > > =A0 =A0 1. Cable is Connected to the Board and the Board is Powered-ON > > =A0 =A0 2. On Cable Lock Error, Close the other application using the > > cable or Remove Cable Locks using "xclean_cablelock" command > > =A0 =A0 3. You have specified the correct JTAG settings for cable type = and > > port. > > > So basically the SDK is not seeing the board. It's odd, because in my > > "Devices and Printers" window it does appear as "Silicon Labs CP210x > > USB to UART Bridge (COM3)". Currently it seems that my computer thinks > > this connection is a wired mouse. (That's the icon it's showing.) > > Earlier it was using the generic "unidentified device" icon, but it > > has been unplugged and reattached a couple times since then. > > > I'm using SDK version 12.3 on a Windows 7 x64 version 6.1.7600 Build > > 7600. > > I tried following the instructions in the included "Getting Started" > > pamphlet to ensure the board was hooked up correctly, and basically > > when I got to the part where the Xilinx logo is supposed to appear > > onscreen I instead get large horizontal green and purple strips, > > overlaid with vertical lines in different shades of grey and black. I > > get the impression that either the board as a whole, or perhaps just > > the adapter piece for the monitor cable is broken. > > > I am getting a solid green and a solid red "Error" LED in the upper- > > right corner of the board. Not sure if these mean anything. Any ideas > > as to how I can get this connected and running projects? > > The SP605 has two mini USB ports on it. One of them is a USB to serial > port, and that appears to be what you have connected to if you see the > Silicon Labs part. The other one is the USB to JTAG port. =A0Try > connecting to that one, and see if the "Failed to Open JTAG Cable" > error message goes away. > > Regards, > > John McCaskillwww.FasterTechnology.com Yeah, I tried that one, and I just got the "could not find drivers" error when Windows tried to set it up.Article: 151363
I have MAX II CPLD with clock of 24.576 MHz as input coming from the external crystal oscillator. This clock is used inside the CPLD to generate sub clocks, thats no problem. Also, my design needs to output the incoming 24.576 MHz clock as it is to the external Audio DAC through one of the I/O pins. So I have three options. Which one is the best option for lowest possible jitter? 1) Output the 24.576 MHz clock through one of the I/O pins that is as close as possible to the input clock pin. This reduces the clock path. Please correct if my assumption is wrong. 2) Use Global clock pins for clock input and output. These are optimized for clock distribution but may have longer paths. 3) Use 1-to-2 buffer (74xxx series) after the oscillator output and split the clock to CPLD and the DAC. Thanks in advance -MarkArticle: 151364
Hi, I have a fully routed Spartan3(Alliance 9,2) that I would like to keep the routing and only change the "IOB Input Switching Characteristic" for all used IOs, I know how to do this in the FPGA Editor but I would like to do this using a new "ucf" file. The reason is that I have some issues and like to try out different Characteristics. Anyone know how to do this? /michaelArticle: 151365
On Mar 28, 5:37=A0am, Michael <michael_laaja...@yahoo.com> wrote: > Hi, > > I have a fully routed Spartan3(Alliance 9,2) that I would like to keep > the routing and only change the "IOB Input Switching Characteristic" for > all used IOs, I know how to do this in the FPGA Editor but I would like > to do this using a new "ucf" file. > > The reason is that I have some issues and like to try out different > Characteristics. > > Anyone know how to do this? > > /michael Going back the UCF file to make this change means that you need start the design implementation over from the map and that could mean changes in your placement and routing. The MAP and PAR tools do offer the option to use a previous NCD file to guide the the mapping and placement. For both MAP and PAR this would be "-gf my_old.ncd -gm exact". The "- gf" is the Guide File and the "-gm" is the Guide Mode. Using FPGA Editor will be far easier to accomplish what you want to do and you don't need to do everything through the GUI. Use the GUI the first time to get the commands to select an IOB and change the IOSTANDARD and then create a text file to replicate these commands across all of your IOBs. You can run this script using the non-GUI version by using the fpga_edline tool instead of fpga_editor. fpga_edline -p my_script.txt my_design.ncd Don't forget to add a save command to write the NCD at the end before quitting. Ed McGettigan -- Xilinx Inc.Article: 151366
Hi, On 03/28/11 04:37 PM, Ed McGettigan wrote: > On Mar 28, 5:37 am, Michael<michael_laaja...@yahoo.com> wrote: >> Hi, >> >> I have a fully routed Spartan3(Alliance 9,2) that I would like to keep >> the routing and only change the "IOB Input Switching Characteristic" for >> all used IOs, I know how to do this in the FPGA Editor but I would like >> to do this using a new "ucf" file. >> >> The reason is that I have some issues and like to try out different >> Characteristics. >> >> Anyone know how to do this? >> >> /michael > > Going back the UCF file to make this change means that you need start > the design implementation over from the map and that could mean > changes in your placement and routing. The MAP and PAR tools do offer > the option to use a previous NCD file to guide the the mapping and > placement. No I don't like to do like that. > > For both MAP and PAR this would be "-gf my_old.ncd -gm exact". The "- > gf" is the Guide File and the "-gm" is the Guide Mode. > > Using FPGA Editor will be far easier to accomplish what you want to do > and you don't need to do everything through the GUI. Use the GUI the > first time to get the commands to select an IOB and change the > IOSTANDARD and then create a text file to replicate these commands > across all of your IOBs. You can run this script using the non-GUI > version by using the fpga_edline tool instead of fpga_editor. > > fpga_edline -p my_script.txt my_design.ncd > > Don't forget to add a save command to write the NCD at the end before > quitting. > > Ed McGettigan > -- > Xilinx Inc. > > Ok, that sounds like the best way thanks!! /michaelArticle: 151367
On Sun, 27 Mar 2011 15:21:10 -0700 (PDT), electrocoder <electrocoder@gmail.com> wrote: >On Mar 27, 7:39 pm, Jonathan Bromley <s...@oxfordbromley.plus.com> >wrote: >> On Sun, 27 Mar 2011 08:42:30 -0700 (PDT), electrocoder >> >> <electroco...@gmail.com> wrote: >> >i want "fpga express 3.6" setup program. i have "ftp://ftp.xilinx.com/ >> >pub/swhelp/M3.1i_updates/fpgaexp35.exe" update files. i want setup >> >program. thanks. >> >> FPGA Express has been very dead and very unsupported for >> a very long time. If you have a client who's insisting >> on its use, tell the client they will have to find you >> an installation and a licence. Otherwise, pick one of >> the available alternatives. What can FPGA Express do >> for you that XST can't? >> -- >> Jonathan Bromley > >I found update files. I want setup program. I have chrome-plated air inlets to improve the performance of a 1958 Studebaker Golden Hawk. Please tell me where I can find a 1958 Studebaker Golden Hawk. -- Jonathan BromleyArticle: 151368
On Mar 28, 1:14=A0pm, Jonathan Bromley <s...@oxfordbromley.plus.com> wrote: > On Sun, 27 Mar 2011 15:21:10 -0700 (PDT), electrocoder > > > > > > <electroco...@gmail.com> wrote: > >On Mar 27, 7:39=A0pm, Jonathan Bromley <s...@oxfordbromley.plus.com> > >wrote: > >> On Sun, 27 Mar 2011 08:42:30 -0700 (PDT), electrocoder > > >> <electroco...@gmail.com> wrote: > >> >i want "fpga express 3.6" setup program. i have "ftp://ftp.xilinx.com= / > >> >pub/swhelp/M3.1i_updates/fpgaexp35.exe" update files. i want setup > >> >program. thanks. > > >> FPGA Express has been very dead and very unsupported for > >> a very long time. =A0If you have a client who's insisting > >> on its use, tell the client they will have to find you > >> an installation and a licence. =A0Otherwise, pick one of > >> the available alternatives. =A0What can FPGA Express do > >> for you that XST can't? > >> -- > >> Jonathan Bromley > > >I found update files. I want setup program. > > I have chrome-plated air inlets to improve > the performance of a 1958 Studebaker Golden Hawk. > Please tell me where I can find a 1958 > Studebaker Golden Hawk. > -- > Jonathan Bromley- Hide quoted text - > > - Show quoted text - :^) AndyArticle: 151369
On Mon, 28 Mar 2011 19:14:43 +0100, Jonathan Bromley <spam@oxfordbromley.plus.com> wrote: >On Sun, 27 Mar 2011 15:21:10 -0700 (PDT), electrocoder ><electrocoder@gmail.com> wrote: > >>On Mar 27, 7:39 pm, Jonathan Bromley <s...@oxfordbromley.plus.com> >>wrote: >>> On Sun, 27 Mar 2011 08:42:30 -0700 (PDT), electrocoder >>> >>> <electroco...@gmail.com> wrote: >>> >i want "fpga express 3.6" setup program. i have "ftp://ftp.xilinx.com/ >>> >pub/swhelp/M3.1i_updates/fpgaexp35.exe" update files. i want setup >>> >program. thanks. >>> >>> FPGA Express has been very dead and very unsupported for >>> a very long time. If you have a client who's insisting >>> on its use, tell the client they will have to find you >>> an installation and a licence. Otherwise, pick one of >>> the available alternatives. What can FPGA Express do >>> for you that XST can't? >>> -- >>> Jonathan Bromley >> >>I found update files. I want setup program. > >I have chrome-plated air inlets to improve >the performance of a 1958 Studebaker Golden Hawk. >Please tell me where I can find a 1958 >Studebaker Golden Hawk. Dateline New York: Financial analysts were surprised to see that automated stock trading programs suddenly all started attempting to go long on Studebaker. (See <http://www.thefiscaltimes.com/Blogs/Business-Buzz/2011/03/23/The-Hathaway-Effect-Is-Ann-Good-for-Berkshire.aspx> for an explanation of the admittedly lame joke.) -- Rich Webb Norfolk, VAArticle: 151370
On Mar 28, 11:01=A0pm, Mark <markjsu...@gmail.com> wrote: > 3) Use 1-to-2 buffer (74xxx series) after the oscillator output and > split the clock to CPLD and the DAC. If you are jitter paranoid, then it is always best to avoid going thru complex logic. -jgArticle: 151371
On Mar 29, 8:25=A0am, Jim Granville <j.m.granvi...@gmail.com> wrote: > On Mar 28, 11:01=A0pm, Mark <markjsu...@gmail.com> wrote: > > > 3) Use 1-to-2 buffer (74xxx series) after the oscillator output and > > split the clock to CPLD and the DAC. > > =A0If you are jitter paranoid, then it is always best to avoid going > thru complex logic. > > -jg Thanks jg. What do you suggest? Normal 74LS/74HC buffers or clock buffers? Is there any advantage of using clock buffers over normal buffers for digital audio? -MarkArticle: 151372
On Mar 29, 4:29=A0pm, Mark <markjsu...@gmail.com> wrote: > Thanks jg. What do you suggest? Normal 74LS/74HC buffers or clock > buffers? Is there any advantage of using clock buffers over normal > buffers for digital audio? I've seen Single-gate logic used for this type of work. The secret seems to be no common mode supply noise from anything other than the clock itself. - as any dV on a finite edge, becomes a dT aka jitter. If you use a non inverting unit, you can design it in, and then see if you can remove it, and measure no change :) -jgArticle: 151373
HELLO
I want to use the below function to the xilinx system generator MCode
Block, but I faced some errors . how to solve this problem.The code
executed well in matlab but when I used MCode Block it gave me errors.
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
%the function is:
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
function s=dyn_focusing(RF,Lin)
prec = {xlSigned, 16, 0, xlRound, xlWrap};
persistent m, m=xl_state(zeros(1,len),prec);
s=m;
len=512;
for k=1:len
if Lin(k)<=len
s(k)=RF(1,Lin(k));
if Lin(k)>len
s(k)=0;
end
end
end
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
where RF and Lin are (1X512) array
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 151374Hey, I need to send data(1158 samples x 21 features) to Spartan 3e FPGA board from the matlab workspace with rs232 and then do K-means classification on that and then return the data (1158samples x 1 group(1-4)) from the FPGA back into the matlab workspace. How do I do that? Kindly let me know if there is some tutorial which is spartan 3e specific on this which can tell me how to do it step by step. Thanks and Regards, Cavalry --------------------------------------- Posted through http://www.FPGARelated.com
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