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>On Apr 26, 10:10=A0am, Berk <berkgura...@gmail.com> wrote: >> On 26 Nisan, 16:39, Gabor <ga...@alacron.com> wrote: >> >> >> >> > On Apr 26, 9:17=A0am, Berk <berkgura...@gmail.com> wrote: >> >> > > Hey everyone, >> >> > > I have been struggling to use the MIG to generate a memory interface >> > > to the DDR2 device. First some background info: I am using the Xilinx= >=AE >> > > Spartan=AE-3A DSP XtremeDSP=99 Starter Platform. I am using ISE 10.1 = >with >> > > MIG v2.3. >> >> > > I have created the MIG from GUI and played around with it. I also >> > > edited the UCF file (just changed the locations basically, did not >> > > mess around with timings). I cannot do any simulation because I am >> > > using Windows 7 and apparently, simulation doesn't work (or maybe some >> > > other problem). There is another thread about that, see: http://www.fpgarelated.com/usenet/fpga/show/92403-1.php >> >> > > Anyway, the thing is I can download the code to the device and I can >> > > see all the signals go up and down in correct times. (like init_done, >> > > user_cmd_ack, user_data_valid etc.) Then I try to write some data to >> > > the memory, I can see user_cmd_ack go high, then I assert burst_done, >> > > then I can see user_cmd_ack go low. (which means write is succesful, >> > > right?) However, whenever I try to 'read' from the memory, I always >> > > get x"00000000" no matter what the address is. What can be wrong with >> > > it? >> >> > > Thanks for the help. >> >> Hello, >> >> > DDR2 timing is not easy to meet in the Spartan parts, so you really >> > can't just muck around with the pinouts. =A0If you changed the location >> > of any memory pins you need to re-run the MIG configuration GUI and >> > use the option to "Verify UCF". =A0This tells MIG to generate new >> > timing and directed routing constraints based on the pin locations >> > from your actual design. >> >> Actually, I did just that. First, I let MIG create a 'wrong' UCF file. >> Then I changed the pinouts correctly. Then I >> selected "Update Design" and pointed it to my newly edited UCF file. >> Then, it changed the pinouts and timings. >> But there is no change in the output. By the way I am changing the UCF >> file under the user_design folder. I think >> this is correct. How can I verify if I'm having a UCF error or >> something else? >> >> > By the way I thought that the Starter boards come with a pre-built >> > version of the MIG design. =A0Have you looked into that? >> > Regards, >> > Gabor >> >> Yeah, I did that but my Starter board is not supported. >> >> Thanks a lot. > >Well the obvious thing you can do is check the pad report >to make sure the correct pinout is in use. You can also go >into the FPGA editor and check that your MIG-related pins >have all the appropriate registers in the IOB tiles. > >Then there's the obvious stuff like checking your clock >and reset inputs to be sure they're hooked up properly. >I've often started going down a head-scratching path >with DDR designs only to find that the active-low >reset input was connected to an active high reset signal, >or that the DCM was being reset be a register clocked >on its own output (this doesn't work with DCM's because >the CLK0 output shuts off when reset is active). > >HTH, >Gabor > Which is why I have found simulation to be so useful. But beware the odd case when the simulation model doesn't match the synthesised behaviour! In my experience, MiG 2.3 DDR2 controllers seem to be ok for Virtex-4. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147426
On Mon, 26 Apr 2010 18:26:25 -0700 (PDT), Patrick Maupin <pmaupin@gmail.com> wrote: >On Apr 26, 7:15 pm, Andy <jonesa...@comcast.net> wrote: >> Cliff's paper is about avoiding race conditions. However, in vhdl >> "blocking assignements" (to unshared variables) are limited to local >> process/subprogram scope anyway, so you never have problems with race >> conditions with them. That is why it is safe and even beneficial to >> use blocking assignments (to unshared variables) in VHDL clocked >> processes. > >Yes, the two process model probably isn't nearly as useful in VHDL. > >As others have been quick to point out, you don't need a combinatorial >process in verilog either, but then you have to be careful about >blocking vs. non-blocking, not using variables which have blocking >assignments to them from other processes, etc. The two process model >is simply an organizing principle that provides a separation of >concerns and simplifies the rules a bit, making it easier to reason >about the code. Extremely simple code doesn't gain anything from >using this model, but a lot of real-world code does. I have to wonder if *that* is the reason the two-process model refuses to die in VHDL textbooks, tutorials, and example designs worldwide. Perhaps too many educators focus on comparing the languages, showing how the same thing is done *the same way* in both languages. I would prefer to see each language shown off at its best. Then VHDL could be illustrated with the (much less verbose) single process model, functions and procedures to raise the abstraction level and simplify the main process, and proper use of the type system to help rather than frustrate the user. (e.g. recently here, there was an example where someone frustrated himself by using a type with integer semantics when he really wanted a type with modular semantics, so he had to code all the wrap-arounds by hand. Easy pitfall for someone used to C which doesn't have any types with integer semantics.) Likewise best practice in Verilog could be illustrated. (I have no idea what that is; hearsay suggests it would include avoiding races, avoiding problems with signed arithmetic, implicit declarations and so on. But Verilog must have real strengths too) - BrianArticle: 147427
On Tue, 27 Apr 2010 10:03:34 +0200, Martin Brückner <bj2spam@alice-dsl.net> wrote: >Am Mon, 26 Apr 2010 22:08:02 +0000 (UTC) >schrieb glen herrmannsfeldt <gah@ugcs.caltech.edu>: > >> Martin Br?ckner <bj2spam@alice-dsl.net> wrote: >> >> > I'm writing a boot loader to start Linux on the PowerPC440 >> > (Virtex5FXT). At first the program copies the kernel into the RAM >> > at address 0x00400000 and afterwards it boots Linux with the >> > following lines: >> >> > #define LINUX_START_ADDRESS 0x004002b4 >> >> (snip) >> >> > (*linux)(); >> >> With the assumption that data pointers can be properly >> cast to function pointers, that line should jump to >> location 0x4002b4 and start executing the code there. I haven't used the PPC since the V2Pro, but... Xilinx example code typically has boilerplate to do things like invalidate caches and set up interrupt state before handing over to "real" code. It is possible that using XMD to reset the CPU does that for you. Have you covered these bases in your own code? - BrianArticle: 147428
On Apr 26, 9:42=A0pm, "Pete Fraser" <pfra...@covad.net> wrote: > "dgreig" <dgr...@ieee.org> wrote in message > > news:8c1c9a60-fef0-4aa2-aa00-54761db33af0@s41g2000vba.googlegroups.com... > > > Perhaps suppose it is image sensor data and feature detection DSP. > > Data is naturally unsigned and the other operand mostly signed. In > > this case say 9*9 and 2D DSP. Losing a bit off the image data is > > certainly undesirable and the alternative cosly or limits function if > > 18*18 multipliers have to be inferred as a kludge. > > One trick I've used is to convert the unsigned data to signed > at the filter input, then back to unsigned on the output. > Most of the video filters I built in the late 70s worked that way. > Once you've wrapped your brain round mid-grey being 0, it's > easy to deal with. Unfortunataly unsigned to signed requires zero padding, adding the extra bit inferres a 18*18 block rather than 9*9. In the case of 18 bit inputs the unsigned to signed requires one more bit than the block actually has. Going the other way does (Altera Cyclone 3 & Quartus) not make use of the dsp block IO registers but at least the multipliers are used. Example 1 : This ends as as 60 extra logic cells + a 9*9 multiplier, not pretty and certainly not desirous -- =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D-- -- COPYRIGHT (c) 2010 DAVID GREIG. This source file is the property of David Greig. This work must not be copied without permission from David Greig. -- -- Any copy or derivative of this source file must include this copyright statement. -- ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------- -- File : SyUS_Mult.vhd -- Author : David Greig (email : dgreig@ieee.org) -- Revision : -- Description : signed input data multiplier with clken output reg ---------------------------------------------------------------------------= --------------------------------------------- -- Notes : 2 clock cycle delay -- : arstn and clk2xen must meet required setup and hold requirements of the register -- =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D-- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D-- entity SyUS_Mult is generic( Gdwidth : natural; Gcoeff_width : natural; Gmult_pref : string ); port( arstn : in std_logic; clk2x : in std_logic; clk2xen : in std_logic; da_i : in std_logic_vector(Gdwidth - 1 downto 0); coeff_i : in std_logic_vector(Gcoeff_width - 1 downto 0); q_o : out std_logic_vector(Gdwidth + Gcoeff_width - 1 downto 0) ); end entity SyUS_Mult; -- =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D-- -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~-- architecture rtl of SyUS_Mult is -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~-- attribute multstyle : string; -- Implementation style, "logic" "dsp" --------------------------------------------------------------------------= ---------------------------------------------- signal da_r : unsigned(Gdwidth - 1 downto 0); signal coeff_r : unsigned(Gcoeff_width - 1 downto 0); signal product_s : signed(Gdwidth + Gcoeff_width - 1 downto 0); signal product_r : signed(Gdwidth + Gcoeff_width - 1 downto 0); attribute multstyle of product_r : signal is Gmult_pref; ---------------------------------------------------------------------------= --------------------------------------------- begin ---------------------------------------------------------------------------= --------------------------------------------- prcs_SyUS_Mult : process(arstn, clk2xen, clk2x) begin if (arstn =3D '0') then da_r <=3D (others =3D> '0'); coeff_r <=3D (others =3D> '0'); product_r <=3D (others =3D> '0'); elsif (clk2xen =3D '0') then null; elsif rising_edge(clk2x) then da_r <=3D unsigned(da_i); coeff_r <=3D unsigned(coeff_i); product_r <=3D product_s; end if; end process prcs_SyUS_Mult; ---------------------------------------- product_s <=3D -(signed(da_r*unsigned(abs(signed(coeff_r))))) when (coeff_r(coeff_r'high) =3D '1') else signed(da_r*unsigned(abs(signed(coeff_r)))); --------------------------------------------------------------------------= ---------------------------------------------- q_o <=3D std_logic_vector(product_r); -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~-- end architecture rtl; -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~-- Example 2 : This is not transportable, but does work for brand A. -- =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D-- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D-- entity SyUS_Mult is generic( Gdwidth : natural; Gcoeff_width : natural; Gmult_pref : string ); port( arstn : in std_logic; clk2x : in std_logic; clk2xen : in std_logic; da_i : in std_logic_vector(Gdwidth - 1 downto 0); coeff_i : in std_logic_vector(Gcoeff_width - 1 downto 0); q_o : out std_logic_vector(Gdwidth + Gcoeff_width - 1 downto 0) ); end entity SyUS_Mult; -- =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D-- -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~-- architecture rtl of SyUS_Mult is -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~-- attribute multstyle : string; -- Implementation style, "logic" "dsp" --------------------------------------------------------------------------= ---------------------------------------------- signal aclr_s : std_logic; component altmult_accum generic ( accum_direction : string; accum_sload_reg : string; addnsub_aclr : string; addnsub_pipeline_reg : string; addnsub_reg : string; dedicated_multiplier_circuitry : string; input_aclr_a : string; input_aclr_b : string; input_reg_a : string; input_reg_b : string; input_source_a : string; input_source_b : string; intended_device_family : string; lpm_type : string; multiplier_reg : string; output_aclr : string; output_reg : string; port_addnsub : string; port_signa : string; port_signb : string; representation_a : string; representation_b : string; sign_aclr_a : string; sign_aclr_b : string; sign_pipeline_reg_a : string; sign_pipeline_reg_b : string; sign_reg_a : string; sign_reg_b : string; width_a : natural; width_b : natural; width_result : natural ); port ( dataa : in std_logic_vector (width_a - 1 downto 0); datab : in std_logic_vector (width_b - 1 downto 0); accum_sload : in std_logic ; aclr0 : in std_logic ; clock0 : in std_logic ; ena0 : in std_logic ; result : out std_logic_vector (width_result - 1 downto 0) ); end component; ---------------------------------------------------------------------------= --------------------------------------------- begin ---------------------------------------------------------------------------= --------------------------------------------- aclr_s <=3D not(arstn); i_altmult_accum : altmult_accum generic map ( accum_direction =3D> "add", accum_sload_reg =3D> "unregistered", addnsub_aclr =3D> "aclr0", addnsub_pipeline_reg =3D> "unregistered", addnsub_reg =3D> "clock0", dedicated_multiplier_circuitry =3D> "AUTO", input_aclr_a =3D> "aclr0", input_aclr_b =3D> "aclr0", input_reg_a =3D> "clock0", input_reg_b =3D> "clock0", input_source_a =3D> "dataa", input_source_b =3D> "datab", intended_device_family =3D> "cyclone iii", lpm_type =3D> "altmult_accum", multiplier_reg =3D> "unregistered", output_aclr =3D> "aclr0", output_reg =3D> "clock0", port_addnsub =3D> "port_unused", port_signa =3D> "port_unused", port_signb =3D> "port_unused", representation_a =3D> "unsigned", representation_b =3D> "signed", sign_aclr_a =3D> "aclr0", sign_aclr_b =3D> "aclr0", sign_pipeline_reg_a =3D> "unregistered", sign_pipeline_reg_b =3D> "unregistered", sign_reg_a =3D> "clock0", sign_reg_b =3D> "clock0", width_a =3D> Gdwidth, width_b =3D> Gcoeff_width, width_result =3D> Gdwidth + Gcoeff_width ) port map ( dataa =3D> da_i, datab =3D> coeff_i, accum_sload =3D> '1', aclr0 =3D> aclr_s, clock0 =3D> clk2x, ena0 =3D> clk2xen, result =3D> q_o ); -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~-- end architecture rtl; -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~--Article: 147429
Martin Br=FCckner wrote: > void (*linux)(); > ... > (*linux)(); Wouldn't the last line have to be just this? linux();Article: 147430
"dgreig" <dgreig@ieee.org> wrote in message news:0ea2c276-604b-4619-baed-9c28551d93a1@r18g2000yqd.googlegroups.com... > Unfortunataly unsigned to signed requires zero padding, Perhaps for multiplier inference but, if you're building the hardware by hand you don't need the extra bit. You can just invert the msb, and consider the middle of your range to be "000000000". PeteArticle: 147431
On Apr 26, 6:52=A0pm, John_H <newsgr...@johnhandwork.com> wrote: <snip> > For M write ports, there are M write sets. =A0Each write set has the N > read memories for the N-port read and also has M-1 reads > from_the_other_write_addresses to complete the XORed data value to > store to those write sets. Ah. Of course! This way you don't have to wait for the read ports to be available to get the data you need to do the XORed write. Thank you! That's funny. I was pondering on the impact of the additional read cycle this solution implied, but if I understand this, just plain replication is the solution. :) You mentioned earlier that you had implemented this at some point in the past. Could you tell me more about where you heard about this (domain, application, etc...) or did you come up with it yourself? I'm just trying to suss out the common origin of the multiple XOR suggestions I've received.Article: 147432
Hi,
I am implementing BMD design as explained in xapp1052(v2.5). Have
implemented the design on AvnetV5LXT/SXT PCIe Development Board using
the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using ISE
10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am using
to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am using
only x1 lane of PCIe in my application. on both the machines i am
facing different problems.
Problem on S5000XVN
on this machine i have 2 x4 slots and 1 x16 slot. wen i
plug in a card on the one of the x4 slot my application runs perfectly
fine but when i plug it on the other x4 slot the data which i get is
not a valid data there is some garbage value shown in the data. What
could b the problem over here? Any idea ?
Problem on S3210SHLC
on this machine i am facing the problem that when i plug in
one of Avnet V5LXT/SXT PCIe Development Board the computer detects the
cards. but i put any other Avnet V5LXT/SXT PCIe Development Board the
system is unable to detect it. i don't understand this strange
behavior why is it showing such a behavior. dose anyone know the
solution to this problem
Article: 147433>Jeff Cunningham wrote: >> The free versions of Modelsim have been available for years (also >> through xilinx - look for "starter edition") but are really usable for >> small designs. Once your design goes over a certain number of statements >> (I think 500 or something like that) execution slows to a crawl. > >there are also free (as free beer or as a gnu) simulators for VHDL : >http://symphonyeda.com/ quite nice >http://ghdl.free.fr/ quite awesome in certain aspects > (yes i'm biased because I use it and it can do things others can't) > >> -Jeff >yg > >-- >http://ygdes.com / http://yasep.org > I have used icarus and GHDL and found them okay for small designs. I used it to model sparse memory (VPI for icarus verilog). The work was posted at: h---://bknpk.no-ip.biz/my_web/MiscellaneousHW//memory_hdl_models.html --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147434
>I'm trying to dump eight hex values per line >into a file, and can't work out how to do it. > > for index in 0 to 127 loop > for sample_sel in 0 to 7 loop > sample_val := integer(scale * sin(phase(sample_sel))); > write ( sample_line, sample_val, RIGHT, 10); > phase(sample_sel) := phase(sample_sel) + phase_inc(sample_sel); > end loop; > writeline ( ip_dat, sample_line ); > end loop; > >does what I want, but with decimal values. > >If I change to: >hwrite ( sample_line, sample_val, RIGHT, 10); >or: >write ( sample_line, to_hstring(sample_val), RIGHT, 10); >it doesn't compile. > >Any thoughts? > >Thanks > >Pete > > > > Here is an example of hex write: hwrite(my_line1, '0' & Ptr.Address); The entire code is posted at: http://bknpk.no-ip.biz/my_web/IP_STACK/sync_wr_vhdl_memory.html --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147435
John Adair wrote: > The early board range names are actually our local Malvern Hills - > Broaddown, Raggedstone, Hollybush. We did miss some of these as being > inappropriate, boring, or even indistinct, e.g. Hangmans Hill. The > later product familiy names are from the Galloway Hills in Scotland > where there are more names of distinction. The later names also have a > size link. It's not a totally accurate naming system but we give > brownie points to anyone can pronounce them properly. Maybe I will > keep score this week in San Jose and see what percentage get them > right or nearly so. OK it makes sense for me now :-) I have absolutely no Scotish culture, which explains why I missed all the references. Thanks everybody, > John Adair > Enterpoint Ltd. yg -- http://ygdes.com / http://yasep.orgArticle: 147436
Although based on an older version of ISE and MIG, you may find the MIG designs posted by Avnet to be helpful. www.em.avnet.com/spartan3a-dsp --> Support Files & Downloads. BryanArticle: 147437
>Hi folks, >I would like to ask you for recomandation of the ethernet development kit >with FPGA (much preferably Xilinx's one). Our requirements are the low >power, as big FPGA as possible and at least 3 ethernet ports at 1Gbps. > >I am not sure it there is currently such kit being distributed, because I >was not able to find it by google. > >Please, could you send information about kits, that could meet the >requirements? (or are close to them?) > >Thank you very much > >Jan > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147438
>Hi folks, >I would like to ask you for recomandation of the ethernet development kit >with FPGA (much preferably Xilinx's one). Our requirements are the low >power, as big FPGA as possible and at least 3 ethernet ports at 1Gbps. > >I am not sure it there is currently such kit being distributed, because I >was not able to find it by google. > >Please, could you send information about kits, that could meet the >requirements? (or are close to them?) > >Thank you very much > >Jan > This project might be interesting for you: "This project implements the lower layers of a standard TCP/IP stack based on a free code from University of Queensland:... Compilation and simulation scripts using GHDL... Synthesis of the VHDL IP stack, using xilinx XST free tool ... Verification using specman..." h---://bknpk.no-ip.biz/my_web/IP_STACK/start_1.html --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147439
Hey, I got it from the AVNET FAE. The link to find the schematics and gerber files is http://www.xilinx.com/products/boards/sp601/reference_designs.htm Hope this helps some other people. Regards, Aditi. On Apr 25, 3:46=A0pm, Aditi <aditi.gro...@gmail.com> wrote: > Hi, > > I am using SPARTAN 6 LX9 device in my new design and would like to get > decoupling capacitor placement diagram ASAP. I have looked at the User > guide for LX16 development board (from AVNET) to find one. It only has > the top view of the board. If some body could guide/help me in getting > the bottom view of the board, that would be really helpful. I have to > send my design to layout and it is kind of urgent. > > Thank you, > Regards, > Aditi.Article: 147440
On Apr 27, 1:03=A0pm, "Pete Fraser" <pfra...@covad.net> wrote: > "dgreig" <dgr...@ieee.org> wrote in message > > news:0ea2c276-604b-4619-baed-9c28551d93a1@r18g2000yqd.googlegroups.com... > > > Unfortunataly unsigned to signed requires zero padding, > > Perhaps for multiplier inference but, if you're building the > hardware by hand you don't need the extra bit. > You can just invert the msb, and consider the middle of > your range to be "000000000". > > Pete Pete Now I follow what you mean - offset binary. Could be done, but would make verification very painful. With numeric_std the number system is two's complement rather than one's complement so inverting the MSB will not work. I am doing a lot of differing large matrix operations (a 21*21 matrix multiplier as one of the datapath operators) and detecting features as sets of multiple peaks alomg rows and colums. Coefficients are calculated adaptively in both the FPGA and a DSP so I have a distinct preference to stay with two's. In total about 80Gmults/sec and about the number of additions/subtractions, all on a Cyclone 3! Asymetric 2D wavelet image processing for feature detection and measurement.Article: 147441
>Hi all, > >as the title says I have to read some information stored in UDP packet >with an FPGA. Now I'm evaluating 3 options: > >1) Use an external processor and send data to FPGA through dedicated >lines >2) Use a microcontroller embedded into the FPGA (i.e. microblaze, >since I'm working on a Xilinx) >3) Write an hardware implementation of the IP stack, or at least of he >part of the stack I need to read those packets > >What are the pros and cons of each solution? Can you suggest me others >way to do that? > >Thanks all > >Dek > might be worth looking at: "This project implements the lower layers of a standard TCP/IP stack based on a free code from University of Queensland...." http://bknpk.no-ip.biz/my_web/IP_STACK/start_1.html --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147442
I have built a design with PR flow 9.2 using bus macros. The dynamic reconfiguration works using Impact and downloading the partial bistreams. I have connected the Virtex 4 ICAP port to the LEON3 processor through the AMBA APB bus. I would like to perform partial reconfiguration through ICAP. I have a C software running on LEON 3 wich writes the partial bistream onto ICAP. The partial bitstream file has been trimmed in order to start with the FFFFFFFF dword (the header has been cut off) and included in the executable as a integer array. The software write all the dwords of the bitstream on the ICAP, but the virtex 4 seems to be not reconfigured as it happens with Impact. I also download 4 NOP packets after the bitstream but it doesn't change anything. Any suggestion?Article: 147443
"dgreig" <dgreig@ieee.org> wrote in message news:07426f9a-724b-42df-b940-1feaa545bff0@j21g2000yqh.googlegroups.com... On Apr 27, 1:03 pm, "Pete Fraser" <pfra...@covad.net> wrote: >> You can just invert the msb, and consider the middle of >> your range to be "000000000". > Now I follow what you mean - offset binary. Could be done, but would > make verification very painful. Perhaps, but not as painful as you think. > With numeric_std the number system is two's complement rather than > one's complement so inverting the MSB will not work. You invert the msb, and regard it as a 2s complement number (-2^(n-1) -> 2^(n-1) -1; ony one zero) This has the advantage of allowing you symmetrical overload in your ladder, for essentially unipolar signals. I used to build large, time variant 1-D and 2-D filters for processing RGB and Y. This was back when the MPY8HJ first came out (1978?). PeteArticle: 147444
"whygee" <yg@yg.yg> wrote in message news:hr6u4o$t96$1@speranza.aioe.org... > I have absolutely no Scotish culture, > which explains why I missed all the references. Don't feel too bad about it. I spent the first 22 years of my life in Scotland, and had always assumed these names were Welsh.Article: 147445
On Mon, 26 Apr 2010 22:50:19 +0200, Martin Brückner wrote:
> Hello,
>
> I'm writing a boot loader to start Linux on the PowerPC440 (Virtex5FXT).
> At first the program copies the kernel into the RAM at address
> 0x00400000 and afterwards it boots Linux with the following lines:
>
> #define LINUX_START_ADDRESS 0x004002b4
>
> int main()
> {
> void (*linux)();
> linux = (void*) LINUX_START_ADDRESS;
>
> ... // here is the code which copies the kernel into ram
>
> (*linux)();
> }
>
Did you setup the stack pointer? The above is going to try and push
the return address on the stack. Compile with -S and look at the
resulting asm output.
[snip]
> Best Regards
> Martin Brückner
--
Joe Chisolm
Marble Falls, Tx.
Article: 147446Joe Chisolm <jchisolm6@earthlink.net> wrote: > On Mon, 26 Apr 2010 22:50:19 +0200, Martin Br?ckner wrote: >> I'm writing a boot loader to start Linux on the PowerPC440 (Virtex5FXT). >> At first the program copies the kernel into the RAM at address >> 0x00400000 and afterwards it boots Linux with the following lines: >> #define LINUX_START_ADDRESS 0x004002b4 (snip) >> (*linux)(); > Did you setup the stack pointer? The above is going to try and push > the return address on the stack. Compile with -S and look at the > resulting asm output. Not knowing at all about the linux boot process, I would have assumed that one of the first thing that the booting kernel does would be to set up its own stack. It might, though, depend on a previous level of boot program to have set up a stack for it. I wouldn't expect the boot ROM to have done it, but often there are multiple levels of boot programs. -- glenArticle: 147447
Hello, I am a beginner interested to learn what PCB design software is suitable for designs using FPGA chips? I also wonder whether free software packages (such as FreePCB, ExpressPCB) are good enough for PCB designs using FPGA chips? Thank you. P.S. As I use Spartan3E 1600E Microblaze Development Board with XC3S1600E chip (FGG320 package) then I am particularly interested how to accomodate this chip on PCB.Article: 147448
On Apr 26, 4:33=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Wastrel <stephensdigi...@gmail.com> wrote: > > (snip) > > > Well Altium support got back to me and said basically the same thing > > you guys are: "It works OK for me" > > They told me to verify that the system environment variable > > "QUARTUS_ROOTDIR" pointed to the right folder - it did. I upgraded the > > OS to Windows 7 Professional from "Home Premium" still no joy. When I > > run Windows' compatibility troubleshooter it comes back with > > "Incompatible Application" so there's something funky going on. I'm > > wasting way to much time on this stupid problem, but it's not so easy > > finding an XP box anymore so I'm not just sure what my next move is. > > As I understand it, starting with Vista Windows won't run 16 bit > code anymore. =A0It seems that a surprising amount of such code > still exists and causes problems, though I am a little surprised > it would happen in this case. > > -- glen First of all, thanks to everyone for all the on point suggestions - much appreciated! Altium support got back to me last night with the following: "Check the 'Ignore version of vendor tools' in DXP---Preferences--- FPGA---Devices View. It is common that FPGA Vendor releases leapfrog the Altium Designer releases. So this setting will enable you to run with the Altera Quartus release that did not exist when Summer09 was released. " This did the trick, much to my relief. As grateful as I am to be back up and running, I think this key information should have been included in a help file, quick start guide or otherwise made available to the hapless newbie...Article: 147449
On Apr 27, 2:26=A0pm, Alex <vict...@gmail.com> wrote: > Hello, > > I am a beginner interested to learn what PCB design software is > suitable for designs using FPGA chips? > > I also wonder whether free software packages (such as FreePCB, > ExpressPCB) are good enough for PCB designs using FPGA chips? > > Thank you. > > P.S. > As I use Spartan3E 1600E Microblaze Development Board with XC3S1600E > chip (FGG320 package) then I am particularly interested how to > accomodate this chip on PCB. I think as soon as you start using high-density packages like BGA's with 0.8mm ball spacing, you're treading on thin ice if you think free tools and your limited experience will result in a usable board design. Check the packages for maximum layer count and whether they have the ability to create copper pours, whether they already have a symbol for your BGA package or have a tool to help generate one, etc. I've generally had a design service do this sort of design for me. I only use the "Express" stuff for little two- or four-layer designs. HTH, Gabor
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