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John - I was actually looking at the Drigmorn4 module and it looks pretty good. If there were more I/O pins added, this would probably be a very viable method for us. Could I have you please send me a private e-mail message so we could discuss some details? Thanks. Dave starfire151@cableone.net On Dec 19, 6:25=A0am, John Adair <g...@enterpoint.co.uk> wrote: > Dave > > If you see anything from our range that catches your eye it is always > worth asking us for the price of semi custom variant of that product. > Unlike many of our compeditors we do offer semi and full custom boards > and it usually works well typically for customer volumes 10 boards+. > > If it is a one off project can also off modules for adaption and tha > typically is a lower cost. Just depends what is needed. > > I will also mention that our popular Drigmorn4 designhttp://www.enterpoin= t.co.uk/drigmorn/drigmorn4.htmlis getting an > upgrade of features the main one being 38 extra pairs of I/O on 2 new > connectors on the rear of the board. These can be used as LVDS or > single ended 3.3V I/O. The full compliment of this new I/O will be > available on LX150 versions but less on other variants of the board. > We will be bringing a wide range of support modules for this new > header including touchscreen, battery packs, wide range input power, > FMC interface and relay modules to name a few. It will also suit a lot > of customers like you that need I/O in a compact form. The size of the > original board is unchanged with this upgrade and it remains > compatible with Drigmorn3 and Drigmorn2 mountings. > > John Adair > Enterpoint Ltd. >Article: 150151
Dave Email the main sales email - boardsales AT companyname .co.uk initially and that will get passed to me. John Adair Enterpoint Ltd. On Dec 20, 8:33=A0pm, Dave <starfire...@cableone.net> wrote: > John - > > I was actually looking at the Drigmorn4 module and it looks pretty > good. =A0If there were more I/O pins added, this would probably be a > very viable method for us. > > Could I have you please send me a private e-mail message so we could > discuss some details? > > Thanks. > > Dave > starfire...@cableone.net > > On Dec 19, 6:25=A0am, John Adair <g...@enterpoint.co.uk> wrote: > > > > > Dave > > > If you see anything from our range that catches your eye it is always > > worth asking us for the price of semi custom variant of that product. > > Unlike many of our compeditors we do offer semi and full custom boards > > and it usually works well typically for customer volumes 10 boards+. > > > If it is a one off project can also off modules for adaption and tha > > typically is a lower cost. Just depends what is needed. > > > I will also mention that our popular Drigmorn4 designhttp://www.enterpo= int.co.uk/drigmorn/drigmorn4.htmlisgetting an > > upgrade of features the main one being 38 extra pairs of I/O on 2 new > > connectors on the rear of the board. These can be used as LVDS or > > single ended 3.3V I/O. The full compliment of this new I/O will be > > available on LX150 versions but less on other variants of the board. > > We will be bringing a wide range of support modules for this new > > header including touchscreen, battery packs, wide range input power, > > FMC interface and relay modules to name a few. It will also suit a lot > > of customers like you that need I/O in a compact form. The size of the > > original board is unchanged with this upgrade and it remains > > compatible with Drigmorn3 and Drigmorn2 mountings. > > > John Adair > > Enterpoint Ltd.- Hide quoted text - > > - Show quoted text -Article: 150152
I have successfully used the SPI peripheral with a SPI Flash. The
only difference that I can see is a call to disable the interrupts
since I use the peripheral in polled mode:
XSpi_mIntrGlobalDisable(&mySpi);
Here's my instantiation from my MHS. I turned on the FIFOs and have
an SCK Ratio of 16 (this is from EDK 10):
BEGIN xps_spi
PARAMETER INSTANCE =3D SPI_FLASH
PARAMETER C_FIFO_EXIST =3D 1
PARAMETER C_SCK_RATIO =3D 16
PARAMETER HW_VER =3D 2.01.b
PARAMETER C_BASEADDR =3D 0x83400000
PARAMETER C_HIGHADDR =3D 0x8340ffff
BUS_INTERFACE SPLB =3D mb_plb
PORT SPISEL =3D net_vcc
PORT SCK =3D fpga_0_SPI_FLASH_SCK_pin
PORT MISO =3D fpga_0_SPI_FLASH_MISO_pin
PORT MOSI =3D fpga_0_SPI_FLASH_MOSI_pin
PORT SS =3D fpga_0_SPI_FLASH_SS_pin
END
Here's the complete example if you are interested:
www.em.avnet.com/spartan3a-evl --> > MicroBlaze Serial Flash Test
Bryan
On Dec 15, 10:05=A0am, Tobias Baumann <ttob...@hotmail.com> wrote:
> Hello
>
> I'm using Xilinx EDK 11.5 with xps_spi core version 2.01b. Core is
> correctly integrated in my SDK, I can see the signals on my DSO.
> Everything seems to be allright. But I've got a little software problem.
>
> In SDK I transfer my data with the function "XSpi_Transfer(&mySPI,
> outBuffer, inBuffer, 2)" (see above). It works exactly one time and I
> get XST_SCCUSS back. But if I call XSpi_Transfer again, I get
> XST_DEVICE_BUSY back.
>
> My program do the following steps:
>
> 1.) initalize SPI (function "XSpi_Initialize")
> 2.) set options (function "XSpi_SetOptions")
> 3.) select slave (function "XSpi_SetSlaveSelect")
> 4.) start SPI (function "XSpi_Start")
> 5.) transfer data (function "XSpi_Transfer")
>
> Every function return XST_SUCCESS, but not Xspi_transfer when I call it
> the second time.
>
> So my question? Is there any bug in the core or have I forgot something?
> I hope someone can help me. I tried to google, found a similar problem,
> but no solution.
>
> Thanks a lot,
>
> Tobias
>
> C-Code:
>
> #include <stdio.h>
> #include "platform.h"
> #include "xbasic_types.h"
> #include "xstatus.h"
> #include "xparameters.h"
> #include "xspi.h"
>
> void SPIini(void);
> void pause(void);
>
> XSpi mySPI;
>
> int main()
> {
> =A0 =A0 =A0init_platform();
>
> =A0 =A0 =A0 =A0 print("SPI Test\n\r");
> =A0 =A0 =A0 =A0 pause();
>
> =A0 =A0 =A0 =A0 Xuint8 inBuffer[4] =3D {0x00, 0x00, 0x00, 0x00};
> =A0 =A0 =A0 =A0 Xuint8 outBuffer[4] =3D {0x00, 0xAA, 0xFF, 0xAA};
>
> =A0 =A0 =A0 =A0 XStatus status =3D XST_SUCCESS;
>
> =A0 =A0 =A0 =A0 SPIini();
>
> =A0 =A0 =A0 =A0 for(Xuint8 i=3D0; i<100; i++) {
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* initialization */
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 status =3D XSpi_Transfer(&mySPI, outBuffe=
r, inBuffer, 2);
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 switch(status)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case XST_SUCCESS: print("=
Status: Erfolgreich gesendet."); break;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case XST_DEVICE_IS_STOPPE=
D: print("Status: Device stopped\n\r"); break;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case XST_DEVICE_BUSY: pri=
nt("Status: Device busy\n\r"); break;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case XST_SPI_NO_SLAVE: pr=
int("Status: Device no slave\n\r"); break;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 pause();
> =A0 =A0 =A0 =A0 }
>
> =A0 =A0 =A0cleanup_platform();
>
> =A0 =A0 =A0return 0;
>
> }
>
> void SPIini(void)
> {
> =A0 =A0 =A0 =A0 XStatus status =3D XST_SUCCESS;
>
> =A0 =A0 =A0 =A0 status =3D XSpi_Initialize(&mySPI, XPAR_TEST_SPI_DEVICE_I=
D);
>
> =A0 =A0 =A0 =A0 switch(status)
> =A0 =A0 =A0 =A0 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case XST_SUCCESS: print("Status: Erfolgre=
ich initialisiert\n\r"); break;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case XST_DEVICE_IS_STARTED: print("Status=
: Device is started\n\r"); break;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case XST_DEVICE_NOT_FOUND: print("Status:=
Device not found\n\r"); break;
> =A0 =A0 =A0 =A0 }
>
> =A0 =A0 =A0 =A0 Xuint32 options =3D XSP_MASTER_OPTION;
> =A0 =A0 =A0 =A0 status =3D XSpi_SetOptions(&mySPI, options);
>
> =A0 =A0 =A0 =A0 switch(status)
> =A0 =A0 =A0 =A0 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case XST_SUCCESS: print("Status: Erfolgre=
ich option gesetzt\n\r"); break;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case XST_DEVICE_BUSY: print("Status: Devi=
ce busy\n\r"); break;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case XST_SPI_SLAVE_ONLY: print("Status: S=
lave only\n\r"); break;
> =A0 =A0 =A0 =A0 }
>
> =A0 =A0 =A0 =A0 XSpi_SetSlaveSelect(&mySPI, 1);
> =A0 =A0 =A0 =A0 XSpi_Start(&mySPI);
>
> }
>
> void pause(void)
> {
> =A0 =A0 =A0 =A0 for(int i=3D0; i<CPU_FREQ; i++);
>
> }
Article: 150153People deserve very good life time and <a href="http://bestfinance-blog.com/topics/personal-loans">personal loans</a> or collateral loan would make it much better. Because freedom is grounded on money state.Article: 150154
Hi, I want to calculate the square Root of a number, so I used the CORDIC of core generator of xilinx but my problem now that I can find a way to connect this CORDIC to the MB on an EDK project! please if any body can help me or has some useful idea please tell me!! thanks in advance INES --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150155
Hi Martin and Bryan You both were right. I had to disable the interrupts with Xspi_mIntrGlobalDisable(&mySpi) and now it works fine. Thanks a lot to you! But unfortunately I have a new problem. I want to stream data to a W-LAN module, so I need a high throughput to max out my performance. The SPI core is very slow, so I can't use the high performance of my W-LAN module. (I get a throughput of 30kB/s, this is much to slow). Has someone an idea how to increase the throughput of my system? A fine solution would be, sending data directly from rams and/or registers via SPI to my module. Maybe DMA is the right keyword, but I'm not sure, because I'm a total beginner of programming microblaze and IP cores. Maybe someone has a hint in which direction I have to search, for finding a solution. Thanks a lot! TobiasArticle: 150156
>Hi, >I want to calculate the square Root of a number, so I used the CORDIC of >core generator of xilinx but my problem now that I can find a way to >connect this CORDIC to the MB on an EDK project! >please if any body can help me or has some useful idea please tell me!! > >thanks in advance >INES > How often do you need the square-root function? If not often, it would be simpler to use the software library 'sqrt' function. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150157
On Dec 21, 4:41=A0am, "ines_fr" <benhlima_ines@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.fr> wrote: > Hi, > I want to calculate the square Root of a number, so I used the CORDIC of > core generator of xilinx but my problem now that I can find a way to > connect this CORDIC to the MB on an EDK project! > please if any body can help me or has some useful idea please tell me!! > > thanks in advance > INES =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com If you do a Google search, your question comes up as the 1st link, and the answer to your question is in links 2 and 3. Google is your friend. You're welcome, RKArticle: 150158
Does anyone have a simple example of how to build a Microblaze application starting with the ISE that includes a GPIO port connected to custom logic? What I'm looking for is something like maybe an 8-bit GPIO input port with an interrupt connected to a custom decoder internal to the FPGA. In addition, maybe an 8-bit GPIO output port connected to custom logic. So it would be something like this: outside world --> FPGA pins --> custom decoder --> GPIO port --> OPB -- > Microblaze |--> GPIO port --> interrupt controller --> Microblaze and outside world <-- FPGA pin <-- custom logic <-- GPIO port <-- OPB <-- Microblaze ThanksArticle: 150159
>Does anyone have a simple example of how to build a Microblaze >application starting with the ISE that includes a GPIO port connected >to custom logic? > >What I'm looking for is something like maybe an 8-bit GPIO input port >with an interrupt connected to a custom decoder internal to the FPGA. >In addition, maybe an 8-bit GPIO output port connected to custom >logic. So it would be something like this: > >outside world --> FPGA pins --> custom decoder --> GPIO port --> OPB -- >> Microblaze > >|--> GPIO port --> interrupt controller --> Microblaze > >and > >outside world <-- FPGA pin <-- custom logic <-- GPIO port <-- OPB <-- >Microblaze > >Thanks > Have you tried the EDK tutorial? You should be able to figure it out after doing that. Also you shouldnt really be using the OPB bus if its a new design. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150160
On Dec 21, 12:34=A0pm, Dave <starfire...@cableone.net> wrote: > Does anyone have a simple example of how to build a Microblaze > application starting with the ISE that includes a GPIO port connected > to custom logic? > > What I'm looking for is something like maybe an 8-bit GPIO input port > with an interrupt connected to a custom decoder internal to the FPGA. > In addition, maybe an 8-bit GPIO output port connected to custom > logic. =A0So it would be something like this: > > outside world --> FPGA pins --> custom decoder --> GPIO port --> OPB -- > > > Microblaze > > |--> GPIO port --> interrupt controller --> Microblaze > > and > > outside world <-- FPGA pin <-- custom logic <-- GPIO port <-- OPB <-- > Microblaze > > Thanks There is something called a "Simple Microblaze" (XAPP1141) that is supposed to be easy to use like a big PicoBlaze. If you're more comfortable using ISE and HDL design than messing around with EDK it might be what you want. You'd need to make your own GPIO, but the bus connections are simpler. You also don't necessarily need the full-blown XPS development environment to use it, just ISE and the SDK (not EDK). http://www.xilinx.com/support/documentation/application_notes/xapp1141.pdf -- GaborArticle: 150161
On Dec 21, 3:00=A0pm, Gabor <ga...@alacron.com> wrote: > > There is something called a "Simple Microblaze" (XAPP1141) that is > supposed to be > easy to use like a big PicoBlaze. =A0If you're more comfortable using > ISE and HDL > design than messing around with EDK it might be what you want. =A0You'd > need > to make your own GPIO, but the bus connections are simpler. =A0You also > don't > necessarily need the full-blown XPS development environment to use it, > just > ISE and the SDK (not EDK). > > http://www.xilinx.com/support/documentation/application_notes/xapp114... > > -- Gabor- Thanks, Gabor.Article: 150162
Some improvement can be made by decreasing the SCK Ratio, but you're still dealing with the PLB. If this is Spartan-6 or Virtex-6, you could look at switching to AXI. You could also look at a designing your own simple SPI peripheral and connect to MicroBlaze via FSL. Bryan On Dec 21, 10:02=A0am, Tobias Baumann <ttob...@hotmail.com> wrote: > Hi Martin and Bryan > > You both were right. I had to disable the interrupts with > Xspi_mIntrGlobalDisable(&mySpi) and now it works fine. Thanks a lot to yo= u! > > But unfortunately I have a new problem. I want to stream data to a W-LAN > module, so I need a high throughput to max out my performance. The SPI > core is very slow, so I can't use the high performance of my W-LAN > module. (I get a throughput of 30kB/s, this is much to slow). > > Has someone an idea how to increase the throughput of my system? A fine > solution would be, sending data directly from rams and/or registers via > SPI to my module. Maybe DMA is the right keyword, but I'm not sure, > because I'm a total beginner of programming microblaze and IP cores. > > Maybe someone has a hint in which direction I have to search, for > finding a solution. > > Thanks a lot! > > TobiasArticle: 150163
You might want trying to run multiple strategies using either PlanAhead and/or SmartXplorer. I've been playing with these tools recently and found them to be quite useful. The way I used them was to first find the best working implementation strategy with PlanAhead (and some strategies would fail completely) and then cycle that particular strategy through SmartXplorer while changing just the seed. Again, I found that some seeds would make the MAP fail completely, while others would produce an order of magnitude different timing scores. /Mikhail "ghelbig" <ghelbig@lycos.com> wrote in message news:f56c2c16-a18b-4c18-a09f-2b0f1620b94f@a28g2000prb.googlegroups.com... > Sorry, but I need to vent. > > I have a design that works just fine with ISE-11.5, and fails 'PAR' > with ISE-12.3 > > I opened a web case about my design failing PAR. The archive of the > project created with ISE was incomplete, so it has taken a while (six > weeks) to get all of the files transferred. > > I just got an email from Xilinx Tech Support: "Your design fails PAR > with ISE-12, can you help ..." > > Sigh. Heavy sigh. > > Thanks for listening, > G.Article: 150164
Thanks for the tip, Gabor. I've hunted around and can't seem to find the SMM distribution on Xilinx's site or in the ISE Webpack 12.2/EDK (trial version) directories, at least on 12.2. Does anyone know where this is available from? JoelArticle: 150165
On Dec 22, 4:45=A0pm, Joel <whydontyoublogabou...@gmail.com> wrote: > Thanks for the tip, Gabor. I've hunted around and can't seem to find > the SMM distribution on Xilinx's site or in the ISE Webpack 12.2/EDK > (trial version) directories, at least on 12.2. Does anyone know where > this is available from? I don't think they have anything specific for 12.2, but the app note and design files are available at: http://www.xilinx.com/support/documentation/anembedprocess.htmArticle: 150166
> I don't think they have anything specific for 12.2, but the app note > and design files are available at:http://www.xilinx.com/support/documentation/anembedprocess.htm Perfect! Thanks very much. JoelArticle: 150167
Am 22.12.2010 17:34, schrieb Bryan: > Some improvement can be made by decreasing the SCK Ratio, but you're > still dealing with the PLB. If this is Spartan-6 or Virtex-6, you > could look at switching to AXI. You could also look at a designing > your own simple SPI peripheral and connect to MicroBlaze via FSL. > I'm working with a Spartan 3A-DSP. After optimizing the settings of the SPI-Core I get a much higher throughput (maybe 500kB/s to 1MB/s, I still have to measure it). I thought that I have to make my own SPI peripheral to optimize my problem, but I hoped that there is a finshed solution. Thanks a lot. TobiasArticle: 150168
>Sorry, but I need to vent. > >I have a design that works just fine with ISE-11.5, and fails 'PAR' >with ISE-12.3 > >I opened a web case about my design failing PAR. The archive of the >project created with ISE was incomplete, so it has taken a while (six >weeks) to get all of the files transferred. > >I just got an email from Xilinx Tech Support: "Your design fails PAR >with ISE-12, can you help ..." > >Sigh. Heavy sigh. > >Thanks for listening, >G. > Are you paying for support? If you don't like Xilinx support then you can switch to Altera's. One of the big complaints about Open Source Software is that there is no sure path to finding a solution to your problems. In the EDA world closed source software is not much better. You have to think of fpgas like you are writing software that must fit into a fixed size rom chip. If your code is one byte over then the tool will fail. You need to understand how your code maps into fpga logic and where the critical timing paths occur. It looks like you design was on the brink and any slight algorithm change could push it over. Try compiling for a larger part or a slower speed. Look for long chains of combinational logic and try to pipeline them John Eaton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150169
I'm happy to announce MyHDL 0.7.
MyHDL is Python used as a Hardware Description Language.
Overview:
http://www.myhdl.org/doku.php/overview
What's new in this release:
http://www.myhdl.org/doc/0.7/whatsnew/0.7.html
Download:
http://sourceforge.net/project/showfiles.php?group_id=91207
Best regards,
Jan Decaluwe
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com
Article: 150170Alessandro Basili <alessandro.basili@CERN.CH> sent on December 13th, 2010: |-------------------------------------------------------------------------------| |"On 12/10/2010 3:57 PM, Thomas Stanka wrote: | |[snip] | |> Open cores tend to have a lack in documentation and verification, | |> which is a no-go for developing space electronics. | | | |[..]" | |-------------------------------------------------------------------------------| Verification is not always tried, though it has been dishonestly claimed to have been achieved in publications such as Sergio Saponara; Francesco Vitullo; Esa Petri; and Luca Fanucci, "A Reusable Pseudo-Random Verification Environment for Complex Digital Designs: the SpaceWire Interface Case Study", IEEE International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications 21-23 September 2009, Rende (Cosenza), Italy. Testing some examples instead of proving is not verification. |--------------------------------------------------------------------------------| |"I just want to mention that on an FPGA based application the choice of the FPGA| |may guarantee certain level of radiation hardness," | |--------------------------------------------------------------------------------| Choose Aeroflex: WWW.Aeroflex.com/ams/pagesproduct/prods-hirel-fpga.cfm |-------------------------------------------------------------------------------| |" while specific design | |techniques may improve the level of hardness even further (TMR, [..]" | |-------------------------------------------------------------------------------| TMR could actually be harmful when using technologies with small feature sizes, if sufficient care is not taken: Blum and Delgado-Frias, "Schemes for Eliminating Transient-Width Clock Overhead From SET-Tolerant Memory-Based Systems", "I.E.E.E. Transactions on Nuclear Science", June 2006. |-------------------------------------------------------------------------------| |"[..] | | | |Even though I believe that Space Agencies around the world are politically and | |technically bond to follow standardization processes based mostly on lessons | |learned, [..] | |[..] | | | |[..]" | |-------------------------------------------------------------------------------| The European Space Agency does not adhere to its own standards. Yours sincerely, Paul Colin GlosterArticle: 150171
Hi, i am using spartan3 with xcf16p eeprom in my design. I have a question, JTAG's TMS is pulled upto 2.5v by FPGA but after sometime, the pin is pulled upto 3.3v automatically. i dont know why is this happening. Can anyone tell me the reason ? regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150172
Hello everybody. I want to implement a security precaution against overbuilding and clonning. However I have some questions. If I am implementing the design in a Spartan 3A Device, I have Device DNA feature but I dont have any on-board cryptographic feature. In the documents from Xilinx it is written that, 1) Read Device DNA Value 2) Generate your active code 3) Compare the active code and previously generated code 4) If they are equal, just enable the real part of your design. Here I wonder that, is that possible a hacker or theft just copies my .bit file while downloading from PROM to FPGA and he makes some modifications in my netlist. This modification can be just to tie the enable bit(s) to Vcc. Then, my security precaution will be bypassed and the real part of my design will work always because of enable bit(s) that tied up to Vcc by hacker. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150173
On Fri, 24 Dec 2010 13:02:23 -0600 "suzero" <orhunsuzer@n_o_s_p_a_m.gmail.com> wrote: > Hello everybody. > I want to implement a security precaution against overbuilding and > clonning. However I have some questions. If I am implementing the > design in a Spartan 3A Device, I have Device DNA feature but I dont > have any on-board cryptographic feature. In the documents from Xilinx > it is written that, > > 1) Read Device DNA Value > 2) Generate your active code > 3) Compare the active code and previously generated code > 4) If they are equal, just enable the real part of your design. > > Here I wonder that, is that possible a hacker or theft just copies > my .bit file while downloading from PROM to FPGA and he makes some > modifications in my netlist. This modification can be just to tie the > enable bit(s) to Vcc. Then, my security precaution will be bypassed > and the real part of my design will work always because of enable > bit(s) that tied up to Vcc by hacker. The Spartan 3 series Device DNA mechanism relies on the netlist modifications you mention being impossible (i.e. it relies on the fact that the "nobody" knows the bitstream format well enough to modify it). The configuration user guide (UG332) states in the introduction section to chapter 15, "The Xilinx bitstream format is both proprietary and confidential.". Is this good enough to actually protect a design? Honestly, I have no idea, though it doesn't seem like a very strong protection to me. But I come from the software world, where reverse engineering is done on a daily basis... ChrisArticle: 150174
On Monday, December 20, 2010 5:28:12 PM UTC+1, al wrote: > can you propose any valid alternative to opencores? You can simply use Github. It's not specific to logic design, but it is superior to many other project hosting websites in many ways. Since I switched to it (and to Git), I wonder how I have lived so long with Subversion and Trac... S.
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