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onsdag den 30. maj 2018 kl. 11.54.51 UTC+2 skrev thing241: > > Maybe you are talking about something like A | B | C where A and B tran= sition while C is always a 1? I am pretty sure in this case there would be= no glitch since there are no intermediate states that will output a 0.=20 > >=20 > Exactly. LUTs don't glitch "where logic wouldn't" (as rickman said). > In a recent exchange with a Xilinx engineer on one of their forums I prop= osed that if a LUT were implementing an AND gate, and one of the inputs was= low, the other inputs could not glitch the output regardless of how they s= witched (collectively). He would not agree, again quoting the Xilinx mantr= a that only "single" inputs are guaranteed not to cause a glitch. looks like the late Peter Alfke agreed https://www.fpgarelated.com/showthread/comp.arch.fpga/32950-1.phpArticle: 160626
On Wednesday, May 30, 2018 at 3:42:41 PM UTC-4, lasselangwad...@gmail.com wrote: > > looks like the late Peter Alfke agreed > > https://www.fpgarelated.com/showthread/comp.arch.fpga/32950-1.php Thanks for the link. I have never seen that claim made by a Xilinx rep before.Article: 160627
I was talking with former employees of NSC, which worked with the CLAy architecture. None of them has the datasheets XD. My other doubts (not related with CLAy) are still there XD. Any help will be apreciated. ThanksArticle: 160628
architecture structural of prince_core is
type round_constants is array(0 to 11) of std_logic_vector(63 downto 0);
type intermediate_signals is array(0 to 11) of std_logic_vector(63 downto 0);
-- Round constants for each round
constant rcs: round_constants := (x"0000000000000000",
x"13198A2E03707344",
x"A4093822299F31D0",
x"082EFA98EC4E6C89",
x"452821E638D01377",
x"BE5466CF34E90C6C",
x"7EF84F78FD955CB1",
x"85840851F1AC43AA",
x"C882D32F25323C54",
x"64A51195E0E3610D",
x"D3B5A399CA0C2399",
x"C0AC29B7C97C50DD");
-- Signals for transporting the data between rounds
signal ims: intermediate_signals;
signal middle1, middle2: std_logic_vector(63 downto 0);
Article: 160629On Wednesday, May 30, 2018 at 8:49:18 PM UTC-4, Rodrigo Melo wrote: > I was talking with former employees of NSC, which worked with the CLAy architecture. None of them has the datasheets XD. > > My other doubts (not related with CLAy) are still there XD. > > Any help will be apreciated. Thanks No small part of the problem is that this was the early days of the Internet and PDF files. I don't recall how quickly PDF was adopted by everyone. Some products that only lasted a few years may have not made it onto PDF files. Rick C.Article: 160630
Yep. Since 1996 there are not many problems, but previous data is difficult to obtain. It depends on somebody which digitalize the doc.Article: 160631
In article <48c017ed-9e97-4ff3-94eb-2fd4e39f5524@googlegroups.com>,
Haimanot Tizazu <htizazu@gmail.com> wrote:
>
>
>architecture structural of prince_core is
> type round_constants is array(0 to 11) of std_logic_vector(63 downto 0);
> type intermediate_signals is array(0 to 11) of std_logic_vector(63 downto 0);
>
> -- Round constants for each round
> constant rcs: round_constants := (x"0000000000000000",
> x"13198A2E03707344",
> x"A4093822299F31D0",
> x"082EFA98EC4E6C89",
> x"452821E638D01377",
> x"BE5466CF34E90C6C",
> x"7EF84F78FD955CB1",
> x"85840851F1AC43AA",
> x"C882D32F25323C54",
> x"64A51195E0E3610D",
> x"D3B5A399CA0C2399",
> x"C0AC29B7C97C50DD");
>
> -- Signals for transporting the data between rounds
> signal ims: intermediate_signals;
> signal middle1, middle2: std_logic_vector(63 downto 0);
How's this for a start?
typedef bit [ 0 : 11 ] [ 63 : 0 ] round_constants;
typedef bit [ 0 : 11 ] [ 63 : 0 ] intermediate_signals;
round_constants rcs = {
'h0,
'h13198A2E03707344,
...
};
// Verilog has a "const" tag too, however, I never use it - can't
// see the point of using it.
intermediate_signals ims;
bit [ 63 : 0 ] middle1. middle2;
Regards,
Mark
Article: 160632Hi, I just started working with IBERT ip from xilinx. Can anyone suggest some references to look into to analyse the ip results and how to adjust the proper 2d eye scan? Thank-You in advance.Article: 160633
Hello all, I used Hamsterwork's http://hamsterworks.co.nz/mediawiki/index.php/Stepper stepper motor controller , there position out for leds etc. How i can make give position back.. I.E. I want to give position to stepper motor controller not push a button.. could some one help me with code ?Article: 160634
The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM blocks in widths of multiples of 9 bits. Some other devices only have RAM widths of multiples of 8 bits or less. Does this make much of a difference to you? Do you use the 9 bit widths in your designs? Rick C.Article: 160635
Am 29.06.2018 um 22:22 schrieb gnuarm.deletethisbit@gmail.com: > > Does this make much of a difference to you? Do you use the 9 bit widths in your designs? > Yes, 9 bit width RAM is very interesting in video processing. When you have RGB data with 12 bit each, then you can use 4x9 bit RAM for storing the 36 bit video data exactly, without wasting any ressources. Sometimes the additional bit is very helpful when dealing with "traditional" 8 bit data and needed an additional parity bit. -- Viele Grüße, Tobi https://www.elpra.deArticle: 160636
On 06/06/2018 17:42, abirov@gmail.com wrote: > Hello all, I used Hamsterwork's http://hamsterworks.co.nz/mediawiki/index.php/Stepper stepper motor controller , there position out for leds etc. > How i can make give position back.. > > I.E. I want to give position to stepper motor controller not push a button.. could some one help me with code ? > testArticle: 160637
On 29/06/2018 21:22, gnuarm.deletethisbit@gmail.com wrote: > The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM blocks in widths of multiples of 9 bits. Some other devices only have RAM widths of multiples of 8 bits or less. > > Does this make much of a difference to you? Do you use the 9 bit widths in your designs? > > Rick C. > I've made use of the extra bits for meta data: For example, in a complicated buffering system for gigabit Ethernet I move data around the chip as 32 bit words stored in 36 bit wide registers (4 x9). The extra 4 bits are used to say if this is the last 32 bit word in a message, how many bytes in the word are valid (always all 4 unless its the last word), and the last bit can invalidate the whole message. I'd miss the extra bits if they weren't available. MKArticle: 160638
On Monday, 2 July 2018 20:00:46 UTC+12, Michael Kellett wrote: > On 06/06/2018 17:42, abirov@gmail.com wrote: > > Hello all, I used Hamsterwork's http://hamsterworks.co.nz/mediawiki/index.php/Stepper stepper motor controller , there position out for leds etc. > > How i can make give position back.. > > > > I.E. I want to give position to stepper motor controller not push a button.. could some one help me with code ? > > > test Given that my email is in the code's header, I am surprised that you didn't email me.... :-)Article: 160639
On Friday, June 29, 2018 at 11:22:52 PM UTC+3, gnuarm.del...@gmail.com wrote: > The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM blocks in widths of multiples of 9 bits. Some other devices only have RAM widths of multiples of 8 bits or less. > > Does this make much of a difference to you? Do you use the 9 bit widths in your designs? > > Rick C. FYI, the only Altera series from "recommended for new designs" list that have RAM blocks in multiples of 9 bits are "CPLD-replacement" MAX10 and decade-old Cyclone10LP. Cyclone5, Arria5, Stratix5, Arria10/Cyclone10GX and Stratix10 all has embedded RAM blocks in multiples of 10 bits.Article: 160640
On Wednesday, July 4, 2018 at 5:45:22 AM UTC-4, already...@yahoo.com wrote: > On Friday, June 29, 2018 at 11:22:52 PM UTC+3, gnuarm.del...@gmail.com wrote: > > The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM blocks in widths of multiples of 9 bits. Some other devices only have RAM widths of multiples of 8 bits or less. > > > > Does this make much of a difference to you? Do you use the 9 bit widths in your designs? > > > > Rick C. > > FYI, the only Altera series from "recommended for new designs" list that have RAM blocks in multiples of 9 bits are "CPLD-replacement" MAX10 and decade-old Cyclone10LP. > Cyclone5, Arria5, Stratix5, Arria10/Cyclone10GX and Stratix10 all has embedded RAM blocks in multiples of 10 bits. I didn't know that. Hmmm... that could be very useful. Rick C.Article: 160641
I've always found 9bits useful, especially when doing just general buffering while waiting for memory to free up. Then put 8 bits of data and a start signal to keep everything in sync all the time. <gnuarm.deletethisbit@gmail.com> wrote in message news:82abdd48-6290-4799-8a3c-aa62845d7e95@googlegroups.com... > The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM > blocks in widths of multiples of 9 bits. Some other devices only have RAM > widths of multiples of 8 bits or less. > > Does this make much of a difference to you? Do you use the 9 bit widths > in your designs? > > Rick C.Article: 160642
Hi folks, I have a little project I've been working on to make a better HDL-like language. It's a subset of C so should be familiar. I am using a Digilent Arty Artix-35T board and have a working UDP example. I am looking for opinions on current progress and ideas for what features/projects to pursue next. Also, if you like correcting bad python - heyo! Check it out eh: https://github.com/JulianKemmerer/PipelineC Thanks, JulianArticle: 160643
http://mymicroprocessor.blogspot.com/2018/08/fpga-simplest-processor.html Go to my blog for more information.Article: 160644
On Thu, 9 Aug 2018 15:28:57 -0700 (PDT) othmana@gmail.com wrote: > http://mymicroprocessor.blogspot.com/2018/08/fpga-simplest-processor.html > > Go to my blog for more information. > I couldn't quickly fine a simple architecture description, only the Java emulation tool. Jan CoombsArticle: 160645
On 09/08/2018 23:28, othmana@gmail.com wrote: > http://mymicroprocessor.blogspot.com/2018/08/fpga-simplest-processor.html > > Go to my blog for more information. > Why not make it easy for us and just give us the UK patent reference here. MKArticle: 160646
On Saturday, August 11, 2018 at 12:18:27 PM UTC-4, Michael Kellett wrote: > On 09/08/2018 23:28, othmana@gmail.com wrote: > > http://mymicroprocessor.blogspot.com/2018/08/fpga-simplest-processor.ht= ml > >=20 > > Go to my blog for more information. > >=20 > Why not make it easy for us and just give us the UK patent reference here= . What is easy about reading patents? =20 The US transmits a time code signal from Colorado which isn't always receiv= able on the east coast. Some 10 years ago (or so) they modified the signal= to include phase modulation which should be easier to receive. The only t= rouble is a company (who may have worked with the US government) got a pate= nt for a receiver of this phase modulated signal. I can't be sure of what = I'm reading in the patent, so I can't try to design around it and sell a ph= ase demodulated receiver. If they were easy to read, I would know just wha= t had been patented and would be able to design a non-infringing receiver.= =20 Rick C.Article: 160647
On Sunday, 12 August 2018 00:18:27 UTC+8, Michael Kellett wrote: > On 09/08/2018 23:28, othmana@gmail.com wrote: > > http://mymicroprocessor.blogspot.com/2018/08/fpga-simplest-processor.html > > > > Go to my blog for more information. > > > Why not make it easy for us and just give us the UK patent reference here. > > MK http://mymicroprocessor.blogspot.com/2018/08/simplest-processor-patent-application.htmlArticle: 160648
On Monday, August 13, 2018 at 7:10:14 AM UTC-4, oth...@gmail.com wrote: > On Sunday, 12 August 2018 00:18:27 UTC+8, Michael Kellett wrote: > > On 09/08/2018 23:28, othmana@gmail.com wrote: > > > http://mymicroprocessor.blogspot.com/2018/08/fpga-simplest-processor.html > > > > > > Go to my blog for more information. > > > > > Why not make it easy for us and just give us the UK patent reference here. > > > > MK > > http://mymicroprocessor.blogspot.com/2018/08/simplest-processor-patent-application.html Ok, I looked at it a bit. Is there something special about this particular design? What were your goals in designing it? What aspects of this design excel in small CPUs? Rick C.Article: 160649
On Thursday, 16 August 2018 04:03:15 UTC+8, gnuarm.del...@gmail.com wrote: > On Monday, August 13, 2018 at 7:10:14 AM UTC-4, oth...@gmail.com wrote: > > On Sunday, 12 August 2018 00:18:27 UTC+8, Michael Kellett wrote: > > > On 09/08/2018 23:28, othmana@gmail.com wrote: > > > > http://mymicroprocessor.blogspot.com/2018/08/fpga-simplest-processo= r.html > > > >=20 > > > > Go to my blog for more information. > > > >=20 > > > Why not make it easy for us and just give us the UK patent reference = here. > > >=20 > > > MK > >=20 > > http://mymicroprocessor.blogspot.com/2018/08/simplest-processor-patent-= application.html >=20 > Ok, I looked at it a bit. Is there something special about this particul= ar design? What were your goals in designing it? What aspects of this des= ign excel in small CPUs?=20 >=20 > Rick C. decoding logic is simplest. Only 16 instructions but unlimited number of op= erators. CPU sim cannot handle this cpu. I need to pretend a few instructio= ns correspond to some operators. You can start with one operator. Immediate data is all used up for the lite= ral or constant. If you need more operators, allocate some bits in the immediate data field. It is the simplest because the 3 opcode bits out of 4, directly control the= mux in the data path. The jump bit, need to share with zero detector in order to provide conditio= nal jump. call return instructions are provided so make the decoding somewhat complic= ated but not by much. In many cases they are not required. For example, the= Lagged Fibonacci Random number generator does not need a call and therefor= e return instruction. I have 2 reserve instructions but committing them to work will need more co= mplicated decoding logic, which may not be justified. E.g. in one reserve instrucion, I wanted to implement a NOP. It is implemen= ted by decoding its 4 bit pattern, and then use it to disable register and = memory write. Just these two functions already crashed my Quartus. Still tr= ying to debug them. Imagine, just by adding 2 2-bit and gates, can crash Qu= artus FPGA CAD. Maybe, it is better not to implement the NOP instruction. We should find ot= her alternatives, such as duplicating instructions.
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