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Can you ask the guy what the email address is of the Xilinx CEO? I wouldn't mind having it when I am stuck at 2am and have nobody to ping. -Simon Ramirez, Consultant -Synchronous Design, Inc. "Victor the Cleaner" <jonathan@the-gimp.canuck.com> wrote in message news:8ohcko$bh6$1@cleavage.canuck.com... > Rant or not, this is the right forum for it, and I can't believe > that this isn't a bigger issue across our industry. What scares > me to death is the possibility that otherwise-intelligent people > who agree with me are keeping quiet because they're afraid of > being seen as "resistant to new technology", regardless of how > misplaced or misapplied that technology might be. If you agree, > please circulate freely. > > jl > > (sent yesterday to databook@xilinx.com and Xilinx's CEO) > > I don't know which semi-literate, multimedia-infatuated moron is > responsible for the so-called "databook on CD" I'm forced to deal > with right now, but you people had better get over it and get back > to paper. > > I'm a career engineer, and having been in design for 20 years. If > you think that makes me some kind of old fart who can't deal with > the Internet and new media, think again. I was away from design for > a couple of years while starting an Internet company, which I still > operate, and we do work for some pretty big companies with pretty > modern content. We also do some pretty challenging software R+D - > ask around and see if anyone you know has ever heard of an "Internet > company" with a Cray. > > I got back into design a couple of years ago, though, and was disgusted > to discover the extent to which actual hard-copy data books had been > replaced by CD distributions, most of them so badly implemented as to > be unusable. I understand the positive motivations: cheaper to produce > and distribute, more "environmentally friendly", etc., etc. > > However, the downside is not worth it. > > I started designing with FPGAs (and learning VHDL) about a year ago, > choosing to use Xilinx because the quality of both the local support > (via Insight) and the data book were top-notch, and especially helpful > to a beginning user. My first design (in Spartan) is now in production > and I'm working on new designs under Spartan II and Virtex that will > be in production before the end of the year. > > The problem, though, is that your 2000 "data book" is making it > increasingly difficult and frustrating to use your products. Imagine > this: You go to the tap to get a glass of water. When you turn the > handle, though, you have to listen to a fifteen-second fanfare *before* > any water will come out the spigot. It might be mildly amusing *once*, > but EVERY SINGLE TIME? With no apparent way to disable it? That's > how I look at the stupid blinking-boxes screen that opens your CD. > > But that's just the beginning. Your nagware then asks me (every single > time) whether I want to install your viewer, which I don't now, and likely > will never wish to. I tried it once, and installing it took me down more > useless tangents than I wish to recall. It asked me whether I wanted to > use the Internet. Even though I indicated "No", it screwed with my > network settings anyway, turning off my modem and switching my connection > to a LAN, which I don't have at the location where I'm presently working - > that's why I'm using the modem. Then it told me the databook was out of > date. Then it told me my acrobat reader was out of date. Then, when I > pretty much decided "fuck it" and wanted to start up my mailer to send you > this mail, I had to go screw with the network settings to restore the > modem connection broken by your viewer application. > > In other words, the whole experience SUCKED, taking minutes to fail to > deliver the information that a real book would have delivered in SECONDS. > > Now, it would be easy for you to misinterpret this mail and send my > complaints, out of context, to your Macromedia-happy multimedia developers > so that they might tweak and adjust out the the offending behaviours. That > would be completely missing the point. The point is that databooks on CD > DO NOT, and CAN NOT work as well as paper books. > > "So", you say, "just print out the parts you want and don't use the CD." > That's just a really dumb thing to do, isn't it? First, being a printer > isn't my job. Printing your databook on an average laser printer would > result in a book on the order of 10 times the size of the paper version > you should be delivering. My paper is 8.5x11, yours is 9x7. My printer > is single-sided, you print double-sided. I use heavy, thick bond paper, > you use much lighter stock. All of which assumes, of course, that acroread, > the printer, and whatever other bits happen to be in the path, work properly > on every page and don't force me to go screw with resolution, etc. But at > the end of the day, I'm a design engineer, and I shouldn't be wasting my > time printing an inferior version of the book it's your responsibility to > supply me with. > > Are you starting to get the message? I don't want blinking flashing splash > screens. I don't want messages from the president. I don't want propaganda > on your product line, and I sure as hell don't want spinning logos. I was > in the virtual reality business in 91/92 when SIGGRAPH banned spinning logos, > so you can be sure there's nothing clever about them in the year 2000. > > So how about getting with the ticket here, folks? Intelligent, literate > designers don't want this crap. They want books. Books they can read in > bed and on the john. Books they can scribble notes in. Books they can take > along for a weekend *away* from the computers. Books whose pages they can > flip back and forth between *infinitely* faster than they can with a > remarkably useless application like acroread (PDF? Around here that stands > for "pedofiles"). Books for smart people. > > I look forward to your reply. > > Jonathan Levine > Canada Connect Corp. > Calgary >Article: 25176
Norman Desal wrote: > > Hi, > > I have run into a problem in a design using a XC95108 by XILINX. > > This is a design including a simple I2C-Slave and some registers for > demultiplexing a 8bit data stream to a 16bit wide. > > I'm encountering faults in the function of the circuit which depend > on the existence or nonexistence of test connections in the FPGA, i.e. > the FPGA doesn't work, I put a test connection to an IOB and (voila) > the circuit works. But not without the test connection. > > I'm not sure what the cause for this behaviour may be. The circuit > is quite full, i.e. 102 of 108 Macrocells are used, some of them > obviously for routing. I suspect a problem with clock skew, but the > design is completely synchronous and the clock frequency is quite low. Sounds like the presence of the test connection prevents some logic from being optimized away. Look at your map reports. Also, have you constrained the design for clock frequency? Even if the frequency is "quite low," the tools may opt to choose area over speed in order to fit your (admittedly tight) design. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25177
Richard, This has been tested and verified with the version of software you are using. The bit is correctly set using the available options. To determine if this is a setup or other issue please contact the Xilinx Hotline to open a case either via the web at http://support.xilinx.com or at 1-800-255-7778.. Best RegardsArticle: 25178
David Kessner wrote: > That option doesn't have any impact on what I'm experiencing. Here's > part of a short message that someone from Xilinx sent me just > minutes ago: > > The test case you provided to the hotline has been > investigated and it was found that the I/O registers > all had IOB=FALSE attributes on them. This mapping directive > takes precedence over use of the "-pr b" command line switch. > This explains why none of the registers were mapped to IOBs. > > The "-pr b" mentioned is the same thing as the option you mentioned, > just the command line version of that option. > > I looked at the EDIF netlist and it sure does set the IOB attribute > to false. The next question is, Why? I didn't tell it to be false. > I guess there is more detective work to be done. Check in the FPGA Express constraints GUI, and make sure you didn't set that attribute to FALSE there. Also, *never* forward-annotate timing constraints from FPGA Express (that is, one of the FPGA Express options is "Export Timing Constraints"). That puts lots of constraints into your EDIF that don't need to be there, especially when most of your constraints will be covered by a simple PERIOD attached to the clock. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25179
Dan Hopper wrote: > This in fact turned out to be a misunderstanding on my part of the > logic sense of the tri-state enable of the output buffer. Whileas > the datasheet schematic implies to me that it is an active high > signal (labeled "OE" and no bubble), it is in fact active low. > Poking around in FPGA Editor and paying more attention on the second > time around showed that the software was aware of it even if I > wasn't. Dig this: at least with FPGA Express 3.3 and the 2.1i tools. FPGA Express doesn't know that the output enables in the XC4KXLA (what I used) IOB have a polarity-select mux in front of them. If you write active-hi output enable code, FPGA Express will use a CLB -- not the mux in the IOB -- to invert your output enable signal. It's not a PAR fault, it's a Synopsys fault. I have not tested this with 3.1i and FPGA Express 3.4. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25180
Jonathan, right! Incidentally, you have been pre-ranted by others (including me) in prievious threads. Peter Alfke said he would kick some heads at Xilinx and try to get future CDs cleaned up. Personally, I greatly prefer paper, too, and I will *not* install any windows apps from anybody's 'databook' CD. JohnArticle: 25181
Victor the Cleaner <jonathan@the-gimp.canuck.com> writes: > I don't know which semi-literate, multimedia-infatuated moron is > responsible for the so-called "databook on CD" I'm forced to deal > with right now, but you people had better get over it and get back > to paper. Um, you haven't heard of the great new invention of compulsory use of time-limited, personally licensed, node-locked university textbooks, then. CD databooks are actually very conservative and consumer friendly products compared to those. http://www.vitalviewer.com/files/VBSolution.html CD databooks are bad but at least lending a Xilinx CD databook to a colleague does not impose 5 years in prison and/or a $500,000 fine ... Zoltan -- +------------------------------------------------------------------+ | ** To reach me write to zoltan in the domain of bendor com au ** | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 25182
sulimma@my-deja.com wrote: > How about partial reconfiguration? It is not mentioned in the spartan-II > datasheet? (unless I am blind) > > Is it supported anyway? The key word here is "supported". To the best of my knowledge no one "supports" partial reconfiguration in any real way. The Spartan-II parts will operate with partial reconfiguration, but you have to do much of the software yourself. The really hard part is generating the placement and routing to fit in the portion of the chip that you are reconfiguring. None of the existing tools will do that. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25183
From what Peter has said in the past, the cost driver for the Spartan-II comes from the smaller geometry that they used in this family, .18 um vs. .25 um for the Virtex parts. Also contributing is the limited availability of package options. They span a range of sizes, but not a lot of different packages for any size part. So the package/part matrix is more sparce than the Virtex parts. This saves Xilinx money in production and inventory costs. As others have said, there is nearly no difference in the two functionally. "S. Ramirez" wrote: > > Does anyone know the exact differences, hardware wise, between a > Spartan II and a Virtex? > Peter mentioned earlier that there was a temperature diode difference > (no diode in Spartan II), but there's got to be more to it in order to > explain the cost differential. > -Simon Ramirez, Consultant > Synchronous Design, Inc. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25184
Just to stick my two cents worth in... I do like data books. I also like PDF files. I do not like any of the data book CDs I have gotten from any companies. A few come close by duplicating their web pages, but the mixing of HTML and PDF is not really the right answer either. So my vote is for the support of both paper on new products which I read like a text book, and PDF files on old products which I refer to as reference material. Certainly there is nothing wrong with distributing PDF files by CD. But there is little right with the way it is done. Leave off the install software and the "viewers". Victor the Cleaner wrote: > > Rant or not, this is the right forum for it, and I can't believe > that this isn't a bigger issue across our industry. What scares > me to death is the possibility that otherwise-intelligent people > who agree with me are keeping quiet because they're afraid of > being seen as "resistant to new technology", regardless of how > misplaced or misapplied that technology might be. If you agree, > please circulate freely. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25185
Wow! This is pretty scary. Instead of software licenses changing to work
like books, they are changing books to be licensed like software! Read
how they think of this process...
For publishers, VSTi offers a content distribution model that
helps publishers create the highest possible quality
next generation conduit for delivering their materials
to students,
significantly increases the number of titles
students purchase each year,
significantly reduces overhead costs associated
with manufacture and distribution of textbooks, and
promises continued licensing of publisher materials
through continuing education.
In the process the VSTi model
creates a copyright compliant environment on campus,
gets rid of the need for used books,
tailor-makes solutions to fit the unique needs of each campus.
To me this sounds like they are trying to minimize the cost of making
text books, minimizing the reusability and maximizing the cost! What a
great marketing scheme!!!
Anyone who would buy a book with an expiration date on it needs to have
his head examined.
Zoltan Kocsi wrote:
>
> Victor the Cleaner <jonathan@the-gimp.canuck.com> writes:
>
> > I don't know which semi-literate, multimedia-infatuated moron is
> > responsible for the so-called "databook on CD" I'm forced to deal
> > with right now, but you people had better get over it and get back
> > to paper.
>
> Um, you haven't heard of the great new invention of compulsory use
> of time-limited, personally licensed, node-locked university textbooks,
> then. CD databooks are actually very conservative and consumer friendly
> products compared to those.
>
> http://www.vitalviewer.com/files/VBSolution.html
>
> CD databooks are bad but at least lending a Xilinx CD databook to a
> colleague does not impose 5 years in prison and/or a $500,000 fine ...
>
> Zoltan
>
> --
> +------------------------------------------------------------------+
> | ** To reach me write to zoltan in the domain of bendor com au ** |
> +--------------------------------+---------------------------------+
> | Zoltan Kocsi | I don't believe in miracles |
> | Bendor Research Pty. Ltd. | but I rely on them. |
> +--------------------------------+---------------------------------+
--
Rick Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design
Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
Internet URL http://www.arius.com
Article: 25186In article <8ohcko$bh6$1@cleavage.canuck.com>, Victor the Cleaner <jonathan@the-gimp.canuck.com> wrote: > The point is that databooks on CD > DO NOT, and CAN NOT work as well as paper books. > I agree with almost everything that you say, except on this one point. There are a few instances where the electronic format is handy. I find that with the browser based software documentation, you can search for the name of a library element or attribute and it takes you there instantly. I find this faster than grabbing the libraries guide, and leafing through to find the element or attribute. I like to have datasheets in electronic format as well as databooks, because I can easily deliver electronic datasheets to my customers as part of a documentation package (this stuff just gets filed anyway). Also, I like to print out things like I/O pin lists so that I can mark them up and check them against my board schematics. > "So", you say, "just print out the parts you want and don't use the CD." > That's just a really dumb thing to do, isn't it? First, being a printer > isn't my job. Printing your databook on an average laser printer would > result in a book on the order of 10 times the size of the paper version > you should be delivering. I requested a datasheet on a part from PMC Sierra. They sent a CD. The data sheet is in the order of 400 pages. I called the rep and said that if they thought I was going to print this that they were nuts, and I asked them to send me a databook. They said okay, proceeded to print the PDF document, and shipped me the resulting ream of paper :( If a datasheet is only a dozen pages, then I don't care if it's in electronic format only. But when you are talking about hundreds of pages, then a handbook is absolutely necessary, in addition to electronic form. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25187
No, the logic and routing resources are virtually identical. As a matter af fact, you can load a virtex50-FG256 with a bitstream for a spartanII50-FG256...so they are identical functionally down to the bitstream level. As Peter previously mentioned, the spartanII replaces the temp sense diode in virtex with a pair of pins that let you put it into a power down but still retain the contents mode. I got the impression the CLB was taped out again to make it physically smaller (less silicon area), and of course the packaging options are very limited. Dan wrote: > > Are you saying the route resource/Logic ratio was decreased in Spartan II. > Thus making it more difficult to route your design in a Spartan II vs. a > similarly sized Virtex ? > > Dan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25188
Norman, A couple of thoughts, forgive me if I'm stating the obvious. 1.) Assuming you have a simulation test bench that is comprehensive enough to demonstrate the basic functionality, then compare the performance of the structural model generated by P&R to the behavioural model fed into the synthesis stage. We use the "timesim.vhd" model in conjunction with the VITAL .sdf file to do a very accurate timing simulation. This will tell you wether or not the tools are screwing up your logic implementation, as can sometimes happen, or if you have a more subtle race or skew problem. 2.) If the structural model simulation looks good, then you may have a ground bounce or VCC bounce problem. There are a number of standard techniques for minimizing these effects. I believe Xilinx has some good app notes on them. You can also look into configuring your bus drivers for "slow slew rate" to see if it reduces the transients. Also look at your clock signals to verify that your edges are clean, especially through the critical transition regions. I've seen small edge glitches occasionally double clock synchronous logic and wreak havoc. I don't think 102/108 is that full. We routinely run at 99-100% with some of our designs. They do get kind of hot though... Good luck, you're going to need it! Tom Meagher ICS Triplex Houston TX "Norman Desal" <nds@iee.et.tu-dresden.de> wrote in message news:8og26m$nu4$1@rks1.urz.tu-dresden.de... > Hi, > > I have run into a problem in a design using a XC95108 by XILINX. > > This is a design including a simple I2C-Slave and some registers for > demultiplexing a 8bit data stream to a 16bit wide. > > I'm encountering faults in the function of the circuit which depend > on the existence or nonexistence of test connections in the FPGA, i.e. > the FPGA doesn't work, I put a test connection to an IOB and (voila) > the circuit works. But not without the test connection. > > I'm not sure what the cause for this behaviour may be. The circuit > is quite full, i.e. 102 of 108 Macrocells are used, some of them > obviously for routing. I suspect a problem with clock skew, but the > design is completely synchronous and the clock frequency is quite low. > > Could some friendly soul give me some hints? > > Thanks, > > NormanArticle: 25189
Greg, supplementary rant: I just *hate* it when a PDF file, on CD or online, has a file name that has nothing to do with the part itself. On the Xilinx CD, all the file names are nonsense, and you have to go through an HTML page or something to find things. This is crazy! JohnArticle: 25190
I printed your rant and I took it to the john. Once printed it was so easy to read. I was so surprised when I got to the end and saw that you were Canadian. I think you've got some yankee blood in you. Anyway, you certainly made some good points and yes it was a good read. I do have a preference for minimizing the data books in my hard library. It has shrunk incredibly over the last two years. Sorry victor but I do like the e-data books. I do agree they need to be more user friendly. DanArticle: 25191
On Mon, 28 Aug 2000 18:34:39 -0700, Jon Kirwan wrote: >On Fri, 25 Aug 2000 19:22:18 -0700 (PDT), "Matthew S. Staben" ><mstaben@poboxes.com> wrote: [snip] >One problem I've observed is the feelings that some folks have over >them. I discussed a recent case where a company had an NDA in hand >that they believed allowed them power they didn't frankly have. In >the process of trying to force the issue, they demolished important >relationships that they needed. > >The court never got involved. But bad feelings abounded over little. Jon, Another point I'd like to make obvious is how restricting a set of signed NDAs could be at subsequent interviews. Q: "Well, I signed this one there, and this other one elsewhere. Do these NDA documents screw me here?" A: "Well, sign this NDA and I'll send these over to our corporate attorney and we'll figure something out." MattArticle: 25192
rickman wrote: > I am not board layout engineer, but one rule that should always work to > give you good signals on a board trace is to use very short point to > point traces. The round trip delay is about 1 nS per foot. Your advise is good, however, light speed is about 1ns/foot in free air one way, not round trip. Signal propagation speed in FR4 (standard PCB material) is less than half as fast. Steven DeLong wrote: > I would like to avoid external terminations My opinion is that at 200 MHz that external terminations are a requirement, and I would suggest trying a low voltage swing, terminated standard like SSTL. -- Phil HaysArticle: 25193
I gave up reading all responses, but have another non-disclosure for them to sign, in case they ask you something they can market or patent... Zoltan Kocsi wrote: > > rickman <spamgoeshere4@yahoo.com> writes: > > > [...] > > A completed application, > > > > A "consumer report" (otherwise known as a credit check) authorization, > > > > A Background questionnaire release form, > > > > Then they want me to leave behind a urine sample for drug testing. > > [...] > > It ain't gonna be too long until you'll have to go through genetic > screening to get the job. A brave, new world, it is ... > > Zoltan > > -- > +------------------------------------------------------------------+ > | ** To reach me write to zoltan in the domain of bendor com au ** | > +--------------------------------+---------------------------------+ > | Zoltan Kocsi | I don't believe in miracles | > | Bendor Research Pty. Ltd. | but I rely on them. | > +--------------------------------+---------------------------------+Article: 25194
Here is some content that my local Xilinx FAE has come up with:
"SpartanII is cheaper than Virtex because it is done on a hybrid process.
The transistors are still .25 u. and the routing and all other features are
done at .18 u. This does allow us to shrink the die and reduce the cost.
The other factor in the cost reduction is the packaging. We targeted only
the cheaper plastic packages and also reduced the number of packages offered
for each density which also reduces the infrastructure costs and, in the
end, reduces the parts cost as well."
So functionally the part is the same, but the hybrid process and
packaging is what drives down the cost. I wonder why they didn't go .18u
all the way. It has to be timing issues.
Now if only they will deliver in time!
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"S. Ramirez" <sramirez@cfl.rr.com> wrote in message
news:3uUq5.2462$_8.341101@typhoon.tampabay.rr.com...
> Does anyone know the exact differences, hardware wise, between a
> Spartan II and a Virtex?
> Peter mentioned earlier that there was a temperature diode difference
> (no diode in Spartan II), but there's got to be more to it in order to
> explain the cost differential.
> -Simon Ramirez, Consultant
> Synchronous Design, Inc.
Article: 25195Hello I would like to simulate project after synthesis proces. What file I should simulate. Where is and what is name the file. For example I synthesized file : databus.v. After synhesis what is that file which i can simulate? I request about detail description of the problem/ With regards Tomek -- Department of Electrical Metrology Technical University of Zielona Gora T.Brychcy@sensor.ime.pz.zgora.plArticle: 25196
Hello Tomek, I use MaxPlus II to simulate after synthesis a project but it works only for Altera FPGA. I save design in an EDIF file for reload it in MaxPlus II. But you can use ModelSim for others projects. So, after synthesis if you can simulate verilog or vhdl files. If you want to have the timing, you can save an SDF file that contains timing informations. When you load your verilog or VHDL file in ModelSim you can choose to link the design with a SDF file. MarcArticle: 25197
Hello, Why after writing a synthesizable project we have to write in this way that latches was the least in the project. Latches are not synhesis efficient, if yes will tell me why? Tomek -- Department of Electrical Metrology Technical University of Zielona Gora T.Brychcy@sensor.ime.pz.zgora.plArticle: 25198
"S. Ramirez" wrote: > > Here is some content that my local Xilinx FAE has come up with: > > "SpartanII is cheaper than Virtex because it is done on a hybrid process. > The transistors are still .25 u. and the routing and all other features are > done at .18 u. This does allow us to shrink the die and reduce the cost. > So functionally the part is the same, but the hybrid process and > packaging is what drives down the cost. I wonder why they didn't go .18u > all the way. It has to be timing issues. Or possibly the voltage. As you reduce the geometry, the power supply voltage needs to decrease as well. Actually I would have preferred that it be a 1.8 volt process to be compatible with some of the DSP chips I would like to use. But these days the core voltages are all over the map. TI has new chips that use 1.5, 1.6 and 1.8 volts. What difference does 0.1 volts make??? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25199
Hi, To duplicate register with FPGA Express, I used to set -> Edit constraints /Modules /Duplicate register merge to allow the duplication. Does any body know how to do the same thing with Leonardo Spectrum (1999). I use the level II with a script. I've read the app note but I want some advice from somebody that already experience this problem. Thank you Bfc Sent via Deja.com http://www.deja.com/ Before you buy.
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