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Greg and Andrew, Thank you both. Re: signal integrity, here's what I know and I can look into this some more: 1. JTAG signals are buffered on the target board. 2. Our implementation follows the ByteBlaster and JAM Player in that we use a 3-phase clock, TDI and TMS change at t=1 while the TCK is stable, then the clock goes up at t=2, down at t=3, then the cycle repeats. 3. I don't 'own' the target board (I 'own' the download system) but others have looked at the signals on it. Regards, -rajeev-Article: 59501
Jeff Sampson wrote: > I guess because the big tables of I/O standards that I didn't recognize scared > me. ;-) And then Peter pointed out that 5V tolerant doesn't mean 5V tolerant > and quoted using limiting resistors. Not true. I made a distinction between "tolerant" and "compatible". > But I tried to balance that with statements > like "You can lead a 286 to water, but you can't make it drink." :-) > > So I went back and checked the spec sheets for the parts I already have defined: > > > Part ViL ViH VoL VoH > > > > IDT 7208 FIFO 0.8 2.0 0.4 2.4 > > KM681000 RAM 0.8 2.2 0.4 2.4 > > ADC1175 1.0 3.0 0.4 2.4 > > LM1881 - - 0.8 4.5 > > OV5017 Imager 0.8 2.0 0.6 2.4 > > > > The ATMega103L on the STK300 board can run at 5V or 3.3V. > > [If I use a big part like Spartan then I probably don't need an external FIFO] > > I see that the only one that may not work seems to be the ADC1175. So open drain > and a pullup to 5V? 3.0 is actually lower than 3.3. So you are safe. Spartan-II overdrives the ADC input by 300 mV. > > So, do I just default all inputs to LVTTL? Read it up in TechXclusives: http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp and go to "What are the...pins doing?", byAustin and Peter, published Jan 03. It tells you that LVTTL is a pin that does nnot have the clamping diode to Vcc. I would go with LVCMOS and Vcco=3.3 V. That gives you the diode to Vcco. Then you configure the output as open collector ( i.e. use the signal that drives the data also to drive the Tristate output signal ( note the polarity, which is up to you to adjust). Now you need an external pull-up resistor to 5 V, and it will pull a whole diode drop higher than Vcco, i.e. to 4.0 V in your case. It's all not necessary, since 3.3 V already gave you enough drive, but apparently you want more noise immunity. Forget about GTL, no need for it. Peter Alfke This gives me 5V tolerance and > doesn't require VREF. Can all outputs also default to LVTTL? Or is one of the > PCI standards a better choice? Except outputs that have to swing higher, then > would I use OBUF_GTL and an extertnal pullup for those? > > And can I do OBUFT_GTL with external pullup? > > If I do a bidirectional do I use IOBUF_GTL with external pullup? But that sets > up a diferential input buffer. Maybe I'll just avoid using bidirectional with a > 5V swing. > > Will setting GTL require the VREF pin? Or is there another way to specify open > drain? If I can specify it directly then I could run LVTTL and tell it the > output is open drain. > > [I'm sorry to be such a pain about this. Does Xilinx have an APP note or White > Paper about 5V interfacing?] > > -- > Jeff Sampson > http://tcrobots.org/members/jsamp.htmArticle: 59502
Mikeandmax wrote: > > jim thought - > >My understanding is the 'free' version is a 6 month demo, and $$$ are > >needed for more than that ? > > Lattice also do not have a separate ABEL download, but instead have one > >very large bundle. > > Seems there would be an opening for a smaller download, of ABEL only, > >for SPLD and CPLDs (eg new 4000 family ) ? > > > >-jg > > Well, the free license expires in 6 months, and you can always get another free > license in 6months, so it'll never cost more than a minute on the weblicense > page. Thanks Mike, The problems with this is not the 'never cost more than a minute', but the real risk exposure of the user, to a change in policy or circumstance at Lattice. Timebombed licenses are a disaster waiting to happen. I can understand 3rd party marketing pressure for time limits, (or crippled/slow versions ) but do you really _need_ to timebomb ABEL ? ( or is it only the 3rd party tools that are timebombed ? ) > Yes, you do need to download a fairly large file, but we have split up the d/l > so you can get just the minimum (still 63 mb :( ) required. Perhaps you should ask about a smaller, ABEL only (and not time-bombed) download ? I could point out that Atmel's CUPL (SPLD/CPLD) tool flow is smaller, and not time bombed :) If we could get a perpetual ABEL tool flow, that was stand-alone, and supported SPLD/Smaller CPLDs, we might look to qualify some of the new Lattice MACH4000 families in our designs. - jg > Mike Thomas > LSC FAEArticle: 59503
JoeG wrote: > > We literally have hundreds of PALs/GALs to maintain. Nevertheless after one > migrates from ABEL to VHDL or Verilog which tool can target the code to a > 22V10 these days? > > JoeG Very few. Translation also exposes version control issues - you have to hope the HDL tools generate the same code as ABEL. If you currently use ABEL Test Vectors, and append these to JED files, then that becomes another problem with VHDL/Verilog flows. Xilinx's ABEL flow used to include SPLDs, but I'm not sure if it still does ( since they no longer sell SPLD ) - jgArticle: 59504
Austin Lesea wrote: > > Joe, > > You are correct: there is a 'hole' here. > > Have looked into it, and the present "official" response is to archive your > software (and support computers) to support the older designs for the standard > commercial customer. > > For the military/high-rel customer, there is no real policy (I was more > optomistic, but I turned out to be wrong -- no one had really sat down and > thought it through for mil-spec). > > There are other business models which also require a much longer term support > method (such as automotive), so you are not 'alone.' This is an area that we > are now looking at. .. and Industrial users.. ( in fact, it's probably ONLY consumer products who are a 'dont care' on legacy support issues :) > > Thank you for bringing it to our attention as a deficiency. Is there a table/matrix of what is hardware keyed, and what software has real problems with new OS (GUI stuff?) and what SW can run ok under newer OS (command line stuff?). Or which Sw/Keys run OK under Philip F's idea of vmware ? Which design flows are affected - Schematic vs HDLs ? - jgArticle: 59505
Unfortunately -- it appears VMWARE supports Windows OSes and Linux -- We originally design our XC4000 series part via Mentor Graphics A4F and XACT 5.2 -- both reside on an old Sun WorkStation under SUNOS 4.1.4. Mentor was used to schematic capture the design -- XACT was used to place/route and generate the bit streams. "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message news:3F43D73B.BB23CBE7@xilinx.com... > Philip, > > What a great idea.... > > Austin > > Philip Freidin wrote: > > > On Wed, 20 Aug 2003 17:21:37 GMT, "JoeG" <JoeG@nowhere.net> wrote: > > >It wasn't a rant but an honest question -- after re-reading my post I > > >noticed I transposed the words "we" and "are" in the final sentence. > > > > > >So are we STUCK with maintaining an OLD machine with OLD Xilinx XACT > > >software --- > > > > > > > > >BTW I've already asked my rep, distrib, and Xilinx the same question -- they > > >all said you need to keep the OLD XACT software and maintain an old > > >Workstation -- again NOT acceptable. > > > > While I have no great solution for the old software, I have a pretty > > good solution for old operating systems and old systems to run them > > on. I use a fine product called VMWare www.vmware.com . With it > > and a few spare gigabytes of disk on my current machine, I maintain > > over a dozen different legacy systems, each with the OS of choice > > for that legacy sw, and an environment that lets it run. I also > > use it for project isolation, for testing out new versions of sw > > that I don't trust to run on my "real" machine, and for isolation > > of packages that may interfere with each other. > > > > Given the current cost of IDE disks at below $1.00 per gigabyte, > > I get a complete, safe, encapsulated, archived computer for less > > than a few dollars, and no physical space in my office. In total, > > I maintain about 20 such legacy/test/isolation computers in a > > 80 gigabyte partition (about 50 GB used), for the cost of about > > $70 > > > > Philip Freidin > > > > Philip Freidin > > Fliptronics >Article: 59506
Jonathan Bromley wrote: > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:3F4396CA.FC62CB8D@xilinx.com... > > > The XC3000 is to a modern FPGA what a '286 is to a Pentium4. Would your > > professors suggest you use a '286? It's a capable computer, but > > hopelessly obsolete and underpowered. So is the XC3000. > > Get with it and use Spartan or Virtex devices. > > "One year in the life of an FPGA is like 15 years in a human". > > By that rule, your XC3000s should be in the old folks' home or the > cemetary. > > Hmmm... Peter, I suspect you are not quite so aware of the constraints > on typical college lecturers and support departments as I am :-) > > Every change of infrastructure entrains a mountain of work: typically, > haggling with central IT services to allow a piece of software to be > installed; fighting for budget to replace obsolete demo hardware > (and don't forget that you probably need to replace a class set); > rewriting endless class teaching material, and reprinting it all. > In the "real world" the cost of this sort of infrastructure shift > is covered by the productivity gains you get from the new stuff; > in teaching, it's all downside - you get the cost, but no gain; > but if you don't spend the effort, pain comes later with software > incompatibility and general unsupportedness. And no, you > can't simply mothball a set of machines to run the old software. > The college's central IT services will probably forbid the > installation of "untrustworthy" software like this WebPack > doohickey they've never heard of, but will without a qualm > update the entire network from NT to XP or whatever happens > to suit the sysadmin's purpose, so elderly software will eventually > become unusable. > > So the poor beleaguered lecturers hang on to what they know > for as long as they can, until external pressures force them > to change. There's no smooth continuous stream of project- > funded design starts to encourage incremental upgrading. > > I got out of that world a few years back. I miss much about > it, but I certainly have no nostalgia for the fights to keep > even halfways up-to-date with practical and lab material. Yes, that puts it quite well, I think.... -jgArticle: 59507
Herr Stumpf, Quartus II version 2.1 SP1 had incorrect values for the IO adder for the 2.5V and 1.8 V IO standards, so it incorrectly reported the tCO. We fixed the values in version 2.2 SP1; this version shows the correct values. You can see in your attached timing analysis that the only value that changed was the CELL right at the pin BLM_SYNC; it changed from 1.905 ns to 4.066 ns, and the 4.066 ns value is correct. From your posting, it sounds like the tCO reported in version 2.2 SP1 does not meet your design constraints. A potential solution is the PLL in the APEX 20KE device. This has the ClockShift feature, whereby you can adjust the clock phase or delay in varying increments. You can then adjust the clock to compensate for this longer tCO to bring it back to your requirement. Doing so will increase the tSU of input registers clocked by the same clock; if this change causes the tSU to not meet your constraints, you can compensate for this effect by turning off the "Input pin to Core" or "Input pin to Input Register" delay. This is on by default to ensure a zero hold time when driving into the device, but when the PLL is used this is not required due to the shorter clock delay. Sincerely, Greg Steinke gregs@altera.com Altera Corporation wolfram.stumpf@diehl-avionik.de (Wolfram Stumpf) wrote in message news:<e9445532.0308192209.28cb74a@posting.google.com>... > I'm synthesising a design targeting the Altera Apex20KE > (EP20K400EFI672-2X). The design uses 2.5V IOs. While moving from > Quartus version 2.1sp1 to 2.2sp1, I realised the the tco-value for my > 2.5V IOs changed. > ...Article: 59508
Hi, I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz clock for other devices. I am using a virtexII device, so I can use the DCM wizard to divide the clock by two. How is this better than using a state machine with two states that inverts the output signal on each rising edge of the input clock? That scheme could be used to divide the clock by any power of two number...Why would I use the DCM for those? Thanks DaveArticle: 59509
Actually, the DCM only works on frequency higher than 24Mhz, so I would need to double the clock in order to use it. ( I heard the DCM can do this, but I just don't see how...I can't do it in the wizard using any options possible...). David "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message news:bi0ufn$6nt$1@home.itg.ti.com... > Hi, > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > clock for other devices. I am using a virtexII device, so I can use the DCM > wizard to divide the clock by two. How is this better than using a state > machine with two states that inverts the output signal on each rising edge > of the input clock? That scheme could be used to divide the clock by any > power of two number...Why would I use the DCM for those? > > Thanks > Dave > >Article: 59510
mikeandmax@aol.com (Mikeandmax) wrote in message news:<20030820061528.06062.00000167@mb-m19.aol.com>... > jim thought - > >My understanding is the 'free' version is a 6 month demo, and $$$ are > >needed for more than that ? > > Lattice also do not have a separate ABEL download, but instead have one > >very large bundle. > > Seems there would be an opening for a smaller download, of ABEL only, > >for SPLD and CPLDs (eg new 4000 family ) ? > > > >-jg > > Well, the free license expires in 6 months, and you can always get another free > license in 6months, so it'll never cost more than a minute on the weblicense > page. Mike, That's really not acceptable. I would imagine that Joe's problem will be that something will need to be fixed, or reprogrammed, or what-have-you, and that's when he'll need the tools. He'll go to his computer, try to run the tools, and get confronted with a "license has expired" complaint. Naturally, this will happen on a Friday night, or a weekend, and he's screwed until Monday. On Monday, he'll waste half the morning getting license files in order, fix the customer's problem, and forget about the design software license bomb until the next customer fire, which will of course be seven months later. And, of course there's no guarantee that Lattice (or whomever) won't change the "free for six months" policy. I've said this before, but it bears repeating: chip-vendor tools exist for one reason -- to enable engineers to design with the chip vendor's devices. To that end, the software should be free, and have no license restrictions. We should be able to install the software on any machine we choose, and get right to work. The usual response is, "well, you pay for tech support." Absolutely -- the yearly technical support contract should be independent of software licensing. If I need factory tech support, certainly I see that as something worth paying for. (Of course, one could further argue that excellent factory tech support enables the designer to complete more designs, and buy more chips, so tech support should also be free ... ) Oh yeah: if I had a dollar for every time I had to fsck around with FlexLM, I'd be rich. --aArticle: 59511
"Jay" <yuhaiwen@hotmail.com> wrote in message news:<bhsqh9$2prtc$1@ID-195883.news.uni-berlin.de>... > Paul, > > I tried to build a FIFO using HDL myself. It was synthesized and mapped into > FFs. > It seems that if I want it to be implemented by MFB, I must instantiate the > macros Lattice provided. Right -- the synthesis tools aren't smart enough to infer this sort of thing. I would hope that Lattice is working with Synplicity and Mentor Graphics to get this kind of thing added to the synth tools. The CAM is pretty cool, too -- too bad it's not in the XPGA. I'm not a synth-tool writer, but I can see that it could be difficult to come up with a template for FIFOs and CAMs. --aArticle: 59512
David, Well, the input clock of the DCM must be greater than 24 MHz, so you can't (by the recommended specifications) use 20 MHz. The advantages of the DCM are the fact that the output will be phase aligned with the input, and the outputs will directly drive the global clock resources. Austin David Lamb wrote: > Hi, > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > clock for other devices. I am using a virtexII device, so I can use the DCM > wizard to divide the clock by two. How is this better than using a state > machine with two states that inverts the output signal on each rising edge > of the input clock? That scheme could be used to divide the clock by any > power of two number...Why would I use the DCM for those? > > Thanks > DaveArticle: 59513
Jonathan, you make a good point. I had not thought about it too much. When I went to college, we used vacuum tubes, and the word software was not yet coined. I apologize for my crass comments, and I offer no solutions, short of better funding for schools and ( perish the thought ) higher taxes. But somehow the next generation engineers must not be educated using wire-wrapped logic boards with 10- to 20-year old devices. That misdirects their imagination in the wrong direction, and stifles their enthusiasm. Peter Alfke ============================= Jonathan Bromley wrote: > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:3F4396CA.FC62CB8D@xilinx.com... > > > The XC3000 is to a modern FPGA what a '286 is to a Pentium4. Would your > > professors suggest you use a '286? It's a capable computer, but > > hopelessly obsolete and underpowered. So is the XC3000. > > Get with it and use Spartan or Virtex devices. > > "One year in the life of an FPGA is like 15 years in a human". > > By that rule, your XC3000s should be in the old folks' home or the > cemetary. > > Hmmm... Peter, I suspect you are not quite so aware of the constraints > on typical college lecturers and support departments as I am :-) > > Every change of infrastructure entrains a mountain of work: typically, > haggling with central IT services to allow a piece of software to be > installed; fighting for budget to replace obsolete demo hardware > (and don't forget that you probably need to replace a class set); > rewriting endless class teaching material, and reprinting it all. > In the "real world" the cost of this sort of infrastructure shift > is covered by the productivity gains you get from the new stuff; > in teaching, it's all downside - you get the cost, but no gain; > but if you don't spend the effort, pain comes later with software > incompatibility and general unsupportedness. And no, you > can't simply mothball a set of machines to run the old software. > The college's central IT services will probably forbid the > installation of "untrustworthy" software like this WebPack > doohickey they've never heard of, but will without a qualm > update the entire network from NT to XP or whatever happens > to suit the sysadmin's purpose, so elderly software will eventually > become unusable. > > So the poor beleaguered lecturers hang on to what they know > for as long as they can, until external pressures force them > to change. There's no smooth continuous stream of project- > funded design starts to encourage incremental upgrading. > > I got out of that world a few years back. I miss much about > it, but I certainly have no nostalgia for the fights to keep > even halfways up-to-date with practical and lab material. > -- > > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 59514
JoeG, How do you support the Mentor schematic capture software? We have archived versions of XACT for PC's. Maybe you could email me directly, and I'll put you in touch with the right folks? As has been pointed out before, I am not really one person, but one person who knows all the right people....to ask. Austin JoeG wrote: > Unfortunately -- it appears VMWARE supports Windows OSes and Linux -- We > originally design our XC4000 series part via Mentor Graphics A4F and XACT > 5.2 -- both reside on an old Sun WorkStation under SUNOS 4.1.4. Mentor was > used to schematic capture the design -- XACT was used to place/route and > generate the bit streams. > > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > news:3F43D73B.BB23CBE7@xilinx.com... > > Philip, > > > > What a great idea.... > > > > Austin > > > > Philip Freidin wrote: > > > > > On Wed, 20 Aug 2003 17:21:37 GMT, "JoeG" <JoeG@nowhere.net> wrote: > > > >It wasn't a rant but an honest question -- after re-reading my post I > > > >noticed I transposed the words "we" and "are" in the final sentence. > > > > > > > >So are we STUCK with maintaining an OLD machine with OLD Xilinx XACT > > > >software --- > > > > > > > > > > > >BTW I've already asked my rep, distrib, and Xilinx the same question -- > they > > > >all said you need to keep the OLD XACT software and maintain an old > > > >Workstation -- again NOT acceptable. > > > > > > While I have no great solution for the old software, I have a pretty > > > good solution for old operating systems and old systems to run them > > > on. I use a fine product called VMWare www.vmware.com . With it > > > and a few spare gigabytes of disk on my current machine, I maintain > > > over a dozen different legacy systems, each with the OS of choice > > > for that legacy sw, and an environment that lets it run. I also > > > use it for project isolation, for testing out new versions of sw > > > that I don't trust to run on my "real" machine, and for isolation > > > of packages that may interfere with each other. > > > > > > Given the current cost of IDE disks at below $1.00 per gigabyte, > > > I get a complete, safe, encapsulated, archived computer for less > > > than a few dollars, and no physical space in my office. In total, > > > I maintain about 20 such legacy/test/isolation computers in a > > > 80 gigabyte partition (about 50 GB used), for the cost of about > > > $70 > > > > > > Philip Freidin > > > > > > Philip Freidin > > > Fliptronics > >Article: 59515
Senjed, Have a look at this webpage for details on implementing BRAM :- http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex11.html#1001085 regards, pradeep senjed wrote: > Hi > could anybody tell me how to tell the XST or Leonardo that I want the > RAM module I write to be implemented as a BlockRAM not a distributed > one? XST says you're using a mode not supported in Spartan II BlockRAMs. > I can't figure it out.Article: 59516
David, Per the spec, no it cannot using the DLL. But, you can send in a frequency lower than 24 MHz if you use the CLKFX, and not the CLK0, 90, 180, 270, 2X, or CLKDV outputs (DFS only) but the CLKFX output must also be greater than 24 MHz! (so M=1 and D=2 is OK, but only for Fin> 48 MHz!!!). Sorry. Use your flip flops. At 12 MHz, you probably are not all that concerned with a few hundred ps of skew or delay. That is why as a practical matter we don't see much need in supporting the CLKIN at frequencies below 24 MHz when talking about precise phase control. (If I am wrong here, please let me know, but we haven't heard any complaints about this that we couldn't provide a good solution for some other way). Austin David Lamb wrote: > Actually, the DCM only works on frequency higher than 24Mhz, so I would need > to double the clock in order to use it. ( I heard the DCM can do this, but I > just don't see how...I can't do it in the wizard using any options > possible...). > David > > "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message > news:bi0ufn$6nt$1@home.itg.ti.com... > > Hi, > > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > > clock for other devices. I am using a virtexII device, so I can use the > DCM > > wizard to divide the clock by two. How is this better than using a state > > machine with two states that inverts the output signal on each rising edge > > of the input clock? That scheme could be used to divide the clock by any > > power of two number...Why would I use the DCM for those? > > > > Thanks > > Dave > > > >Article: 59517
Pin locking in current FPGAs is not nearly the issue it was in earlier families.
For the ancient 3000 and orphaned 5200 families, pin locking is imperative. Plan
you pin assingments very carefully, or you will find yourself having to redo the
board. Logic usage as well as timing requirements contribute to pin locking
problems.
These parts are also not supported with the current tools, so you are going to have
to find an old copy of XACT and it's dongle and a suitable computer to run it on
unless you already have it.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 59518Dave, obviously you can use a simple toggling flip-flop to generate a half-frequency output. And you can use a more sophisticated synchronous counter for all sorts of clock division. The only advantage of using the DCM is that you can eliminate the through-delay. In other words you can make the clock edges of the two frequencies to coincide with very little skew, while a flip-flop plus routing etc might delay the edge by a few ns. If that doesn't matter, go for the toggling flip-flop. (In certain situations it might even be better to guarantee that the rising edge of your 10 MHz clock is later than the incoming 20 MHz rising edge. It all depends...) Peter Alfke David Lamb wrote: > > Hi, > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > clock for other devices. I am using a virtexII device, so I can use the DCM > wizard to divide the clock by two. How is this better than using a state > machine with two states that inverts the output signal on each rising edge > of the input clock? That scheme could be used to divide the clock by any > power of two number...Why would I use the DCM for those? > > Thanks > DaveArticle: 59519
JoeG wrote: > We literally have hundreds of PALs/GALs to maintain. Nevertheless after one > migrates from ABEL to VHDL or Verilog which tool can target the code to a > 22V10 these days? There is the ipal project at icarus.com that has languished due to lack of interest. This is support for 22V10 and that ilk of PLD devices, it generates a JEDEC file ready for the prom programmer. What ipal needs is someone to take an interest. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 59520
Austin Lesea wrote: > Joe, > > You are correct: there is a 'hole' here. > > Have looked into it, and the present "official" response is to archive your > software (and support computers) to support the older designs for the standard > commercial customer. You can't buy new computers that can run old Windows/DOS. The situation with Solaris/SPARC is a bit better, I suspect, as new systems have a better chance of running old software there. Doesn't it seem plausible that the hopelessly obsolete stuff can be "freed" (remove dongle checking and license managers) and offered for free download? I'm sure people like Joe would love to help themselves and leave you alone with the old stuff if given half a chance. (For the sake of full disclosure, this is one of my favorite reasons for open source software.:-) -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 59521
Go into Frequency Synthesis mode, and use M=2, D=4. But why? Do you need coincident edges? As a general rule: Always tell us a little more than the absolute bare-bone question... Peter Alfke ======================= David Lamb wrote: > > Actually, the DCM only works on frequency higher than 24Mhz, so I would need > to double the clock in order to use it. ( I heard the DCM can do this, but I > just don't see how...I can't do it in the wizard using any options > possible...). > David > > "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message > news:bi0ufn$6nt$1@home.itg.ti.com... > > Hi, > > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > > clock for other devices. I am using a virtexII device, so I can use the > DCM > > wizard to divide the clock by two. How is this better than using a state > > machine with two states that inverts the output signal on each rising edge > > of the input clock? That scheme could be used to divide the clock by any > > power of two number...Why would I use the DCM for those? > > > > Thanks > > Dave > > > >Article: 59522
Problem with PALs is that they will be obsolete in not too long - I can get little max devices for less than PALs, and they allow me to use code (verilog) that will probably be around for longer than ABEL - I know that some companies will say that they will continue to support PALs, but Intel told me that the 960 line would be supported for 10 years in 1995 - eight years later - no support at all. Bet your future on things that are present, rather than things that are obsolete now in the semiconductor industry. Andrew Stephen Williams wrote: > JoeG wrote: > >> We literally have hundreds of PALs/GALs to maintain. Nevertheless >> after one >> migrates from ABEL to VHDL or Verilog which tool can target the code >> to a >> 22V10 these days? > > > There is the ipal project at icarus.com that has languished due > to lack of interest. This is support for 22V10 and that ilk of > PLD devices, it generates a JEDEC file ready for the prom programmer. > > What ipal needs is someone to take an interest.Article: 59523
Hi Bill,
Yes, you did ask the million dollar question. Here is a quick run down the
list of things you could do to squeeze performance out of a FPGA
1. Firstly, make sure the coding style is optimized for FPGAs. See Xilinx
documentation for more info.
There are pointers for efficient use of their architecture and dedicated
resources.
2. You could always overconstrain your design but this might not get you
much if you design is 80%+ utilized.
3. If you really need to get in there and meet timing then you could try the
new FPGA physical synthesis tool from Mentor Graphics. For more info, go to
http://www.mentor.com/precisionphysical/
Anil
"Bill Diehls" <billabloke@yahoo.com> wrote in message
news:aus6kvggsip6vhhgce8tsnktp8ev43dmcb@4ax.com...
> Hi all,
> I've been working with the Xilinx Webpack on FPGA designs for a few
> months with good success. A recent design is approaching full device
> utilization and parts of my design are breaking because they no longer
> meet timing constraints.
>
> Being a newbie, I suspect that some of the layout tools and timing
> constraint managers need to be employed to tweak my design back into
> shape, but I'm having trouble figuring out how to use these. I'm
> wondering if there is some good documentation out there for how to do
> this, namely with Xilinx -- or better yet, a book of some sort (?)
>
> I can find lots of information of HDLs for synthesis, but no
> information on how to effectively squeeze performance out of an
> already synthesized design. Maybe this is the million dollar
> question... Any help would be greatly appreciated!
>
> Best regards,
> Bill Diehls
Article: 59524On Wed, 20 Aug 2003 17:18:14 -0700, Stephen Williams <spamtrap@icarus.com> wrote: > >You can't buy new computers that can run old Windows/DOS. The situation >with Solaris/SPARC is a bit better, I suspect, as new systems have a >better chance of running old software there. Well, you can run old Windows/DOS if you add VMWare. I don't know of any equivalent for Solaris/SPARC. >Doesn't it seem plausible that the hopelessly obsolete stuff can be >"freed" (remove dongle checking and license managers) and offered for >free download? I'm sure people like Joe would love to help themselves >and leave you alone with the old stuff if given half a chance. I'll second this, since there is still the issue of magic license numbers and dongles with the old software. Philip Philip Freidin Fliptronics
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