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On Sat, 03 Nov 2012 18:14:22 -0700, mehdi bousfiha wrote: > Hi everyone, i'm realy excited about starting my first project in VHDl > programming, by using FPGA card, my project is about monitoring cameras, > and i didn't find any information about it, basiclly i'm realy confused > about starting this project without any guides or information sources, > it's my first step trought materials and FPGA card, except some basic > tranings on it, i hope someone will help me to get what i need. > > Thank you in advance. If you are more interested in the algorithm than the FPGA-ness of the thing this may be far easier to do on a good fast PC, particularly if you can find an image processing tool kit. The FPGA work just to get video into and out of the FPGA is not trivial, but it pales beside the work to do the motion detection -- and modern PCs are set up to do that sort of image processing, in an environment that's easier to code than inside an FPGA. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.comArticle: 154476
Hi, For a filter implementation in FPGA/ASIC, there are two efficient architect= ures for the MAC. One is distributed arithmetic, while the other is serial-= parallel multiplication based. I know that DA normally is for one of the mu= ltiplicant is constant. The serial-parallel mulication has no such requirem= ent. When one of the multiplicant is constant, it can save some logic gates= indeed. Both methods process one bit with one clock cycle. What the differ= ences are for these two architectures? Thanks.Article: 154477
On Sat, 10 Nov 2012 16:48:35 -0800, fl wrote: > Hi, > > For a filter implementation in FPGA/ASIC, there are two efficient > architectures for the MAC. One is distributed arithmetic, while the > other is serial-parallel multiplication based. I know that DA normally > is for one of the multiplicant is constant. The serial-parallel > mulication has no such requirement. When one of the multiplicant is > constant, it can save some logic gates indeed. Both methods process one > bit with one clock cycle. What the differences are for these two > architectures? > > Thanks. Define "efficient". Operations per clock? Number of gates? Shortness of pipeline? Joules per operation? To my knowledge, most FPGAs these days come with built-in, hard-coded MAC units (at least, you can't seem to swing a cat inside a Xilinx FPGA without hitting one). So, by many definitions, using one is "most efficient" if you have such an FPGA. While I freely admit that I don't have the knowledge base to answer your question vis-a-vis ASICs, or FPGAs lacking hard-coded MAC, I strongly suspect that the real answer is that you need to investigate each one, and decide which best matches _your_ idea of "efficient". -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.comArticle: 154478
Tim Wescott wrote: > On Sat, 10 Nov 2012 16:48:35 -0800, fl wrote: > >> Hi, >> >> For a filter implementation in FPGA/ASIC, there are two efficient >> architectures for the MAC. One is distributed arithmetic, while the >> other is serial-parallel multiplication based. I know that DA normally >> is for one of the multiplicant is constant. The serial-parallel >> mulication has no such requirement. When one of the multiplicant is >> constant, it can save some logic gates indeed. Both methods process one >> bit with one clock cycle. What the differences are for these two >> architectures? >> >> Thanks. > > Define "efficient". Operations per clock? Number of gates? Shortness > of pipeline? Joules per operation? > > To my knowledge, most FPGAs these days come with built-in, hard-coded MAC > units (at least, you can't seem to swing a cat inside a Xilinx FPGA > without hitting one). So, by many definitions, using one is "most > efficient" if you have such an FPGA. > > While I freely admit that I don't have the knowledge base to answer your > question vis-a-vis ASICs, or FPGAs lacking hard-coded MAC, I strongly > suspect that the real answer is that you need to investigate each one, > and decide which best matches _your_ idea of "efficient". > All the fun part is done in the magjack anyway. An Ethernet MAC is mostly tedium. -- Les CargillArticle: 154479
On Sun, 11 Nov 2012 17:13:20 -0600, Les Cargill wrote: > Tim Wescott wrote: >> On Sat, 10 Nov 2012 16:48:35 -0800, fl wrote: >> >>> Hi, >>> >>> For a filter implementation in FPGA/ASIC, there are two efficient >>> architectures for the MAC. One is distributed arithmetic, while the >>> other is serial-parallel multiplication based. I know that DA normally >>> is for one of the multiplicant is constant. The serial-parallel >>> mulication has no such requirement. When one of the multiplicant is >>> constant, it can save some logic gates indeed. Both methods process >>> one bit with one clock cycle. What the differences are for these two >>> architectures? >>> >>> Thanks. >> >> Define "efficient". Operations per clock? Number of gates? Shortness >> of pipeline? Joules per operation? >> >> To my knowledge, most FPGAs these days come with built-in, hard-coded >> MAC units (at least, you can't seem to swing a cat inside a Xilinx FPGA >> without hitting one). So, by many definitions, using one is "most >> efficient" if you have such an FPGA. >> >> While I freely admit that I don't have the knowledge base to answer >> your question vis-a-vis ASICs, or FPGAs lacking hard-coded MAC, I >> strongly suspect that the real answer is that you need to investigate >> each one, and decide which best matches _your_ idea of "efficient". >> >> > > All the fun part is done in the magjack anyway. An Ethernet MAC is > mostly tedium. I hope you realize that I meant "multiply and accumulate", not "media access" or whatever MAC means to Ethernet. At any rate, count my leg as pulled. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.comArticle: 154480
Tim Wescott wrote: > On Sun, 11 Nov 2012 17:13:20 -0600, Les Cargill wrote: > >> Tim Wescott wrote: >>> On Sat, 10 Nov 2012 16:48:35 -0800, fl wrote: >>> >>>> Hi, >>>> >>>> For a filter implementation in FPGA/ASIC, there are two efficient >>>> architectures for the MAC. One is distributed arithmetic, while the >>>> other is serial-parallel multiplication based. I know that DA normally >>>> is for one of the multiplicant is constant. The serial-parallel >>>> mulication has no such requirement. When one of the multiplicant is >>>> constant, it can save some logic gates indeed. Both methods process >>>> one bit with one clock cycle. What the differences are for these two >>>> architectures? >>>> >>>> Thanks. >>> >>> Define "efficient". Operations per clock? Number of gates? Shortness >>> of pipeline? Joules per operation? >>> >>> To my knowledge, most FPGAs these days come with built-in, hard-coded >>> MAC units (at least, you can't seem to swing a cat inside a Xilinx FPGA >>> without hitting one). So, by many definitions, using one is "most >>> efficient" if you have such an FPGA. >>> >>> While I freely admit that I don't have the knowledge base to answer >>> your question vis-a-vis ASICs, or FPGAs lacking hard-coded MAC, I >>> strongly suspect that the real answer is that you need to investigate >>> each one, and decide which best matches _your_ idea of "efficient". >>> >>> >> >> All the fun part is done in the magjack anyway. An Ethernet MAC is >> mostly tedium. > > I hope you realize that I meant "multiply and accumulate", not "media > access" or whatever MAC means to Ethernet. At any rate, count my leg as > pulled. > I went halfway through the thread before I realized it *was* a "Multiply and Acucmulate", which was the inspiration for the joke. We're running out of TLAs. -- Les CargillArticle: 154481
Hi, around 2004, there was an effort by ST Micro to enter the FPGA market. In t= his context, ST published a set of open source EDA tools named "GOSPL" on h= ttp://www.gospl.org - the tools were mentioned, e.g., in a thread at http:/= /www.fpgarelated.com/usenet/fpga/show/16814-2.php Unfortunately, the GOSPL website is long gone and archive.org only provides= a few of the pages. I would be interested to have a look at the GOSPL code, so if anyone happen= s to have a copy lying around, I would be happy if you could get in touch w= ith me. Of course, if you have any experience with the tools, I would love = to learn more. Thanks, MichaelArticle: 154482
Hi, we have a very old project where schematic entry was used using the xil= inx foundation 3 software with aldec schematics. New xilinx systems are not= able to read these schematics. Is anybody around who still has this softwa= re lying around or is able to read such schematics (perhaps using a newer A= ldec package?) Would be very very welcome. T. Walstra, university of amsterdamArticle: 154483
Taco Walstra wrote: > Hi, we have a very old project where schematic entry was used using the xilinx foundation 3 software with aldec schematics. New xilinx systems are not able to read these schematics. Is anybody around who still has this software lying around or is able to read such schematics (perhaps using a newer Aldec package?) > Would be very very welcome. > T. Walstra, university of amsterdam I have Foundation 4.1i running under Windows XP. There are no new licenses available for this from Xilinx, however existing licenses still work. What are you trying to accomplish? Do you just need to view the schematics? If so it's possible to make .pdf prints from them. If you need to use the design for updates or to port it to a new architecture, your best hope is to contact Aldec, whose latest products can still read these schematics if I'm not mistaken. Normally I only use Foundation 4.1i to support existing designs that were created ten years ago and run on already obsolete chips. -- GaborArticle: 154484
Op woensdag 14 november 2012 15:26:27 UTC+1 schreef Gabor het volgende: > Taco Walstra wrote: >=20 > > Hi, we have a very old project where schematic entry was used using the= xilinx foundation 3 software with aldec schematics. New xilinx systems are= not able to read these schematics. Is anybody around who still has this so= ftware lying around or is able to read such schematics (perhaps using a new= er Aldec package?) >=20 > > Would be very very welcome. >=20 > > T. Walstra, university of amsterdam >=20 >=20 >=20 > I have Foundation 4.1i running under Windows XP. There are no new >=20 > licenses available for this from Xilinx, however existing licenses >=20 > still work. What are you trying to accomplish? Do you just need >=20 > to view the schematics? If so it's possible to make .pdf prints >=20 > from them. If you need to use the design for updates or to port >=20 > it to a new architecture, your best hope is to contact Aldec, whose >=20 > latest products can still read these schematics if I'm not mistaken. >=20 > Normally I only use Foundation 4.1i to support existing designs >=20 > that were created ten years ago and run on already obsolete chips. >=20 >=20 >=20 > -- Gabor Hi no pdfs are fine for a start! can Are you willing to help with importing= it into foundation and export some pdfs? I can put the files into some dro= pbox and invite you to it. Would be very, very welcome (send me a mail: tac= owalstra with the extension gmail.com . We are really stuck with this, beca= use old foundation is not available anymore. TacoArticle: 154485
Does anyone have a HW-V2000-MLTA Virtex-II Multimedia board as made by Xilinx about ten years ago? I need one right away. Thanks. --Jim email: jbryce@bryce.comArticle: 154486
Hi,
I do not understand the .tcl command, which is issued by Matlab Simulink to run Modelsim in HDL Coder. More specifically, I do not understand the 'after' command below.
After I search some website, I guess 'after' may means after 100 nS. But when it runs, I do not see the 'after' effect. The input and output signals are there as usual. Could you explain that line meaning to me?
................
vsim('tclstart' , ...
{ 'cd hdlsrc_tb', ...
'vlib work', ...
'vcom Hc_stage1.vhd', ...
'vcom Hc_stage2.vhd', ...
'vcom Hc.vhd', ...
'vsimulink work.Hc', ...
'after 100 add wave -height 200 -radix decimal -format analog-step -scale 0.002 -offset 32000 sim:/Hc/filter_in', ...
'after 100 add wave -height 200 -radix decimal -format analog-step -scale 0.002 -offset 32000 sim:/Hc/filter_out ', ...
'after 100 add wave -height 200 -radix decimal -format analog-step -scale 0.002 -offset 32000 sim:/Hc/ce_out ', ...
'catch { wm geometry $vsimPriv(WaveWindows) 521x600+10+10 }', ...
'catch { wave zoomfull }'})
.................
In the Modelsim window, it shows:
,,,,,,,,,,,,
# -- Loading entity hc_stage2
# vsim -foreign {simlinkserver {C:/Program Files/MATLAB/R2011a/toolbox/edalink/extensions/modelsim/windows32/liblfmhdls_tmwvs.dll} } work.Hc
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.hc(rtl)#1
# Loading work.hc_stage1(rtl)#1
# Loading work.hc_stage2(rtl)#1
# Loading C:/Program Files/MATLAB/R2011a/toolbox/edalink/extensions/modelsim/windows32/liblfmhdls_tmwvs.dll
# after#672
# after#675
# after#678
# 1
# 0
# -----------------------------------------
# Running Simulink Cosimulation block.
# Fri Nov 16 2:22e 2012
# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
# Time: 0 ps Iteration: 0 Instance: /hc/u_hc_stage1
# Fri Nov Time 2012
# Simulation halt requested by foreign interface.
.................
The 'after' is followed #672 etc. Does this echo have relationship with the tcl 'after'?
Thanks,
Article: 154487
On 16/11/2012 19:31, fl wrote:
> Hi,
>
> I do not understand the .tcl command, which is issued by Matlab Simulink to run Modelsim in HDL Coder. More specifically, I do not understand the 'after' command below.
>
> After I search some website, I guess 'after' may means after 100 nS. But when it runs, I do not see the 'after' effect. The input and output signals are there as usual. Could you explain that line meaning to me?
It doesn't affect your simulation, it simply delays the "add wave
command". I suspect vsimulink is using sockets and hence they need to
delay the communication between Simulink and Modelsim. You can type the
"after 100 add wave.." in the Modelsim transcript window and see the effect.
I am not sure what the number is after the "after" command, anybody?
Hans.
www.ht-lab.com
> ................
> vsim('tclstart' , ...
> { 'cd hdlsrc_tb', ...
> 'vlib work', ...
> 'vcom Hc_stage1.vhd', ...
> 'vcom Hc_stage2.vhd', ...
> 'vcom Hc.vhd', ...
> 'vsimulink work.Hc', ...
> 'after 100 add wave -height 200 -radix decimal -format analog-step -scale 0.002 -offset 32000 sim:/Hc/filter_in', ...
> 'after 100 add wave -height 200 -radix decimal -format analog-step -scale 0.002 -offset 32000 sim:/Hc/filter_out ', ...
> 'after 100 add wave -height 200 -radix decimal -format analog-step -scale 0.002 -offset 32000 sim:/Hc/ce_out ', ...
> 'catch { wm geometry $vsimPriv(WaveWindows) 521x600+10+10 }', ...
> 'catch { wave zoomfull }'})
> .................
> In the Modelsim window, it shows:
> ,,,,,,,,,,,,
> # -- Loading entity hc_stage2
> # vsim -foreign {simlinkserver {C:/Program Files/MATLAB/R2011a/toolbox/edalink/extensions/modelsim/windows32/liblfmhdls_tmwvs.dll} } work.Hc
> # Loading std.standard
> # Loading ieee.std_logic_1164(body)
> # Loading ieee.numeric_std(body)
> # Loading work.hc(rtl)#1
> # Loading work.hc_stage1(rtl)#1
> # Loading work.hc_stage2(rtl)#1
> # Loading C:/Program Files/MATLAB/R2011a/toolbox/edalink/extensions/modelsim/windows32/liblfmhdls_tmwvs.dll
> # after#672
> # after#675
> # after#678
> # 1
> # 0
> # -----------------------------------------
> # Running Simulink Cosimulation block.
> # Fri Nov 16 2:22e 2012
> # ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
> # Time: 0 ps Iteration: 0 Instance: /hc/u_hc_stage1
> # Fri Nov Time 2012
> # Simulation halt requested by foreign interface.
> .................
> The 'after' is followed #672 etc. Does this echo have relationship with the tcl 'after'?
>
> Thanks,
>
Article: 154488
Hi,
I know some VHDL, but totally new to verilog. Now I am reading a verilog template. I do not know the meaning of the following code:
assign ce_hciccomp_decode = (cur_count == 0 && clk_enable == 1'b1)? 1 :
(cur_count == 2 && clk_enable == 1'b1)? 1 :
(cur_count == 4 && clk_enable == 1'b1)? 1 :
(cur_count == 7 && clk_enable == 1'b1)? 1 :
(cur_count == 10 && clk_enable == 1'b1)? 1 :
(cur_count == 13 && clk_enable == 1'b1)? 1 :
(cur_count == 16 && clk_enable == 1'b1)? 1 :
(cur_count == 18 && clk_enable == 1'b1)? 1 :
(cur_count == 20 && clk_enable == 1'b1)? 1 :
(cur_count == 22 && clk_enable == 1'b1)? 1 :
(cur_count == 24 && clk_enable == 1'b1)? 1 :
(cur_count == 26 && clk_enable == 1'b1)? 1 :
(cur_count == 29 && clk_enable == 1'b1)? 1 :
(cur_count == 32 && clk_enable == 1'b1)? 1 :
(cur_count == 34 && clk_enable == 1'b1)? 1 :
(cur_count == 36 && clk_enable == 1'b1)? 1 :
(cur_count == 38 && clk_enable == 1'b1)? 1 :
(cur_count == 40 && clk_enable == 1'b1)? 1 :
(cur_count == 42 && clk_enable == 1'b1)? 1 :
(cur_count == 45 && clk_enable == 1'b1)? 1 :
(cur_count == 48 && clk_enable == 1'b1)? 1 :
(cur_count == 50 && clk_enable == 1'b1)? 1 :
(cur_count == 52 && clk_enable == 1'b1)? 1 :
(cur_count == 54 && clk_enable == 1'b1)? 1 :
(cur_count == 56 && clk_enable == 1'b1)? 1 :
(cur_count == 58 && clk_enable == 1'b1)? 1 :
(cur_count == 61 && clk_enable == 1'b1)? 1 : 0;
Could you explain it to me?
Thanks.
Article: 154489The assign statement is one of the ways used to implement combinational logic (as opposed to registered logic). The basic syntax of what you have here is: assign out = condition ? true_data : false_data; If condition is true, out gets the value true_data, else it gets the value false_data. So if cur_count is equal to one of the numerical values listed and clk_enable is equal to 1 at the same time, the ce_hciccomp_decode gets 1, else it gets 0. Regards, BobH On 11/17/2012 5:55 PM, fl wrote: > Hi, > > I know some VHDL, but totally new to verilog. Now I am reading a verilog template. > I do not know the meaning of the following code: > > assign ce_hciccomp_decode = (cur_count == 0 && clk_enable == 1'b1)? 1 : > (cur_count == 2 && clk_enable == 1'b1)? 1 : > (cur_count == 4 && clk_enable == 1'b1)? 1 : > (cur_count == 7 && clk_enable == 1'b1)? 1 : > (cur_count == 10 && clk_enable == 1'b1)? 1 : > (cur_count == 13 && clk_enable == 1'b1)? 1 : > (cur_count == 16 && clk_enable == 1'b1)? 1 : > (cur_count == 18 && clk_enable == 1'b1)? 1 : > (cur_count == 20 && clk_enable == 1'b1)? 1 : > (cur_count == 22 && clk_enable == 1'b1)? 1 : > (cur_count == 24 && clk_enable == 1'b1)? 1 : > (cur_count == 26 && clk_enable == 1'b1)? 1 : > (cur_count == 29 && clk_enable == 1'b1)? 1 : > (cur_count == 32 && clk_enable == 1'b1)? 1 : > (cur_count == 34 && clk_enable == 1'b1)? 1 : > (cur_count == 36 && clk_enable == 1'b1)? 1 : > (cur_count == 38 && clk_enable == 1'b1)? 1 : > (cur_count == 40 && clk_enable == 1'b1)? 1 : > (cur_count == 42 && clk_enable == 1'b1)? 1 : > (cur_count == 45 && clk_enable == 1'b1)? 1 : > (cur_count == 48 && clk_enable == 1'b1)? 1 : > (cur_count == 50 && clk_enable == 1'b1)? 1 : > (cur_count == 52 && clk_enable == 1'b1)? 1 : > (cur_count == 54 && clk_enable == 1'b1)? 1 : > (cur_count == 56 && clk_enable == 1'b1)? 1 : > (cur_count == 58 && clk_enable == 1'b1)? 1 : > (cur_count == 61 && clk_enable == 1'b1)? 1 : 0; > > Could you explain it to me? > Thanks. >Article: 154490
fl <rxjwg98@gmail.com> wrote: > I know some VHDL, but totally new to verilog. Now I am > reading a verilog template. I do not know the meaning > of the following code: > assign ce_hciccomp_decode = (cur_count == 0 && clk_enable == 1'b1)? 1 : > (cur_count == 2 && clk_enable == 1'b1)? 1 : > (cur_count == 4 && clk_enable == 1'b1)? 1 : (snip) > Could you explain it to me? It is similar to the conditional operator in C, but in a continuous assignment statement. That said, I don't know why anyone would do it that way. It seems much more obvious to do with || instead. -- glenArticle: 154491
On Sat, 17 Nov 2012 09:05:22 +0000, HT-Lab wrote:
> On 16/11/2012 19:31, fl wrote:
>> Hi,
>>
>> I do not understand the .tcl command, which is issued by Matlab
>> Simulink to run Modelsim in HDL Coder. More specifically, I do not
>> understand the 'after' command below.
>>
>> After I search some website, I guess 'after' may means after 100 nS.
>> But when it runs, I do not see the 'after' effect. The input and output
>> signals are there as usual. Could you explain that line meaning to me?
>
> It doesn't affect your simulation, it simply delays the "add wave
> command". I suspect vsimulink is using sockets and hence they need to
> delay the communication between Simulink and Modelsim. You can type the
> "after 100 add wave.." in the Modelsim transcript window and see the
> effect.
>
> I am not sure what the number is after the "after" command, anybody?
>
> Hans.
> www.ht-lab.com
>
>
>
>
>> ................
>> vsim('tclstart' , ...
>> { 'cd hdlsrc_tb', ...
>> 'vlib work', ...
>> 'vcom Hc_stage1.vhd', ...
>> 'vcom Hc_stage2.vhd', ...
>> 'vcom Hc.vhd', ...
>> 'vsimulink work.Hc', ...
>> 'after 100 add wave -height 200 -radix decimal -format analog-step
>> -scale 0.002 -offset 32000 sim:/Hc/filter_in', ... 'after 100 add
>> wave -height 200 -radix decimal -format analog-step -scale 0.002
>> -offset 32000 sim:/Hc/filter_out ', ...
>> 'after 100 add wave -height 200 -radix decimal -format analog-step
>> -scale 0.002 -offset 32000 sim:/Hc/ce_out ', ... 'catch { wm
>> geometry $vsimPriv(WaveWindows) 521x600+10+10 }', ...
>> 'catch { wave zoomfull }'})
>> .................
>> In the Modelsim window, it shows:
>> ,,,,,,,,,,,,
>> # -- Loading entity hc_stage2 # vsim -foreign {simlinkserver
>> {C:/Program
>> Files/MATLAB/R2011a/toolbox/edalink/extensions/modelsim/windows32/
liblfmhdls_tmwvs.dll}
>> } work.Hc # Loading std.standard # Loading ieee.std_logic_1164(body)
>> # Loading ieee.numeric_std(body)
>> # Loading work.hc(rtl)#1 # Loading work.hc_stage1(rtl)#1 # Loading
>> work.hc_stage2(rtl)#1 # Loading C:/Program
>> Files/MATLAB/R2011a/toolbox/edalink/extensions/modelsim/windows32/
liblfmhdls_tmwvs.dll
>> # after#672 # after#675 # after#678 # 1 # 0 #
>> -----------------------------------------
>> # Running Simulink Cosimulation block.
>> # Fri Nov 16 2:22e 2012 # ** Warning: NUMERIC_STD."=": metavalue
>> detected, returning FALSE # Time: 0 ps Iteration: 0 Instance:
>> /hc/u_hc_stage1 # Fri Nov Time 2012 # Simulation halt requested by
>> foreign interface.
>> .................
>> The 'after' is followed #672 etc. Does this echo have relationship with
>> the tcl 'after'?
http://www.tcl.tk/man/tcl/TclCmd/after.htm
"after ms
Ms must be an integer giving a time in milliseconds."
Regards,
Allan
Article: 154492
On 11/17/2012 7:55 PM, fl wrote:
> Hi,
>
> I know some VHDL, but totally new to verilog. Now I am reading a verilog template. I do not know the meaning of the following code:
>
> assign ce_hciccomp_decode = (cur_count == 0&& clk_enable == 1'b1)? 1 :
> (cur_count == 2&& clk_enable == 1'b1)? 1 :
> (cur_count == 4&& clk_enable == 1'b1)? 1 :
> (cur_count == 7&& clk_enable == 1'b1)? 1 :
> (cur_count == 10&& clk_enable == 1'b1)? 1 :
> (cur_count == 13&& clk_enable == 1'b1)? 1 :
> (cur_count == 16&& clk_enable == 1'b1)? 1 :
> (cur_count == 18&& clk_enable == 1'b1)? 1 :
> (cur_count == 20&& clk_enable == 1'b1)? 1 :
> (cur_count == 22&& clk_enable == 1'b1)? 1 :
> (cur_count == 24&& clk_enable == 1'b1)? 1 :
> (cur_count == 26&& clk_enable == 1'b1)? 1 :
> (cur_count == 29&& clk_enable == 1'b1)? 1 :
> (cur_count == 32&& clk_enable == 1'b1)? 1 :
> (cur_count == 34&& clk_enable == 1'b1)? 1 :
> (cur_count == 36&& clk_enable == 1'b1)? 1 :
> (cur_count == 38&& clk_enable == 1'b1)? 1 :
> (cur_count == 40&& clk_enable == 1'b1)? 1 :
> (cur_count == 42&& clk_enable == 1'b1)? 1 :
> (cur_count == 45&& clk_enable == 1'b1)? 1 :
> (cur_count == 48&& clk_enable == 1'b1)? 1 :
> (cur_count == 50&& clk_enable == 1'b1)? 1 :
> (cur_count == 52&& clk_enable == 1'b1)? 1 :
> (cur_count == 54&& clk_enable == 1'b1)? 1 :
> (cur_count == 56&& clk_enable == 1'b1)? 1 :
> (cur_count == 58&& clk_enable == 1'b1)? 1 :
> (cur_count == 61&& clk_enable == 1'b1)? 1 : 0;
>
> Could you explain it to me?
> Thanks.
This is something like an address compare with an enable. So the output
will be a 1 when any of the cur_count compares match and the clk_enable
is 1.
There are a couple of ways this could have been done with less typing.
The logic is a series of compares and then the clk_enable is really just
one enable to the whole thing. So why not code it similarly? For example,
assign ce_hciccomp_decode = (clk_enable == 0'b1) ? 0 :
(cur_count == 0) ? 1 :
(cur_count == 2) ? 1 :
(cur_count == 4) ? 1 :
(cur_count == 7) ? 1 :
...
(cur_count == 61) ? 1 : 0;
Personally I think this is a lot more clear as well as less typing.
Rick
Article: 154493
rickman <gnuarm@gmail.com> wrote:
> On 11/17/2012 7:55 PM, fl wrote:
>> I know some VHDL, but totally new to verilog. Now I am reading
>> a verilog template. I do not know the meaning of the following code:
(snip)
> This is something like an address compare with an enable. So the output
> will be a 1 when any of the cur_count compares match and the clk_enable
> is 1.
> There are a couple of ways this could have been done with less typing.
> The logic is a series of compares and then the clk_enable is really just
> one enable to the whole thing. So why not code it similarly? For example,
> assign ce_hciccomp_decode = (clk_enable == 0'b1) ? 0 :
> (cur_count == 0) ? 1 :
> (cur_count == 2) ? 1 :
> (cur_count == 4) ? 1 :
> (cur_count == 7) ? 1 :
> ...
> (cur_count == 61) ? 1 : 0;
> Personally I think this is a lot more clear as well as less typing.
But how about instead:
assign ce_hciccomp_decode = (clk_enable == 0'b1) && (
(cur_count == 0) ||
(cur_count == 2) ||
(cur_count == 4) ||
(cur_count == 7) ||
...
(cur_count == 61) );
The conditional operator is nice when you have a value wider than
one bit, or sometimes a more complicated expression, but doesn't
help much (especially in readability) in cases like this.
Have you ever seen C code like:
if(x>0) y=1;
else y=0;
or:
y=(x>0) ? 1:0;
When you could write instead: y=(x>0);?
-- glen
Article: 154494Hi, I'm just starting to learn Verilog/systemverilog and I've been running some of my code through simulators to ensure that it works, but I am looking into acquiring a development board for further testing and learning experience. Assuming I already had a program that I wanted to run (primarily for network purposes if this matters,) what would I use to estimate the amount of required LE's or CLB's in the FPGA in order to execute the code?Article: 154495
Am Montag, 19. November 2012 04:51:15 UTC+1 schrieb Ivan Tolkachev: > Hi, I'm just starting to learn Verilog/systemverilog and I've been running some of my code through simulators to ensure that it works, but I am looking into acquiring a development board for further testing and learning experience. > > > > Assuming I already had a program that I wanted to run (primarily for network purposes if this matters,) what would I use to estimate the amount of required LE's or CLB's in the FPGA in order to execute the code? Hi, an FPGA is not executing code or running programs. It is implementing a logic network. To get an idea about the ammout of hardware elements needed for a specific design description you can simply run the synthesis tool and read the reports. If you are using IP cores you might need to run the whole implementation flow to see the true ressource usage numbers. Have a nice synthesis EilertArticle: 154496
goouse99@gmail.com wrote: > Am Montag, 19. November 2012 04:51:15 UTC+1 schrieb Ivan Tolkachev: >> Hi, I'm just starting to learn Verilog/systemverilog and I've >> been running some of my code through simulators to ensure that >> it works, but I am looking into acquiring a development board >> for further testing and learning experience. >> Assuming I already had a program that I wanted to run (primarily >> for network purposes if this matters,) what would I use to estimate >> the amount of required LE's or CLB's in the FPGA in order to >> execute the code? (snip) > an FPGA is not executing code or running programs. > It is implementing a logic network. Yes, I was about to write the same thing. > To get an idea about the ammout of hardware elements needed for > a specific design description you can simply run the synthesis > tool and read the reports. > If you are using IP cores you might need to run the whole > implementation flow to see the true ressource usage numbers. The easiest way to do IP, though, is to implement a soft processor in the FPGA and then run IP software, in which case you are running programs. -- glenArticle: 154497
glen herrmannsfeldt wrote:
> rickman <gnuarm@gmail.com> wrote:
>> On 11/17/2012 7:55 PM, fl wrote:
>>> I know some VHDL, but totally new to verilog. Now I am reading
>>> a verilog template. I do not know the meaning of the following code:
>
> (snip)
>
>> This is something like an address compare with an enable. So the output
>> will be a 1 when any of the cur_count compares match and the clk_enable
>> is 1.
>
>> There are a couple of ways this could have been done with less typing.
>> The logic is a series of compares and then the clk_enable is really just
>> one enable to the whole thing. So why not code it similarly? For example,
>
>> assign ce_hciccomp_decode = (clk_enable == 0'b1) ? 0 :
>> (cur_count == 0) ? 1 :
>> (cur_count == 2) ? 1 :
>> (cur_count == 4) ? 1 :
>> (cur_count == 7) ? 1 :
>> ...
>> (cur_count == 61) ? 1 : 0;
>
>> Personally I think this is a lot more clear as well as less typing.
>
> But how about instead:
>
> assign ce_hciccomp_decode = (clk_enable == 0'b1) && (
> (cur_count == 0) ||
> (cur_count == 2) ||
> (cur_count == 4) ||
> (cur_count == 7) ||
> ...
> (cur_count == 61) );
>
> The conditional operator is nice when you have a value wider than
> one bit, or sometimes a more complicated expression, but doesn't
> help much (especially in readability) in cases like this.
>
> Have you ever seen C code like:
>
> if(x>0) y=1;
> else y=0;
>
> or:
>
> y=(x>0) ? 1:0;
>
> When you could write instead: y=(x>0);?
>
> -- glen
There's lots of ways to skin a cat...
Whenever I see a huge pile of ? : operators in an assignment, my
first impression is that someone really wanted to use a case
statement, but of course in Verilog that means changing the
wire to a reg and using an always @* process. For those who
started with Verilog before Verilog 2001, the sensitivity list
may have been seen as more work than coding it this way.
How about:
reg ce_hciccomp_decode;
always @*
case (cur_count)
2, 4, 7, 10, 13, 16, 18, 20,
22, 24, 26, 29, 32, 34, 36,
38, 40, 42, 45, 48, 50, 52,
54, 56, 58, 61: ce_hciccomp_decode = clk_enable;
default: ce_hciccomp_decode = 0;
endcase
-- Gabor
Article: 154498On 18/11/2012 11:04, Allan Herriman wrote: > On Sat, 17 Nov 2012 09:05:22 +0000, HT-Lab wrote: > >> On 16/11/2012 19:31, fl wrote: >>> Hi, >>> .. >> >> I am not sure what the number is after the "after" command, anybody? >> >> Hans. >> www.ht-lab.com >> .. > > http://www.tcl.tk/man/tcl/TclCmd/after.htm > > "after ms > Ms must be an integer giving a time in milliseconds." > > Regards, > Allan > Sorry I wasn't clear, I meant the number displayed by Modelsim after the "after" command: For example: after 100 echo "Hello World" # after#1668 # Hello World after 100 echo "Hello World" # after#1677 # Hello World after 100 echo "Hello World" # after#1685 # Hello World Where does 1668,1677 etc come from? It doesn't seem to be related to any of the simstats values. Not important, just curious, Hans www.ht-lab.comArticle: 154499
On Monday, 24 September 2012 12:30:01 UTC-4, Rob Gaddi wrote:
> On Sun, 23 Sep 2012 13:03:13 -0500
>
> "gaurav3110" <3677@embeddedrelated> wrote:
>
>
>
> >
>
> > Hello,
>
> >
>
> >
>
> >
>
> > I am new to Xilinx and bash scripting. I am using Xilinx 13.4. I am trying
>
> > to run implementation(ngdbuild, map, par etc) to create the bit file
>
> > through a bash script, but I am getting an error. Following is the snippet
>
> > of my error :-
>
> >
>
> > Running synthesis...
>
> >
>
> > bash -c "cd synthesis; ./synthesis.sh"
>
> > xst -ifn system_xst.scr -intstyle silent
>
> > Running XST synthesis ...
>
> > PMSPEC -- Overriding Xilinx file
>
> > </tools/Xilinx/13.4/ISE_DS/EDK/virtex5/data/virtex5.acd> with local file
>
> > </tools/Xilinx/13.4/ISE_DS/ISE/virtex5/data/virtex5.acd>
>
> > XST completed
>
> > error status of previous command:0
>
> > => Starting xst: Xst log file is: no_file.syr
>
> > Using xst file - no_file.xst
>
> >
>
>
>
> Yeah, it's looking for some reason for an XST script file called
>
> no_file.xst, and can't find it. The problem is probably in your
>
> system_xst.scr file (which I wouldn't swear up and down is allowed to
>
> have an extension other than .xst)
>
>
>
> I use a Makefile scripted flow for all my Xilinx projects. On the
>
> most recent one I'm working on, my command line call is:
>
> xst -ifn top_level_gen.xst -ofn 28C940A-xst.log
>
>
>
> And this is my top_level_gen.xst:
>
> set -xsthdpdir ./_xst
>
> set -tmpdir ./_xst/tmp
>
> run
>
> -resource_sharing NO
>
> -keep_hierarchy SOFT
>
> -glob_opt allclocknets
>
> -opt_level 2
>
> -opt_mode speed
>
> -rtlview yes
>
> -bufg 0
>
> -ifn 28C940A.prj
>
> -ofn 28C940A
>
> -top top_level
>
> -iobuf YES
>
> -uc synth/28A940.xcf
>
> -p xc3s1500-4-fg456
>
> -generics {REV='A' CODE=28940 STAMP=1347396632}
>
>
>
>
>
> --
>
> Rob Gaddi, Highland Technology -- www.highlandtechnology.com
>
> Email address domain is currently out of order. See above to fix.
Hi Rob,
I am working on my assignment which is to use scripting to invoke all the xilinx tools such as synthesis,Translate,map,Par and bitgen.I am using makefile for my assignment.I have a problem running this command in the terminal.
xst -ifn filename.xst -ofn filename.syr
The error in the terminal reads like this:
make: execvp : xst :permission denied.
Please help me on this as i am new to xilinx.Thanks,
Sathish
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