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"Al Clark" <aclark@danvillesignal.com> wrote in message news:XnsA3168F143979Caclarkdanvillesignal@69.16.179.20... >I am designing my own Altera Cyclone V SoM board. It is not > intended to be a dev board. It will be a function module that > also includes Analog Devices' SHARC DSPs. > > I am working on the JTAG connection strategy. It seems to me > that separate JTAG connections make more sense than chaining > since Quartus may be running separately from the ARM (HPS). > > Unless someone tells me something different, my plan is to use a > pair of 2mm 2x5 headers, one for the FPGA and the other for the > HPS. These would be identical to the Altera pinouts, just > smaller. > > I expect that the board will be running uLinux, probably GCC. > > Here are my questions: > > 1. I know that many of the Altera Cyclone V dev boards use a USB > Blaster 2 circuit. Does anyone sell a USB Blaster 2 download > cable? I have lots of USB Blaster clones already. > > 2. What should I do about the HPS TRST#. It is not supported on > the USB Blaster? > > 3. The HPS Trace connections might be useful but these are > needed for their alternate I/O functions. I am assuming that the > Mictor interface will not be that helpful. > > I would appreciate any other comments or insight. I'd say take a schematic piece from a development kit and copy that. Original USB Blasters are sold from various distributors, however I've used a chinese clone and original one. Basically I see no difference between chinese and original one. P.S. Disable that AVAST advertise.Article: 156551
"Tomas D." <mailsoc_del_spam_@gmail.com> wrote in news:lj699g$td2$1@dont-email.me: > "Al Clark" <aclark@danvillesignal.com> wrote in message > news:XnsA3168F143979Caclarkdanvillesignal@69.16.179.20... >>I am designing my own Altera Cyclone V SoM board. It is not >> intended to be a dev board. It will be a function module >> that also includes Analog Devices' SHARC DSPs. >> >> I am working on the JTAG connection strategy. It seems to >> me that separate JTAG connections make more sense than >> chaining since Quartus may be running separately from the >> ARM (HPS). >> >> Unless someone tells me something different, my plan is to >> use a pair of 2mm 2x5 headers, one for the FPGA and the >> other for the HPS. These would be identical to the Altera >> pinouts, just smaller. >> >> I expect that the board will be running uLinux, probably >> GCC. >> >> Here are my questions: >> >> 1. I know that many of the Altera Cyclone V dev boards use >> a USB Blaster 2 circuit. Does anyone sell a USB Blaster 2 >> download cable? I have lots of USB Blaster clones already. >> >> 2. What should I do about the HPS TRST#. It is not >> supported on the USB Blaster? >> >> 3. The HPS Trace connections might be useful but these are >> needed for their alternate I/O functions. I am assuming >> that the Mictor interface will not be that helpful. >> >> I would appreciate any other comments or insight. > > I'd say take a schematic piece from a development kit and > copy that. Original USB Blasters are sold from various > distributors, however I've used a chinese clone and > original one. Basically I see no difference between chinese > and original one. > > P.S. Disable that AVAST advertise. > Thanks Tomas for your comments. I too have found that the clone USB Blasters are fine. The USB Blaster II uses high speed, not full speed USB. I have also noticed that pin 6 & pin 8 sometimes have alternate functions like warm reset and TRST#. I don't know if these are supported in the USB Blaster II. I have been reviewing a variety of dev kit schematics for ideas. On my design I used a pair of 2x5 2mm headers. I will make an adapter that will optionally allow chaining. I may break out to a mictor header as well as a 2x5 0.100 style Altera header. I just changed an AVAST setting. Hopefully, the AVAST tag disappears with this post. I don't like it either. Al --- This email is free from viruses and malware because avast! Antivirus protection is active. http://www.avast.comArticle: 156552
Al Clark <aclark@danvillesignal.com> wrote: > I too have found that the clone USB Blasters are fine. The USB > Blaster II uses high speed, not full speed USB. I have also > noticed that pin 6 & pin 8 sometimes have alternate functions > like warm reset and TRST#. I don't know if these are supported > in the USB Blaster II. The standard 11Mbps USB Blaster is essentially an FT245 USB-to-parallel converter chip followed by a small CPLD doing parallel to serial conversion. Pins 6 and 8 are extra 'GPIOs' from the FT245 - they get used for doing other non-JTAG modes like Active Serial. They're not needed for standard FPGA programming. The USB2 USB Blaster II uses a Cypress USB microcontroller instead of an FT245. Usually it's integrated onto boards. I've not seen it for sale as a separate device, though there are manuals dated Jan 2014 for it so it must exist. It looks like it's fairly new since it says it's only fully supported in Quartus 14.0 (USB2 support on other boards has existed for the last 2 years or so). Note that some boards have an additional high-speed link for System Console - this requires an extra bus from the FPGA into the Blaster CPLD: it won't work for a standalone JTAG programmer (but you can use System Console over slower JTAG instead). The manual for the standalone Blaster II: http://www.altera.co.uk/literature/ug/ug_usb_blstr_II_cable.pdf shows that it does wire all the pins for Active Serial mode. My guess would be that the 'USB Interface Chip' is the Cypress FX2 microcontroller as there isn't a USB2 version of the FT245. That being so, don't expect clones anytime soon until someone duplicates the software. TheoArticle: 156553
>I'm working on implement the basic ethernet switch on FPGA. But I don't kno= >w how to parse packet when they enter to switch. I have already used ip cor= >e (Ethernet MAC and fifo )to receive and transmit packet. Does any one has = >vhdl code or referene? Thank you > a few free examples in bknpk vhdl --------------------------------------- Posted through http://www.FPGARelated.comArticle: 156554
Hi everyone, I must admit that I'm pretty new to tcl scripting so this error might be plain stupid but I've failed to understand it so far. I have a makefile (taken from the openrisc repo on opencores.org and adapted to my needs) which has a set of rules to control the whole place and route flow, from compilation to bitstream generation. Among these rules there's one to extract timing reports that goes like this: ># Generate reports >$(TCL_SCRIPT_REPORT): > TCL_FILE=$@ $(MAKE) tcl-common > $(Q)echo "run_designer \"Generating timing reports\" \" " >> $@ > $(Q)echo " open_design $$""proj_name.adb " >> $@ > TCL_FILE=$@ $(MAKE) dump-actel-report-project-tcl > $(Q)echo "\"">> $@ The tcl-common provides a set of common parameters to each step of the flow and works fine, while the dump-actel-report-project-tcl looks like this: ># TCL commands to generate timing reports of project >dump-actel-report-project-tcl: > $(Q)echo " report " \\ >> $(TCL_FILE) > $(Q)echo " -type timing " \\ >> $(TCL_FILE) > $(Q)echo " -analysis max " \\ >> $(TCL_FILE) > $(Q)echo " -print_summary yes " \\ >> $(TCL_FILE) > $(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE) > $(Q)echo " -print_paths yes " \\ >> $(TCL_FILE) > $(Q)echo " -max_paths 5 " \\ >> $(TCL_FILE) > $(Q)echo " -max_expanded_paths 1 " \\ >> $(TCL_FILE) > $(Q)echo " -include_user_sets no " \\ >> $(TCL_FILE) > $(Q)echo " -include_pin_to_pin yes " \\ >> $(TCL_FILE) > $(Q)echo " -select_clock_domains no " \\ >> $(TCL_FILE) > $(Q)echo " "$(DESIGN_NAME)"-timing.rpt " >> $(TCL_FILE) > $(Q)echo " report " \\ >> $(TCL_FILE) > $(Q)echo " -type timing_violations " \\ >> $(TCL_FILE) > $(Q)echo " -analysis max " \\ >> $(TCL_FILE) > $(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE) > $(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE) > $(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE) > $(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE) > $(Q)echo " "$(DESIGN_NAME)"-timmaxdly.rpt " >> $(TCL_FILE) > $(Q)echo " report " \\ >> $(TCL_FILE) > $(Q)echo " -type timing_violations " \\ >> $(TCL_FILE) > $(Q)echo " -analysis min " \\ >> $(TCL_FILE) > $(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE) > $(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE) > $(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE) > $(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE) > $(Q)echo " "$(DESIGN_NAME)"-timmindly.rpt " >> $(TCL_FILE) When I run the 'make report' I get the following error at the end: >debian@debian:place_route$ make report >TCL_FILE=report.tcl make tcl-common >make[1]: Entering directory `/home/debian/repo/9123_FOCS_ITA/branches/false-path-study/mbfocs/target/rtax1000s352_1/place_route' >rm -f report.tcl; >echo; echo "\tGenerating "report.tcl; echo > > Generating report.tcl > [skipping unnecessary lines] >Designer: Generating timing reports >Actel Designer Software >Version: 9.1.5.1 >Release: v9.1 SP5 > >Info: The design focs.adb was last modified by software version 9.1.5.1. >Opened an existing design focs.adb. >Wrote timing report to file: focs-timing.rpt > >The Report command succeeded ( 02:20:16 ) >Wrote timing_violations report to file: focs-timmaxdly.rpt > >The Report command succeeded ( 00:00:09 ) >Wrote timing_violations report to file: focs-timmindly.rpt > >The Report command succeeded ( 00:00:09 ) > >The Execute Script command succeeded ( 02:20:35 ) >Design closed. > > while executing >"exec designer SCRIPT:designer.tcl LOGFILE:report.log" > (procedure "run_designer" line 6) > invoked from within >"run_designer "Generating timing reports" " > open_design $proj_name.adb > report \ > -type timing \ > -analysis max \ > -print_summary yes \ > -..." > (file "report.tcl" line 18) >Command exited with non-zero status 1 >real 8703.72 >user 8413.83 >sys 6.62 >make: *** [report] Error 1 Apparently all the timing reports are saved correctly, but the tcl script exits with an error that I'm not able to spot. Any help is appreciated. Al -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 156555
=D0=BF=D1=8F=D1=82=D0=BD=D0=B8=D1=86=D0=B0, 24 =D0=B0=D0=B2=D0=B3=D1=83=D1= =81=D1=82=D0=B0 2012=C2=A0=D0=B3., 0:01:07 UTC+4 =D0=BF=D0=BE=D0=BB=D1=8C= =D0=B7=D0=BE=D0=B2=D0=B0=D1=82=D0=B5=D0=BB=D1=8C General Schvantzkoph =D0= =BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0=BB: > How do you set up search paths in Vivado so that it will find `includes= =20 >=20 > files? XST supported incdir (in the form of the -vlgincdir switch). I=20 >=20 > haven't found an incdir in the Vivado documentation, does anyone know wha= t=20 >=20 > the tcl command is for incdir? I don't know how to do it as a TCL command, but know how to do it from Viva= do GUI: you should press Project Settings, you will be at the General Setti= ngs group. At the bottom line "Language options" you should press "..." but= ton from the right. Then press "..." button at the up-most line "Verilog op= tions" and you will see the "Verilog include files search paths" field. Tha= t's it )Article: 156556
Any one did ethernet interfacing in Xilinx Vertex 5.Article: 156557
Akshay Eldho Jose wrote: > Any one did ethernet interfacing in Xilinx Vertex 5. Yes.Article: 156558
"GaborSzakacs" <gabor@alacron.com> wrote in message news:ljoert$a0u$1@dont-email.me... > Akshay Eldho Jose wrote: >> Any one did ethernet interfacing in Xilinx Vertex 5. > > Yes. I dunned it two.Article: 156559
Hi,
I'm running into a problem with a memory controller design (mid-range FPGA,=
76% utilization) and am wondering if anyone out there has seen synthesis /=
place-n-route options causing a design to fail when programmed onto a boar=
d?
Functional simulation passes all tests, and the RTL has been frozen for a w=
hile, and I am experimenting with different synthesis and place-&-route opt=
ions to see if I can get better area and speed results. My steps are: I cha=
nge a few options, re-compile, program the board and do a few functional te=
sts.
What happens is if I use non-default options for synthesis and/or place-&-r=
oute, the functional hardware read/write tests fail in an erratic way. I've=
narrowed it down to (not 100% sure) possibly synthesis options involving s=
tate-machine encoding, but am wondering if there are flaws in my RTL, const=
raints or design that are causing these.
Here are some questions that I'm trying to get a handle on:
1. Could these problems be due to bugs in my synthesis / place-&-route tool=
?
(Am omitting the vendors here to avoid debates on whose tools are bette=
r but both the synthesis and par tool are versions that are older than the =
latest versions by a couple of software generations).
2. If you have experienced such problems, were they more due to synthesis o=
ptions or to place-&-route ones? In the sense that, if the synthesis tool i=
s causing problems, maybe I can just fiddle with par options instead.
3. Will formal verification or some sort of pre-/post-synthesis or par equi=
valence checking help resolve such problems?
If anyone has seen such issues before, I'd appreciate it if you can share s=
ome of your experiences (and solutions!).
Much appreciated,
Harnhua
Article: 156560Hi, Am Mittwoch, 30. April 2014 09:19:04 UTC+2 schrieb har...@plunify.com: > I'm running into a problem with a memory controller design (mid-range FPG= A, 76% utilization) and am wondering if anyone out there has seen synthesis= / place-n-route options causing a design to fail when programmed onto a bo= ard? At least 95% of such problems are due to wrong handling of clock-domain-cro= ssing (CDC), which I would check first.=20 Usually if a design is proper constraint and static timing analysis is succ= essful, there is no problem in synthesis but in your code. There are a sma= ll number of bugs in synthesis/par/fpga which will affect usually no standa= rd design, assume the affected designs due to tool bugs beeing in small ppm= . Equivalence checking helps in identifying real bugs of synthesis and par to= ols, but more likely will help you identifying that code that synthesis is = allowed to interpret other than you expect. There are several possibilities to write code that simulates well (under c= ertain circumstances) but is not describing the HW you intended to get. When it comes to wrong constraint code (like multicycle constraint or false= -path constraint on critical paths) or wrong handled CDC, you will have no = benefit using equivalence check.=20 regards ThomasArticle: 156561
Thomas Stanka wrote: > Hi, > > Am Mittwoch, 30. April 2014 09:19:04 UTC+2 schrieb har...@plunify.com: >> I'm running into a problem with a memory controller design (mid-range FPGA, 76% utilization) and am wondering if anyone out there has seen synthesis / place-n-route options causing a design to fail when programmed onto a board? > > At least 95% of such problems are due to wrong handling of clock-domain-crossing (CDC), which I would check first. > > Usually if a design is proper constraint and static timing analysis is successful, there is no problem in synthesis but in your code. There are a small number of bugs in synthesis/par/fpga which will affect usually no standard design, assume the affected designs due to tool bugs beeing in small ppm. > > Equivalence checking helps in identifying real bugs of synthesis and par tools, but more likely will help you identifying that code that synthesis is allowed to interpret other than you expect. > > There are several possibilities to write code that simulates well (under certain circumstances) but is not describing the HW you intended to get. > > When it comes to wrong constraint code (like multicycle constraint or false-path constraint on critical paths) or wrong handled CDC, you will have no benefit using equivalence check. > > regards Thomas If it seems that FSM encoding changes the behavior, it's likely that you have a CDC within your state logic, i.e. an asynchronous input to the state machine. Some encodings, especially binary with complete use of all possible states, can survive an event while other encodings, especially one-hot, can end up in a stuck state, like zero-hot, from an event. Changes in placement and routing can cause these problems to show up or get masked, depending on the relative routing delay to multiple loads of the same async signal. -- GaborArticle: 156562
Hi, I think Make assumes that an exit code of 0 means success, and anything else implies failure. That seems to be why there is an error. From your log, it doesn't look like the Tcl script exited with an error. HTH, Harnhua On Monday, 28 April 2014 15:32:38 UTC+8, alb wrote: > Hi everyone, > > > > I must admit that I'm pretty new to tcl scripting so this error might be > > plain stupid but I've failed to understand it so far. > > > > I have a makefile (taken from the openrisc repo on opencores.org and > > adapted to my needs) which has a set of rules to control the whole place > > and route flow, from compilation to bitstream generation. Among these > > rules there's one to extract timing reports that goes like this: > > > > ># Generate reports > > >$(TCL_SCRIPT_REPORT): > > > TCL_FILE=$@ $(MAKE) tcl-common > > > $(Q)echo "run_designer \"Generating timing reports\" \" " >> $@ > > > $(Q)echo " open_design $$""proj_name.adb " >> $@ > > > TCL_FILE=$@ $(MAKE) dump-actel-report-project-tcl > > > $(Q)echo "\"">> $@ > > > > The tcl-common provides a set of common parameters to each step of the > > flow and works fine, while the dump-actel-report-project-tcl looks like > > this: > > > > ># TCL commands to generate timing reports of project > > >dump-actel-report-project-tcl: > > > $(Q)echo " report " \\ >> $(TCL_FILE) > > > $(Q)echo " -type timing " \\ >> $(TCL_FILE) > > > $(Q)echo " -analysis max " \\ >> $(TCL_FILE) > > > $(Q)echo " -print_summary yes " \\ >> $(TCL_FILE) > > > $(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE) > > > $(Q)echo " -print_paths yes " \\ >> $(TCL_FILE) > > > $(Q)echo " -max_paths 5 " \\ >> $(TCL_FILE) > > > $(Q)echo " -max_expanded_paths 1 " \\ >> $(TCL_FILE) > > > $(Q)echo " -include_user_sets no " \\ >> $(TCL_FILE) > > > $(Q)echo " -include_pin_to_pin yes " \\ >> $(TCL_FILE) > > > $(Q)echo " -select_clock_domains no " \\ >> $(TCL_FILE) > > > $(Q)echo " "$(DESIGN_NAME)"-timing.rpt " >> $(TCL_FILE) > > > $(Q)echo " report " \\ >> $(TCL_FILE) > > > $(Q)echo " -type timing_violations " \\ >> $(TCL_FILE) > > > $(Q)echo " -analysis max " \\ >> $(TCL_FILE) > > > $(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE) > > > $(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE) > > > $(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE) > > > $(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE) > > > $(Q)echo " "$(DESIGN_NAME)"-timmaxdly.rpt " >> $(TCL_FILE) > > > $(Q)echo " report " \\ >> $(TCL_FILE) > > > $(Q)echo " -type timing_violations " \\ >> $(TCL_FILE) > > > $(Q)echo " -analysis min " \\ >> $(TCL_FILE) > > > $(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE) > > > $(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE) > > > $(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE) > > > $(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE) > > > $(Q)echo " "$(DESIGN_NAME)"-timmindly.rpt " >> $(TCL_FILE) > > > > > > When I run the 'make report' I get the following error at the end: > > > > >debian@debian:place_route$ make report > > >TCL_FILE=report.tcl make tcl-common > > >make[1]: Entering directory `/home/debian/repo/9123_FOCS_ITA/branches/false-path-study/mbfocs/target/rtax1000s352_1/place_route' > > >rm -f report.tcl; > > >echo; echo "\tGenerating "report.tcl; echo > > > > > > Generating report.tcl > > > > > [skipping unnecessary lines] > > >Designer: Generating timing reports > > >Actel Designer Software > > >Version: 9.1.5.1 > > >Release: v9.1 SP5 > > > > > >Info: The design focs.adb was last modified by software version 9.1.5.1. > > >Opened an existing design focs.adb. > > >Wrote timing report to file: focs-timing.rpt > > > > > >The Report command succeeded ( 02:20:16 ) > > >Wrote timing_violations report to file: focs-timmaxdly.rpt > > > > > >The Report command succeeded ( 00:00:09 ) > > >Wrote timing_violations report to file: focs-timmindly.rpt > > > > > >The Report command succeeded ( 00:00:09 ) > > > > > >The Execute Script command succeeded ( 02:20:35 ) > > >Design closed. > > > > > > while executing > > >"exec designer SCRIPT:designer.tcl LOGFILE:report.log" > > > (procedure "run_designer" line 6) > > > invoked from within > > >"run_designer "Generating timing reports" " > > > open_design $proj_name.adb > > > report \ > > > -type timing \ > > > -analysis max \ > > > -print_summary yes \ > > > -..." > > > (file "report.tcl" line 18) > > >Command exited with non-zero status 1 > > >real 8703.72 > > >user 8413.83 > > >sys 6.62 > > >make: *** [report] Error 1 > > > > Apparently all the timing reports are saved correctly, but the tcl > > script exits with an error that I'm not able to spot. > > > > Any help is appreciated. > > > > Al > > > > -- > > A: Because it messes up the order in which people normally read text. > > Q: Why is top-posting such a bad thing? > > A: Top-posting. > > Q: What is the most annoying thing on usenet and in e-mail?Article: 156563
Hi, I downloaded Lattice's MICO system for windows. It opens up Eclipse, where I can add processor and memory, make bus connections or open an example. But now I'm stuck: It won't generate. There's a "G" button in the toolbar and a "platform tools / run generator" menu entry. Both are grayed out. No idea why - the log is empty and I can't click the button, so there is no error message. Do I need a "Diamond" installation as well? I understood it would work standalone? Cheers Markus --------------------------------------- Posted through http://www.FPGARelated.comArticle: 156564
Problem solved. "Generate" button appeared after Diamond installation and reboot. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 156565
I have dug out an old board with Spartan-II XC2S100 chip and I could use it, if only I could get some documentation for it. It looks exactly like this: https://support.dce.felk.cvut.cz/nms/img/hwzoo/spartan-ii-1.jpg It has "Insight" and Xilinx logos on it and marking "Spartan II Demo Doard" at the lower edge. Board revision is 3.0, which seems to be important. I have managed to find some pdf, but it is missing description for a couple jumpers, so it is probably for earlier revisions. If anyone could post link to some docs, it would be appreciated.Article: 156566
Thank you very much for the pointers, Thomas and Gabor. I'll look into the interfaces and areas where CDC might cause problems. There is already some FIFO circuitry to address clock domain crossing in so= me modules but judging by your comments, I should do an in-depth check. Regards, Harnhua On Wednesday, 30 April 2014 21:42:40 UTC+8, Gabor wrote: > Thomas Stanka wrote: >=20 > > Hi, >=20 > >=20 >=20 > > Am Mittwoch, 30. April 2014 09:19:04 UTC+2 schrieb har...@plunify.com: >=20 > >> I'm running into a problem with a memory controller design (mid-range = FPGA, 76% utilization) and am wondering if anyone out there has seen synthe= sis / place-n-route options causing a design to fail when programmed onto a= board? >=20 > >=20 >=20 > > At least 95% of such problems are due to wrong handling of clock-domain= -crossing (CDC), which I would check first.=20 >=20 > >=20 >=20 > > Usually if a design is proper constraint and static timing analysis is = successful, there is no problem in synthesis but in your code. There are a= small number of bugs in synthesis/par/fpga which will affect usually no st= andard design, assume the affected designs due to tool bugs beeing in small= ppm. >=20 > >=20 >=20 > > Equivalence checking helps in identifying real bugs of synthesis and pa= r tools, but more likely will help you identifying that code that synthesis= is allowed to interpret other than you expect. >=20 > >=20 >=20 > > There are several possibilities to write code that simulates well (und= er certain circumstances) but is not describing the HW you intended to get. >=20 > >=20 >=20 > > When it comes to wrong constraint code (like multicycle constraint or f= alse-path constraint on critical paths) or wrong handled CDC, you will have= no benefit using equivalence check.=20 >=20 > >=20 >=20 > > regards Thomas >=20 >=20 >=20 > If it seems that FSM encoding changes the behavior, it's likely >=20 > that you have a CDC within your state logic, i.e. an asynchronous >=20 > input to the state machine. Some encodings, especially binary with >=20 > complete use of all possible states, can survive an event while >=20 > other encodings, especially one-hot, can end up in a stuck state, >=20 > like zero-hot, from an event. Changes in placement and routing >=20 > can cause these problems to show up or get masked, depending on >=20 > the relative routing delay to multiple loads of the same async >=20 > signal. >=20 >=20 >=20 > --=20 >=20 > GaborArticle: 156567
In article <909f22bd-80b3-4ca6-889b-e0798d7563f0@googlegroups.com>, Brane2 <brankob@avtomatika.com> writes: >I have dug out an old board with Spartan-II XC2S100 chip and >I could use it, if only I could get some documentation for it. How much is your time worth? -- These are my opinions. I hate spam.Article: 156568
Dne petek, 02. maj 2014 18:31:02 UTC je oseba Hal Murray napisala: > In article <909f22bd-80b3-4ca6-889b-e0798d7563f0@googlegroups.com>, > > Brane2 writes: > > >I have dug out an old board with Spartan-II XC2S100 chip and > > >I could use it, if only I could get some documentation for it. > > > > How much is your time worth? At the moment not that much. I need to cobble up some simple interface, but I need to work with TTL so it would be nice to have 5V tolerance. Since it is just one-off and temporary thing, this seems like fastest option, if I get docs. No need to fsck around with PCB design, level converters etc. Just a few wires to and from the boards and that would be it.Article: 156569
On 02/05/2014 00:19, Brane2 wrote: > I have dug out an old board with Spartan-II XC2S100 chip and I could use it, if only I could get some documentation for it. > > It looks exactly like this: > > https://support.dce.felk.cvut.cz/nms/img/hwzoo/spartan-ii-1.jpg > > It has "Insight" and Xilinx logos on it and marking "Spartan II Demo Doard" at the lower edge. Board revision is 3.0, which seems to be important. > > I have managed to find some pdf, but it is missing description for a couple jumpers, so it is probably for earlier revisions. > > > > If anyone could post link to some docs, it would be appreciated. > I can't see any docs for V3. As you say there is a V1.2 version here:- http://embebidos-cidetec.com.mx/profesores/jcrls/doctos/usersguide1_2.pdf (you will have to re-jpoin the URL) which seems a good starting point. It has tables mapping the pin numbers the various peripherals.Article: 156570
Dne petek, 02. maj 2014 19:21:04 UTC je oseba Dave napisala: > which seems a good starting point. It has tables mapping the pin > > numbers the various peripherals. Yes, I planned to do that. But since I could fuck up something around voltage setting jumpers etc and I don't have spare chip at hand, this would mean more cautious work, which means extra time. Also, board hase extra few bits for various programming options, so I thought to try my luck on the net, if anyone has good pdf. I tried at several places, some of which might have it or even a board or two to spare, so I'll put it aside for a few days. I pulled old Xilinx parallel port configuration cable ( Parallel cable IV) from the same heap and it seems open source Linux driver for it is working, so I have made some progress... ;o) Thanks for your time.Article: 156571
I have a Xilinx Platform Cable USB. With Xilinx iMPACT I can use it to program CPLDs. Is there a free alternative (preferably some command-line tool that works on Linux)? PhilippArticle: 156572
On 05/03/2014 10:16, Philipp Klaus Krause wrote: > I have a Xilinx Platform Cable USB. With Xilinx iMPACT I can use it to > program CPLDs. Is there a free alternative (preferably some command-line > tool that works on Linux)? I don't have any Xilinx hardware, so I haven't tested, but perhaps xc3sprog might work? http://xc3sprog.sourceforge.net/ HTH-- Torfinn Ingolfsen, NorwayArticle: 156573
Philipp Klaus Krause <pkk@spth.de> wrote: > I have a Xilinx Platform Cable USB. With Xilinx iMPACT I can use it to > program CPLDs. Is there a free alternative (preferably some command-line > tool that works on Linux)? Look for xc3sprog. Please compile from trunk: svn checkout svn://svn.code.sf.net/p/xc3sprog/code/trunk xc3sprog-code Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 156574
On 5/3/2014 4:16 AM, Philipp Klaus Krause wrote: > I have a Xilinx Platform Cable USB. With Xilinx iMPACT I can use it to > program CPLDs. Is there a free alternative (preferably some command-line > tool that works on Linux)? > > Philipp > Xilinx "Lab Tools" are free, and Impact doesn't even need a license or key. So, I'm not sure why you need a third-party product to use the cable unless you wanted to program non-Xilinx parts. -- Gabor
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