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Threads Starting Sep 1995

1791: 95/09/03: kayvon irani: Need verilog model
1792: 95/09/03: Maya Reuveni: timing constraints in xilinx
    1794: 95/09/04: George Noten: Re: timing constraints in xilinx
1793: 95/09/03: Michael Gschwind: WWW Site about Synthesis for FPGAs
    1819: 95/09/06: Murdo McKissock: Re: WWW Site about Synthesis for FPGAs
        1858: 95/09/11: Murdo McKissock: Re: WWW Site about Synthesis for FPGAs
1795: 95/09/04: Conor McLaughlin Proyecto ERASMUS: Re: Comp.Arch.FPGA Reflector V1 #305
1796: 95/09/04: Felix K.C. CHEN: Altera's Max+Plus2 vhdl output, bad!
    1813: 95/09/06: Jan Decaluwe: Re: Altera's Max+Plus2 vhdl output, bad!
        1873: 95/09/13: <Todd>: UART for Actel FPGA needed
            1900: 95/09/18: <todd>: Kayvon! (was UART for FPGA)
            1955: 95/09/25: eric: Re: UART for Actel FPGA needed
1797: 95/09/04: Satnam Singh: Call for Papers: DCC'96
1801: 95/09/05: muzo: looking for fpga burn and PCB design house in BA
1804: 95/09/05: Sean Murphy: ICCAD-95 Program and Forms Available at http://www.e2w3.com/iccad/
1805: 95/09/05: STUART CLUBB: Re: Xilinx PROMs
1808: 95/09/05: Jim Tompkins: FPGA to masked gate array conversion
    1811: 95/09/05: John Walton: Re: FPGA to masked gate array conversion
        1812: 95/09/05: <davem@hbmltd.demon.co.uk>: Re: FPGA to masked gate array conversion
1809: 95/09/05: Karl Beil: Questionnaire for my Technical Writing class.
1814: 95/09/06: Maya Reuveni: pci board design guide
    1827: 95/09/07: 0000-Admin(0000): Re: pci board design guide
    1854: 95/09/10: Alex Koegel: Re: pci board design guide
    1859: 95/09/11: Michael Ruettger: Re: Re: pci board design guide
1815: 95/09/06: Oded Ilan: SDRAM memory control
    1828: 95/09/07: 0000-Admin(0000): Re: SDRAM memory control
1816: 95/09/06: Jarek Lis: Lattice ispLSI problem
    1852: 95/09/09: <jothi@singnet.com.sg>: Re: Lattice ispLSI problem
1817: 95/09/06: Ingo Cyliax: Xilinx FPGA(XC3000) netlister for Chipmunk/diglog
1818: 95/09/06: Ingo Cyliax: Xilinx FPGA(XC3000) netlister for Chipmunk/diglog
1820: 95/09/06: Adam Krolnik: ABEL language software
1821: 95/09/06: Michael Rickey: Looking for a Chip Supplier
1829: 95/09/07: Mohamad Mohamad: beginner need help with verilog language
1830: 95/09/07: Andre Klindworth: Altera MAX+plusII with Windows '95
1832: 95/09/07: Kevin McCluskey: Re: FPGA to masked gate array conversion
1833: 95/09/07: <course@garnet.berkeley.edu>: Berkeley CVD & ESD courses in Sept/Oct
1834: 95/09/07: John Cooley: Jury Verdict + Test Benches
    1840: 95/09/08: Jason Flood: Re: Jury Verdict + Test Benches
1835: 95/09/07: Mike Diack: WTB:Max2PLUS software
1837: 95/09/07: Sean Murphy: VHDL International (VI) Home Page on-line at http://www.e2w3.com/
1839: 95/09/08: Jared L. Colflesh: looking for a book
1841: 95/09/08: Vasant Hansakul: Girl of the Moment
1842: 95/09/08: Bill Cox: Can someone send me '96 FPGA call for papers?
    1853: 95/09/09: Brad Hutchings: Re: Can someone send me '96 FPGA call for papers?
1843: 95/09/08: Vince Dugar: Aptix Experience?
1844: 95/09/09: Frankie Chung: QuickLogic SpDE 5.0
1845: 95/09/09: Greg Omond: Protel Libs,XC2000,XC3000
1846: 95/09/09: Greg Omond: Protel Libs,XC2000,XC3000
1847: 95/09/09: Greg Omond: Protel Libs,XC2000,XC3000
1848: 95/09/09: Greg Omond: Protel Libs,XC2000,XC3000
1849: 95/09/09: Greg Omond: Protel Libs,XC2000,XC3000
1850: 95/09/09: Greg Omond: Protel Libs,XC2000,XC3000
1851: 95/09/09: Stefan Kamps: Looking for Scan-Path-Insertion-Too
    1861: 95/09/11: 0000-Admin(0000): Re: Looking for Scan-Path-Insertion-Too
        1864: 95/09/11: Steven K. Knapp: Re: Looking for Scan-Path-Insertion-Too
    1862: 95/09/11: 0000-Admin(0000): Re: Looking for Scan-Path-Insertion-Too
1855: 95/09/10: David Svensson: Overview of FPGAs available?
1856: 95/09/11: Rolande Kendal: Q: using FPGA for data compression\decompression
1857: 95/09/11: Rolande Kendal: Q: FPGA used for data compression/decompression
1860: 95/09/11: Dimitris Phoukas: ATMEL WWW site?
    1865: 95/09/12: Scott Evans: Re: ATMEL WWW site?
        1928: 95/09/20: Doug Smith: Re: ATMEL WWW site?
1863: 95/09/11: Steven K. Knapp: CORRECTED PINOUT: XC4010 and XC4013 in 225-Pin Ball Grid (BG225) Package
1866: 95/09/12: Jeffrey M. Arnold: Archive reminder
1867: 95/09/12: <eugen@research.nj.nec.com>: positions available-hardware design
1868: 95/09/12: John Cooley: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    1875: 95/09/13: Jan Decaluwe: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
        1880: 95/09/15: John Cooley: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
            1882: 95/09/15: jos de laender sh144 7461: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                1895: 95/09/16: Jan Decaluwe: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
            1893: 95/09/16: Erik Jessen: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
            1894: 95/09/16: Jan Decaluwe: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                1943: 95/09/22: Robert Tjarnstrom: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                    1951: 95/09/23: Jonathan AH Hogg: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                        1959: 95/09/25: jos de laender sh144 7461: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                    1958: 95/09/25: jos de laender sh144 7461: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                        1964: 95/09/25: Robert Tjarnstrom: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                            1968: 95/09/26: Jonathan AH Hogg: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                1974: 95/09/27: Robert Tjarnstrom: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                    1984: 95/09/28: Jonathan AH Hogg: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                        1993: 95/09/29: Ad Verschueren: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                        2010: 95/10/02: Torben AEgidius Mogensen: Re: REPOST: Design Contest Write-up (
                                        2060: 95/10/08: Jan Decaluwe: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                            2064: 95/10/09: Jonathan AH Hogg: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                    1996: 95/09/29: Torben AEgidius Mogensen: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                    2411: 95/12/01: Chris Burton: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                1986: 95/09/28: Miriam Leeser: Re: Functional Languages for Hardware Description was REPOST: Design Contest Write-up
                                2003: 95/09/30: Bernd Paysan: Re: REPOST: Design Contest Write-up (
                        1969: 95/09/26: Joao Geada: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                        2410: 95/12/01: Chris Burton: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                        2452: 95/12/07: Chris Burton: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                    1981: 95/09/28: Jan Decaluwe: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                        1992: 95/09/29: John Cooley: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                            2102: 95/10/14: Jan Decaluwe: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                        2030: 95/10/04: Robert Tjarnstrom: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                            2031: 95/10/04: Brad Hutchings: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                2046: 95/10/06: Robert Tjarnstrom: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                    2129: 95/10/18: Gord Wait S-MOS Systems Vancouver Design Center: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                            2041: 95/10/05: Mike Seningen: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                            2042: 95/10/05: Joe Buck: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                2047: 95/10/06: Robert Tjarnstrom: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                            2103: 95/10/15: Jan Decaluwe: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                                2123: 95/10/18: Sinbad Wilmot: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
        1888: 95/09/15: John E. Winkler: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
            1897: 95/09/18: Jan Decaluwe: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
            1898: 95/09/18: Jan Decaluwe: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
                1922: 95/09/20: Charles F. Shelor: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1870: 95/09/13: <pac1@waikato.ac.nz>: XC3030 XC1736 "Done still low"
    1876: 95/09/14: Philip Freidin: Re: XC3030 XC1736 "Done still low"
1871: 95/09/13: John Godden: Newbie question about PLDshell
    1874: 95/09/13: Ka-Chung Wong: Re: Newbie question about PLDshell
1872: 95/09/13: Ola Torudbakken: Fast FPGA's?
    1877: 95/09/14: Murdo McKissock: Re: Fast FPGA's?
        1881: 95/09/15: Ola Torudbakken: Re: Fast FPGA's?
            1884: 95/09/15: <randraka@ids.net>: Re: Fast FPGA's?
                1903: 95/09/18: Ka-Chung Wong: Re: Fast FPGA's?
                    1912: 95/09/19: Steven K. Knapp: Re: Fast FPGA's?
                        1915: 95/09/19: David Gesswein: Re: Fast FPGA's? (No XILINX PREP data)
                            1917: 95/09/19: Peter Alfke: Re: Fast FPGA's? (No XILINX PREP data)
                1916: 95/09/19: Michael C. Kim: Re: Fast FPGA's?
                    1919: 95/09/20: Bill Banzhof: Re: Fast FPGA's?
                    1926: 95/09/20: <randraka@ids.net>: Re: Fast FPGA's?
                    1931: 95/09/20: Steven K. Knapp: Re: Fast FPGA's?
            1886: 95/09/15: Steven K. Knapp: Re: Fast FPGA's?
                1890: 95/09/15: Joseph Navarro Hong -FT-: Re: Fast FPGA's?
            1918: 95/09/19: Jonathan Griffitts: Re: Fast FPGA's?
                1927: 95/09/20: Rainer Malzbender: Re: Fast FPGA's?
    1885: 95/09/15: Hakan Pettersson: Re: Fast FPGA's?
1879: 95/09/14: Lyle Kraft: Anyone using Altera 8820A ?
    1925: 95/09/20: Ralph Watson: Re: Anyone using Altera 8820A ?
        1962: 95/09/25: Lyle Kraft: Re: Anyone using Altera 8820A ?
    1949: 95/09/23: Matthew Miller: Re: Anyone using Altera 8820A ?
1883: 95/09/15: Alan Weir: Is there a reprogramable XC17256D available?
    1901: 95/09/18: David Gesswein: Re: Is there a reprogramable XC17256D available?
        1935: 95/09/22: Dan Bartram: Re: Is there a reprogramable XC17256D available?
            1946: 95/09/22: <jothi@singnet.com.sg>: Re: Is there a reprogramable XC17256D available?
    1905: 95/09/18: <jothi@singnet.com.sg>: Re: Is there a reprogramable XC17256D available?
1887: 95/09/15: Bill Cox: Re: Fast FPGA's from 3100?
1889: 95/09/15: <twtmail@twt.co.il>: Why does MAX5000 is getting hot?
    1909: 95/09/19: Ian Baines: Re: Why does MAX5000 is getting hot?
    1945: 95/09/22: Roger Campana: Re: Why does MAX5000 is getting hot?
    1966: 95/09/25: Andrew Wheeler: Re: Why does MAX5000 is getting hot?
1891: 95/09/15: Simon Méthot: ECL fpga
    1910: 95/09/19: Ken Goldman: Re: ECL fpga
    1914: 95/09/19: Rolf Blom: Re: ECL fpga
    1963: 95/09/25: Simon Méthot: Re: ECL fpga
1892: 95/09/15: Steve Trimberger: Design Automation Conference
1896: 95/09/17: <kent@infoserv.com>: Editors that understand VHDL under UNIX
    1933: 95/09/21: Jörgen Gade: Re: Editors that understand VHDL under UNIX
1899: 95/09/18: Maurizio Lippi: palce16v8hd obsolescence
    1942: 95/09/22: <granville@decus.org.nz>: Re: palce16v8hd obsolescence
1902: 95/09/18: <daveau@verdon>: Help needed-how to instantiate Xbloc component with synopsys
    1907: 95/09/19: Yuce Beser: Re: Help needed-how to instantiate Xbloc component with synopsys
        1939: 95/09/22: Michael Gschwind: Re: Help needed-how to instantiate Xbloc component with synopsys
1904: 95/09/19: Yuefang Xiang: Altera and Synopsys Interface
    1911: 95/09/19: Qian Zhang: Re: Altera and Synopsys Interface
        1940: 95/09/22: Michael Gschwind: Re: Altera and Synopsys Interface
    1947: 95/09/22: Richard A Springer: Re: Altera and Synopsys Interface
1906: 95/09/19: Doris Cheng: FAQ?
1908: 95/09/19: John B. McCluskey: Will Protel EDIF output work as input to Neocad?
1913: 95/09/19: Mohammed Khalid: present status of Field Programmable MCMs?
1920: 95/09/20: mccask: Re: QuickLogic SpDE 5.0
1921: 95/09/20: mccask: Re: Fast FPGA's?
1923: 95/09/20: Evagelia Diamantakou: Simulation using XC3000 libraries
    1932: 95/09/21: Yuce Beser: Re: Simulation using XC3000 libraries
1924: 95/09/20: Glenn Brown: Satellite Video Conference: User Interface Strategies '96
1929: 95/09/20: Brian Antao: Custom Integrated Circuits Conference -- Call for Papers
1930: 95/09/20: Doug Smith: DMA design needed for Xilinx FPGA
1934: 95/09/21: Evagelia Diamantakou: Functional simulation of XC3000 libraries
    1938: 95/09/22: Yuce Beser: Re: Functional simulation of XC3000 libraries
1936: 95/09/22: TWColl: Altera FLEX 10K Seminars: 100,000 gates???
1937: 95/09/22: Alexander B. Taubin: Reminder on Async96 Symposium
1941: 95/09/22: Felix K.C. CHEN: LFSR's solution
    1944: 95/09/22: Michael C. Kim: Re: LFSR's solution
1948: 95/09/22: Martin Mason: Reprogrammable 17CXXX devices.
1950: 95/09/23: <Politics@usa.com>: Proposed State & Federal Regulations for the INTERNET!
1952: 95/09/23: Nico Coesel: cheap (free) fpga design software
    1965: 95/09/25: Steven K. Knapp, Xilinx, Inc.: Re: cheap (free) fpga design software
        1997: 95/09/29: Mike Diack: Re: cheap (free) fpga design software
            2011: 95/10/02: Troy R. Pesola: Re: cheap (free) fpga design software
                2014: 95/10/03: Brad Ree: Re: cheap (free) fpga design software (VHDL)
                    2022: 95/10/03: Jeff Hunsinger: Re: cheap (free) fpga design software (VHDL
                        2028: 95/10/04: Andreas Kugel: Re: cheap (free) fpga design software (VHDL
                            2052: 95/10/06: David Mauro: Re: cheap (free) fpga design software (VHDL
1953: 95/09/24: Rolande Kendal: PCMCIA interface written in VHDL needed
1954: 95/09/24: John Cooley: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    1980: 95/09/27: Jan Decaluwe: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1956: 95/09/25: kayvon irani: FPGA for a 20k gates micro-controller
    1973: 95/09/27: Jan Gray: Re: FPGA for a 20k gates micro-controller
        2045: 95/10/06: Philip Freidin: Re: FPGA for a 20k gates micro-controller
1957: 95/09/25: kayvon irani: FFT in FPGAs ?
    2000: 95/09/29: John Noll: Re: FFT in FPGAs ?
        2007: 95/10/01: Ray Andraka: Re: FFT in FPGAs ?
        2049: 95/10/06: Russell Petersen: Re: FFT in FPGAs ?
        2062: 95/10/09: Geoffrey Liersch: Re: FFT in FPGAs ?
1960: 95/09/25: Herman Schmit: PREP benchmarks
    1971: 95/09/27: Trevor Hall: Re: PREP benchmarks
1961: 95/09/25: DCUI: Wanted-Application Engineer
1967: 95/09/26: Terry Bailey: NEW person
    1976: 95/09/27: Michael J. Wirthlin: Re: NEW person
        2039: 95/10/05: Ken Goldman: Re: NEW person
1970: 95/09/26: Mathew J. Lamb: Alliance, FPGA's, VHDL code......
    1972: 95/09/27: Eric Smith: Re: Alliance, FPGA's, VHDL code......
1975: 95/09/27: Steve Swam: Protel Xilinx Libraries
    1982: 95/09/28: Steven K. Knapp, Xilinx, Inc.: Re: Protel Xilinx Libraries
1977: 95/09/28: <granville@decus.org.nz>: Re: FPGA for a 20k gates micro-controller.
    1979: 95/09/27: Ray Andraka: Re: FPGA for a 20k gates micro-controller.
        1983: 95/09/28: Steven K. Knapp, Xilinx, Inc.: Re: FPGA for a 20k gates micro-controller.
            2069: 95/10/10: John Forrest: Re: FPGA for a 20k gates micro-controller.
    1989: 95/09/29: Cahill schmitz Cahill: Re: FPGA for a 20k gates micro-controller.
        2013: 95/10/02: Steven K. Knapp, Xilinx, Inc.: Re: FPGA for a 20k gates micro-controller.
            2024: 95/10/03: Raquette Eric: Re: FPGA for a 20k gates micro-controller.
1978: 95/09/27: David Mauro: XACT <-> Orcad Interface
1985: 95/09/28: NICOLAS TRIBIE: Xilinx Flash FPGA ??
    1991: 95/09/29: Peter Alfke: Re: Xilinx Flash FPGA ??
    1998: 95/09/29: Y. Jason Hou: Re: Xilinx Flash FPGA ??
    2006: 95/10/01: Stan Eker: Re: Xilinx Flash FPGA ??
        2012: 95/10/02: Steven K. Knapp, Xilinx, Inc.: Re: Xilinx Flash FPGA ??
    2009: 95/10/02: John Forrest: Re: Xilinx Flash FPGA ??
1987: 95/09/28: Vincent Rowley: Re: FPGA for a 20k gates micro-controller.
1988: 95/09/28: Brad Ree: Re: FPGA for a 20k gates micro-controller.
1990: 95/09/29: John Cooley: *** NEED HELP ON 'Cadence: The Good, The Bad, and The Ugly' ***
1994: 95/09/29: Martin Radetzki: Altera Sim. with Leapfrog
    2004: 95/09/30: Zeev Yelin: Re: Altera Sim. with Leapfrog
1995: 95/09/29: J.Walliker: Altera EPX880QC132-10 Availability?
1999: 95/09/29: Chelman Wong: AT&T ORCA usable gate count?
    2005: 95/10/01: John B. McCluskey: Re: AT&T ORCA usable gate count?
2001: 95/09/30: Ray Saarela: FlexLogic download cable/schematics for one ?
    2008: 95/10/01: David Van den Bout: Re: FlexLogic download cable/schematics for one ?
    2020: 95/10/03: Ian Baines: Re: FlexLogic download cable/schematics for one ?
2002: 95/09/30: Sea-Hawon Choi: Info needed for courses using FPGA and VHDL


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