Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Authors (O)

o:
    68754: 04/04/16: Document State Machines?
o pere o:
    154011: 12/07/11: Completely puzzled: Strange shift register behaviour
    154013: 12/07/11: Re: Completely puzzled: Strange shift register behaviour
    154016: 12/07/12: Re: Completely puzzled: Strange shift register behaviour
    154017: 12/07/12: Re: Completely puzzled: Strange shift register behaviour
    154019: 12/07/12: Re: Completely puzzled: Strange shift register behaviour
    154023: 12/07/13: Re: Completely puzzled: Strange shift register behaviour
    154025: 12/07/13: Re: Completely puzzled: Strange shift register behaviour
    154455: 12/11/05: Re: Xilinx XC3S400 reproducibility madness
    154694: 12/12/19: FPGA DSP basics: clock enable / new clock
    154696: 12/12/19: Re: FPGA DSP basics: clock enable / new clock
    154699: 12/12/20: Re: FPGA DSP basics: clock enable / new clock
    154990: 13/03/21: Re: Using Quartus II without GUI
    155172: 13/05/22: Re: Development/Experimenter's kits
    155189: 13/05/24: Re: Development/Experimenter's kits
    156473: 14/04/09: Re: on-chip bypass caps
    158605: 16/01/21: Re: Fully preposterous gate arranger
    158724: 16/04/06: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
    159280: 16/09/21: Re: requirement for PC for VHDL design
    159383: 16/10/19: Re: Microsoft's FPGA Translates Wikipedia in less than a Tenth of a
    159524: 16/12/02: Re: Phrasing!
O. Olson:
    124775: 07/10/03: Companies that Manufacture Multi-FPGA Hardware
    124812: 07/10/05: Re: Companies that Manufacture Multi-FPGA Hardware
    132164: 08/05/16: Incorporating FPGAs on PCBs
    132169: 08/05/16: Re: Incorporating FPGAs on PCBs
    132176: 08/05/16: Re: Incorporating FPGAs on PCBs
    132178: 08/05/16: Re: Incorporating FPGAs on PCBs
    132183: 08/05/16: Re: Incorporating FPGAs on PCBs
    132190: 08/05/16: Re: Incorporating FPGAs on PCBs
O.J.K.:
    157236: 14/11/06: Re: practical experience with GPL IP core in commercial product
<o0o0ozd@gmail.com>:
    136340: 08/11/12: clock problem
    136343: 08/11/12: Re: clock problem
    136353: 08/11/12: Re: clock problem
    136354: 08/11/12: Re: clock problem
    136366: 08/11/13: Re: clock problem
oar:
    65257: 04/01/22: Re: OT: liability insurance
OC team:
    18853: 99/11/19: HDL coders wanted
    19253: 99/12/08: press release
OC-team:
    141513: 09/06/26: Re: opencores again with problems?
    141641: 09/07/02: 50 000 registered users at OpenCores.org
    141642: 09/07/02: Sign up for Multimedia SoC project
OCR Bee:
    29735: 01/03/06: Re: School project
Octavian Florea:
    15683: 99/04/08: FPGA testing board
Oded Ilan:
    1697: 95/08/17: high pinout - low logic devices
    1815: 95/09/06: SDRAM memory control
    2089: 95/10/12: Re: Needed: PCI prototyping board, for use testing with FPGA interface
    2191: 95/10/29: Re: AMCC pci kit- problems
<oeiur@565465.com>:
oen_br:
    110019: 06/10/09: FPGA to SRAM port interface
    110029: 06/10/09: Re: FPGA to SRAM port interface
    110050: 06/10/10: Re: FPGA to SRAM port interface
    110067: 06/10/10: Re: FPGA to SRAM port interface
    110068: 06/10/10: Re: FPGA to SRAM port interface
    110069: 06/10/10: Re: FPGA to SRAM port interface
    110073: 06/10/10: Re: FPGA to SRAM port interface
    110113: 06/10/11: Re: FPGA to SRAM port interface
    110115: 06/10/11: Re: FPGA to SRAM port interface
    110150: 06/10/11: Re: FPGA to SRAM port interface
    113537: 06/12/15: Re: Spartan-3A launched
    131501: 08/04/23: Re: FPGA comeback
    137952: 09/02/03: Re: Spartan-6
    138393: 09/02/19: Re: Spartan-6
<oen_no_spam@yahoo.com.br>:
    86377: 05/06/27: Re: Spartan-3e order of availability?
    86538: 05/06/29: Re: Spartan-3e order of availability?
    86765: 05/07/06: Re: Spartan-3e order of availability?
    86966: 05/07/11: Re: Spartan-3e order of availability?
    87827: 05/08/02: Re: Sparan S3E availability update
    87854: 05/08/02: Re: Sparan S3E availability update
    87984: 05/08/04: Re: Sparan S3E availability update
    88127: 05/08/10: Welcome back Mr. Knapp
    88397: 05/08/17: Re: Antti's last comp.arch.fpga posting
    99785: 06/03/29: Stratum4E holdover
    99813: 06/03/29: Re: Stratum4E holdover
    99853: 06/03/30: Re: Stratum4E holdover
    99872: 06/03/30: Re: Stratum4E holdover
    99944: 06/03/31: Spartan3E Phase-Shifter
    100077: 06/04/03: Re: Spartan3E Phase-Shifter
officerpeabody@yahoo.com:
Ogah:
    46005: 02/08/14: Testing the X2S_USB Spartan 2 board
Oggie:
    51221: 03/01/07: Re: asynchronous inputs
ogrenci:
    125655: 07/10/31: ERROR:Simulator:222 - Generated C++ compilation was unsuccessful
<oguzyilmaz@gmail.com>:
    154857: 13/01/19: Re: full tcp offload solution with tcp session setup/teardown support
<oguzyilmazlist@gmail.com>:
    154855: 13/01/19: full tcp offload solution with tcp session setup/teardown support
    154862: 13/01/20: Re: full tcp offload solution with tcp session setup/teardown support
Oh In Hee:
    7610: 97/09/27: vme vs compact pci
Oh Sheau Pyng:
    18470: 99/10/26: Pc system requirment for Foundation Series
    19359: 99/12/16: Virtex boards
    19390: 99/12/18: Virtex boards
    19936: 00/01/19: Need advice on timing problem
    19950: 00/01/20: Need advice on timing problem
    27614: 00/11/30: how to constaint a design without inserting pad?
<ohtyxd@britshit.org>:
Oil4war:
    76917: 04/12/15: Re: Pal programming
<oipugliufed@8uihsdrfsa.com>:
    17060: 99/06/28: Adults Only! 46829
<oivan@my-deja.com>:
    24719: 00/08/17: Clock recovery in FPGA
    24755: 00/08/17: Re: Clock recovery in FPGA
    24797: 00/08/18: Re: multiplying DLL in Virtex
<oivanov@westell.com>:
    5395: 97/02/13: [Q].FIFO in FPGA XILINX
    7331: 97/08/27: FIFO in Altera
Okashii:
    92259: 05/11/24: XST :division and mod in vhdl
    92297: 05/11/25: Re: XST :division and mod in vhdl
    92298: 05/11/25: Re: XST :division and mod in vhdl
    92548: 05/12/01: Any fpga tutorials online?
<okmbsi@faqlist.be>:
    14588: 99/02/05: _____FAQ for this NEWSGROUP_____ 2269
oksid:
    145425: 10/02/09: Re: using an FPGA to emulate a vintage computer
<oktem@su.sabanciuniv.edu>:
    138676: 09/03/04: writing current date to a register
    138695: 09/03/05: Re: writing current date to a register
    140074: 09/04/27: hard macro basic clock reset question
OL:
    111986: 06/11/14: Re: problem about license of Modelsim in Altera quartus webpack
Ola Torudbakken:
    1872: 95/09/13: Fast FPGA's?
    1881: 95/09/15: Re: Fast FPGA's?
ola@mail.gr:
    125357: 07/10/23: XILINX CDs
Olaf:
    17121: 99/07/01: Re: Heat disspa
    18025: 99/09/24: Re: Fineline BGAs
    19170: 99/12/03: Re: Connection of light diode and FPGA
    19646: 00/01/06: Re: BGA sockets and Virtex
    120543: 07/06/09: linux and USB JTAG at Spartan 3e starter
    120551: 07/06/09: xilinx windrv install on linux
    120552: 07/06/09: Re: linux and USB JTAG at Spartan 3e starter
    120553: 07/06/09: Re: linux and USB JTAG at Spartan 3e starter
    120558: 07/06/10: Re: linux and USB JTAG at Spartan 3e starter
    129734: 08/03/04: PARAMETER C_SPLIT error
    129735: 08/03/04: Re: PARAMETER C_SPLIT error
    129737: 08/03/04: Re: PARAMETER C_SPLIT error
    129770: 08/03/05: EDK 9.2 MicroBlaze Tutorial and SDRAM TestApp_memory
Olaf Birkeland:
    16299: 99/05/14: Re: Fancy Dram problem
    22959: 00/06/06: Re: SPICE help
    22996: 00/06/08: Re: XCV vs. XCV-E ?
    23559: 00/06/30: Re: PCI with Xilinx controller
    24969: 00/08/23: Re: Permanently programming FPGAs
    25021: 00/08/24: Re: Permanently programming FPGAs
    25338: 00/09/07: Re: bga->dip?
    26909: 00/11/03: Re: Need a PCB speaker driven by XCV100
    27414: 00/11/21: Re: Xilinx and Tri state I/O
    34191: 01/08/16: Re: Slowing PCI for FPGA
Olaf Kaluza:
    134932: 08/09/07: Re: Spartan 3E evaluation board manufacturers
    134936: 08/09/07: Re: Spartan 3E evaluation board manufacturers
    134956: 08/09/08: Re: Spartan 3E evaluation board manufacturers
    142458: 09/08/12: Re: Spartan-6 Boards - Your Wish List
Olaf Petzold:
    92246: 05/11/24: Re: Memory in VHDL
    92289: 05/11/25: Convert Enumeration to Integer
    92292: 05/11/25: subtractor
    92315: 05/11/27: Re: subtractor
    92321: 05/11/27: Re: subtractor
    92322: 05/11/27: Re: subtractor
    92411: 05/11/29: Re: subtractor
    95305: 06/01/22: post-fit simulation failed
    95306: 06/01/22: Re: post-fit simulation failed
    95309: 06/01/22: Re: post-fit simulation failed
Olaf Reichenbaecher:
    33640: 01/08/01: May I connect two pins to the same net?
    34211: 01/08/16: Xilinx Floorplanner in batch mode?
Olafur Gunnlaugsson:
    145454: 10/02/10: Re: using an FPGA to emulate a vintage computer
    145473: 10/02/11: Re: using an FPGA to emulate a vintage computer
Olav Gundersen:
    18756: 99/11/12: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
Olav Woelfelschneider:
    6804: 97/06/29: Re: Smart Card Design and Interface. How?
Old Radio Days:
    49297: 02/11/08: Online pinouts of glue chips
old_guy:
    78116: 05/01/25: Re: Don't touch in altera maxplus 2
    78244: 05/01/27: Re: Don't touch in altera maxplus 2
Ole:
    47840: 02/10/05: Re: Low power design
Ole Christian Midtbust:
    6227: 97/04/30: Laptop
    6451: 97/05/25: NMEA and HW connection
Oleg:
    64857: 04/01/15: Re: Quantization levels of received symbol for viterbi decoder
    68461: 04/04/05: Designing MUX with tri sate bus in xilinx virtex II FPGA
    68700: 04/04/14: System Generator HDL co-simulatin problem
    68733: 04/04/15: Re: System Generator HDL co-simulatin problem
    71013: 04/07/05: FPGA/ASIC design comparaison
    71017: 04/07/05: ISE
    71054: 04/07/06: RAMB16_Sx instantiation template
    71067: 04/07/07: Re: RAMB16_Sx instantiation template
    71069: 04/07/07: Urgent : Xilinx PACE question
    71116: 04/07/08: Re: Urgent : Xilinx PACE question
Oleg Voitiuk:
    7325: 97/08/27: This my test!
oleg afanasjev:
    44827: 02/07/02: synthesis using FPGA Express from Aldec 4.2 fails
Oleg O.:
    102129: 06/05/10: Re: Opteron HT coprocessors
Oleg Sheynin:
    2360: 95/11/22: Xilinx Viewlogic simulation
    2373: 95/11/24: Re: Xilinx Viewlogic simulation
    3930: 96/08/21: Re: XACT6.0:prosim and routed design
    5681: 97/03/06: Waveform files from Workview into WVOffice
Oleg Slonsky:
    70613: 04/06/22: JTAG - XC2S200E-PQ208
<oleg@writeme.com>:
    22596: 00/05/12: Cheap Quicklogic parts....
Oleksandr Redchuk:
    55509: 03/05/11: Re: Altera Flex EPF81188A
Oli Charlesworth:
    117321: 07/03/28: Re: How is it possible to design a convolutional interleaver with sequential memory writes?
<olive_dominguez@yahoo.fr>:
    112032: 06/11/15: Impedance I/O SPARTAN3 board
    112045: 06/11/15: Re: Impedance I/O SPARTAN3 board
    112153: 06/11/17: FPGA board
    114860: 07/01/25: EDK-Modelsim XE
    117412: 07/03/30: Xilkernel-EDK8.2
oliver:
    73388: 04/09/21: Multiple Clockdomains in Handel-C
Oliver Amft:
    30884: 01/05/02: Re: failed to configure virtex
    32931: 01/07/12: Re: Downloading file to Xilinx (Vertex_E) FPGA.
Oliver Bartels:
    6278: 97/05/08: Re: Advantages/disadvantages between CMOS/BiCMOS
Oliver Diessel:
    5363: 97/02/11: XC6200 config resources
    16419: 99/05/21: Call for Papers: RAW 2000 (Reconfigurable Architectures Workshop)
    22011: 00/04/12: CFP: PART2000 - Seventh Australasian Parallel and Real-Time Systems
    35172: 01/09/25: RAW 2002 Call for Papers
Oliver Faust:
    139448: 09/03/30: Fiber optics protocols for mid range speed
    139451: 09/03/30: Re: Fiber optics protocols for mid range speed
    139468: 09/03/31: Re: Fiber optics protocols for mid range speed
    139473: 09/03/31: Re: Fiber optics protocols for mid range speed
Oliver Huang:
    19331: 99/12/14: How to probe internal signals of P&R-ed Xilinx device with Verilog timing simulation ?
Oliver King-Smith:
    21582: 00/03/26: FPGA chip for PalmPilot
Oliver Maischberger:
    22836: 00/05/26: Q:Itegration of FPGA functionality in an ASIC?
Oliver Mattos:
    149329: 10/10/17: Combined Microprocessor and FPGA
    149336: 10/10/17: Re: Combined Microprocessor and FPGA
    149337: 10/10/17: Re: Combined Microprocessor and FPGA
    149507: 10/11/01: Re: Combined Microprocessor and FPGA
Oliver Meike:
    35435: 01/10/04: Converting VHDL into state machine with FPGA advantage 5.1
Oliver Paray:
    3666: 96/07/10: Re: emulation software
Oliver Weber:
    3624: 96/07/04: Re: FSM encoding in VHDL with MAX+plusII
Oliver Wong:
    104820: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
    104853: 06/07/07: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
Oliver WOOD:
    7902: 97/10/28: Modeling using Altera devices
    7966: 97/11/04: Vital files generated by maxplus2
<oliver.amft@ch.abb.com.nospam>:
    30879: 01/05/02: FPGA SPROM boot problem
oliver.hofherr@googlemail.com:
    139842: 09/04/16: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2 (Virtex
    141422: 09/06/24: How do you use multiple bitfiles with different designs on the same
<Oliver.W@gmx.ch>:
    22300: 00/05/04: Re: Vital glitch
olivier:
    32061: 01/06/12: Force routing on an Apex
Olivier Galibert:
    9483: 98/03/17: Re: Xilinx could gaurd its secrets better (Re: Strange Xilinx question?)
    9770: 98/04/04: Re: XactStep6 - The cure for a dongle
olivier GALLAY:
    12800: 98/10/30: Re: Xilinx mode pins.
Olivier Hebert:
    13443: 98/12/03: Xilinx FPGA configuration problems... Help!
    13444: 98/12/03: Xilinx FPGA configuration problems... Help!
    13469: 98/12/04: Re: Xilinx FPGA configuration problems... Help!
    13445: 98/12/03: Xilinx FPGA configuration problems... Help!
olivier JEAN:
    34695: 01/09/04: SEARCH a model core DAC
    34696: 01/09/04: Re: fpga dev
    34777: 01/09/07: To mix frequency with a FPGA
    36024: 01/10/26: Problem with IOBUF in WEBPACK 4.1
    37332: 01/12/07: Re: where is designed FPGA for apple II computer...?
    43914: 02/06/06: How design a 10 bits counter by using an XILINX FPGA
Olivier MALLINGER:
    30944: 01/05/04: Use of record type in a hierarchical architecture
Olivier R:
    27798: 00/12/08: Re: Altera free development tools
Olivier Regnault:
    27254: 00/11/16: Re: VHDL & Spartan: How to power-up a Register to '1' ?
    27304: 00/11/17: Re: COREGEN ROM in VHDL... How do I use it?
    27427: 00/11/21: Re: Help :asynchronous Reset has no effect
    27428: 00/11/21: Re: Resetting Flip-Flops in Virtex
    27666: 00/12/01: Re: Xilinx's www down again?
Olivier REGNAULT:
    27631: 00/11/30: Re: FPGA Express warning
    27795: 00/12/08: Re: FPGA starter kit
Olivier Scalbert:
    93604: 05/12/26: Spartan-3 Starter Kit newbie question
    93606: 05/12/26: Re: Spartan-3 Starter Kit newbie question
    114052: 07/01/03: newbie needs help
    114078: 07/01/04: Re: newbie needs help
    114104: 07/01/04: Re: newbie needs help
    114105: 07/01/04: Re: newbie needs help
Olivier Wagner:
    11343: 98/08/05: http://myweb.vector.ch/olwagner/
olivier.regnaultavnet.com:
    27632: 00/11/30: Re: Xilinx Coolrunner going on last time buy?
Olli:
    105608: 06/07/27: EDK : *.bit and *.elf Files
    105610: 06/07/27: Re: EDK : *.bit and *.elf Files
    105663: 06/07/28: Re: EDK : *.bit and *.elf Files
    105737: 06/07/30: Re: EDK : *.bit and *.elf Files
olliH:
    137571: 09/01/22: Re: converting floating point number to integer and vice versa
    139860: 09/04/17: Re: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2
    140064: 09/04/27: Re: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2
    143363: 09/10/06: fpga custom cpu VS. cuda
<olson_ord@yahoo.it>:
    112124: 06/11/16: Synthesis size of Circuits?
    112214: 06/11/17: Re: Synthesis size of Circuits?
    112215: 06/11/17: Re: Synthesis size of Circuits?
    112395: 06/11/21: Re: Synthesis size of Circuits?
    112396: 06/11/21: Re: Synthesis size of Circuits?
    112472: 06/11/22: Division of a (rather large) Gate level Combinational Design
    112487: 06/11/23: Re: Division of a (rather large) Gate level Combinational Design
    112494: 06/11/23: Re: Division of a (rather large) Gate level Combinational Design
Om:
    62113: 03/10/19: USB 2.0 controller using ISP1581 device
    62158: 03/10/20: Re: USB 2.0 controller using ISP1581 device
omair50:
    142267: 09/07/31: ERROR:Pack:679 - Unable to obey design constraints
Omar Hammami:
    2190: 95/10/29: small superscalar design ?
    14304: 99/01/25: CFP ICPP99-PERH99
Omer Osman:
    144731: 09/12/29: EPCS vs SPI Flash
<omid@rocketmail.com>:
    18512: 99/10/28: Duty-cycle change in Virtex
Ondrej Zoubek:
    55415: 03/05/07: Problem erasing Coolrunner
    58835: 03/08/02: NOREDUCE attribute
One Day & A Knight:
    63780: 03/12/04: Synchronization between CPU-clock and FPGA clock.
    63818: 03/12/05: Re: Synchronization between CPU-clock and FPGA clock.
    63987: 03/12/11: Re: Maximum bus speed of APB.
    64264: 03/12/23: Net name convention for Xilinx UCF files.
    64280: 03/12/24: Re: Net name convention for Xilinx UCF files.
    64333: 03/12/29: This design contains an RPM macro bm_0 which is to be automatically placed, but it contains TBUF elelements that are not allowed during automatic placement of RPMs?
    64352: 03/12/30: Re: This design contains an RPM macro bm_0 which is to be automaticallyplaced, but it contains TBUF elelements that are not allowed during automaticplacement of RPMs?
onecard:
    128151: 08/01/16: help definining a secure SMARTCARD CHIP BASED, USB UNIT
onenanometer@gmail.com:
    90564: 05/10/16: Re: Xilinx ML403 Board Beginner
    123390: 07/08/27: Interview Questions
<oner@paris.usc.edu>:
    1099: 95/04/27: How to use XBLOX librariers in VHDL in Synopsys?
OneStone:
    22347: 00/05/05: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22388: 00/05/07: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22402: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22403: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22444: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22478: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22479: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22480: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22481: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22486: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    24657: 00/08/16: Re: Non-disclosures in job interviews
    24733: 00/08/17: Re: Non-disclosures in job interviews
oneweek:
    103820: 06/06/12: Re: How to get lowest price for a ModelSim license?
Oniria:
    16599: 99/05/29: SE TI INTERESSA ARCHICAD 6.0,LIHTWAVE 5.6,PHOTOSHOP5.0,AUTOCAD 14ita,etc ,postami.
onkars:
    147232: 10/04/19: Xilinx Pipelined/Streaming FFT Architecure?
    147240: 10/04/20: Re: Xilinx Pipelined/Streaming FFT Architecure?
    147244: 10/04/20: Re: Xilinx Pipelined/Streaming FFT Architecure?
    147264: 10/04/21: Re: Xilinx Pipelined/Streaming FFT Architecure?
    147275: 10/04/21: Tutorial for C based bit-accurate hardware modeling ?
    147609: 10/05/06: Xilinx FFT core -- Is varying precision through the core possible?
    147611: 10/05/06: Re: Xilinx FFT core -- Is varying precision through the core possible?
    147874: 10/05/28: Estimating resource utilization of cores (from Xilinx CoreGen)
    147890: 10/05/30: Re: Estimating resource utilization of cores (from Xilinx CoreGen)
    148188: 10/06/25: how to know that SRL16 was infered on xilinx?
    148454: 10/07/24: Weighted Round Robin Arbiter
    148455: 10/07/24: Re: Weighted Round Robin Arbiter
    150138: 10/12/16: report_timing -from -to
onlinebooks:
Only_me:
    66848: 04/02/27: Surplus cplds
onlyspam@online.ms:
    112904: 06/11/30: LVDS output pins of Altera Cyclone II
    112940: 06/12/01: Re: LVDS output pins of Altera Cyclone II
    112960: 06/12/02: Re: LVDS output pins of Altera Cyclone II
    113219: 06/12/08: Re: LVDS output pins of Altera Cyclone II
Onmate:
    132: 94/08/25: Re: QuickLogic (was Re: FPGA Hobbyist...)
    139: 94/08/30: Re: QuickLogic (was Re: FPGA Hobbyist...)
    153: 94/09/02: Re: QuickLogic (was Re: FPGA Hobbyist...)
onmate:
    460: 94/11/24: Re: Help: Seeking Your Opinion of EDN Article
    461: 94/11/24: QuickLogic Design V5.0 (QuickWorks)
Ono noriaki:
    19373: 99/12/17: Question:Logic change with Quartus
<onwuka.arisa@gmail.com>:
    135365: 08/09/28: Difference between PLD and General purpose CPU`
onyx:
    71187: 04/07/11: Xilinx Student Edition 4.2i
    73290: 04/09/17: Atmel DK2 kit
<onyx49@juno.com>:
    88025: 05/08/06: Re: Good intro books on OFDM?
    89477: 05/09/15: Re: Looking for a DIgital Systems book with JPEG example code
    100634: 06/04/13: Re: ARM Emulator
<onyxx@netway.at>:
    11836: 98/09/12: solution 2000......year 2000 crisis
oopere:
    101080: 06/04/25: Simulated Quartus II delays are much greater than measured
    101090: 06/04/25: Re: Simulated Quartus II delays are much greater than measured
    101091: 06/04/25: Re: Simulated Quartus II delays are much greater than measured
    105330: 06/07/20: clock hold time problems reported in quartus II
    105381: 06/07/21: Re: clock hold time problems reported in quartus II
    105382: 06/07/21: Re: clock hold time problems reported in quartus II
    111699: 06/11/08: Non deterministic behaviour in quartus II ?
    111702: 06/11/08: Re: Non deterministic behaviour in quartus II ?
    111733: 06/11/09: Re: Non deterministic behaviour in quartus II ?
    111734: 06/11/09: Re: Non deterministic behaviour in quartus II ?
    111764: 06/11/09: Re: Non deterministic behaviour in quartus II ?
    111790: 06/11/10: Re: Non deterministic behaviour in quartus II ?
    136637: 08/11/27: Altera ethernetblaster problem
<ooze3d@gmail.com>:
    136875: 08/12/10: Looking for FPGA engineer for HD camera project
    136884: 08/12/10: Re: Looking for FPGA engineer for HD camera project
OP:
    66711: 04/02/25: difference btw H/W & S/W implementations !!
    67019: 04/03/03: Different Finite Field Multipliers!!!
Opal Kelly Incorporated:
    82583: 05/04/14: ANN: USB/FPGA board with programmer's interface
Opende2001:
    34144: 01/08/15: fpga dev
<openmarco@gmail.com>:
    158008: 15/06/25: Re: does anybody use systemc in FPGA flow?
operator jay:
    115318: 07/02/07: Re: question about power dissipation
Ops:
    18371: 99/10/20: Opportunities for HDL specialists NOW
<opworld@worldnet.fr>:
    2797: 96/02/09: Looking for OPAL, PALASM, PLAN
<orachat@imap2.asu.edu>:
    4116: 96/09/12: Implement FPGA multiplier using VHDL synthesis
    5258: 97/02/02: Problem with XACT and Orcad interface
    5624: 97/03/03: Using internal clock of XC4000
Orbit:
    72848: 04/09/05: PDSPs vs FPGAs for DSP
    72853: 04/09/05: Re: PCI Noise
    72858: 04/09/06: Re: PCI Noise
<304830983@098340938.org>:
    18568: 99/11/01: *Latest Inkjetz for Sale*
Orlls:
    38032: 02/01/02: Verilog code
    38115: 02/01/05: simprims_ver/xilinxcorelib_ver /unisims_ver
    38137: 02/01/06: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
<orly.bialer@me.com>:
    155917: 13/10/16: Re: xilinx spi example under linux
orthogonal:
    104576: 06/06/29: Help on simulating ddr controler generated by MIG!!
Os:
    1688: 95/08/16: goodness me
OS:
    3036: 96/03/18: Re: Xact6.o too slow
oscar:
    133480: 08/07/01: Re: chipscope analyzer error
Oscar:
    136819: 08/12/07: Re: Invalid devices when initialising scan chain with Nexys2
    142517: 09/08/14: Initializing BRAM & ISE 10.1
Oscar Almer:
    143945: 09/11/04: Re: problem fpga aera optimization
    143993: 09/11/06: Re: OK Xilinx users, it's time I was let in on the joke...
    144099: 09/11/11: Re: OK Xilinx users, it's time I was let in on the joke...
    144392: 09/12/03: Re: Does Xilinx sync FIFO use dual port memory? Does this affect
    148126: 10/06/22: Re: Asynchronous FIFO in Spartan6
    148697: 10/08/18: Re: Getting started with FPGA
Oscar Calvo:
    1272: 95/05/24: Xiling missing file
Oscar Garnica:
    69951: 04/05/25: Read/Write data from/to SRAM
<oscar.odetti@gmail.com>:
    130480: 08/03/25: EDK9.2 microblaze tutorial
    130560: 08/03/27: Re: EDK9.2 microblaze tutorial
osedax:
    85695: 05/06/14: Re: Somewhat OT - falling behind the times ...
OSFT Inc.:
    28238: 01/01/03: Hardware Eng IV : FPGA/ASIC Design Engineer/Arch, $80 to $110, Ottawa, Large Telecom
    28239: 01/01/03: Hardware Engineer/FPGA's for Ruggedized PC/Driver Design, Excellent $$$, Toronto
    28240: 01/01/03: ASICS Design, VoIP, FPGA, $70k to $100+relocation, Ottawa
    28241: 01/01/03: IC Hardware Design, Telecom company, Ottawa, $70k to $100k+great benefits, relocation
    28242: 01/01/03: Boston/Senior Software engineer FPGA/ Well Funded Start up/100k+++/Hot Data Storage Market
<oshea@mail.uri.edu>:
    131300: 08/04/18: Chipscope is Failing
Oskar Mencer:
    10028: 98/04/22: PAM-Blox version 1.0
Osnet:
    97213: 06/02/18: MontaVista Linux and Virtex-II & 4
<osodipe@eng.ucsd.edu>:
    157007: 14/08/25: Bidirectional Pin FPGA (Parallel ADC)
    157009: 14/08/25: Re: Bidirectional Pin FPGA (Parallel ADC)
    157011: 14/08/26: Re: Bidirectional Pin FPGA (Parallel ADC)
osquillar:
    135128: 08/09/17: SDRAM question
    135141: 08/09/17: Re: SDRAM question
    135142: 08/09/17: Re: SDRAM question
    135224: 08/09/22: Re: SDRAM question
    135240: 08/09/23: Re: SDRAM question
    135282: 08/09/24: Re: SDRAM question
    136592: 08/11/24: opencores can core
osr:
    117819: 07/04/10: Query in Parallel CRC(urgent)
Otomo:
    37873: 01/12/22: Re: Virtex-2 maximum clock speed
Ottavio Campana:
    133525: 08/07/02: connecting fpga to TI emif
Otto Baumann:
    6024: 97/04/06: In search of free/low cost PAL/PEEL design sw
Otto Bruggeman:
    15320: 99/03/18: Re: How can I improve an adder?
Otto's CAD Auction:
    3886: 96/08/14: Re: Technical Job posting ( and ads) not related to the newsgroup.
Ottwald Holler:
    23807: 00/07/10: XC2018 development system xact5 or xact6 sale?
    23877: 00/07/13: Re: XC2018 development system xact5 or xact6 sale?
Ouadid:
    79429: 05/02/18: Any suggestion for an IP project
ouadid abdelkarim:
    57020: 03/06/20: How to trace the FPGA signals without a logical analyzer?
    57932: 03/07/09: Please help in soft-decision decoding of convolutionel codes
<ouadid@iquebec.com>:
    66984: 04/03/03: Any help about this demo board
    67101: 04/03/05: A newbie question
    67114: 04/03/05: Re: A newbie question
    67116: 04/03/05: Software for synthesis
ouadrani:
    151503: 11/04/14: ML505 NOT RECOGNIZED BY THE PC THROUGH PCI EXPRESS
ouj:
    74097: 04/10/03: Uploading data to the DDR memory on the ML300 board
    78341: 05/01/29: Re: i need xilinx edk
<outo@Wfsdfsdf.com>:
    17061: 99/06/28: Fresh Young 53427
OutputLogic:
    140922: 09/05/29: Re: Online tool that generates parallel CRC and Scrambler
    141008: 09/06/02: Re: Has anyone tried to install a Xilinx floating license? The
    141025: 09/06/02: Re: Xilinx GbE performance
    141043: 09/06/03: Re: Xilinx GbE performance
    141076: 09/06/04: Re: Open source processors
    141088: 09/06/04: Re: Help with Remote debugging ideas.
    141155: 09/06/09: Re: ISE 11.1
    141169: 09/06/10: Re: Xilinx Block RAM Sim
    141196: 09/06/10: Safe margin in FPGA static timing analysis
    141197: 09/06/10: Re: Virtex 5 LUT Outpus
    141281: 09/06/15: Re: About Altera patent application "Logic Cell Supporting Addition
    141369: 09/06/20: Re: TimingAnalyzer is now freeware
    141609: 09/06/29: Re: SATA Phy
    141617: 09/06/30: Re: Can we expect ISE Gui and makefile to produce identical bit
    141667: 09/07/02: Re: USB Book
    141921: 09/07/17: Re: Configure FPGA via PCIe
    142182: 09/07/28: Re: Has anyone tried to install a Xilinx floating license? The
    142217: 09/07/29: Re: cool chart
    145450: 10/02/09: Re: What is the most area efficient CRC method
    147863: 10/05/27: Re: crc16 with 16 bit inputs
    148963: 10/09/15: Re: Providing FPGA-specific evaluation IP
    148972: 10/09/16: Re: New release of HDLmaker
    149889: 10/11/30: ReportXplorer: online report viewer application
    150198: 10/12/30: Re: XST Fails 2D array wild card sensitivity list
    151521: 11/04/16: Re: ML505 NOT RECOGNIZED BY THE PC THROUGH PCI EXPRESS
    151699: 11/05/06: Re: ise 10.1 (Linux) contraints problem
    151871: 11/05/26: Re: PCI Express Cable
    151907: 11/06/02: Re: How could I get LUT-level netlist in Xilinx ISE?
    151974: 11/06/15: Re: Determine latency of GTX links vs Aurora+LVDS
    152010: 11/06/21: Re: How to open the interface GUI of ChipScope Pro Analyzer on linux
    152011: 11/06/21: Re: How to open the interface GUI of ChipScope Pro Analyzer on linux
    152037: 11/06/23: Re: Depth of logical Circuit
    152270: 11/07/29: Re: Bitstream compression
    152436: 11/08/22: Re: MAXDELAY constraint
    152587: 11/09/15: Re: LFSR in xilinx 13.2
    156188: 14/01/11: Re: FPGA Synthesis to LUT: Looking for papers/algorithms
    156189: 14/01/11: Re: Altera Primitives Library
outsideedge:
    83139: 05/04/24: Space Invaders!
Ovidiu Lupas:
    37048: 01/11/29: 128-bit scrambling and CRC computations
    37077: 01/11/29: Re: 128-bit scrambling and CRC computations
    37122: 01/11/30: Re: 128-bit scrambling and CRC computations
ovilup:
    12087: 98/09/28: I2C controller references needed!
    12109: 98/09/29: I2C : thank you
    12669: 98/10/22: Need VHDL tools for Win NT/ Win 95
    12757: 98/10/28: I2C core design
    13015: 98/11/11: Example of clock circuit needed !
    13017: 98/11/11: Looking for a good documentation on FPGA
    14128: 99/01/14: Digital design services
Owen Duffy:
    135579: 08/10/09: Update Altera MAXII UFM post production
    135848: 08/10/17: Re: Update Altera MAXII UFM post production
    135909: 08/10/21: Re: Update Altera MAXII UFM post production
Owenh:
    157723: 15/02/16: Kintex UltraScale board with two DDR4 interfaces?
<owlcdg@thankyou.com>:
    17010: 99/06/23: Disney vacation 1006
owner:
    64442: 04/01/04: Xilinx Logicore PCI64 Problem
    64494: 04/01/05: Re: Xilinx Logicore PCI64 Problem
    64502: 04/01/06: Re: Xilinx Logicore PCI64 Problem
    68792: 04/04/19: OT: Gigabit Ethernet MAC Throughput
    68837: 04/04/20: Re: OT: Gigabit Ethernet MAC Throughput
    68874: 04/04/20: Re: OT: Gigabit Ethernet MAC Throughput
OxbIEcum:
    19164: 99/12/02: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
<oxpbsxby@hotmail.com>:
    12856: 98/11/02: Music stations live from internet
<ozfbgs@hotmail.com>:
    18735: 99/11/10: ## Information Auction - Sell What You Know -Buy What You Dont ## 3845
Ozgur Kayalar:
    17940: 99/09/18: Synplfy 5.21 and 5.08a
Ozkan Dikmen:
    34682: 01/09/03: APEX20KE: Global Line for internal logic


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search