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Hi everybody, Is there an equation where the inputs are the widths of the multiplier and the multiplicand which computes the amount of logic (LUTs) required for the operation. Is there a way to compute the amount of logic required when the desired width of the output is less than the width computed ? It is FPGA architecture dependant but is there some equation which gives a rough estimate ? Thanks,Article: 68451
Rajeev, Make sure to turn on the VHDL-93 switch. You can do this in the compile options menu item under compile in 5.7. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Rajeev wrote: > Hello all, > > I'm still working with DSPBuilder. Here's a VHDL problem > that I can fix but don't understand. DSPBuilder.vhd has a line > > obj:lpm_add_sub <snip> port map (cin => '1'); > > Quartus is happy with this, and in fact I use constant port values > in my own VHDL all the time. But Model Technology (Altera Edition 5.7e) > complains: > > # ** Error: Actual for formal cin is not a signal. > # ** Error: Value associated with cin does not have a static name. > > So first I tried > > constant one : std_logic := '1'; > ... > obj:lpm_add_sub <snip> port map (cin => one); > > and got > # ** Error: Actual for formal cin is not a signal. > > And finally > > signal one : std_logic := '1'; > ... > obj:lpm_add_sub <snip> port map (cin => one); > > which worked. > > My questions are: > > (1) Why is port map(cin=>'1') not considered OK ? > > (2) Is it bad practice to do this ? > > Thanks in advance for any pointers. > > Btw, The component declaration for lpm_add_sub is > > COMPONENT lpm_add_sub > GENERIC ( <snip> ); > PORT ( <snip> > cin: IN STD_LOGIC := '0'; > <snip> > ); > END COMPONENT; > > -rajeev-Article: 68452
Thanks for your reply. I am working on something that will require more multipliers than the dedicated ones in the Virtex II, where I may have to implement some in logic and use the dedicated ones as well. I was wondering if there is some sort of a computation method whereby we know the widths of the multiplier and the multiplicand and using the method we can compute the resources (like LUTs) the multiplication operation would use. Peter Alfke <peter@xilinx.com> wrote in message news:<BC9340F2.5D96%peter@xilinx.com>... > In the newer FPGAs (like Virtex-II etc) you get ready-made multipliers that > do not "cost" any flip-flops, but you can use pipeline flip-flops inside for > free. > For multiplier-intensive applications, you ask the wrong question. > Multiplication is often implemented as a combinatorial function, without any > flip-flops, except for pipelining. > You can of course do it sequntially, and there is an endless number of > option. But for speed reasons, most users prefer the "hard" combinatorial > multipliers in the newer chipc. > Peter Alfke > > > From: spanchag@yahoo.com (spanchag) > > Organization: http://groups.google.com > > Newsgroups: comp.arch.fpga > > Date: 2 Apr 2004 15:23:01 -0800 > > Subject: Logic required for multiplication > > > > Hi > > > > I would like to find out if there is some sort of an equation where we > > give the size of the two inputs and it tells us how many flip flops it > > is going to use to implement the multiplier function. > > > > (It may be specific to the architecture of the chip but a rough > > estimate would do) > > > > Thanks,Article: 68453
none wrote: > Hendra Gunawan wrote: > >> Hi folks, >> Most companies that sell EDA tools, such as Xilinx, Altera, Synopsys, >> Synplicity, Model Technology etc require you to renew the license >> annualy. >> Can anyone give a good reason for this? I mean, other very expensive >> software, such as Microsoft Office Professional, I can just install it >> once >> and it will run forever. With EDA tools, I have to renew the license >> every >> year, why is that? > > > > Not really. > I was told the purchased full version of Quartus runs forever. > It then doesn't support the latest chips though. > > Rene I'm fairly certain this is true of Xilinx ISE as well, although I could be wrong. I don't even think I have a license file, just an activation code when I first install it. -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 68454
In article <80e4f9e8.0404050657.233e9164@posting.google.com>, spanchag wrote:
> Thanks for your reply. I am working on something that will require
> more multipliers than the dedicated ones in the Virtex II, where I may
> have to implement some in logic and use the dedicated ones as well.
>
> I was wondering if there is some sort of a computation method whereby
> we know the widths of the multiplier and the multiplicand and using
> the method we can compute the resources (like LUTs) the multiplication
> operation would use.
Assuming Virtex1/Virtex2-type logic cells (4-input LUT plus carry
logic and Flip-Flop):
Generic combinatorial N x M multiplier takes ~ (N-1)*M cells.
Loadable KCM, also combinatorial, takes ~ (N/2-1)*(M+3) cells.
Scaling Accumulator multiplier, N clock cycles, takes M arithmetic
cells. Depending on your infrastructure, you may have to count
another N cells to serialize the multiplier, plus another N cells
to store the LSBs that shift out.
If you haven't read Ray Andraka's page on multiplication
http://www.fpga-guru.com/multipli.htm
yet, do so now.
I believe all of this also applies to Altera chips, except there
the KCM is not loadable.
- Larry
Article: 68455"Leon Heller" <leon_heller@hotmail.com> a écrit dans le message news: 407153a3$0$3300$cc9e4d1f@news-text.dial.pipex.com... > < snip > > I've always found Xilinx and Altera support very good for their CPLDs and > FPGAs. Perhaps you are using the wrong chips. 8-) > Well, does Xilinx/Altera have a *low* power *5V* CPLD offer ? Too bad Xilinx threw away the 5V Coolrunner parts. Plus the ATMEL "logic doubling" is a nice thing that allow me to pack my design in a 64MC-TQFP44 device instead of a 128MC. The board is pretty dense and have no room for 128MC which would've made mandatory a much bigger (to me) 80-100 pin package. Thanks, Fred.Article: 68456
Iam using Sparatn II 200 connected to XC18V02 I have founded that the programing of the FPGA takes a long time so that I lost my master reset ... The question is : Can I use the done signal internally to reset my design ?Article: 68457
Hello, I would like to request some help for some students that work on an Altera Stratix EP1S25 developpement board. They try to deal with the Conversion Numeric/Analog , so they wrote programs on VHDL where they declare a bit vector with a certain value, and send it to the CNA to see the values on the output. But... no matter the value they use, they always have zero volt on the outputs However, I think they were very careful with the pins numbers assignements of the components on the board. And it seems they have the same kind of problem with the CAN (receiving a simple voltage, and transfer it directly to the outputs via the Stratix). Can someone please help them (and me, by the way ?). I'm just searching for some VHDL code to test the CNA and CAN conversions. Many thanks, Regards, A. AbellardArticle: 68458
Dear All,
So, I've got this design. It has several clocks, all asynchronous to
each other. Lets call them Clk1, Clk1 .. ClkN. So, I generate a new
clock 'masterclock' from a DCM, and use it to generate clock enables
from the clocks, Clk1, Clk1 .. ClkN. The 'masterclock' made in a DCM
and is going at a faster rate than each of the clocks. This means I
have a nice synchronous design with just masterclock coming from a
BUFG.
Now the Clk1, Clk1 .. ClkN clocks feed this circuit, copied from a CAF
post by Rickman, through the general routing fabric, i.e. no BUFG
involved.
|------- Metastable -------|
__________
| | _____
|------O| inverter |-------|---------------| | Enable
| |__________| | | XOR |---->
| ______ ______ | ______ |--|_____| Out
| | | | | | | | |
|---| D Q |-----| D Q |--|--| D Q |--|
| | | | | |
Clk1 | | | | | |
-------|> | ---|> | |---|> |
|______| | |______| | |______|
| |
|___________|___________ Masterclock
I'm keen to keep the delays around the metastable bit of the circuit
as short as possible, so I included in my UCF file stuff like this:
NET "masterclock" TNM_NET = "masterclock_FFS_grp";
NET "clk1" TNM_NET = "clk1_FFS_grp";
TIMESPEC TS1 = FROM : clk1_FFS_grp TO masterclock_FFS_grp :
1.350ns;
TIMESPEC TS2 = FROM : masterclock_FFS_grp TO clk1_FFS_grp :
1.350ns;
and so on for the other clocks upto ClkN.
So far, so good. Then it fails the timing with reports like this in
timing analyser:-
Slack: -0.941ns (requirement - (data path - clock
path skew + uncertainty))
Source: clock_in_ff (FF)
Destination: clock_in_d (FF)
Requirement: 1.350ns
Data Path Delay: 1.347ns (Levels of Logic = 0)
Clock Path Skew: -0.944ns
Source Clock: clk1 rising
Destination Clock: masterclock rising
Clock Uncertainty: 0.000ns
The timing analyser inserts a mystery value for 'Clock Path Skew'. It
seems to only do this if the 'Source Clock' comes from a DCM. (In this
example Clk1 happened to come from a DCM. I get the same problem with
TS2 even if Clk1 comes from outside the device and doesn't go near a
DCM.)
So, the question is, where does the 'Clock Path Skew' value come from?
How can it make up skew between two unrelated clocks?
Thanks, Syms.
p.s. The work around is to put MAXDELAY constraints on the nets, but
then this doesn't take into account Tcko and Tdick. This design is in
several different FPGA families, and I'd like for these timings to be
included automatically.
Article: 68459Are you using master serial mode? Why does it take a long time ? You can read the number of clock cycles required in the data book. You can start a new configuration by pulling PROG Low. Peter Alfke =========== > From: haythamazmi@hotmail.com (H.Azmi) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 5 Apr 2004 09:18:11 -0700 > Subject: Can I use the Done signal in FPGA to reset my design > > Iam using Sparatn II 200 connected to XC18V02 > I have founded that the programing of the FPGA takes a long time so > that I lost my master reset ... > The question is : Can I use the done signal internally to reset my > design ?Article: 68460
Hi, I'm guessing he's got a "master reset" signal run out to an I/O pin, and his FPGA isn't in user mode (done with configuration) until some time long after "master reset" has been deasserted. I would suggest that he simply make sure his "master reset" is used in the FPGA design as an asynchronous reset. This way, all of the flip flops will be initialized to the desired state at the end of configuration (by GSR) and it doesn't matter if "master reset" is asserted or not, for this one time event when configuration ends. On subsequent "master resets" while the user design is active, the reset will initialize the design as desired. Eric Peter Alfke wrote: > > Are you using master serial mode? Why does it take a long time? > You can read the number of clock cycles required in the data > book. You can start a new configuration by pulling PROG Low. > Peter Alfke > =========== > > > From: haythamazmi@hotmail.com (H.Azmi) > > Organization: http://groups.google.com > > Newsgroups: comp.arch.fpga > > Date: 5 Apr 2004 09:18:11 -0700 > > Subject: Can I use the Done signal in FPGA to reset my design > > > > I am using Sparatn II 200 connected to XC18V02. I have founded > > that the programing of the FPGA takes a long time so that I lost > > my master reset ... The question is : Can I use the done signal > > internally to reset my design ?Article: 68461
Hi, Need help (VHDL code), please, for using tri-state bus (buffer) instead of normal mux to realize a multiplexer of 16:1 (each of 16 vectors is 4 bits large). This alow you to save on CLB. Question : is it good from timing point of view to use these tri state bus(buffer)???? Any help is very appreciated.Article: 68462
Use 'Z's:
y=d0 when sel="00" else (others=>'Z');
y=d1 when sel="01" else (others=>'Z');
y=d2 when sel="10" else (others=>'Z');
y=d3 when sel="11" else (others=>'Z');
It can save timing, but only if the TBUFs are hand placed. In VirtexII, I
think a carefully placed mux design will outperform the TBUFs, at least or
reasonably sized muxes. Besides, the spacing of the TBUFs is not
sufficient to connect up arithmetic that uses the carry chain.
Oleg wrote:
> Hi,
> Need help (VHDL code), please, for using tri-state bus (buffer)
> instead of normal mux to realize a multiplexer of 16:1 (each of 16
> vectors is 4 bits large). This alow you to save on CLB.
> Question : is it good from timing point of view to use these tri state
> bus(buffer)????
> Any help is very appreciated.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68463
On Monday, in article
<4071836c$0$14178$636a15ce@news.free.fr>
fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo
"Fred Bartoli" wrote:
>"Leon Heller" <leon_heller@hotmail.com> a ?crit dans le message news:
>407153a3$0$3300$cc9e4d1f@news-text.dial.pipex.com...
>>
>< snip >
>
>> I've always found Xilinx and Altera support very good for their CPLDs and
>> FPGAs. Perhaps you are using the wrong chips. 8-)
>>
>
>Well, does Xilinx/Altera have a *low* power *5V* CPLD offer ?
>Too bad Xilinx threw away the 5V Coolrunner parts.
I know too well about that demise, but it was on the cards when Xilinx
bought out Philips Coolrunner. I personally prefer the old Philips tools for
Coolrunners over the Webpack (your own 100baseT connection to Xilinx server
for the downloads required).
--
Paul Carpenter | paul@pcserv.demon.co.uk
<http://www.pcserv.demon.co.uk/> Main Site
<http://www.gnuh8.org.uk/> GNU H8 & mailing list info.
<http://www.badweb.org.uk/> For those web sites you hate.
Article: 68464Fred Bartoli wrote: > Hello, > > I've designed in an instrument board an ATMEL CPLD. > For that purpose I had to use their "low cost" software. > First I tried the CUPL tool, but it was too much bugged. Then I used their > VHDL "prochip designer" which is based on altium tool and their proprietary > fitters. > After some fighting with VHDL (my first project) I finally had it all OK > with simulation, synthesis and fitting (PAR). I had to work around some > strange synthesizer results but finally got it OK. > > Then came the time of timing analysis, using the vital files provided by > their fitter. > Again some annoying bugs, like (traced by comparing the vital/edif/fitter > equations report files) > - generated vital files not compatible with their provided vital library > (quickly derived from their fpga library) > - some vital outputs with the wrong polarity > - some floating vital CPLD internal signals > - some *strange* results like DFFs with permanent reset, or permanently > disabled CE... > > OK, so far I think (I've not tested the CPLD as I still don't have the > board) I know where the errors are in their outputs and that my final design > is OK. > > I've made a *nice* bug report to ATMEL with all my analysis, my commented > sources, their file results, and all that's needed to help them quickly > reproduce the bugs, and also an enquiry about whether my analysis and > consequently my jedec output files were good or not. > All that sent, as requested, to their pld support 2 weeks ago. I had no > acknowledge, no answer, not even an evidence of live, despite one reminder a > few days ago. > > Are these guys serious ? > Any experience ? CUPL has a number of component pieces. The low level compiler and functional simulator certainly have some quirks, but these are predictable, stable, and easily avoided. The CUPL shell we avoid, instead using a std Pgmr Editor, and the command line compiler. When working on designs near the ceiling, much of the effort is in check/control of the fitter, and CUPL is better at low level control than VHDL is. Timing simulations I would not sweat too much over with a CPLD, you can always use a calculator and the fitter report, to check some 'key suspect paths'. The fitter is the same in both flows. -jgArticle: 68465
Paul Carpenter wrote: > On Monday, in article > <4071836c$0$14178$636a15ce@news.free.fr> > fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo > "Fred Bartoli" wrote: > > >>"Leon Heller" <leon_heller@hotmail.com> a ?crit dans le message news: >>407153a3$0$3300$cc9e4d1f@news-text.dial.pipex.com... >> >>< snip > >> >>>I've always found Xilinx and Altera support very good for their CPLDs and >>>FPGAs. Perhaps you are using the wrong chips. 8-) >>> >> >>Well, does Xilinx/Altera have a *low* power *5V* CPLD offer ? >>Too bad Xilinx threw away the 5V Coolrunner parts. > > > I know too well about that demise, but it was on the cards when Xilinx > bought out Philips Coolrunner. I personally prefer the old Philips tools for > Coolrunners over the Webpack (your own 100baseT connection to Xilinx server > for the downloads required). Lattice claim 5V tolerant I/O on their new LC4xxx family, but they do need multiple supplies. -jgArticle: 68466
Kelly wrote: > > Thanks - we use those - but I was hoping for a niche or even > association type site that had career listings.... My experience has been that in this time of an oversupply of engineers, having a current TSSI is a ticket to immediate work, at least in the Washington DC area. You can even get hiring bonuses for the right people. So don't expect to find workers easily and be prepaired to settle for less than excellent skills. I have let my clearances lapse, so I am out of the market. But I could easily be bringing down $110K+ if I wanted to get back in the rat race. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 68467
Unroll the iterations, provide hardware for the worst case, and then have an exit strategy
such as bypass with matching delays or execute null iterations for the remaining ones.
YunghaoCheng wrote:
> Ray Andraka <ray@andraka.com> wrote in message news:<406AF4DE.B027EE6B@andraka.com>...
> > OK, so webcam type stuff. These have a low pixel rate and image size compared to other
> > video. Bit serial arithmetic works great for this. I think the gradient vector flow
> > might be a little easier to do.
> >
> > YunghaoCheng wrote:
> >
> > > Ray Andraka <ray@andraka.com> wrote in message news:<406A644A.67629932@andraka.com>...
> > > > You didn't mention your image size or pixel rate. Those are a factor in
> > > > determining the best approach.
> > > >
> > > > YunghaoCheng wrote:
> > > >
> > > > > Hi folks!!
> > > > > Now ,I am designing a real-time visual tracking system based on FPGAs.
> > > > >
> > > > > The images are captured by the CCD camera, and we do edge detection
> > > > > by using (Sobel-mask) 2D convolver.
> > > > > We also use two consecutive image
> > > > > frames I(k) and I(k-1) to subtracted pixel by pixel ,in order to
> > > > > find out the moving object.
> > > > >
> > > > > A "Moving Edge" is include by doing a logic AND operation between the
> > > > > subtracted image and the edge image(obtained by Sobel-mask)of the
> > > > > current frame.
> > > > >
> > > > > After finding out the "Moving Edge" we must to extract the object's
> > > > > shape
> > > > > by using Active Contour Model(or snake).
> > > > >
> > > > > Now I have implemented the "Moving Edge" detection function on
> > > > > a Xilinx FPGA.The next step is to design the "Snake-Based Outline
> > > > > Extraction"
> > > > > function block. I've found a lot of reference papers on the Google
> > > > > about the
> > > > > "active contour model" and finally I want to choose two methods--> One
> > > > > is Greedy algorithm based snake-model and the other one is Gradient
> > > > > Vector Flow (GVF)based algorithm.
> > > > > I wonder which one is more suitable for FPGA based architecture
> > > > > design?
> > > > > Could anyone can give me some recommendations or you have any other
> > > > > good ideas
> > > > > to design the object outline extraction function on FPGA..??
> > > > >
> > > > > Thanks a lot!!
> > > >
> > > > --
> > > > --Ray Andraka, P.E.
> > > > President, the Andraka Consulting Group, Inc.
> > > > 401/884-7930 Fax 401/884-7950
> > > > email ray@andraka.com
> > > > http://www.andraka.com
> > > >
> > > > "They that give up essential liberty to obtain a little
> > > > temporary safety deserve neither liberty nor safety."
> > > > -Benjamin Franklin, 1759
> > >
> > > Yes ..
> > >
> > > The image size is 320x240 and in order to meet a nearly real-time constraint,
> > > each image frame (320x240) processing time must be less than 34 ms.
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
>
> Yes ..
>
> Bit-serial methods can be used to deal with the heavy arithmetic operations
> in the computing of Gradient Vector and Energy Function. I also found a lot of
> tutorial materials on your Web site(www.andraka.com) and they gave us
> some useful information.
> But now we still face a problem that the GVF method is like
> one kind of "Optimization Method" and it consumes several
> iterations before reaching its optimal solution. And the iteration
> numbers may differ from case by case.
>
> My question is that -- "how to design a flexible structure
> on FPGA?" Flexible means the numbers of iteration can be changed.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68468
There are many ways to multiply, and where you have lots of multiplies to do it may make
sense to either time multiplex the existing multipliers or if it is for a sum of products
use distributed arithmetic. We really need more information about your specific application
in order to give you better guidance. Modern FPGAs can handle clock rates at 200+ MHz with
carefully executed designs. Use that capability to fold the multiplications into a smaller
area.
spanchag wrote:
> Thanks for your reply. I am working on something that will require
> more multipliers than the dedicated ones in the Virtex II, where I may
> have to implement some in logic and use the dedicated ones as well.
>
> I was wondering if there is some sort of a computation method whereby
> we know the widths of the multiplier and the multiplicand and using
> the method we can compute the resources (like LUTs) the multiplication
> operation would use.
>
> Pe
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68469Ray Andraka wrote: > Unroll the iterations, provide hardware for the worst case, and then have an exit strategy > such as bypass with matching delays or execute null iterations for the remaining ones. I think that the low frame rates and resolutions involved argue for a processor based control algorithm with hardware acceleration for the per-pixel image processing. Snake-based segmentation departs from the typical per-pixel image processing operators - indeed these are just a preprocessing step in the overall algorithm. The hard work takes place at a higher level of abstraction, that might be difficult and unnecessary to implement fully in hardware. Were it my project, I would investigate putting a microblaze or similar core in the FPGA to handle the iterative, control-type processes, with the parallelisable grunt-work farmed out to specialised hardware units. This might also permit a gradual migration of a C-based implementation into hardware. Get your prototype code running on a PC, port it across to the embedded processor, and go from there. Really depends on where your skills lie, and what your requirements are. Regards, JohnArticle: 68470
Jim Granville wrote: > > Paul Carpenter wrote: > > > On Monday, in article > > <4071836c$0$14178$636a15ce@news.free.fr> > > fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo > > "Fred Bartoli" wrote: > > > > > >>"Leon Heller" <leon_heller@hotmail.com> a ?crit dans le message news: > >>407153a3$0$3300$cc9e4d1f@news-text.dial.pipex.com... > >> > >>< snip > > >> > >>>I've always found Xilinx and Altera support very good for their CPLDs and > >>>FPGAs. Perhaps you are using the wrong chips. 8-) > >>> > >> > >>Well, does Xilinx/Altera have a *low* power *5V* CPLD offer ? > >>Too bad Xilinx threw away the 5V Coolrunner parts. > > > > > > I know too well about that demise, but it was on the cards when Xilinx > > bought out Philips Coolrunner. I personally prefer the old Philips tools for > > Coolrunners over the Webpack (your own 100baseT connection to Xilinx server > > for the downloads required). > > Lattice claim 5V tolerant I/O on their new LC4xxx family, but they do > need multiple supplies. They do have a 3.3 volt only version that just uses one supply, however it is not "zero" power. As to the 5 volt tolerance, Read the fine print carefully. The Lattice parts have a max number of IOs that can be above 3.3 volts at the same time. I ended up using an Altera EP1K part which is fully 5 volt tolerant even with the power off. But of course it is RAM based, not Flash. MCU anyone? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 68471
Hi All - I am trying to use bi-directional I/O pin in VHDL (inout). When I run it through the Xilinx ISE, in the Pad report it converts the inout pin as output. Is there any sample example/code which I can try to make sure I am not writing something incorrect. Thanks. - SunilArticle: 68472
Hello FPGA gurus..
I am designing a micro using Quartus II v4.0 and the target FPGA is Flex10K
(EPF10K20RC240-4). I know it's a very outdated FPGA, but that's all I have
:(
The ALU unit when I compile stand along compiles and works as expected.
However when the ALU is combined with the rest of the micro, during
'analysis & synthesis' I get a long list of warning..
..
here is the warning list
-----------
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00040|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00038|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00036|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00034|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00032|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00030|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00028|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00026|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00024|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00022|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00020|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00018|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00016|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00014|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00012|muxlut:$00018|$00012 contains fan-out
to more than one destination
Warning: CASCADE primitive
SneakALU:ALU|lpm_mux:Mux|muxlut:$00010|muxlut:$00018|$00012 contains fan-out
to more than one destination
------------
After this stage, QII crashes and gives the following error (with option to
contact Altera)
----------
Internal Error: Sub-system: FTM, File: ftm_main.cpp, Line: 5851
oterm->get_number_of_fanout() == 1
Quartus II Version 4.0 Build 190 1/28/2004 SJ Full Version
----------
Now I have only one mux in my ALU. All that mux does is decides which result
to put on the output result bux depending on the value of the sel line
(which is decided
in some other module).. The code of the lpm_mux is as follows:
----------
Gen_2D_Out2 : FOR sig_Cnt IN 0 TO 15 GENERATE
sig_Output_Array (0, sig_Cnt) <= sig_ALU_AddSub_IncDec_Result
(sig_Cnt);
sig_Output_Array (1, sig_Cnt) <= sig_ALU_AND_Result (sig_Cnt);
sig_Output_Array (2, sig_Cnt) <= sig_ALU_NAND_Result (sig_Cnt);
sig_Output_Array (3, sig_Cnt) <= sig_ALU_OR_Result (sig_Cnt);
sig_Output_Array (4, sig_Cnt) <= sig_ALU_XOR_Result (sig_Cnt);
sig_Output_Array (5, sig_Cnt) <= sig_ALU_Abs_Result (sig_Cnt);
sig_Output_Array (6, sig_Cnt) <= sig_ALU_MpyH_Result (sig_Cnt);
sig_Output_Array (7, sig_Cnt) <= sig_ALU_MpyL_Result (sig_Cnt);
sig_Output_Array (8, sig_Cnt) <= sig_ALU_LogicalShift_Result (sig_Cnt);
sig_Output_Array (9, sig_Cnt) <= sig_ALU_RotateShift_Result (sig_Cnt);
sig_Output_Array (10, sig_Cnt) <= sig_ALU_Divide_Result (sig_Cnt);
END GENERATE;
Mux : lpm_mux
GENERIC map (
LPM_WIDTH => 16,
LPM_SIZE => 11,
LPM_WIDTHS => 4,
LPM_PIPELINE => 0,
LPM_TYPE => "LPM_MUX",
LPM_HINT => "UNUSED"
)
PORT map (
data => sig_Output_Array,
--aclr => ,
--clock => ,
sel => ALU_Result_Mux,
result => ALU_Result
);
----------
Can someone pls help me with this problem..
Thanks in advance
Article: 68473>It can save timing, but only if the TBUFs are hand placed. In VirtexII, I >think a carefully placed mux design will outperform the TBUFs, at least or >reasonably sized muxes. Besides, the spacing of the TBUFs is not >sufficient to connect up arithmetic that uses the carry chain. TBUFs are (were?) nice for the job where you had a batch of registers and a microcoded machine to read them onto a shared bus and load them from the bus. Is there some obvious pattern to build a mux-equivalent that works well for reading one of 5 or 10 registers? I'm thinking of something like a column would have an equivalent of the TBUF enable signal. Each bit slice would pass through the chain from the left and switch in its data bit if the TBUF was enabled. That switch could be an OR or MUX, whatever is easiest to implement. (It could even be an AND if you turn things upside down.) When you get to the end of the chain, you have the bus, and you turn it around and send it back to all the places that need to read it. The obvious way uses 3 inputs on a LUT to make a 1 bit MUX. It seems as though there should be something better than using a whole column just to emulate a TBUF reading the adjacent register. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68474
Hi A. Abellard a écrit: > Hello, > I would like to request some help for some students that work on an > Altera Stratix EP1S25 developpement board. > They try to deal with the Conversion Numeric/Analog , so they wrote > programs on VHDL where they declare a bit vector with a certain value, > and send it to the CNA to see the values on the output. But... no > matter the value they use, they always have zero volt on the outputs > However, I think they were very careful with the pins numbers > assignements of the components on the board. They should make sure that the control signals are correctly generated. It is sometimes not enought to juste put some digital values onto the data bus of the DAC. This is where a logic analyzer comes in handy but an oscilloscope can be enough. Some DAC have a current output, not a voltage output. Make sure that the output is loaded (1kohm should be ok) > And it seems they have the same kind of problem with the CAN > (receiving a simple voltage, and transfer it directly to the outputs > via the Stratix). Are they sure they don't receive any digital value? > Can someone please help them (and me, by the way ?). I'm just > searching for some VHDL code to test the CNA and CAN conversions. A simple counter generates nice sawtooth waveforms. I once did a simple AM modulator to test such a design, I still might have the VHDL somewhere. It was basically a sine look-up table, a counter and a multiplier. (and if you need further information, you can email me and even write in french ;o) -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/
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