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Authors (H)

H:
    92696: 05/12/05: Re: What if....
H G:
    128815: 08/02/07: Shutdown parts of core logic on FPGA
H Girard:
    9145: 98/02/24: Re: Correlation implementation...
    9144: 98/02/24: Re: Correlation implementation...
*** H. F. ***:
    9536: 98/03/21: Need your Experience
H. Peter Anvin:
    55576: 03/05/12: Re: MJL Stratix Dev Kit
    55639: 03/05/14: Re: MJL Stratix Dev Kit
    55640: 03/05/14: Re: how to calculate the gate count required for a FPGA design
    55651: 03/05/14: Re: how to calculate the gate count required for a FPGA design
    55682: 03/05/15: Re: Low power, high temperature CPLD
    55693: 03/05/15: Re: Low power, high temperature CPLD
    55978: 03/05/25: Re: FPGA Board
    56173: 03/05/29: Re: Antifuse and SRAM FPGA
    56175: 03/05/29: Re: FPGA design: firmware or hardware?
    56212: 03/05/30: Re: FPGA design: firmware or hardware?
    56262: 03/06/01: Re: FPGA design: firmware or hardware?
    56291: 03/06/02: Re: FPGA design: firmware or hardware?
    56438: 03/06/04: Re: Galois Fields Applications
    56439: 03/06/05: Re: Antifuse and CCC FPGA
    56529: 03/06/07: Re: spartan2e vs cyclone
    56530: 03/06/07: Re: Logical analyzer via USB or printer port
    56789: 03/06/15: Re: FPGA CPU Development Board
    56878: 03/06/17: Re: PC-104 dev Boards
    56926: 03/06/18: Re: PC-104 dev Boards
    56936: 03/06/18: Re: PC-104 dev Boards
    56969: 03/06/19: Re: PC-104 dev Boards
    56970: 03/06/19: Re: PC-104 dev Boards
    57012: 03/06/20: Re: PC-104 dev Boards
    57054: 03/06/22: Re: PC-104 dev Boards
    57123: 03/06/23: Quartus II for Linux
    57176: 03/06/24: Re: Quartus II for Linux
    57455: 03/06/30: Re: ASIC divider in FPGA?
    57595: 03/07/02: Re: Regarding NRZ
    57726: 03/07/04: Re: Regarding NRZ
    57817: 03/07/07: Re: QuartusII software licencing
    57959: 03/07/10: Re: Fpga design with multiple audio rate (44, 48khz ...)
    60135: 03/09/05: Re: Thinking out loud about metastability
    60237: 03/09/08: Re: mouse to Nios Development kit
    60287: 03/09/09: Re: Sending and receiving Ethernet traffic
    60369: 03/09/11: Re: Altera's Quartus II "smart compilation" feature killed my design?
    60370: 03/09/11: Re: mouse to Nios Development kit
    60442: 03/09/12: Z-busses and synthesis
    60449: 03/09/13: Re: Altera's Quartus II "smart compilation" feature killed my design?
    60483: 03/09/14: What CPU for Quartus II?
    60619: 03/09/17: Quartus II 2.2 smart compile ignoring .mif
    60653: 03/09/18: Re: mouse to Nios Development kit
    61178: 03/09/29: ByteBlaster with USB<->PP adapter?
    61387: 03/10/02: Re: Looking for recent Altera Quartus Verilog synthesis experience
    61388: 03/10/02: Re: High-performance workstation
    61389: 03/10/02: Re: ByteBlaster with USB<->PP adapter?
    61445: 03/10/03: Re: Bit error rate
    61553: 03/10/06: Re: Design question (Working with Altera EPXA1F484C1)
    61554: 03/10/06: Re: Problem with PCI cards
    61673: 03/10/08: Re: Digesting runs of ones or zeros "well"
    61674: 03/10/08: Re: Problem with PCI cards
    61678: 03/10/08: Re: Problem with PCI cards
    61743: 03/10/09: Re: pci-x133 to parallel pci-66
    62070: 03/10/17: Re: How to select a FPGA
    62138: 03/10/20: Re: To our future engineers, smart and otherwise...
    62141: 03/10/20: Re: BGA packages in high vibration environments
    62142: 03/10/20: Re: CPU vs. FPGA vs. RAM
    62185: 03/10/21: Re: CPU vs. FPGA vs. RAM
    62305: 03/10/25: Re: Running Quartus II on ReadHat Linux 9.0
    62535: 03/10/31: Re: How to protect fpga based design against cloning?
    62651: 03/11/04: Prototyping board with 4+ MB SRAM?
    62816: 03/11/07: Re: Programmer's unpaid overtime.
    62817: 03/11/07: Re: Arithmetics with carry
    62949: 03/11/11: Re: Linux and FPGA compatibility
    62950: 03/11/11: Re: Home grown CPU core legal?
    62954: 03/11/11: Re: Home grown CPU core legal?
    62967: 03/11/11: Re: Home grown CPU core legal?
    62969: 03/11/11: Re: Home grown CPU core legal?
    62971: 03/11/11: Re: Arithmetics with carry
    62982: 03/11/11: Re: Home grown CPU core legal?
    62983: 03/11/11: Re: Home grown CPU core legal?
    63489: 03/11/22: Re: Altera's altsyncram MAXIMUM_DEPTH
    63490: 03/11/22: Re: Memory Initialization: mif, coe, hex, etc,
    66955: 04/03/01: Mailing list for NIOS kit/Lancelot hackers
    68504: 04/04/06: Re: Can I use the Done signal in FPGA to reset my design
    72813: 04/09/02: Re: DDR SDRAM
    72913: 04/09/07: Re: vga to ethernet converter
    72936: 04/09/08: Re: spartan 2 vs Spartan 3
    73734: 04/09/28: Re: How to get 27MHz from 10 MHz in FPGA???
    73740: 04/09/29: Quartus II annoyance
    73747: 04/09/29: Re: FPGAs as a PCI (target) controller
    73807: 04/09/29: Re: FPGAs as a PCI (target) controller
    73828: 04/09/30: Re: MicroBlaze is now available as Open-Source!! (from independant 3rd party)
    73839: 04/09/30: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
    73844: 04/09/30: Re: VHDL Project Verilog open core compatibility?
    73846: 04/09/30: Re: FPGAs as a PCI (target) controller
    73904: 04/09/30: Re: embedded linux on FPGA?
    73918: 04/10/01: Re: Quartus II annoyance
    73997: 04/10/02: Re: Quartus II annoyance
    74033: 04/10/02: Re: FPGA vs ASIC area
    74034: 04/10/02: Re: FPGA vs ASIC area
    74037: 04/10/02: Re: FPGA+ggiabit ethernet and protocols
    73421: 04/09/21: From whence the MAC on an Altera NIOS devel kit board?
    73422: 04/09/21: Re: Twister + Lancelot
    73442: 04/09/22: Re: From whence the MAC on an Altera NIOS devel kit board?
    73523: 04/09/23: Re: [ALTERA] NIOS-II + MMU + FPU
    73525: 04/09/23: Re: using both edges of clocks in a design - effects on synthesis
    73526: 04/09/23: Re: 5V Tolerant?
    74072: 04/10/03: Re: FPGA+ggiabit ethernet and protocols
    74086: 04/10/03: Re: FPGA for OCR processing
    74133: 04/10/04: Re: Altera Quartus II 4.1 double-click on QPF-File doesn't work
    74192: 04/10/06: Re: 8-bit word to 4-digit, 7-segment display
    74193: 04/10/06: Re: Hash algorithm for hardware?
    74324: 04/10/08: Re: Synplify on Fedora C2
    74326: 04/10/08: Re: 64 bit version of xilinx ISE
    74327: 04/10/08: Re: FPGA for OCR processing
    74603: 04/10/15: Re: EP1C12 or XC3S400?
    74673: 04/10/16: Re: How many Altera LE's to Xilinx Slices????
    94464: 06/01/11: Re: FPGA -> ASIC`
    96576: 06/02/06: Re: realize pci in fpga
    114939: 07/01/26: Anyone have a Lancelot card for sale?
    114950: 07/01/27: Re: On-chip randomness (V4FX)
    117799: 07/04/10: CPLD + =?UTF-8?B?wrVDIHdpdGggcmVhc29uYWJseS1wcmljZWQgdG9vbHM/?=
    117809: 07/04/10: Re: CPLD + =?ISO-8859-1?Q?=B5C_with_reasonably-priced_tool?=
    117817: 07/04/10: Re: CPLD + =?ISO-8859-1?Q?=B5C_with_reasonably-priced_tool?=
    117889: 07/04/12: Re: CPLD + =?ISO-8859-1?Q?=B5C_with_reasonably-priced_tool?=
    119250: 07/05/15: Re: how to choose the perfect fpga support
    119270: 07/05/15: Re: clock wide pulse transfer b/w clock domains
    121496: 07/07/05: Re: vista 64 bits
    124833: 07/10/05: Re: Opteron performance tuning (for Quartus / Linux)?
    124944: 07/10/11: Quartus II 7.2 web edition - Linux or not?
    124963: 07/10/12: Re: Quartus II 7.2 web edition - Linux or not?
    127773: 08/01/07: Re: Ethernet on recent FPGAs
    127774: 08/01/07: Re: Ethernet on recent FPGAs
    127936: 08/01/10: Re: Place-and-Route : Intel vs AMD
    127987: 08/01/11: Re: Place-and-Route : Intel vs AMD
    128007: 08/01/12: Re: Place-and-Route : Intel vs AMD
    131515: 08/04/23: Re: FPGA comeback
    134871: 08/09/04: Re: Quartus II priority 19 under Linux
    136284: 08/11/09: Re: FPGA implementation of a PCI module
    136285: 08/11/09: Re: Linux on Microblaze
    136336: 08/11/11: Re: Linux on Microblaze
    136667: 08/11/30: Terasic DE1 board commentary
    136680: 08/11/30: Re: make phone calls from fpga. is it possible?
    136707: 08/12/02: Re: how to read images from a microSD card ?
    136715: 08/12/02: Re: how to read images from a microSD card ?
    136743: 08/12/03: Relationship between high and low speed clocks
    136747: 08/12/03: Re: Relationship between high and low speed clocks
    136752: 08/12/03: Re: Relationship between high and low speed clocks
    136756: 08/12/04: Re: Relationship between high and low speed clocks
    136771: 08/12/04: Re: Relationship between high and low speed clocks
    136828: 08/12/07: Re: Inverting bus connection order in Verilog
    136850: 08/12/08: Re: FPGA-ASIC Migration
    136999: 08/12/17: Re: Gigabit Ethernet PHY without NDA?
    137013: 08/12/18: Re: Altera Quartus II - 64 bit?
    137152: 08/12/28: Re: Terasic DE1 board commentary
    137154: 08/12/28: Re: Terasic DE1 board commentary
    137157: 08/12/29: Re: DIP PACKAGE ?
    137158: 08/12/29: Re: DIP PACKAGE ?
    137209: 09/01/02: Re: Altera - Create sof file with software inside.
    137213: 09/01/02: Re: Altera - Create sof file with software inside.
    137220: 09/01/03: Re: time limited netlist generation
    137222: 09/01/03: Re: time limited netlist generation
    137316: 09/01/08: Re: Which revision control do fpga designers use (2009)
    137471: 09/01/18: Re: Time to de-assert RAM for changing CLK
    137906: 09/02/02: Re: byteblaster cloning
    145381: 10/02/07: Re: using an FPGA to emulate a vintage computer
    148952: 10/09/14: Re: Question about OC PCI Cores
    149530: 10/11/02: Re: Nios 2 Cyclone II board problem with simple logic
    149555: 10/11/05: Re: Nios 2 Cyclone II board problem with simple logic
    150806: 11/02/13: Re: Cyclone Based FPGA Dev Board With USB Cable Program Path
    152437: 11/08/22: Re: 5V FCT TO Cyclone II
H. Ploog:
    6702: 97/06/17: How to (xilinx)?
    9418: 98/03/12: Re: DES: beginner FPGA questions.
    11251: 98/07/30: On how to protect your IP
H.Azmi:
    50779: 02/12/19: FPGA-based FSK Caller ID
    60761: 03/09/22: Regarding XC6216
    60814: 03/09/23: FPGA RESEARCH FSK
    65416: 04/01/28: Asking about FPGA-SPARTAN error in synthizer
    66756: 04/02/26: VHDL FSM Problem
    68456: 04/04/05: Can I use the Done signal in FPGA to reset my design
    68524: 04/04/07: Re: Can I use the Done signal in FPGA to reset my design
h.e.:
    136462: 08/11/18: Re: Xilinx-3E Starter Kit - USB connection with Linux
    138016: 09/02/04: Re: xilinx platform usb cable linux troubles
    138028: 09/02/04: Re: xilinx platform usb cable linux troubles
    141270: 09/06/15: Re: Xilinx bitstream decompiler has been made and working
h.f.:
    18893: 99/11/20: Re: WHERE can I find xc9536_v2.bsd??!
<h.katarki@gmail.com>:
    119882: 07/05/29: Re: Proper word for total delay?
H.L:
    34470: 01/08/27: System Requirements
    34552: 01/08/29: Re: System Requirements
    37076: 01/11/29: xilinx foundation 3.1 and pentium 4
    37080: 01/11/29: Re: xilinx foundation 3.1 and pentium 4
    37307: 01/12/06: xilinx ise 4.1i
    37317: 01/12/06: xilinx ise 4
    37497: 01/12/12: Re: xilinx ise 4
    37512: 01/12/13: Re: xilinx ise 4
    37801: 01/12/20: Re: Clock pins in Virtex-E
    37803: 01/12/20: Clock pins in Virtex-E
    37828: 01/12/20: Re: Clock pins in Virtex-E
    37829: 01/12/20: Re: Hardware FPGA questions
    37837: 01/12/21: Re: Clock pins in Virtex-E
    37973: 01/12/28: memory arbiter
    38285: 02/01/10: FPGA Synthesis and implementation
    38297: 02/01/10: Re: FPGA Synthesis and implementation
    38329: 02/01/11: Re: FPGA Synthesis and implementation
    38435: 02/01/14: Synthesis in FPGA Express
    38511: 02/01/16: Re: Synthesis in FPGA Express
    38577: 02/01/18: Re: service pack8 can't use
    39785: 02/02/19: Virtex-E BRAM timing
    39847: 02/02/21: Re: Virtex-E BRAM timing
    40135: 02/02/28: Rising and falling edge of a clk
    40175: 02/03/01: Re: Rising and falling edge of a clk
    40239: 02/03/03: Re: Rising and falling edge of a clk
    40240: 02/03/03: Re: Rising and falling edge of a clk
    40310: 02/03/05: Re: Rising and falling edge of a clk
    40462: 02/03/07: Re: Rising and falling edge of a clk
    40697: 02/03/13: Re: high active and low active reset signal mixed in a design
    40728: 02/03/14: Virtex BUFGDLL
    40778: 02/03/15: Re: Virtex BUFGDLL
    40975: 02/03/19: STARTUP_VIRTEX primitive
    41070: 02/03/20: Re: STARTUP_VIRTEX primitive
    41122: 02/03/21: simulation issues
    41445: 02/03/28: core generator bus multiplexer and simulation
    42070: 02/04/15: Re: DLL property control in UCF
    42266: 02/04/19: virtex-e DLL and clock skew
    42267: 02/04/19: Re: virtex-e DLL and clock skew
    42332: 02/04/20: Re: virtex-e DLL and clock skew
    42339: 02/04/21: clock management in Virtex-E (DLL)
    42340: 02/04/21: I hope this figure is better
    42346: 02/04/21: Re: I hope this figure is better
    42351: 02/04/21: Re: clock management in Virtex-E (DLL)
    42407: 02/04/23: Re: clock management in Virtex-E (DLL)
    42466: 02/04/24: Virtex DLL (part 10393)
    42953: 02/05/08: PAR warnings and errors
    43003: 02/05/09: Re: PAR warnings and errors
    43015: 02/05/09: Virtex -E LVDS pins' rules
    43200: 02/05/16: Virtex-E interconnection
    43208: 02/05/16: Re: Virtex-E interconnection
    43534: 02/05/23: Xilinx chip scope: Comments
    43592: 02/05/25: Re: Xilinx chip scope: Comments
    43648: 02/05/28: Virtex CLKDLLHF output
    43669: 02/05/29: Re: Xilinx chip scope: Comments
    43763: 02/06/01: chipscope: Tips to get more speed
    43848: 02/06/04: Re: VirtexE DLL Output clock phase
    44297: 02/06/17: Many thanks to everyone!!
    47567: 02/09/29: Chipscope cores
    49376: 02/11/11: Chipscope 3.3 and pentium 4
H.R.YAZDI:
    166: 94/09/06: Help, Please (Urgent)
<h.rawnsley@gmail.com>:
    85684: 05/06/13: Re: How to convert Matlab to HDL?
H.Spaargaren:
    4288: 96/10/10: Re: Xilinx Startup symbol instantiation in VHDL using Viewlogic ?
h230184:
    80960: 05/03/15: Virtex DeviceSimulator
Ha Young Youl:
    16715: 99/06/04: [Q] low cost asic
    17995: 99/09/22: [Q] simple Queue implementation with external RAM
HAAH:
    140384: 09/05/12: Re: which low cost fpga for space?
Habib Bouaziz-Viallet:
    127583: 08/01/03: WebPack on GNU/Linux
    127585: 08/01/03: Re: WebPack on GNU/Linux
    127588: 08/01/03: Re: WebPack on GNU/Linux
    127589: 08/01/03: Re: [Resolved]WebPack on GNU/Linux
    127591: 08/01/03: Re: WebPack on GNU/Linux
    127625: 08/01/04: Re: WebPack on GNU/Linux
    127668: 08/01/05: Re: [Resolved]WebPack on GNU/Linux
    127669: 08/01/05: Re: WebPack on GNU/Linux
    127670: 08/01/05: rbt to C array
    131065: 08/04/09: Xilinx CPLD programming tool under Linux
    131068: 08/04/09: Re: Xilinx CPLD programming tool under Linux
    131086: 08/04/10: Re: Xilinx CPLD programming tool under Linux
    131093: 08/04/10: Re: Xilinx CPLD programming tool under Linux
    131193: 08/04/15: Xilinx JTAG Linux programming
    143739: 09/10/23: Re: CPLD/FPGA with Linux
    148445: 10/07/23: Re: WTB: Xilinx USB JTAG Cable
habib bouaziz-viallet:
    81959: 05/04/05: WebPack_7.1 on Linux ?
hack:
    46678: 02/09/05: Re: Hardware Code Morphing?
Hack-Man:
    5469: 97/02/18: Re: Using FPGA for PCI interface
<hacka@wp.pl>:
    81505: 05/03/25: xilinx+modelsim total newbie
hackbox.info:
    95733: 06/01/25: Flex8000 / MAX+plus II 10.2 / license from altera.com
    95736: 06/01/25: Re: Flex8000 / MAX+plus II 10.2 / license from altera.com
hafezmg48:
    157734: 15/02/25: Microblaze problem with FSL core
    157742: 15/02/26: Re: Microblaze problem with FSL core
Hagen Ploog:
    9694: 98/03/31: Re: New radix-4 CORDIC for computing sine and cosine
    10084: 98/04/26: Re: C++, C, Java to hardware compiler
    10101: 98/04/27: Re: Make a delay in Xilinx FPGAs (more Details)?
    10833: 98/06/24: Re: Q: I squared C on an FPGA
    12665: 98/10/22: Re: Digital Sine Generator
    12666: 98/10/22: Re: I2C Core
    12667: 98/10/22: Re: Processor Cores
    12668: 98/10/22: Re: DES in FPGA
    18383: 99/10/21: Re: free Online ASIC course
    31064: 01/05/10: Re: 32 bit limit on integers
Hagen2:
    87690: 05/07/28: Synplify 8.1 - View Synthesis Report
    87717: 05/07/29: re:Synplify 8.1 - View Synthesis Report
<haghdoost@gmail.com>:
    120295: 07/06/05: Topics and Ideas for BS Project
Hahnsolo:
    89561: 05/09/19: Unknown price difference for xilinx fpga
    89594: 05/09/20: Re: Unknown price difference for xilinx fpga
    94459: 06/01/11: Dev board prices going up?
    94637: 06/01/15: Re: FPGA Journal Article
Haile Yu (Harry):
    131327: 08/04/20: How to instantiate macro in verilog
haim:
    69898: 04/05/24: spartan 2 demo example
haim moshe:
    40730: 02/03/14: XILINX XC2V6000
HAIR-WAN:
    133810: 08/07/16: AURORA streaming
<HairyTheASICGuy@gmail.com>:
    131578: 08/04/25: Breaking News ... Accellera Verification Working Group Forming
<haitaoz@gmail.com>:
    88211: 05/08/11: Re: System Engineering in the R/D World
    88212: 05/08/11: Re: System Engineering in the R/D World
    88213: 05/08/11: Re: ASIC suggestions
Haiwen:
    153352: 12/02/05: 'x' state on one bit of the input bus of an adder cause the output
    153493: 12/03/12: Internal BUS design: MUX or OR-GATE?
    153496: 12/03/14: Re: Internal BUS design: MUX or OR-GATE?
    153507: 12/03/19: Re: Internal BUS design: MUX or OR-GATE?
haiyan:
    43630: 02/05/28: xc2v-6000 BF957 orcad symbol !!!!!
<hajimow@unconfigured.xvnews.domainSayed>:
    4433: 96/10/29: Question on Wavelet implementation
Hajimowlana Hossain:
    3797: 96/08/02: Re: Question: FPGA versus ASIC design.
Hajimowlana Sayed:
    3733: 96/07/22: Designing Dual Port RAM with 4000 series.
    3747: 96/07/24: Does XACT(ver5.2) support 4000E series?
Hajimowlana-Hossain:
    3776: 96/07/30: Question: FPGA versus ASIC design.
Hakan Pettersson:
    1885: 95/09/15: Re: Fast FPGA's?
Hakan Thyr:
    6754: 97/06/24: ASIC/FPGA in Boston?
<hakan.aydin@gmail.com>:
    112269: 06/11/18: spartan-3e starter kit and ethernet
<hakan.sakman@gmail.com>:
    98210: 06/03/07: Xilinx LVDS
    98219: 06/03/07: Re: Xilinx LVDS
Hakjs:
    64674: 04/01/11: Xilinx ISE6.1 Verilog `define macro?
Hakon Lislebo:
    34350: 01/08/22: Confusion around BUS LVDS in Virtex-II
    34390: 01/08/23: Re: Confusion around BUS LVDS in Virtex-II
    34500: 01/08/28: Re: System Requirements
    44996: 02/07/09: DCM - LOCKED output stays high when it shouldn't?
    45024: 02/07/10: Re: DCM - LOCKED output stays high when it shouldn't?
    46010: 02/08/13: How to interpret the XILINX post layout timing report
    53134: 03/03/04: Using Xilinx DCM's (DLL) with RESET tied to GND is dangerous!!
    53182: 03/03/05: Re: Xilinx EDIF Flow and Blackbox Instantiation
    59580: 03/08/22: Why can't Xilinx DCM's regain lock without a RESET??
    59628: 03/08/25: Re: Why can't Xilinx DCM's regain lock without a RESET??
hal:
    22918: 00/06/02: Foundation problem with verilog & Xilinx 5200
Hal Fred Murray:
    5076: 97/01/21: Re: Oscillator with PLD's or FPGA's
Hal Murray:
    388: 94/11/04: Re: about downloading FPGAs
    758: 95/02/24: Re: Can I implement a digital PLL in an FPGA??
    809: 95/03/05: Re: Questions of implementing asynchronous circuits using FPGAs.
    896: 95/03/23: Any suggestions for chips to implement uCode machines?
    1073: 95/04/25: Re: Is anybody using FPGA's to do PCI interfaces?
    1151: 95/05/05: Re: Compression algo's for FPGA's
    1319: 95/06/01: Re: Latch up in Xilinx 3000 Series FPGA's. Part smokes & smells bad.
    2853: 96/02/17: Re: Xilinx is NOT specified MINIMUM delay -
    2897: 96/02/26: Re: Xilinx is NOT specified MINIMUM delay -
    3896: 96/08/15: Re: Xilinx XC3090 intermittent place/route problem
    4174: 96/09/21: Re: manchester clock recovery
    4175: 96/09/21: Re: manchester clock recovery
    4786: 96/12/14: Re: Xilinx configuration PROM
    4838: 96/12/19: Re: Proper target for design
    6226: 97/04/30: Re: Low power PLD?
    6496: 97/05/28: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
    6936: 97/07/10: Re: Xilinx Prom Generation Problem
    8008: 97/11/07: Re: Digital reverberator on FPGA
    8145: 97/11/21: Re: what is metastability time of a flip_flop
    8175: 97/11/25: Re: what is metastability time of a flip_flop
    8388: 97/12/12: Re: what is metastability time of a flip_flop
    8341: 97/12/09: Re: what is metastability time of a flip_flop
    8364: 97/12/10: Re: what is metastability time of a flip_flop
    8479: 97/12/20: Re: md5 in a FPGA?
    8567: 98/01/09: Re: Xilinx Configuration Problem
    8774: 98/01/25: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    9721: 98/04/02: Re: Digital PLL's or Manual Synching?
    9937: 98/04/15: Re: XactStep6 - The cure for a dongle
    10050: 98/04/24: Re: Arbiter help !!!
    10063: 98/04/24: Re: Xilinx Serial Proms
    10109: 98/04/27: Re: Xilinx Serial Proms
    10150: 98/04/29: Re: High Speed FPGAs??
    10173: 98/05/01: Re: Make a delay in Xilinx FPGAs (more Details)?
    10261: 98/05/08: Re: Low power FPGA design
    10463: 98/05/20: Re: Building signal delays inside an FPGA
    10613: 98/06/05: Re: Non-periodic clock
    10629: 98/06/07: Re: Is there tiling software?
    10879: 98/06/27: Re: Free Computer (Read--Easy, No money down)
    11839: 98/09/12: Re: A Linear Feedback Shiftregister
    12060: 98/09/26: Re: Design Security Question
    12099: 98/09/29: Re: Metastability
    13508: 98/12/07: Re: Which parts are fastest for 3-state enables?
    13440: 98/12/03: Re: Interfaces to an Asynchronous SRAM
    13823: 98/12/29: Re: 22V10 Metastability - help please
    13905: 99/01/01: Re: Can a cross coupled latch "oscillate"? was Re: ..........
    13907: 99/01/02: Re: Can a cross coupled latch "oscillate"? was Re: ..........
    13915: 99/01/02: Re: Can a cross coupled latch "oscillate"? was Re: ..........
    13917: 99/01/02: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    13951: 99/01/05: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    13987: 99/01/06: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    14025: 99/01/08: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    14034: 99/01/08: Re: 22V10 Metastability - help please
    14082: 99/01/12: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    14083: 99/01/12: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    14230: 99/01/21: Re: Can we get back to DSP again? Was Re: Who cares what DSP programmers think?
    14807: 99/02/18: Re: Xilinx Spartan and pin-locking
    15861: 99/04/17: Re: Illegal States in 1 Hot State Machines
    16314: 99/05/15: Re: How synthesize tools concern with size of the design?
    16315: 99/05/15: Re: How do I design this ?(synchronous interface)
    16316: 99/05/15: Re: Synchronizer design?
    16317: 99/05/15: Re: Synchronizer design?
    16351: 99/05/18: Re: 4062XL problems and solutions
    16794: 99/06/09: Re: Evolutionary computation
    17469: 99/07/30: Re: NRZ Deserializing in Virtex
    17484: 99/07/31: Re: Semi-deterministic behaviour in FPGA's
    18339: 99/10/16: Re: VITERBI
    18426: 99/10/23: Re: Xilinx Orientation Question
    18563: 99/11/01: Re: Comparison between Altera and Xilinx
    18587: 99/11/02: Re: Comparison between Altera and Xilinx
    18556: 99/10/31: Re: Comparison between Altera and Xilinx
    18677: 99/11/07: Re: Input metastability
    18678: 99/11/07: Re: Why DSP in a FPGA?
    18699: 99/11/08: Re: Input metastability
    18788: 99/11/16: Re: Altera NOT-gate push back
    18855: 99/11/19: Re: How to use GSR-net in Virtex?
    18905: 99/11/21: Re: Why not Lucent ORCA FGPAs?
    18975: 99/11/23: Re: implementing TCP/IP on PLD
    19006: 99/11/24: Re: How to use GSR-net in Virtex?
    19208: 99/12/06: Re: data serializer/decoder FPGA solution
    19254: 99/12/09: Re: JTAG on PCI slot
    19423: 99/12/21: Re: Speed grade
    19580: 00/01/02: Re: Design security
    19597: 00/01/03: Re: Design security
    19714: 00/01/09: Re: Design security
    19877: 00/01/15: Re: Design security
    19931: 00/01/19: Re: Random Number Generator
    19949: 00/01/20: Re: looping FIFO?
    19951: 00/01/20: Re: Random Number Generator
    19980: 00/01/21: Re: Biphase mark decoder
    19991: 00/01/21: Re: Random Number Generator
    19992: 00/01/21: Re: Xilinx vs. other FPGAs manufactrers
    20343: 00/02/06: Re: Xilinx "WebCD" gripes
    20403: 00/02/09: Re: ADC to DSP... FIFO?
    20508: 00/02/13: Re: Master/Serial mode for Virtex
    20509: 00/02/13: Re: xilinx
    20510: 00/02/13: Re: A FPGA hickup
    20569: 00/02/15: Re: Xilinx Virtex Reset
    20737: 00/02/20: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
    20762: 00/02/21: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
    20763: 00/02/21: Re: A FPGA hickup
    20764: 00/02/21: Re: xilinx
    21112: 00/03/07: Re: SpartanXL route and place
    21140: 00/03/08: Re: antifuse fpga's replacing xilinx
    22282: 00/05/04: Re: How to Prevent theft of FPGA design
    22342: 00/05/05: Re: How to Prevent theft of FPGA design
    22386: 00/05/07: Re: Start Up Reset after config on Virtex design
    22794: 00/05/24: Re: Xilinx Logic Cell counts and carry chains
    23314: 00/06/22: Re: How to cut the power disipation down ?
    23411: 00/06/24: Re: Xilinx xc4000
    23412: 00/06/24: Re: a lot of basic questions - where's the FAQ?
    23413: 00/06/24: Re: How to cut the power disipation down ?
    23414: 00/06/24: Re: 500 million transistor FPGA's
    23535: 00/06/29: Re: PSN Generator
    23577: 00/07/01: Re: Maximum Speed on obtainable on FPGAs?
    23592: 00/07/02: Re: Maximum Speed on obtainable on FPGAs?
    23929: 00/07/16: Re: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
    23617: 00/07/03: Re: why???
    23634: 00/07/04: Re: How to augment the output of a Xilinx lfsr in verilog??
    23800: 00/07/10: Re: Remedies after the Fathers' Day Massacre
    23833: 00/07/12: Re: Remedies after the Fathers' Day Massacre
    23835: 00/07/12: Re: C++/Java generators vs. synthesizers
    24096: 00/07/26: Re: Variable shifting
    24201: 00/07/29: Re: Virtex DLL problem.
    24339: 00/08/04: Re: Who needs all those printed ac parameters?
    24340: 00/08/04: Re: Who needs all those printed ac parameters?
    24769: 00/08/18: Re: Deterministic FPGA routing?
    24772: 00/08/18: Re: Comparing Xilinx FPGAs
    24815: 00/08/19: Re: Non-disclosures in job interviews
    24816: 00/08/19: Re: Further FPGA metastability questions
    24817: 00/08/20: Re: Further FPGA metastability questions
    24820: 00/08/20: Re: Further FPGA metastability questions
    24824: 00/08/20: Re: Permanently programming FPGAs
    24832: 00/08/20: Re: Permanently programming FPGAs
    24833: 00/08/20: Metastability and antifuze
    24834: 00/08/20: Re: Further FPGA metastability questions
    24839: 00/08/20: Metastability measurement
    24869: 00/08/21: Re: Non-disclosures in job interviews, Round One
    25055: 00/08/25: Re: Metastability and antifuze
    24912: 00/08/22: Re: Further FPGA metastability questions
    24913: 00/08/22: Re: Metastability and antifuze
    24914: 00/08/22: Re: Some notes on metastability
    24919: 00/08/22: Re: Mealy vs Moore FSM model
    25560: 00/09/14: Re: Xilinx and CD databooks (rant)
    25668: 00/09/16: Re: Reassurance on Xilinx Sought
    25667: 00/09/16: Re: Simon , decoupling caps
    25674: 00/09/17: Virtex-E: LVDS vs LVPECL
    25733: 00/09/18: Re: Virtex clock fanout
    25732: 00/09/18: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
    26198: 00/10/08: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26305: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26411: 00/10/15: Re: DLL's Spread Spectrum Compatible ??
    26979: 00/11/06: Re: High fan out CE signal.
    27022: 00/11/08: Re: unique serial nr
    27055: 00/11/08: Linux/Unix code to drive Xilinx download cable
    27137: 00/11/12: Re: manchester decoder
    27182: 00/11/14: Re: CRC, LFSR and scramblers
    27216: 00/11/15: Re: Job posting info
    27226: 00/11/16: Hidden DLL mode bit - 1x vs 2x feedback
    27370: 00/11/20: Re: CRC, LFSR and scramblers
    27503: 00/11/25: Re: Clock Skew : Does Xilinx know what they're doing?
    27512: 00/11/27: Re: Fifo design problem
    27553: 00/11/28: Re: Fifo design problem
    27618: 00/11/30: Re: Fifo design problem
    27620: 00/11/30: Re: 150MHz LVDS vs. 75MHz TTL
    27638: 00/11/30: Re: 150MHz LVDS vs. 75MHz TTL
    27720: 00/12/05: Re: Synplify Benchmarks
    27804: 00/12/09: Re: 150MHz LVDS vs. 75MHz TTL
    27805: 00/12/09: Re: Virtex II DLL at 311MHz on XCV300e-8ES
    27782: 00/12/08: Re: XC9500/9500XL CPLD Clocks
    27802: 00/12/09: Re: Hey there anybody!!
    27803: 00/12/09: Re: which I/O pin belongs to each bank
    27806: 00/12/09: Linear Regulator troubles
    27812: 00/12/10: Re: Linear Regulator troubles
    27819: 00/12/11: Re: Linear Regulator troubles
    27835: 00/12/11: Re: Linear Regulator troubles
    27840: 00/12/12: Re: Linear Regulator troubles
    27982: 00/12/18: Re: Setup violation
    27998: 00/12/19: Re: Is it necessary to synchronize the reset signal in an FPGA ?
    28042: 00/12/19: Re: Hold time constraints in virtex?
    28053: 00/12/20: Re: dual port ram for altera
    28055: 00/12/20: Re: really fast counter in SpartanXL?
    28099: 00/12/21: Re: Is it necessary to synchronize the reset signal in an FPGA ?
    28100: 00/12/21: Metastability rant (was Re: dual port ram for altera)
    28133: 00/12/22: Re: testbench generation tool
    28134: 00/12/22: Re: Is it necessary to synchronize the reset signal in an FPGA ?
    28152: 00/12/23: Re: Question about Xilinx pins at high-frequency
    28153: 00/12/23: Re: Methodology
    28202: 00/12/28: Re: really fast counter in SpartanXL?
    28232: 01/01/03: Re: really fast counter in SpartanXL?
    28231: 01/01/03: Re: Newbie question on clock timing generation
    28230: 01/01/03: More than 4 clocks on VirtexE
    28292: 01/01/05: Re: Spartan-II DLL Usage
    28316: 01/01/06: Re: Spartan-II DLL Usage
    28382: 01/01/11: Re: Alliance for Linux
    28422: 01/01/12: Re: Alliance for Linux
    28425: 01/01/12: Re: Spartan-II DLL Usage
    28478: 01/01/15: Re: Spartan-II DLL Usage
    28556: 01/01/17: Re: FPGA driving clock line
    28639: 01/01/19: Re: FPGA driving clock line
    29213: 01/02/09: Re: Xilinx vs Altera
    29647: 01/03/03: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29682: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29833: 01/03/13: Re: VirtexE LVPECL I/O Ports? experience?
    29934: 01/03/19: Re: Spartan II power
    29935: 01/03/19: Re: Parallel Port EPP
    29936: 01/03/19: Re: Parallel Port EPP
    29977: 01/03/20: Re: Spartan-II VREF and VCCO
    30034: 01/03/21: Re: Jobs....?
    30060: 01/03/22: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
    30101: 01/03/23: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
    30330: 01/04/03: Re: pseudo random numbers
    30331: 01/04/03: Re: Parallel Port EPP
    30381: 01/04/05: Re: High Speed PLA/FPGA
    30446: 01/04/08: Re: FPGA configuration from processor
    30606: 01/04/19: Re: clocking on both edges
    32591: 01/07/01: Re: clock speed in XC95288XL
    32654: 01/07/04: Re: xr16vx: a GPL 16-bit xr16 microcontroller in JHDL
    33735: 01/08/03: Re: In-Circuit Power Supply Verification of Xilinx Chips
    33789: 01/08/05: About those "babble" posts here.
    33906: 01/08/08: Re: Which is the best Design Toolchain?
    34019: 01/08/11: Re: Q: Revision and Database Control for FPGA Designs
    34178: 01/08/16: Re: Replication of FFs in Xilinx XC4000
    34179: 01/08/16: Re: Slowing PCI for FPGA
    34185: 01/08/16: Re: Replication of FFs in Xilinx XC4000
    34275: 01/08/18: Re: Virtex-II and 5V devices
    34588: 01/08/30: Re: Version Control
    34770: 01/09/07: Re: Missing bits
    35400: 01/10/03: Re: comp.arch.fpga : Unusual clock divider ckt
    35508: 01/10/09: Re: ROM based FSMs
    35510: 01/10/09: Re: FPGA reset
    35576: 01/10/11: Re: Virtex-2 maximum clock speed
    35577: 01/10/11: Re: 155MHz to DLL in Spartan II
    35579: 01/10/11: Re: FPGA reset
    36907: 01/11/24: Re: How to make an implementable big counter?
    37046: 01/11/29: Re: Creating a jitter free clock
    37047: 01/11/29: Re: Creating a jitter free clock
    38371: 02/01/12: Re: Repost: Should clock skew be included for setup time analysis?
    38394: 02/01/13: Re: Repost: Should clock skew be included for setup time analysis?
    38637: 02/01/20: Re: Repost: Should clock skew be included for setup time analysis?
    38750: 02/01/24: Re: effective high resolution counter using DLL clock phases
    38751: 02/01/24: Re: Atmel FPGA configuration memory?!
    38831: 02/01/26: Re: Xilinx webpack
    38832: 02/01/26: Re: Atmel FPGA configuration memory?!
    38974: 02/01/29: Re: tri-state vs. Mux
    38986: 02/01/29: Re: tri-state vs. Mux
    39026: 02/01/30: Re: FPGA or Micro-controller in Lowpower designs?
    39041: 02/01/30: Re: Java or bytecode processors??
    39703: 02/02/16: Speaking of ORCA...
    39704: 02/02/16: Re: FPGA choices and questions
    39927: 02/02/22: Tristate meets mux
    39982: 02/02/23: Re: Coolrunner and ISP
    39994: 02/02/23: Re: Coolrunner and ISP
    39997: 02/02/24: Re: Coolrunner and ISP
    40252: 02/03/03: Re: Embedding counting in an FSM.
    40823: 02/03/16: Re: Reply to Kevin
    40824: 02/03/16: Re: High speed clock routing
    40830: 02/03/16: Re: Proto boards for labs
    40832: 02/03/16: Re: Why do I want to do this ??
    41042: 02/03/20: Re: Unused I/Os + External Clock on Virtex II
    41174: 02/03/22: Re: High speed clock routing
    41176: 02/03/22: Re: more questions
    41177: 02/03/22: Re: which is the fastest FPGA ?
    41181: 02/03/22: Re: XPOWER accuracy? Commendations
    41184: 02/03/22: Re: Unused I/Os + External Clock on Virtex II + P-P Jitter
    41430: 02/03/28: Re: I2C Slave sampling edge
    41434: 02/03/28: Re: XC9500 low temp. problem
    41503: 02/03/31: Re: I2C Slave sampling edge
    41926: 02/04/11: Re: ChipScope Speed
    41928: 02/04/11: Re: Low-cost FPGA + processor board?
    42320: 02/04/20: Re: 1000 I/O Pins -- What is cheapest FPGA?
    42321: 02/04/20: Re: fpga limitation
    42565: 02/04/27: Re: SpartanII design considerations...
    42567: 02/04/27: Re: Maximum Usage in a Virtex FPGA
    42644: 02/04/30: Re: fpga limitation
    42646: 02/04/30: Re: Xilinx Easypath- Selling parts with known defects
    42751: 02/05/02: Delivery problems..
    42808: 02/05/03: Re: Availability of XC2S150E-6FG456I
    42809: 02/05/03: Re: Availability of XC2S150E-6FG456I
    42833: 02/05/04: Re: Xilinx 2GB limit... something has to be done
    42839: 02/05/04: Re: SpartanII design considerations...
    42979: 02/05/08: Re: PCI bus software for Xilinx PCI core
    43038: 02/05/10: Re: power supply sequencer for Virtex II
    43039: 02/05/10: Checklist for tool sets
    43123: 02/05/14: Re: Driving high speed external devices from an FPGA
    43127: 02/05/14: Anyody else get spam about "FPGA Video Seminar"?
    43160: 02/05/15: Re: Frequency synthesiser
    43238: 02/05/17: Re: PCI Board Project
    43243: 02/05/17: Re: Frequency synthesiser
    43246: 02/05/17: Re: What properties has FPGA?
    43248: 02/05/17: Re: Architecture for high-level reconfigurable computing
    43289: 02/05/18: Re: virtex 2 block rams
    43302: 02/05/18: Re: virtex 2 block rams
    43317: 02/05/18: Re: Bidirectional DONE?
    43321: 02/05/18: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
    43475: 02/05/22: Re: Synchronous Single Clock Designs
    43533: 02/05/23: Re: xc2v-6000 FF1152 orcad symbol ???
    43560: 02/05/24: Re: Time for a new computer. Suggestions?
    43724: 02/05/31: Re: Engineering Samples for free?
    43912: 02/06/06: Re: FPGA destruction possible?
    43995: 02/06/08: Re: Do I have metastability issues?
    43996: 02/06/08: Re: Quick newbie question...
    44271: 02/06/15: Re: TTL library in Xilinx?
    45144: 02/07/13: Re: serial configuration in parallel? Xilinx Spartan-II
    45569: 02/07/27: Re: TMS 1000
    45570: 02/07/27: Re: I want to buy 4 Xilinx FPGA
    45586: 02/07/27: Re: Design Techniques for Memory Mapped Registers.
    45631: 02/07/30: Re: secure FPGA
    45986: 02/08/13: Re: RBT versus BIT file
    46151: 02/08/20: Re: Xilinx FPGA start-up
    46364: 02/08/27: Re: FPGA speed level
    46391: 02/08/28: Re: Any FSM optimizer?
    46443: 02/08/30: Re: Use SSTL2_I or SSTL2_II for bidir?
    46446: 02/08/30: Re: Any FSM optimizer?
    46472: 02/08/30: Silicon lifetime
    46599: 02/09/04: Re: FPGA speed level
    46635: 02/09/04: Re: Virtex-2 BRAM
    46749: 02/09/07: Re: QUARTUS II V2.1 LINUX (C) ALTERA
    46846: 02/09/10: Re: minimalist FPGA system
    46848: 02/09/10: Re: XCR3384XL availability
    46849: 02/09/10: Re: Metastability numbers
    46880: 02/09/10: Re: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
    46902: 02/09/11: Re: Metastability numbers
    46961: 02/09/13: Re: ... milk for free, Opencores?
    46980: 02/09/13: Re: exploiting metastability
    47407: 02/09/25: Re: Can a fpga replace external inverters in a crystal osc ?
    47408: 02/09/25: Re: pulldown resistor value for Xilinx CPLD
    47528: 02/09/27: Re: Dual Port RAM
    47542: 02/09/28: Re: Altera Cyclone low-cost FPGA chips?
    47543: 02/09/28: Re: pulldown resistor value for Xilinx CPLD
    47588: 02/09/30: Re: Does it need any protection circuit for Interfacing FPGA device with PC ISA slot?
    47648: 02/10/01: Re: TCP/IP in FPGA
    47731: 02/10/03: Re: Help for Altera's FPGAs' pinout
    47734: 02/10/03: Re: Moving average filter
    47736: 02/10/03: Re: Need advice wiring up a CPLD
    47852: 02/10/05: Re: DCM outputs skew question
    47860: 02/10/06: Re: TCP/IP in FPGA
    47863: 02/10/06: Re: TCP/IP in FPGA
    48104: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
    48109: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
    48191: 02/10/13: Re: where can I find the FAQs for this news group???
    48251: 02/10/15: Re: Why can Xilinx sw be as good as Altera's sw?
    48252: 02/10/15: Re: Sync Reset without clocks
    48253: 02/10/15: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
    48324: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48325: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48327: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48328: 02/10/16: Re: A nice one-off project for a competent UK based FPGA designer :)
    48367: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48368: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48390: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48399: 02/10/17: Re: multiple clocks
    48403: 02/10/17: Re: Xilinx microblaze vs. picoblaze
    48465: 02/10/18: Re: Xilinx microblaze vs. picoblaze
    48481: 02/10/18: Re: Xilinx microblaze vs. picoblaze
    48503: 02/10/18: Re: Cyclic Redundancy Check generator
    48632: 02/10/22: Re: 6502 core available
    48633: 02/10/22: Re: Floorplanner RPM. How to use it?
    48780: 02/10/24: Re: Silly Virtex 2 Pro question...
    48842: 02/10/25: Re: LVDS standard
    48843: 02/10/25: Re: PCI burst reads w/ Spartan
    49267: 02/11/07: Re: Question about algorithm implementing in FPGA
    49268: 02/11/07: Re: LUT Consumption in Virtex-2
    49304: 02/11/08: Re: Online pinouts of glue chips
    49328: 02/11/09: Re: Xilinx LUT-based FPGAs
    49355: 02/11/10: Re: CLB numbers for various ops?
    49372: 02/11/11: Re: Quicklogic PAsic problem
    49419: 02/11/12: Re: FPGA Size?
    49585: 02/11/16: Re: DLL again :-)
    49587: 02/11/16: Re: DLL again :-)
    49596: 02/11/16: Re: Metastability in FPGAs
    49597: 02/11/16: Re: DLL again :-)
    49618: 02/11/18: Re: Metastability in FPGAs
    49651: 02/11/18: Re: Metastability in FPGAs
    49652: 02/11/18: Re: Metastability in FPGAs
    49661: 02/11/19: Re: Metastability in FPGAs
    49677: 02/11/19: Re: Metastability in FPGAs
    49679: 02/11/19: Re: Metastability in FPGAs
    49681: 02/11/19: Re: Metastability in FPGAs
    49682: 02/11/19: Re: Metastability in FPGAs
    49785: 02/11/21: Re: XCS-05-3PC84 and XCS10-3PC84 Question
    49878: 02/11/23: Re: BGA footprints
    49881: 02/11/24: Re: Metastability in FPGAs
    49915: 02/11/25: Re: Virtex-II Place and Route...
    49925: 02/11/26: Re: How do I measure power consumption?
    50082: 02/11/30: Re: Fast Digital Synthesis Generator
    50083: 02/12/01: Re: question about programmable oscillator ?
    50210: 02/12/05: Re: clock difference between DLL input and output?
    50213: 02/12/05: Re: FPGA Actual Power Measurement
    50231: 02/12/05: Re: series termination question
    50234: 02/12/06: Re: FPGA Actual Power Measurement
    50237: 02/12/06: Re: FPGA Actual Power Measurement
    50265: 02/12/07: Re: Clocking in a Spartan IIE
    50267: 02/12/07: Re: series termination question
    50275: 02/12/07: Re: Clocking in a Spartan IIE
    50315: 02/12/09: FPGA/PCI on low budget
    50331: 02/12/09: Re: FPGA/PCI on low budget
    50332: 02/12/09: Re: clock recovery suggestions
    50365: 02/12/10: Re: Clocking in a Spartan IIE
    50366: 02/12/10: Re: How to assign pins in VHDL?
    50368: 02/12/10: Re: FPGA/PCI on low budget
    50369: 02/12/10: Re: How to assign pins in VHDL?
    50371: 02/12/10: Re: clock recovery suggestions
    50459: 02/12/11: Re: FPGA/PCI on low budget
    50460: 02/12/11: Re: Tiny Forth Processors
    50534: 02/12/12: Re: FPGA/PCI on low budget
    50611: 02/12/14: Re: MTBF Calculation
    50677: 02/12/17: Re: Matrics Memory controller
    50762: 02/12/19: Re: What voltage level is considered as "floating"?
    50815: 02/12/20: Re: Multi cycle Paths..
    50839: 02/12/20: Re: Gray code comparisons
    50842: 02/12/20: Re: Async RAM on an FPGA board
    50868: 02/12/21: Re: Async RAM on an FPGA board
    50882: 02/12/21: Re: FPGA Supercomputing opportunity
    50933: 02/12/23: Re: FPGA Supercomputing opportunity
    50948: 02/12/24: Re: thermal issues on FPGA
    50988: 02/12/24: Re: Combinatorial clock source question
    50992: 02/12/25: Re: thermal issues on FPGA
    51009: 02/12/26: Re: State of the PCB world
    51038: 02/12/27: Re: optimization
    51223: 03/01/07: Re: asynchronous inputs
    51298: 03/01/10: Re: Spartan-2 reset: sync or async?
    51299: 03/01/10: Re: Virtex-II Pro misfire?
    51316: 03/01/10: Re: Virtex-II Pro misfire?
    51677: 03/01/18: Re: Booting Spartan IIE from SPI
    51687: 03/01/19: Re: SChematic design approach compared to VHDL entry approach
    51692: 03/01/19: Re: Schematic design approach compared to VHDL entry approach
    51794: 03/01/22: Re: quality of software tools in general
    51798: 03/01/22: Re: VHDL or Verilog?
    52144: 03/02/03: Re: More than four clocks within a spartan-ii device?
    52162: 03/02/03: Re: one hot encoding
    52247: 03/02/05: Re: Xilinx ISE optimization
    52503: 03/02/12: Re: Quartus / ModelSim
    52510: 03/02/12: Re: Newbie Starting Places + Books?
    52696: 03/02/19: Re: PCB Design for a Xilinx Spartan-II FPGA
    52702: 03/02/19: Re: PCB Design for a Xilinx Spartan-II FPGA
    52714: 03/02/20: Re: About automatically programming my FPGA
    52715: 03/02/20: Re: PCMCIA + FPGA/CPLD
    52717: 03/02/20: Re: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
    52719: 03/02/20: Re: PCB Design for a Xilinx Spartan-II FPGA
    52722: 03/02/20: Re: PCB Design for a Xilinx Spartan-II FPGA
    52964: 03/02/27: Re: Extend PCI slot to outside PC
    53064: 03/03/03: Re: PCB board design software vs outsourcing?
    53067: 03/03/03: Re: FPGA demo board schematic
    53229: 03/03/07: Re: Implementation of latch in FPGA
    53463: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
    53580: 03/03/17: Re: RESET --- Synchronous Vs Asynchronous
    53649: 03/03/19: Re: fpga implementation problems
    53689: 03/03/20: Re: Generic SoundCard Driver/API for FPGA Device
    53735: 03/03/21: Re: Using FPGAs as coprocessors in a PC
    53760: 03/03/21: Re: troubleshooting programming of spartan2e
    53873: 03/03/26: Re: Permanent Local Damage to FPGA
    53903: 03/03/27: Re: FPGA FFT Questions
    54004: 03/03/31: Re: $4000 FPGAs
    54228: 03/04/05: Re: Xilinx announces 90nm sampling today!
    54232: 03/04/05: Re: Xilinx announces 90nm sampling today!
    54434: 03/04/10: Re: Balanced Presentation
    54505: 03/04/12: Re: Double Edge FlipFlop
    54627: 03/04/15: Re: error correcting codes
    54628: 03/04/15: Re: error correcting codes
    54786: 03/04/18: Re: Distributing clock to external devices
    54829: 03/04/19: Re: LFSR MAXIMUM LENGTH
    55004: 03/04/24: Re: Xilinx has released SpartanIII
    55062: 03/04/25: Re: Challenge: (n mod 3) in hardware???
    55156: 03/04/29: Re: NIOS Development Board and Flash Protection
    55185: 03/04/30: Re: Virtex-II DCM frequency synthesizer
    55228: 03/05/01: Re: Low power, high temperature CPLD
    55321: 03/05/04: PLL chips
    55338: 03/05/04: Microcode in FPGAs (was 802.11)
    55410: 03/05/07: Re: PLL chips
    55459: 03/05/09: Re: accurate power measurements
    55462: 03/05/09: Re: I want a 800 k gates FPGA in 40 pin DIL
    55466: 03/05/09: Re: accurate power measurements
    55529: 03/05/12: Re: help on FPGA-programming tutorial for students
    55650: 03/05/15: Re: how to calculate the gate count required for a FPGA design
    55710: 03/05/16: Re: smallest embedded cpu.
    55792: 03/05/20: Re: a (PC) workstation for FPGA development
    55797: 03/05/20: Re: High-Speed Clock & Data Recovery
    55937: 03/05/23: Re: Nois generator - project
    55945: 03/05/24: Re: FPGA Board
    55951: 03/05/24: Re: FPGA design: firmware or hardware?
    56005: 03/05/27: Re: Why is there a large gulf between CPLD and FPGA?
    56064: 03/05/28: Re: FIFO Controller
    56127: 03/05/29: Re: need help on sending 500Mbit/s data through 100 feet of cable, Giga-Ethernet?
    56129: 03/05/29: Re: 20 to 5 encoder optimization?
    56151: 03/05/29: Re: Nois generator - project
    56152: 03/05/29: Re: smallest embedded cpu....and the most pain?
    56205: 03/05/30: Re: FIFO Controller
    56206: 03/05/30: Re: FIFO Controller
    56387: 03/06/04: Re: FPGA's an Flash
    56432: 03/06/05: Re: Clk between multiple boards
    56487: 03/06/06: Re: IDE CUSTOM DRIVER
    56509: 03/06/07: Re: Xilinx Block RAM
    56524: 03/06/07: Re: Logical analyzer via USB or printer port
    56576: 03/06/09: Re: Controlling FPGA speed with VCCINT
    56583: 03/06/10: Re: Shift registers
    56593: 03/06/10: Re: Xilinx Block RAM
    56629: 03/06/10: Re: Pseudo random shift register - > DAC
    56640: 03/06/10: Re: PC-104 dev Boards
    56656: 03/06/11: Re: XC95288 programming problem
    56658: 03/06/11: Re: Controlling FPGA speed with VCCINT
    56743: 03/06/13: Re: Analog signals connected to xilinx spartan2
    57527: 03/07/02: Re: ARM C/C++ compiler independent of OS
    57568: 03/07/02: Re: PCB Problem
    57925: 03/07/10: Re: Rant mode ON
    58038: 03/07/13: Re: Graduation Day: My first 4-layer PCB
    58060: 03/07/14: Re: Graduation Day: My first 4-layer PCB
    58152: 03/07/16: Re: Combinational logic and gate delays - Help
    58153: 03/07/16: Re: JTAG standard connector
    58161: 03/07/16: Re: edge card connectors and high speed design
    58165: 03/07/16: Re: Graduation Day: My first 4-layer PCB
    58183: 03/07/16: Re: Graduation Day: My first 4-layer PCB
    58211: 03/07/17: Re: DVI with a Virtex-II - summary
    58212: 03/07/17: Re: PROM size for spartan
    58213: 03/07/17: Re: Xilinx Block RAM
    58254: 03/07/18: Re: External crystal oscillator for Spartan IIE
    58568: 03/07/27: Re: CRC questions
    58569: 03/07/27: Re: FPGA Editor
    58698: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
    58830: 03/08/02: Re: DDS question. How to generate a square from a sine wave?
    58849: 03/08/02: Re: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
    58948: 03/08/05: Re: 'Virtual Grounds'
    58949: 03/08/05: Re: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
    59001: 03/08/06: Re: 'Virtual Grounds'
    59041: 03/08/07: Re: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
    59689: 03/08/26: Re: Enhancing PAR with FPGA floorplanners
    59691: 03/08/26: Re: Thinking out loud about metastability
    59724: 03/08/27: Re: Thinking out loud about metastability
    59876: 03/08/30: Re: Moving Sum
    59878: 03/08/30: Re: Mitigating metastability.
    59879: 03/08/31: Re: Thinking out loud about metastability
    59880: 03/08/31: Re: Thinking out loud about metastability
    59899: 03/09/01: Re: Off topic - Re: FPGA/DSP Expert - business partner for innovative FFT
    60008: 03/09/03: Re: Thinking out loud about metastability
    60032: 03/09/04: Re: Thinking out loud about metastability
    60441: 03/09/13: Re: Crystal Input to FPGA
    60474: 03/09/14: Re: Xilinx S3 I/O robustness question
    60528: 03/09/16: Re: Xilinx S3 I/O robustness question
    60529: 03/09/16: Re: opinions are OK
    60673: 03/09/19: Re: divide by on spartan3?
    60675: 03/09/19: Re: Xilinx
    60783: 03/09/22: Re: Transistor count
    60806: 03/09/23: Re: Xilinx S3 I/O robustness question
    60807: 03/09/23: Re: Synchronous counter enable pulse length
    60885: 03/09/24: Re: Interfacing external NVRAM
    61067: 03/09/27: Re: Graphics rendering
    61070: 03/09/27: Re: Regulator for Spartan 2
    61089: 03/09/27: Re: FPGA implementation of a lexer and parser - feasible?
    61101: 03/09/28: Re: spam poll
    61188: 03/09/30: Re: Bit error rate
    61265: 03/10/01: Re: Bit error rate
    61343: 03/10/02: Re: Wirelessly Connecting two FPGA development boards (Celoxica RC100 boards)
    61347: 03/10/02: Re: ISE WebPack 6.1 Impact problem
    61448: 03/10/04: Re: Interesting article about FPGAs
    61451: 03/10/04: Re: Digesting runs of ones or zeros "well"
    61469: 03/10/05: Re: Digesting runs of ones or zeros "well"
    61484: 03/10/05: Re: Digesting runs of ones or zeros "well"
    61531: 03/10/06: Re: Should I worry about metastability
    61533: 03/10/06: Re: Should I worry about metastability
    61572: 03/10/07: Re: Xilinx courses
    62032: 03/10/17: Re: Spartan-3 non-ES availability, and misleading pricing info
    62286: 03/10/24: Re: 74 logic to CPLD. how easy for a Newbie?
    62338: 03/10/27: Re: Electronic Dice VHDL Program
    62448: 03/10/30: Re: How to protect fpga based design against cloning?
    62485: 03/10/30: Re: Xilinx XC95108 Chip
    62502: 03/10/31: Re: Xilinx XC95108 Chip
    62519: 03/10/31: Re: Minimalist RS232 on Cyclone
    62592: 03/11/03: Re: Vendor supplied symbol/part models?
    62598: 03/11/03: Re: Vendor supplied symbol/part models?
    62679: 03/11/04: Re: help with 120MHz comparator
    62841: 03/11/09: Re: 0.13u device with 5V I/O
    62980: 03/11/12: Re: 0.13u device with 5V I/O
    62989: 03/11/12: Re: Layout examples
    63024: 03/11/12: Re: Frequency Doubler - VHDL/Verilog
    63060: 03/11/13: Re: How to bring PLL's output to Pin_F1
    63096: 03/11/14: Re: PCI Slot Expansion
    63125: 03/11/15: Re: More basic questions about Spartan 2 IOB
    63141: 03/11/16: Re: PCI Slot Expansion
    63143: 03/11/17: Re: Layout examples
    63203: 03/11/18: Re: Do I need to connect all Vref in a bank together?
    63355: 03/11/20: Re: State Machines....
    63402: 03/11/21: Re: Memory Initialization: mif, coe, hex, etc,
    63418: 03/11/21: Re: State Machines....
    63486: 03/11/22: Re: State Machines....
    63539: 03/11/25: Re: Slightly unmatched UART frequencies
    63657: 03/11/27: Re: 5V I/O with 1.8V Core
    63745: 03/12/03: Re: Exact Timing Constraints vs. Over-Constraining
    63746: 03/12/03: Re: Exact Timing Constraints vs. Over-Constraining
    64045: 03/12/13: Re: Soldering of FPGAs
    64092: 03/12/16: Re: Rocket IO testing
    64093: 03/12/16: Re: download ise foundation
    64295: 03/12/25: Re: How to get first bit '0' position in certain register?
    64339: 03/12/29: Re: predictable timing for xilinx cpld?
    64646: 04/01/10: Re: Anybody know what the REAL story is? Jim figured it out.
    64697: 04/01/11: Re: Xilinx ECS - connecting a single net to multiple bus lines?
    64705: 04/01/12: Re: Synthesis in VHDL vs. Verilog
    64760: 04/01/13: Re: Altera Cyclone data is incomplete or messy
    64789: 04/01/14: Re: ASMBL - hmmm ---- hmmmm -- Wow? -- "Hard-tocopy" rant -- skip if desired
    64790: 04/01/14: Re: Synthesis in VHDL vs. Verilog
    64910: 04/01/16: Re: Which version of ISE Webpack has FPGA Editor on it?
    64912: 04/01/16: Re: Spartan-IIE as an ASYNC RAM?
    64913: 04/01/16: Re: Hardware to test (FPGA-based) prototype?
    64970: 04/01/17: Re: Power-up input value detection
    64971: 04/01/17: Re: Can XILINX run in multiple instances?
    64973: 04/01/17: Re: Hardware to test (FPGA-based) prototype?
    65313: 04/01/24: Re: RocketIO evaluation
    65327: 04/01/24: Re: Good/Affordable Stater kits
    66218: 04/02/14: Re: DCM Jitter?
    66239: 04/02/15: Re: Xilinx DB-01 info?
    66240: 04/02/15: Re: 74ls193 in coolrunner
    66303: 04/02/17: Re: Plea for help - 29PL141
    66309: 04/02/17: Re: Manual Partitioning to Multiple FPGAs
    66397: 04/02/18: Re: regarding synchronization
    66466: 04/02/20: Re: Multiple PicoBlaze/Bus access
    66510: 04/02/20: Re: multiple clocking in FPGA
    66524: 04/02/21: Re: Spartan 3 - avaliable in small quantities?
    66540: 04/02/21: Re: Can FPGA bootstrap itself?
    66548: 04/02/22: Re: GZIP algorithm in FPGA
    66600: 04/02/24: Re: Spartan 3 - avaliable in small quantities?
    66609: 04/02/24: Re: Dual-stack (Forth) processors
    66674: 04/02/25: Re: SmartMedia writer (implments using VHDL)....
    66822: 04/02/27: Re: Stratix 2 ALUT architecture patented ?
    66823: 04/02/27: Re: FSM in fpga's
    66986: 04/03/03: Re: Any help about this demo board
    67025: 04/03/04: Re: Need to speed up Stratix compiles.
    67160: 04/03/07: Re: Bus interface - read, write signals
    67174: 04/03/08: Re: Release asynchrounous resets synchronously
    67176: 04/03/08: Re: Release asynchrounous resets synchronously
    67241: 04/03/09: Re: Release asynchrounous resets synchronously
    67242: 04/03/09: Re: Release asynchrounous resets synchronously
    67312: 04/03/10: Re: Using ALTPLL
    67319: 04/03/10: Re: xilinx configuration problem
    67320: 04/03/10: Re: Basic jitter from a CPLD (XC7500XL)
    67321: 04/03/10: Re: Dual-stack (Forth) processors
    67569: 04/03/15: Re: copy protection on FPGA using embedded serial number
    67619: 04/03/16: Re: Device/Board Selection (CPU Design)
    67711: 04/03/17: Re: Xilinx RAMB16_Sm_Sn timing diagram
    67826: 04/03/19: Re: PCI Development Board
    67830: 04/03/20: Re: Why It Is not Recommended to Infer latches in VLSI Design...
    67846: 04/03/21: Re: Why It Is not Recommended to Infer latches in VLSI Design...
    67873: 04/03/22: Re: Why It Is not Recommended to Infer latches in VLSI Design...
    67988: 04/03/24: Re: Fried a XC2S200!
    67995: 04/03/24: Re: Synchronization of data
    68125: 04/03/27: Re: Xilinx map -timing through ise gui
    68131: 04/03/27: Re: CPLD: assign pins first, or design content first?
    68180: 04/03/29: Re: study verilog or vhdl?
    68205: 04/03/30: Re: study verilog or vhdl?
    68206: 04/03/30: Re: study verilog or vhdl?
    68253: 04/03/31: Re: Metastablility
    68254: 04/03/31: Re: rs232 interface on nios
    68263: 04/03/31: Re: Metastablility
    68473: 04/04/06: Re: Designing MUX with tri sate bus in xilinx virtex II FPGA
    68656: 04/04/13: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    68698: 04/04/14: Re: Yet Another Altera Online Support Is USELESS Rant...
    68711: 04/04/15: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    68714: 04/04/15: Re: DDS-Based PLL
    68791: 04/04/19: FPGA techniques for D/A and A/D
    68794: 04/04/19: Re: OT: Gigabit Ethernet MAC Throughput
    68830: 04/04/20: Re: Clock Enables and Power
    68833: 04/04/20: Re: FPGA techniques for D/A and A/D
    68834: 04/04/20: Re: OT: Gigabit Ethernet MAC Throughput
    68850: 04/04/20: Re: OT: Gigabit Ethernet MAC Throughput
    68868: 04/04/21: Re: calculate the number of logic gate in FPGA
    68878: 04/04/21: Re: calculate the number of logic gate in FPGA
    69078: 04/04/26: Re: transport applications
    69095: 04/04/27: Re: device driver
    69129: 04/04/27: Re: Data transfer for real time analysis
    69130: 04/04/27: Re: transport applications
    69209: 04/04/30: Re: Data transfer for real time analysis
    69214: 04/04/30: Re: Ethernet & FPGA
    69480: 04/05/11: Re: Monolithic state machine or structured state machine?
    69634: 04/05/16: Re: Phase relationship management
    69643: 04/05/17: Re: Phase relationship management
    69797: 04/05/20: Re: Timing Questions?
    69798: 04/05/20: Re: Phase relationship management
    70009: 04/05/26: Re: What can I do if my chip can't meet timing?
    70034: 04/05/28: Re: Tool to help detecting race conditions with asych inputs?
    70045: 04/05/28: Re: Tool to help detecting race conditions with asych inputs?
    70070: 04/06/01: Re: Serial I/O Standards
    70084: 04/06/02: Re: Tool to help detecting race conditions with asych inputs?
    70139: 04/06/04: Re: tri-state in altera and xilinx
    70270: 04/06/10: Re: Virtex-II Pro slave serial configuration problem....
    70271: 04/06/10: Re: tri-state in altera and xilinx
    70321: 04/06/11: Re: SDRAM
    70333: 04/06/12: Re: SDRAM
    70400: 04/06/15: Re: Using Altera libraries for Nios Dev Board
    70453: 04/06/17: Re: C Header files for User Design Logic in the Nios.
    70504: 04/06/17: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
    70608: 04/06/21: Re: CPLD mistery. Help.... reHelp.
    70611: 04/06/22: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
    70752: 04/06/26: Re: Newbie question -fanout of iopins in fpga
    70757: 04/06/26: Re: DPLL in CPLD
    70813: 04/06/29: Re: How to add clock delay in CPLD?
    70814: 04/06/29: Re: Nios stops responding to interrupts
    70862: 04/06/30: Re: simprim X_FF component
    71148: 04/07/09: Re: Spartan 3 termination question (DCI)
    71159: 04/07/10: Re: FSM in illegal state
    71171: 04/07/10: Re: Do i need to use DCM ?
    71175: 04/07/10: Re: Do i need to use DCM ?
    71177: 04/07/10: Re: PCI Timings
    71218: 04/07/12: Re: FPGA to PCI Bus Interface
    71295: 04/07/13: Re: WinCUPL state machine for 16V8
    71299: 04/07/13: Re: mcu vs fpga help me to choose !!
    71300: 04/07/14: Re: FPGA to PCI Bus Interface
    71301: 04/07/14: Re: FSM in illegal state (conclusion)
    71318: 04/07/14: Re: WinCUPL state machine for 16V8
    71410: 04/07/17: Re: FPGA in a Compact Flash format.
    71485: 04/07/20: Re: Using Verilog to embed the synthesis date and time
    71503: 04/07/20: Re: Spartan 3 termination question (DCI)
    71533: 04/07/21: Re: Low Power Applications - enumerate
    71906: 04/08/03: Re: 1GHz FPGA counters
    72072: 04/08/07: Re: LEGO mindstorms and FPGA
    72146: 04/08/09: Re: Now I am really confused!
    72157: 04/08/10: Re: Sync data between two clock domains
    72235: 04/08/11: Re: new XILINX 9500XL datasheets
    72241: 04/08/11: Re: CLOCK_SIGNAL Constraint.
    72267: 04/08/12: Re: Attention Xilinx: command line tools would be useful [Was: Re: why?]
    72361: 04/08/16: Re: Spooling from FPGA to the PC
    72494: 04/08/20: Re: embedded PCI
    72545: 04/08/23: Re: Ethernet
    72628: 04/08/26: Re: 6.1 vs. 6.2
    73751: 04/09/29: Re: Spartan-3 VCCIO ramp up time
    73752: 04/09/29: Re: VHDL inout used for non bidirectional uses
    73840: 04/09/30: Re: NV on-chip memory?
    73841: 04/09/30: Re: Xilinx Read First Write First
    73842: 04/09/30: Re: FPGAs as a PCI (target) controller
    73843: 04/09/30: Re: Read back FPGA configuration
    73921: 04/10/01: Re: Spartan-3 VCCIO ramp up time
    73922: 04/10/01: Re: NV on-chip memory?
    73923: 04/10/01: Re: ASIC vs FPGA and In-Circuit Reconfigurability (ICR)?
    73987: 04/10/01: Re: FPGA vs ASIC area
    74001: 04/10/02: Re: JOP on Spartan-3 Starter Kit
    74004: 04/10/02: Re: spartan-3 sram
    74006: 04/10/02: Re: FPGA vs ASIC area
    74049: 04/10/02: Re: Removing set/reset logic for shift register (HDL ADVISOR )
    73050: 04/09/12: Re: Need some help with some technical claims...
    73097: 04/09/14: Re: Would flash/antifuse-based vendors be more likely to disclose bitstream formats?
    73145: 04/09/14: Re: Virtex 4 released today
    73211: 04/09/15: Re: Xilinx DCMs
    73308: 04/09/18: Re: adder VS increment
    73431: 04/09/21: Re: combinatorial loops / feedback paths discussion
    73457: 04/09/22: Re: From whence the MAC on an Altera NIOS devel kit board?
    73458: 04/09/22: Re: Stratix II vs. Virtex 4 - features and performance
    73460: 04/09/22: Re: USER RESET in XILINX FPGA
    73556: 04/09/23: Re: 5V Tolerant?
    73588: 04/09/24: Re: Xilinx DCMs
    73596: 04/09/24: Re: Getting info from a digital line
    73597: 04/09/24: Re: spartan-3 sram
    73661: 04/09/27: Re: spartan-3 sram
    73677: 04/09/28: Re: NV on-chip memory?
    73680: 04/09/28: Re: Spartan-3 VCCIO ramp up time
    75038: 04/10/25: Re: Low-power FPGAs?
    75045: 04/10/25: Re: Low-power FPGAs?
    75086: 04/10/26: Re: Clock Extraction from Bi-Phase Data
    75112: 04/10/26: Re: Clock Extraction from Bi-Phase Data
    75117: 04/10/26: Re: Clock Extraction from Bi-Phase Data
    75165: 04/10/28: Re: Low-power FPGAs?
    75167: 04/10/28: Re: Programmable I/O Card for the PC - does it exist ?
    75174: 04/10/28: Re: Low-power FPGAs?
    75207: 04/10/29: Re: Do you know this board?
    75240: 04/10/30: Re: Low-power FPGAs?
    75241: 04/10/30: Re: Low-power FPGAs?
    75263: 04/10/31: Re: Low-power FPGAs?
    75264: 04/10/31: Re: Feeding PLL
    75276: 04/10/31: Re: Low-power FPGAs?
    75296: 04/11/01: Re: XST: suppressing incorrect optimizations in VHDL code
    75306: 04/11/01: Re: "frying" FPGAs
    74088: 04/10/03: Re: FPGA for OCR processing
    74422: 04/10/11: Re: Xilinx DCMs
    74613: 04/10/15: Re: Metastability pipeline causes bad juju
    74656: 04/10/15: Re: WebPACK post-PAR min clock period?
    74681: 04/10/15: Re: How many Altera LE's to Xilinx Slices????
    74767: 04/10/18: Re: Internal Capture of clock in FPGA
    74785: 04/10/19: Re: spartan 3 on 4 layers
    74817: 04/10/19: Re: spartan 3 on 4 layers
    74829: 04/10/20: Re: spartan 3 on 4 layers
    74891: 04/10/20: Re: unstable fpga design
    74892: 04/10/20: Re: Simultaneously Switching Outputs in Spartan-II
    75385: 04/11/03: Re: need an fpga board
    75558: 04/11/09: Re: Where to find very basic FPGAs
    75588: 04/11/10: Re: Where to find very basic FPGAs
    75605: 04/11/10: DDR Mux - how does it work?
    75606: 04/11/10: Re: VirtexII-Pro MGT: 8/10 coding bypass problems
    75713: 04/11/12: Re: Obsolete processors resurected in FPGAs
    75715: 04/11/12: Re: DDR Mux - how does it work?
    75719: 04/11/12: Spartan3 Block RAM from WebPACK
    75736: 04/11/13: Re: Obsolete processors resurected in FPGAs
    75833: 04/11/16: Re: Spartan3 Block RAM from WebPACK
    75876: 04/11/17: Re: Newbie FPGA Qs
    76165: 04/11/27: Re: Choice of FPGA device -- my view on benchmarks
    76285: 04/11/29: Re: dual-write port BRAM with XST/Webpack
    76326: 04/11/30: Re: Config Spartan3 in serial slave mode
    76366: 04/11/30: Re: Config Spartan3 in serial slave mode
    76367: 04/11/30: Re: Stupid tools question...
    76409: 04/12/01: Re: CMOS capacitive loads, transition probabilities and FPGAs
    76511: 04/12/05: Re: how to speed up my accumulator ??
    76595: 04/12/06: Re: How to direct download to SRAM on Xilinx Spartan3?
    76603: 04/12/07: Re: how to speed up my accumulator ??
    76618: 04/12/07: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
    76640: 04/12/07: Re: "Hello World" project for an FPGA (on a Spartan3 board)
    76750: 04/12/10: Re: Open source FPGA EDA Tools
    76908: 04/12/15: Re: storing convolution coeeff's Xilinx V2 8000
    76915: 04/12/15: Digital clock synthesis
    76936: 04/12/16: Re: Digital clock synthesis
    76939: 04/12/16: Re: Digital clock synthesis
    76941: 04/12/16: Re: Digital clock synthesis
    76984: 04/12/18: Re: PCI doubt
    76998: 04/12/19: Re: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
    77008: 04/12/19: Re: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
    77081: 04/12/21: Re: Using low-core-voltage devices in industrial applications
    77255: 05/01/01: Re: Quartus and Cyclone programming problem
    77491: 05/01/07: Re: signals inside a process
    77496: 05/01/08: Re: San Jose job offer - need advice
    77518: 05/01/08: Re: WebPack download problem
    77900: 05/01/19: Re: Comparison of LEON2, Microblaze and Openrisc processors
    77994: 05/01/21: Re: Configuring FPGA using PROM/uP
    77997: 05/01/21: Re: Out of memory error : XPS, microblaze, EDK
    78051: 05/01/23: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
    78443: 05/02/01: Re: Asynchronous Inputs Question
    78500: 05/02/02: Re: Synchronizing multibit bus - 2
    78567: 05/02/03: Re: Source of reset for synchronous reset can lead to metastability?
    78608: 05/02/04: Re: Source of reset for synchronous reset can lead to metastability?
    78609: 05/02/04: Re: See Peter's High-Wire Act next Tuesday
    78711: 05/02/06: Re: See Peter's High-Wire Act next Tuesday
    78901: 05/02/09: Re: second flop in asyn reset distribution
    78999: 05/02/10: Re: Newbie : Xilinx Ml310 platform
    79045: 05/02/11: Re: second flop in asyn reset distribution
    79076: 05/02/13: Re: second flop in asyn reset distribution
    79535: 05/02/20: Re: why are PCI-based FPGA cards so expensive ?
    79577: 05/02/21: Re: does anyone have a c compiler for the picoblaze
    79777: 05/02/24: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
    79928: 05/02/26: Re: Digilent D2SB FPGA Boards
    79991: 05/02/27: Re: Maximum Current utilized by Spartan-3
    80103: 05/03/01: Re: pin assignment on an expansion module
    80197: 05/03/02: Re: RocketIO, where to start?
    80770: 05/03/11: Re: Xilinx eagle package (PQ208)
    80833: 05/03/12: Re: XC3000 non-recoverable lockup problem
    80836: 05/03/12: Re: (Stupid/Newbie) Question on UART
    81205: 05/03/19: Re: (Stupid/Newbie) Question on UART
    81227: 05/03/19: Re: (Stupid/Newbie) Question on UART
    81420: 05/03/23: Re: Xilinx backups
    81421: 05/03/23: Re: XC3000 non-recoverable lockup problem
    81466: 05/03/24: Re: (Stupid/Newbie) Question on UART
    81625: 05/03/29: Re: Multi-FPGA PCB data aggregation?
    81865: 05/04/02: Re: Achieving required speed in Virtex-II Pro FPGA
    82394: 05/04/12: Re: Xilinx VirtexII master serial mode problem(cclk)
    83193: 05/04/25: Re: Virtex 4 Power consumption
    83283: 05/04/26: Re: Virtex 4 Power consumption
    83718: 05/05/05: Re: System Ace: How many FPGA's in the JTAG chain before require buffers?
    83803: 05/05/06: Re: newbie question
    83997: 05/05/11: Re: Xilinx versus Elixent; other radically different concepts?
    84119: 05/05/12: Re: "Mine is bigger than yours..."
    85824: 05/06/16: Re: Good FPGA introduction book ?
    85920: 05/06/18: Re: LUT, how to?
    85939: 05/06/18: Re: CPLD fusemap data - why the secrecy?
    86325: 05/06/25: Re: How do I convert a polynomial into a parallel scrambler formula?
    86345: 05/06/25: Re: interfacing to multiple converters
    86399: 05/06/27: Re: Poor PCI performance during read accesses (in master mode)
    88031: 05/08/06: Re: System Engineering in the R/D World
    88255: 05/08/13: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
    88274: 05/08/13: Re: high speed image capture
    88392: 05/08/17: Re: Spartan-3 configuration -- peculiar problem
    88530: 05/08/22: Re: Symmetric clocks with ALTERA Quartus
    88625: 05/08/24: Re: xilinx or digilent
    88787: 05/08/28: Re: CPLD Jitter
    88800: 05/08/29: Re: mails from Aman Mediratta
    90361: 05/10/11: Re: Eliminates meta stability (yes or no)?
    90362: 05/10/11: Re: Synchronizer Flip Flop / Metastability
    90402: 05/10/12: Re: LUT 4:1 VS FF
    90430: 05/10/12: Re: [OT]Re: converting 12v signal to 3.3v
    90491: 05/10/14: Re: How to Reduce Interconnects (VDD and VSS)
    90828: 05/10/21: Re: MAC Architectures
    90839: 05/10/22: Re: MAC Architectures
    90968: 05/10/26: Re: Xilinx FIFO Generator: FIFO Length
    91046: 05/10/27: Re: another FPGA/asic vendor dead :(
    91219: 05/11/01: Re: can ethereal detect an ethernet packet for which crc is wrong
    91220: 05/11/01: Re: can ethereal detect an ethernet packet for which crc is wrong
    91423: 05/11/06: Re: xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine
    91469: 05/11/07: Re: Xilinx Package/Logic Options
    91500: 05/11/07: Re: looking for FPGA pin header board
    91505: 05/11/07: Re: Adder synthesis
    91517: 05/11/08: Re: Delay insertion in Xilinx Verilog
    91565: 05/11/08: Re: What are important factors when selecting Intellectual Property?
    91768: 05/11/12: Re: Kingston ValueRAM double deckers
    91769: 05/11/12: Re: fastest possible USB
    92018: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
    92193: 05/11/23: Re: We need to program several thousands Xilinx flashes XCF025...
    92216: 05/11/24: Re: Unconnected Ports
    92374: 05/11/28: Re: Virtex 4 Configuration
    92449: 05/11/29: Re: first time managing a project
    92456: 05/11/30: Re: Q-bus or Unibus bus transactions in FPGA?
    92457: 05/11/30: Re: async fifo design
    92658: 05/12/03: Re: async fifo design
    92687: 05/12/05: Re: What if....
    93169: 05/12/15: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
    93448: 05/12/22: Re: Xilinbx Online store XC2C32A, XC2C64A missing ?
    93522: 05/12/23: Re: More beginner's verilog questions
    93588: 05/12/25: Re: Spartan 3 power requirements
    93608: 05/12/26: Re: Spartan 3 power requirements
    94057: 06/01/05: Re: basic DSP with FPGA
    93887: 06/01/03: Re: Clock generation
    94056: 06/01/05: Re: Xilinx new year Puzzle: binary counter 0,5,2,3,4,1,6,7...
    94051: 06/01/04: Re: Schematic Entry, Xilinx or Altera?
    94196: 06/01/07: Re: Programming Xilinx PowerPC
    94228: 06/01/08: Re: CRC error correction
    94227: 06/01/08: Re: CRC error correction
    94249: 06/01/09: Re: CRC error correction
    94906: 06/01/19: Re: best evm for virtex-4 and linux
    94496: 06/01/12: Re: FPGA Journal Article
    94621: 06/01/14: Re: FPGA Journal Article
    94654: 06/01/15: Re: FPGA Journal Article
    94631: 06/01/15: Re: Caution, Rant follows
    94908: 06/01/19: Re: How much do you trust your CAD Program?
    94907: 06/01/19: Re: How much do you trust your CAD Program?
    96204: 06/01/31: Re: Digilent FPGA & Handel-C
    96476: 06/02/04: Re: why such fast placement?
    96493: 06/02/04: Re: BGA central ground matrix
    96498: 06/02/04: Re: BGA central ground matrix
    96579: 06/02/06: Re: BGA central ground matrix
    96851: 06/02/11: Re: which one among the available FPGAs is best for a fresher?
    96882: 06/02/12: Re: spartan3 starter kit.
    96957: 06/02/14: Re: Problem programming Altera flex 10k100 & EPC2
    97024: 06/02/15: Re: digital logic library by 74xxxx part number?
    97241: 06/02/19: Re: Communication between FPGA and PC with ethernet
    97242: 06/02/19: Re: realize pci in fpga
    97295: 06/02/20: Re: Implementing a two-modulus PLL divider in Altera Stratix II
    97337: 06/02/20: Re: FPGA - software or hardware -2-
    97343: 06/02/21: Re: FPGA - software or hardware -2-
    97349: 06/02/21: Re: DIFF_OUT buffer example
    97432: 06/02/22: Re: FPGA - software or hardware -2-
    97434: 06/02/22: Re: Is FPGA code called gateware?
    97479: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
    97631: 06/02/24: Re: FPGA - software or hardware -2-
    97637: 06/02/25: Re: 8051 IP core with JTAG debugger for FPGA?
    97638: 06/02/25: Re: [EDK] XilNet throughput
    97651: 06/02/25: Re: V4 FIFO16 and SRAM
    97652: 06/02/25: Re: Input stage for VHF frequency counter in an FPGA?
    97679: 06/02/26: Re: Low power consumption board with memory
    97946: 06/03/02: Re: FPGA communication, I2C and DAC
    98569: 06/03/13: Re: Combinatorial Division?
    98571: 06/03/13: Re: LEON processor core
    99028: 06/03/19: Re: for all those who have stopped listening, and are ranting now...
    99029: 06/03/19: Re: using EDK with the gcc -g option...
    99077: 06/03/19: Re: reading data off a virtex-ii pro board
    103686: 06/06/08: Re: IOBDELAY's delay value
    103787: 06/06/11: Re: stable, tested 6502 core
    104199: 06/06/21: Re: FSM State Minimization on FPGAs
    104278: 06/06/22: Re: keys to the Kingdom
    104285: 06/06/22: Re: RS232 to access TX registers of Aurora
    104321: 06/06/23: Re: stimulus for FPGA
    104468: 06/06/28: Re: is picoblaze worth in my project?
    104710: 06/07/04: Re: Chaos in FF metastability
    104743: 06/07/05: Re: Chaos in FF metastability
    104905: 06/07/09: Re: Can I use all 18bits of a BlockRAM?
    104918: 06/07/09: Re: Chaos in FF metastability
    104919: 06/07/09: Re: PCI IOs, tiofoi, source sampling bypass
    105044: 06/07/12: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
    105067: 06/07/12: Re: Assigning unused pins in Quartus II
    105306: 06/07/19: Re: Which PCI core for Cyclone II board?
    109321: 06/09/23: Re: X4000 bad configuration
    109598: 06/09/29: Re: state machine dead problem
    109651: 06/10/02: Re: LatticeMico32 extremly poor performance without caches
    109847: 06/10/06: Re: Design of a programmable delay line
    123278: 07/08/22: Re: ML401 (Virtex 4 development board) as a USB peripheral
    123283: 07/08/22: Re: Power Reduction Strategy
    123284: 07/08/22: Re: ML401 (Virtex 4 development board) as a USB peripheral
    123365: 07/08/24: Re: Speed test between FPGA and DSP or PC.
    123649: 07/08/31: Re: what does asynchronous loop mean?
    123702: 07/09/02: Re: PCB Impedance Control
    123703: 07/09/02: Re: PCB Impedance Control
    123793: 07/09/04: Re: Multiple CPLDs on a PCB.
    123835: 07/09/05: Re: PCB Impedance Control
    123861: 07/09/06: Re: high bandwitch ethernet communication
    123927: 07/09/07: Re: Clock boundary crossing
    123960: 07/09/07: Re: high bandwitch ethernet communication
    123961: 07/09/07: Re: high bandwitch ethernet communication
    124044: 07/09/11: Re: Uses of Gray code in digital design
    124145: 07/09/12: Re: Uses of Gray code in digital design
    124184: 07/09/13: Re: Uses of Gray code in digital design
    124187: 07/09/13: Re: Uses of Gray code in digital design
    124365: 07/09/19: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124366: 07/09/19: Re: FPGA history
    124370: 07/09/19: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124374: 07/09/19: Re: Gated Clock Problems
    124375: 07/09/19: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124380: 07/09/20: Re: Clock boundary crossing
    124399: 07/09/20: Re: Gated Clock Problems
    124401: 07/09/20: Re: Gated Clock Problems
    124404: 07/09/20: Re: Clock boundary crossing
    124411: 07/09/20: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124412: 07/09/20: Re: hardware software codesign
    124433: 07/09/21: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124442: 07/09/21: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124445: 07/09/21: Re: Gated Clock Problems
    124522: 07/09/25: Re: Own soft-processor
    124532: 07/09/25: Re: Never buy Altera!!!!
    124538: 07/09/26: Re: Never buy Altera!!!!
    124568: 07/09/26: Re: Logic minimization software with LUT6 support?
    124600: 07/09/27: Re: Basic questions about the Nios II.
    124632: 07/09/28: Re: Never buy Altera!!!!
    124634: 07/09/28: Re: Programming the ARM7 used to download our Xilinx FPGA
    124648: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124650: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    125320: 07/10/21: Re: Own soft-processor
    125371: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
    125808: 07/11/05: Re: FPGA I/O Selection in UCF
    126039: 07/11/13: Re: Structured way of changing eg time constants for real world build / simulation?
    126241: 07/11/17: Re: Quartus II warning: "pass-through logic has been added"
    126246: 07/11/17: Re: Quartus II warning: "pass-through logic has been added"
    126335: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
    126451: 07/11/22: Re: DCM with instable clock
    127776: 08/01/07: Re: Where are the LCD or OLED bitmapped displays?
    128022: 08/01/13: Re: Real examples of metastability causing bugs
    128159: 08/01/17: Re: Basic FPGA question about Reset
    128206: 08/01/18: Re: Basic FPGA question about Reset
    128253: 08/01/19: Re: Source of accurate frequency
    128254: 08/01/19: Re: Source of accurate frequency
    128261: 08/01/19: Re: Source of accurate frequency
    128271: 08/01/19: Re: Source of accurate frequency
    128276: 08/01/19: Re: Source of accurate frequency
    128277: 08/01/20: Re: How is FIFO implemented in FPGA and ASIC?
    128278: 08/01/20: Re: Debbuging a RISC processor on an FPGA
    128282: 08/01/20: Re: Source of accurate frequency
    128313: 08/01/22: Re: Source of accurate frequency
    128357: 08/01/22: Re: FPGA decoupling calculation
    128454: 08/01/27: Re: FPGA decoupling calculation
    128463: 08/01/27: Re: FPGA decoupling calculation
    131320: 08/04/18: Re: Survey: FPGA PCB layout
    133130: 08/06/18: Re: Synthesis results when testing for 'X' and 'U'
    133141: 08/06/19: Re: Synplify beeping
    133365: 08/06/26: Re: Configuration Management Best Practices
    133503: 08/07/01: Re: How do I program an fpga once it has been designed and layout is complete
    133666: 08/07/09: Re: Virtex 4 expected production end-of-life
    133836: 08/07/16: Re: Xilinx/Altera gate equivalence
    136277: 08/11/09: Re: RS-232 Bus controller design in VHDL
    136291: 08/11/10: Re: How to handle the problem "timing constraint not met"?
    136317: 08/11/11: Re: How to handle the problem "timing constraint not met"?
    136318: 08/11/11: Re: Data transfer between CPU and FPGA over PCI bus
    136329: 08/11/11: Re: How to handle the problem "timing constraint not met"?
    136431: 08/11/16: Re: Digilent Spartan3e starter kit, Not working.
    136433: 08/11/16: Re: Digilent Spartan3e starter kit, Not working.
    136475: 08/11/18: Re: Aligned PLL clocks in RTL simulation
    136553: 08/11/21: Re: Generate sample rate ...
    136562: 08/11/22: Re: Generate sample rate ...
    136563: 08/11/22: Re: Generate sample rate ...
    136676: 08/11/30: Re: How to evaluate program efficiency/functionality
    136714: 08/12/02: Re: reading registers
    136722: 08/12/03: Re: Hold Time Requirement
    136739: 08/12/03: Re: Dynamical alteration of signal path
    136746: 08/12/03: Re: Relationship between high and low speed clocks
    136755: 08/12/03: Re: Relationship between high and low speed clocks
    136769: 08/12/04: Re: Relationship between high and low speed clocks
    136770: 08/12/04: Re: Hold Time Requirement
    136933: 08/12/14: Re: FIFO with External Memory
    136935: 08/12/14: Re: FIFO with External Memory
    137042: 08/12/20: Re: FPGA partial/catastrophic failure mode question
    137052: 08/12/21: Re: Bit width in CPU cores
    137068: 08/12/21: Re: Bit width in CPU cores
    137069: 08/12/21: Re: FPGA for Contoll
    137098: 08/12/23: Re: Bit width in CPU cores
    137099: 08/12/23: Re: Bit width in CPU cores
    137113: 08/12/23: Re: DFFR using DFF (only, may be extra gates)
    137221: 09/01/03: Re: time limited netlist generation
    137226: 09/01/04: Re: Xilinx QUIZ 2008
    137395: 09/01/14: Re: ttl compatible
    137564: 09/01/22: Re: rank beginner here, need to know where to start to get RS232 comm's working, and ...
    137565: 09/01/22: Re: FPGA granularity
    137723: 09/01/28: Re: What software do you use for PCB with FPGA ?
    137866: 09/02/01: Re: Heavily pipelined design
    138089: 09/02/06: Re: Xilinx Powerpc issue with custom peripherals
    138127: 09/02/06: Re: Rotary Encoder - Microblaze and ML505
    138174: 09/02/08: Re: Is this phase accumulator trick well-known???
    138188: 09/02/09: Re: Experiencing problems when moving an FPGA-based implementation to an ASIC
    138496: 09/02/25: Re: mb-gcc producing incorrect code ???
    138511: 09/02/25: Re: Configure FPGA via PCIe
    138512: 09/02/25: Re: mb-gcc producing incorrect code ???
    138531: 09/02/26: Re: Send data from FPGA to PC via USB
    138548: 09/02/26: Re: mb-gcc producing incorrect code ???
    138549: 09/02/26: Re: Configure FPGA via PCIe
    138569: 09/02/27: Re: Configure FPGA via PCIe
    138570: 09/02/27: Re: mb-gcc producing incorrect code ???
    138611: 09/03/02: Re: Configure FPGA via PCIe
    138612: 09/03/02: Re: Character generator ROM and VGA controller for Spartan 3E
    138689: 09/03/04: Re: Warning Search Engine Links
    138715: 09/03/05: Re: writing current date to a register
    138867: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138870: 09/03/12: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
    138963: 09/03/17: Re: Zero operand CPUs
    138978: 09/03/17: Re: Zero operand CPUs
    138980: 09/03/17: Re: Zero operand CPUs
    138981: 09/03/17: Re: Zero operand CPUs
    139040: 09/03/19: Re: Xilinx XAPP052 LFSR and its understanding
    139046: 09/03/19: Re: Bullshit! - Re: Zero operand CPUs
    139167: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on the chip.
    139236: 09/03/24: Re: ERROR:Pack:1564 on Virtex 4
    139239: 09/03/24: Re: Silicon Blue last datesheet correct URL
    141630: 09/07/01: Re: How to keep documentation of control and status registers and VHDL code in sync
    141823: 09/07/10: Re: How to implementa an FSM in block ram
    141870: 09/07/14: Re: How to initialize a Rom with a list of coefficients
    141912: 09/07/16: Re: How to implementa an FSM in block ram
    141916: 09/07/16: Re: Do you prefer paper or plastic... er, I mean paper or e-books?
    141917: 09/07/16: Re: Generating a negated clock
    141918: 09/07/16: Re: Using DCMs in a spartan 3 FPGA
    141919: 09/07/16: Re: How to implementa an FSM in block ram
    141922: 09/07/17: Re: How to implementa an FSM in block ram
    144881: 10/01/11: Re: How to gracefully terminate the PCIe read request
    144897: 10/01/13: Re: How to gracefully terminate the PCIe read request
    145259: 10/02/03: Re: What is the most area efficient CRC method
    145350: 10/02/06: Re: Matching hadware and software CRC
    149617: 10/11/11: Re: cool BGA pattern
    149864: 10/11/29: Re: Multiple clock domains
    150107: 10/12/14: Re: ISIM simulation speed
    150342: 11/01/11: Re: FPGA to PHY/MAC chip
    150362: 11/01/12: Re: FPGA to PHY/MAC chip
    150789: 11/02/10: Re: Simple clock question
    150797: 11/02/11: Re: Simple clock question
    150821: 11/02/15: Re: Simple clock question
    150860: 11/02/16: Re: PLD suggestions for classroom use
    151004: 11/02/28: Re: Simulating mutiplication of 'X' with '0'
    151306: 11/03/22: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
    151322: 11/03/22: Re: SRL as a synchroniser
    151434: 11/04/07: Re: Ethernet MAC on Virtex 4
    151471: 11/04/12: Re: Source of Dynamic Power Consumption in FPGAs
    151640: 11/04/29: Re: same RTL on two same boards giving different behaviour
    151655: 11/05/02: Re: help with a power pc processor based software
    152170: 11/07/15: Re: Looking for a FPGA board
    152856: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    153064: 11/11/24: Re: XC7V2000T, the perfect Thanksgiving gift
    153159: 11/12/16: Re: Clock distribution for ADC and jitter
    153729: 12/05/01: Re: Smallest GPL UART
    153744: 12/05/04: Re: Smallest GPL UART
    153747: 12/05/04: Re: Smallest GPL UART
    153800: 12/05/23: Re: Logic Glitches in Spartan-3?
    153979: 12/07/06: Re: accumulator (again)
    154194: 12/09/03: Re: Delay in Verilog for Asics design which is synthesizable
    155016: 13/03/28: Re: What a Xilinx fpga could do in 1988
    155974: 13/10/31: Re: reset strategy FPGA Igloo
    156108: 13/11/23: Re: microZed adventures
    156456: 14/04/08: Re: on-chip bypass caps
    156567: 14/05/02: Re: Old Spartan-II demo board from Insight - seeking docs..
    156681: 14/06/03: Re: ECG signals Compression/Decompression
    156698: 14/06/05: Re: ECG signals Compression/Decompression
    156735: 14/06/09: Re: 22V10 programmer
    156909: 14/07/26: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
    156910: 14/07/26: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
    156959: 14/08/07: Re: strange effect with tristate output
<Hal.Turner@HalTurnerShow.com>:
Halit Evli:
    10791: 98/06/19: [Fwd: FPGA-Express Probs]
    10790: 98/06/19: FPGA-Express Probs
HALL Daniel:
    12292: 98/10/08: Re: Help Desperately Needed with Altera Microprocessor Design.
Hall Kinion:
    7671: 97/10/01: postings
halong:
    139151: 09/03/22: Re: DVI in FPGA
    139505: 09/04/01: Re: DCM vs PLL
    139783: 09/04/13: Re: Xilinx ISE bug, or?
    139822: 09/04/15: Re: S3A starterkit weird behaviou (mini quiz)
    140166: 09/05/01: Re: Xilinx ground pin
    140441: 09/05/13: Re: I don't like Xilinx
    140449: 09/05/13: Re: which low cost fpga for space?
    140808: 09/05/26: Re: Architecture of FPGA
Hamid Kavianathar:
    158553: 15/12/23: FPGA for a beginner
    158555: 15/12/23: Re: FPGA for a beginner
    158557: 15/12/23: Re: FPGA for a beginner
    158559: 15/12/25: Re: FPGA for a beginner
    158614: 16/02/03: watermarking on FPGA
    158615: 16/02/03: Re: watermarking on FPGA
Hamilton:
    4722: 96/12/06: Name this chip !!
hamilton:
    5022: 97/01/13: Re: Efficient DES Keysearch
    21354: 00/03/18: Re: UPDATED ENGINEERING PAGE: Please Visit
    48705: 02/10/22: Re: Altera FPGA and EPLD Download ByteBlaster
    52402: 03/02/07: Re: Contract Rates?
    60182: 03/09/07: Re: Low-cost FPGA Development Board with built-in Computer core
    60184: 03/09/07: Re: CMOS camera w/ USB2 -- crazy?
    65009: 04/01/18: WTD: info on AMD palce22v10
    65058: 04/01/19: Re: info on AMD palce22v10
    65382: 04/01/26: Re: isp Cable for Lattice CPLD
    66733: 04/02/25: Re: SmartMedia writer (implments using VHDL)....
    66829: 04/02/26: Re: SmartMedia writer (implments using VHDL)....
    73830: 04/09/29: Re: embedded linux on FPGA?
    73910: 04/09/30: Re: embedded linux on FPGA?
    73612: 04/09/25: Re: Looking for a Design for a Small FPGA Board
    75014: 04/10/24: Re: PacoBlaze 1.3b
    147226: 10/04/19: Re: Need to run old 8051 firmware
    148195: 10/06/26: Re: Free bitmap font
    148199: 10/06/26: Re: Free bitmap font
    152951: 11/11/03: Re: Fundamental DSP/speech processing patent for sale
    154151: 12/08/21: PKzip cracker
    154209: 12/09/09: Re: Looking for an extremely cheap FPGA board (in quantity, academic
    154213: 12/09/09: Re: Looking for an extremely cheap FPGA board (in quantity, academic
    154217: 12/09/10: Re: Looking for an extremely cheap FPGA board (in quantity, academic
    154310: 12/09/25: Re: Getting in to the industry
    154321: 12/09/27: Replacing Logic with an FPGA/CPLD in a 510K device.
    154644: 12/12/09: Re: Where to move for an embedded software engineer.
    154655: 12/12/12: Re: Where to move for an embedded software engineer.
    154667: 12/12/14: Re: Where to move for an embedded software engineer.
    154956: 13/03/03: IP for SDIO serial port
    155094: 13/04/11: Re: IP for SDIO serial port
    155126: 13/04/24: Low cost and/or small size CPU in an FPGA
    155130: 13/04/24: Re: Low cost and/or small size CPU in an FPGA
    155150: 13/05/01: Re: Low cost and/or small size CPU in an FPGA
    155351: 13/06/24: Re: FPGA Exchange
    155807: 13/09/18: Re: Legal Issues Reproducing Old CPU
    156065: 13/11/21: Re: FPGA Cryptosystem
    156281: 14/02/05: Re: Jobs going in New Zealand
    156724: 14/06/08: 22V10 programmer
    156731: 14/06/09: Re: 22V10 programmer
    156734: 14/06/09: Re: 22V10 programmer
    156739: 14/06/10: Re: 22V10 programmer
    156748: 14/06/15: Re: 22V10 programmer
    156758: 14/06/18: Re: NAND flash interface through FPGA
    157168: 14/10/23: Re: Altera 100-pins chip
    157465: 14/12/11: Re: Using FPGA to feed 80386
    157518: 14/12/14: Re: Using FPGA to feed 80386
    157563: 14/12/16: Re: Using FPGA to feed 80386
    157570: 14/12/16: Re: Using FPGA to feed 80386
    157571: 14/12/16: Re: Using FPGA to feed 80386
    157573: 14/12/16: Re: Using FPGA to feed 80386
    158126: 15/08/13: Re: Finally! A Completely Open Complete FPGA Toolchain
Hamish Moffatt:
    7760: 97/10/12: free router for Xilinx 3000?
    10477: 98/05/21: Re: FPGA-based CPUs (was Re: Minimal ALU instruction set)
    10602: 98/06/05: Re: TESTBENCH
    11211: 98/07/26: Re: Schematic Symbol Generation
    11903: 98/09/17: programming via RS-232
    11956: 98/09/21: Re: programming via RS-232
    14232: 99/01/21: Re: Free max+plus ll simulator on win95
    14549: 99/02/04: Re: Off topic DRAM/SIMM question....
    14601: 99/02/06: dual port RAM on XC4000
    14609: 99/02/06: Re: dual port RAM on XC4000
    14629: 99/02/07: Re: dual port RAM on XC4000
    14630: 99/02/07: Re: dual port RAM on XC4000
    14639: 99/02/08: xc4000 obselete to xc4000e
    14711: 99/02/12: M1 error message
    14714: 99/02/12: Re: M1 error message
    14731: 99/02/13: M1 problems with TDO pin
    14851: 99/02/20: Re: "Altera FreeCore Library" back on the web
    15105: 99/03/07: Re: Student edition!
    15467: 99/03/25: Re: Free Xilinx Vendor Tools ... NOT :-(
    15526: 99/03/29: Re: Free Xilinx Vendor Tools ... NOT :-(
    15811: 99/04/15: Re: Obsolete Xilinx series - how to use them?
    36007: 01/10/26: Re: transferring data between related clocks
    75881: 04/11/18: Async and sync resets
    75915: 04/11/19: Re: Async and sync resets
    75916: 04/11/19: Re: Async and sync resets
    75925: 04/11/20: Re: Async and sync resets
    76024: 04/11/23: Re: Async and sync resets
    76121: 04/11/26: Re: Async and sync resets
Hamish Moffatt VK3SB:
    28484: 01/01/15: Re: revision control tools ??
    28515: 01/01/16: Re: revision control tools ??
    28565: 01/01/17: Re: revision control tools ??
    28612: 01/01/18: Re: revision control tools ??
    30661: 01/04/22: Re: PAR single pass vs multi-pass differences
Hamish Shufflebotham:
    135654: 08/10/11: Re: XMOS XC-1 kits are shipping
    135657: 08/10/11: Re: XMOS XC-1 kits are shipping
    135659: 08/10/11: Re: XMOS XC-1 kits are shipping
    135680: 08/10/12: Re: DDR FLOP?
    135682: 08/10/12: Re: XMOS XC-1 kits are shipping
<hamish@cloud.net.au>:
    31092: 01/05/11: Nasty "register ordering" in map
    31143: 01/05/13: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
    31210: 01/05/15: Re: Nasty "register ordering" in map
    31211: 01/05/15: Re: free simulator
    31213: 01/05/15: Re: Virtex-2 - experiences ?
    31351: 01/05/20: Re: Nasty "register ordering" in map
    31352: 01/05/20: Re: Xilinx Service Pack 8 Now Available
    31402: 01/05/22: Re: RLocs on Inferred registers??
    31429: 01/05/23: Re: RLocs on Inferred registers??
    31955: 01/06/09: Re: Force tristate enable register into IOB
    31956: 01/06/09: Re: Force tristate enable register into IOB
    32155: 01/06/16: Re: From EDF to VHDL?
    32299: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
    32300: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
    32418: 01/06/26: Re: Xilinx Configuration Bitstream
    32419: 01/06/26: Re: Register balancing in FPGA Express
    34063: 01/08/13: Re: Q: Revision and Database Control for FPGA Designs
    34064: 01/08/13: Re: how to acheive high frquency in Xinlinx Virtex E
    34100: 01/08/14: Re: Q: Revision and Database Control for FPGA Designs
    34142: 01/08/15: Re: Q: Revision and Database Control for FPGA Designs
    34303: 01/08/20: Re: Internal clock skew when using DLL
    34304: 01/08/20: Re: Spartan2 5V PCI IO
    34354: 01/08/22: Re: Slowing PCI for FPGA
    34462: 01/08/26: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
    34660: 01/09/02: Re: Xilinx Device Update under Solaris
    34698: 01/09/04: Re: Xilinx Device Update under Solaris
    34727: 01/09/05: Re: Special counter for scheduling
    34755: 01/09/06: Re: Special counter for scheduling
    34949: 01/09/15: Re: Block RAM initialization
    35135: 01/09/23: Re: how to simulate virtex components?
    35136: 01/09/23: Re: Synplicity logic replication
    35137: 01/09/23: Re: Clockin on rising AND falling edge
    35225: 01/09/26: Re: how to simulate virtex components?
    35330: 01/09/29: Re: Xilinx 4.1 software
    35403: 01/10/03: Re: Virtex II current consumption
    35427: 01/10/04: Re: Virtex II current consumption
    35495: 01/10/08: Re: ROM based FSMs
    35679: 01/10/13: Re: future Xilinx products wish list ...
    35698: 01/10/14: Re: future Xilinx products wish list ...
    35699: 01/10/14: Re: Instantiating Virtex II library macros.
    35745: 01/10/16: Re: Instantiating Virtex II library macros.
    35857: 01/10/21: Re: Verilog vs. VHDL
    35931: 01/10/24: Re: Verilog vs. VHDL
    35932: 01/10/24: Re: Verilog vs. VHDL
    35970: 01/10/25: transferring data between related clocks
    36075: 01/10/28: Re: transferring data between related clocks
    36354: 01/11/07: Re: Synplicity, Xilinx, & unwanted BUFGs
    36526: 01/11/11: Re: Synplicity, Xilinx, & unwanted BUFGs
    36527: 01/11/11: Re: Xpower and vcd files
    36528: 01/11/11: Re: Hex numbers in VHDL
    36529: 01/11/11: Re: How to set timing constraint in Xilinx VirtexII device when using DCM
    36717: 01/11/17: Re: Virtex 2 parts availability???
    36718: 01/11/17: Re: Clock Divider or Multiplier ???
    36794: 01/11/20: Re: Xilinx Fpga Editor support for Virtex 2...does it exist in 3.x? How about 4.x?
    36826: 01/11/21: Re: don't cares and X's in a case statement?
    36863: 01/11/22: Re: Synplicity & BlockRAMs
    37113: 01/11/30: Re: How to set timing constraint in Xilinx VirtexII device when using DCM
    37160: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
    37161: 01/12/02: Re: What do you like/dislike about place and route tools?
    37222: 01/12/04: Re: How to increase clock skew for Spartan-II
    37223: 01/12/04: Re: Is there a full open-source synthesis path for any FPGA?
    37224: 01/12/04: Re: What do you like/dislike about place and route tools?
    37888: 01/12/23: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
    38006: 01/12/30: Re: Innoveda Speedwave vs. Modelsim?
    38016: 01/12/31: Re: exclude a path in TRACE timing
    38030: 02/01/02: Re: Synplicity to Xilinx hierarchical net names
    38056: 02/01/03: Re: Problem/Question about the timing report on Xilinx ISE 4.1
    38079: 02/01/04: Re: Problem/Question about the timing report on Xilinx ISE 4.1
    38104: 02/01/05: Re: asic vs. fpga
    38358: 02/01/12: Re: [WebPACK or ISE] Mixing Verilog and EDIF?
    38359: 02/01/12: Re: Avoid routing through a certain area (Xilinx)
    38361: 02/01/12: Re: bufg instantiation in ISE 4.1
    38365: 02/01/12: Re: Repost: Should clock skew be included for setup time analysis?
    38376: 02/01/13: Re: Repost: Should clock skew be included for setup time analysis?
    38377: 02/01/13: Re: Repost: Should clock skew be included for setup time analysis?
    38463: 02/01/15: Re: CLKDLL cascade questions
    38464: 02/01/15: Re: Falling edge in PLD
    38465: 02/01/15: Re: Repost: Should clock skew be included for setup time analysis?
    38466: 02/01/15: Re: Repost: Should clock skew be included for setup time analysis?
    38516: 02/01/16: Re: Repost: Should clock skew be included for setup time analysis?
    38517: 02/01/16: Re: Repost: Should clock skew be included for setup time analysis?
    38519: 02/01/16: Re: Synthesis: Protel 99SE to XC2S200
    38633: 02/01/20: Re: Repost: Should clock skew be included for setup time analysis?
    38758: 02/01/24: Re: Repost: Should clock skew be included for setup time analysis?
    39151: 02/02/02: Re: Linking IP
    39152: 02/02/02: Re: MUX with or without clk ??
    39254: 02/02/05: Re: Coregen & PAR
    39255: 02/02/05: Re: RAM question
    39311: 02/02/06: Re: FPGA vs GAL : Lattice
    39400: 02/02/08: Re: Xilinx ISE 3.3 upgrade to 4.1
    39401: 02/02/08: Re: Xilinx ISE 3.3 upgrade to 4.1
    39551: 02/02/13: Re: par and carry chains not allowing manual floorplanning
    39552: 02/02/13: Re: par and carry chains not allowing manual floorplanning
    39554: 02/02/13: Re: spi4-02.0
    39694: 02/02/16: Re: Modelsim questions
    39695: 02/02/16: Re: Xilinx ISE 3.3 upgrade to 4.1
    40384: 02/03/06: Re: exceeding 2GB limits in xilinx
    40438: 02/03/07: Re: exceeding 2GB limits in xilinx
    40557: 02/03/10: Re: exceeding 2GB limits in xilinx
    40707: 02/03/13: Re: Pointer Processor for OC192
    40836: 02/03/16: Re: XST duplicates unnecessary IOB OE FFs
    40867: 02/03/17: Re: Extracting schematics to a vector file
    40870: 02/03/17: Re: XST duplicates unnecessary IOB OE FFs
    41340: 02/03/26: Re: XST duplicates unnecessary IOB OE FFs
    41566: 02/04/02: Re: A petition for Synplify's new fature (FPGA synthesis tool)
    42761: 02/05/02: Re: SpartanII design considerations...
    42837: 02/05/04: Re: SpartanII design considerations...
    42838: 02/05/04: Re: Xilinx 2GB limit... something has to be done
    42925: 02/05/07: Re: Timing Scores
    42955: 02/05/08: Re: PAR warnings and errors
    42956: 02/05/08: Re: Xilinx 2GB limit... something has to be done
    43048: 02/05/10: Re: PAR warnings and errors
    43424: 02/05/21: Re: RPMs
    43538: 02/05/23: Re: P&R times
    43540: 02/05/23: Re: Time for a new computer. Suggestions?
    43764: 02/06/01: Re: Timing Analyzer lockups
    43884: 02/06/05: Re: OFFSET timing contraints
    43959: 02/06/07: Re: IOSTANDARD
    43960: 02/06/07: Re: xc3042
    43961: 02/06/07: Re: Xilinx guided PAR problem
    44235: 02/06/14: Re: MAP problem with RLOC'ed macros
    44304: 02/06/17: Re: Xilinx ISE BaseX... What is it?
    44639: 02/06/25: Re: Bad Virtex2 devices - any similar experiences
    44915: 02/07/05: Re: Maximum frequency in Virtex and Virtex-E Devices
    45435: 02/07/23: Re: Xilinx ISE 4.2i Is A Step Backwards! Beware!!!
    45689: 02/08/01: Re: timing got worse?
    45751: 02/08/04: Re: Safe design speed
    45842: 02/08/07: Re: New XILINX ISE not supporting 4000 series FPGAs?
    45911: 02/08/10: Re: ... milk for free, Opencores?
    45912: 02/08/10: Re: xilinx RLOC usage
    45926: 02/08/11: Re: xilinx RLOC usage
    46283: 02/08/24: Re: How to include Xilinx library for both ModelSim and Synplify?
    46286: 02/08/24: Re: upgrade S/W -> timing worse
    46300: 02/08/25: Re: upgrade S/W -> timing worse
    47206: 02/09/20: Re: ieee.math_real for presynthesis table calculation in vhdl
    47215: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
    47240: 02/09/21: Re: Xilinx ISE5.1 and Windows NT
    47241: 02/09/21: Re: Xilinx ISE5.1 and Windows NT
    47695: 02/10/02: Re: RPM_GRID (was MAP problem: Trivial RPM fails)
    47696: 02/10/02: Re: question on ISE 5.1 and SMP machines...
    47697: 02/10/02: Re: Unpredictable Place and Route
    47698: 02/10/02: Re: Xilinx ISE5.1 and Windows NT
    47861: 02/10/06: Re: ANN: Embedded processor for Tcl language
    47862: 02/10/06: Re: question on ISE 5.1 and SMP machines...
    47870: 02/10/06: Re: ANN: Embedded processor for Tcl language
    47871: 02/10/06: Re: ANN: Embedded processor for Tcl language
    48004: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
    48150: 02/10/12: Re: Why can Xilinx sw be as good as Altera's sw?
    48151: 02/10/12: Re: Why can Xilinx sw be as good as Altera's sw?
    48152: 02/10/12: Re: how do initialised signals really get set in Xilinx slices?
    48256: 02/10/15: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
    48532: 02/10/19: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
    48643: 02/10/22: Re: Floorplanner RPM. How to use it?
    48644: 02/10/22: Re: Floorplanner RPM. How to use it?
    48715: 02/10/23: Re: High Performance FPGA's - Xilinx and ??????
    49132: 02/11/01: Re: FDRE inference in Synplify
    49490: 02/11/13: Re: How to disable IOB register packing?
    49492: 02/11/13: Re: Tristate buffers + leonardo Spectrum
    49588: 02/11/16: Re: Webpack and Virtex Pro?
    49736: 02/11/20: Re: Webpack and Virtex Pro?
    49737: 02/11/20: Re: Virtex is the 4th Xilinx Fpga generation
    50635: 02/12/15: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
    50638: 02/12/15: Re: RPM Using ISE5.1i FloorPlanner
    50639: 02/12/15: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    51681: 03/01/19: Re: XST vs Synplify observations
    51886: 03/01/24: Re: Parsing Xilinx Timing Reports
    51887: 03/01/24: Re: VHDL or Verilog?
    52129: 03/02/02: Re: Virtex-II and LVDS clocks.
    52426: 03/02/09: Re: Virtex-II Pro PowerPC cache memory as main program/data storage?
    52598: 03/02/15: Re: Xilinx Foundation 5.1: reasons to upgrade
    52683: 03/02/19: Re: Xilinx multi-cycle constraints report
    52806: 03/02/23: Re: Xilinx multi-cycle constraints report
    53269: 03/03/09: Re: Using Xilinx DCM's (DLL) with RESET tied to GND is dangerous!!
    53977: 03/03/29: Re: CLKDLL synthesized with synplify pro
    57129: 03/06/24: Transfer between clock domains at 350 MHz
    57168: 03/06/24: Re: Transfer between clock domains at 350 MHz
    57172: 03/06/25: Re: Transfer between clock domains at 350 MHz
    57173: 03/06/25: Re: Transfer between clock domains at 350 MHz
    57311: 03/06/27: Re: Xilinx par at max effort
    57314: 03/06/27: Re: Xilinx Webpack bugs bugs bugs
    57353: 03/06/28: Re: why so many problems Xilinx ?
    57354: 03/06/28: Re: ModelSim 5.7 and xilinx libraries
    57413: 03/06/30: Re: Schematics, was : Re: Xilinx Webpack bugs bugs bugs
    57414: 03/06/30: Re: SPARTAN-3 vs. VIRTEX-II
    57470: 03/07/01: Re: MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk) or BUFGP symbol "u1" (output signal=u1), IPAD-IBUFG should only be LOC'd to GCLKIOB site."
    57634: 03/07/03: Re: Xilinx ISE drops support for more parts
    57739: 03/07/05: Re: Xilinx ISE drops support for more parts
    57742: 03/07/05: Re: Why not DDR in FPGAs?
    57743: 03/07/05: Re: Excel and FPGA's
    57985: 03/07/11: Re: Xilinx ISE drops support for more parts
    58174: 03/07/16: Re: Xilinx ISE drops support for more parts
HamishR:
    89435: 05/09/14: Re: Migration Altera APEX20KE to ???
hamkanen:
    150514: 11/01/25: Zero Padding Circuit Design
<42hammer@gmail.com>:
    103036: 06/05/24: Embedded Programming of Altera EPCS device
hammouda:
    120934: 07/06/20: ML402 card (video starter kit) : Read/write on the ddr
    120937: 07/06/20: Re: ML402 card (video starter kit) : Read/write on the ddr
Hampus Thorell:
    104584: 06/06/30: lwIP on Xilinx Virtex 2 Pro
    104642: 06/07/03: LwIP
hamze60:
    140360: 09/05/11: which low cost fpga for space?
    140363: 09/05/11: Re: difficulty during processing
    140527: 09/05/15: Re: which low cost fpga for space?
Han Phan:
    122508: 07/07/29: Odelay usage in virtex5
    122522: 07/07/30: Re: Odelay usage in virtex5
Han, MT:
    38246: 02/01/09: Where to buy Altera APEX20K with reasonable price?
Hananiel Sarella:
    36916: 01/11/26: FFT with Distributed Arithmatic
    36964: 01/11/27: Re: FFT with Distributed Arithmatic
    36966: 01/11/27: Re: FFT with Distributed Arithmatic
    37186: 01/12/03: Benchmarking RC
handi:
    14607: 99/02/05: Fpga Express and Xilinx Alliance1.5 questions
handyman:
    106872: 06/08/21: Configuring an Altera Serial Prom/Flash using a 8051 CPU
Haneef D. Mohammed:
    18422: 99/10/23: Announcing Free VHDL Simulator for Windows
    18430: 99/10/23: Re: Announcing Free VHDL Simulator for Windows
    18433: 99/10/23: Re: Announcing Free VHDL Simulator for Windows
    18480: 99/10/26: Re: Announcing Free VHDL Simulator for Windows
    18487: 99/10/27: Re: Announcing Free VHDL Simulator for Windows
    18501: 99/10/27: Looking for exemplar_1164 package
    18507: 99/10/28: Re: Looking for exemplar_1164 package
    18564: 99/10/31: Re: Announcing Free VHDL Simulator for Windows
    18980: 99/11/22: VHDL Simili from Symphony EDA adds support for Xilinx libraries
Haneef Mohammed:
    39341: 02/02/07: Announce: VHDL Simili 2.0 - Graphics, Windows, Linux, Affordable
    39361: 02/02/07: Re: Announce: VHDL Simili 2.0 - Graphics, Windows, Linux, Affordable
    39388: 02/02/08: Re: Announce: VHDL Simili 2.0 - Graphics, Windows, Linux, Affordable
hanifkagdi:
    97958: 06/03/02: rocketio in serdes mode
Hank:
    71043: 04/07/06: spartan3 board for newbie: xilinx XC3S200 starter kit or nu-horizons XC3S400 board???
    71155: 04/07/10: xilinx spartan 3 $99 board...help
    71157: 04/07/10: Re: xilinx spartan 3 $99 board...help
    71158: 04/07/10: Re: xilinx spartan 3 $99 board...help
    71217: 04/07/12: Re: Programable Logic & Video stuff
Hank Wallace:
    2476: 95/12/13: Your PLD/FPGA Experiences Needed for Article
Hank777:
    10038: 98/04/23: Prototype building help wtd in return for equity in cool new product
    11476: 98/08/18: QAM/QPSK guru wanted by garage startup
    12068: 98/09/27: Sweat equity engineer needed for consumer electronics hardware
Hanks Lee:
    43622: 02/05/27: XC95288 Programming
Hanna Bruno:
    25200: 00/08/30: More than 4 clocks in virtex
    25251: 00/09/01: Re: More than 4 clocks in virtex
    25926: 00/09/26: Re: Global clock buffers and secondary clock buffers.
Hannu Ylioja:
    31982: 01/06/10: Re: Help in FIFO design
Hans:
    3161: 96/04/17: Re: Actel ACT1 Slow Rise Time
    3173: 96/04/18: Re: high gate count FPGA for small volumn production?
    7511: 97/09/18: Re: PIC Model
    7772: 97/10/14: Re: VHDL Simulation
    8543: 98/01/07: Synthesize large LUT
    8596: 98/01/12: Re: Synthesize large LUT
    8786: 98/01/27: Re: Radhard FPGA Vendors?
    9468: 98/03/16: Re: Suggestions on synthesis/simulation packages under $10K
    9615: 98/03/26: Re: Looking for space qualified FPGAs/ASICs
    9788: 98/04/05: Re: Rees-Solomon
    10193: 98/05/03: Re: Need to duplicate Actel A1020B-PL84C
    11329: 98/08/05: Re: Silicore VHDL 8-bit RISC uC core for FPGA
    11339: 98/08/05: Re: Silicore VHDL 8-bit RISC uC core for FPGA
    12061: 98/09/26: Re: Design Security Question
    12366: 98/10/10: Re: Altera's reply to request for Max+Plus II under Linux
    12791: 98/10/29: Re: 8B/10B Encoder Decoder
    13135: 98/11/17: Re: Modifying Disk serial number in boot sector....anyone have any problems with it?
    13599: 98/12/11: Re: Synthesis with Actel
    13956: 99/01/05: Re: PLL in FPGAs?
    14730: 99/02/13: Re: Supercomputer uses 280 Xilinx FPGAs
    15208: 99/03/13: Re: Actel FPGA
    16839: 99/06/13: Re: Digital filters in VHDL
    17454: 99/07/29: Re: Microcomputer buses for use inside FPGA/ASIC devices?
    17481: 99/07/30: Re: Microcomputer buses for use inside FPGA/ASIC devices?
    17923: 99/09/17: Re: simple UART for ACTEL (SX) wanted
    19241: 99/12/08: Re: hobbyist friendly pld?
    24176: 00/07/28: Foreign generated EDIF file in Foundation 2.1i
    34298: 01/08/20: JTAG
    53084: 03/03/03: Re: FPGA demo board schematic
    53909: 03/03/27: Re: Anyone have difficulty downloading this core?
    54083: 03/04/02: Re: Shove a binary file into Xilinx 4.2 as input for testing...
    55443: 03/05/08: Re: Modelsim generating (Sigsegv BadPointer Access)-error on winXP
    57976: 03/07/11: Re: Leonardo changes name of lpm megafunction
    60677: 03/09/19: Re: ISE 6.1 and Redhat 9
    60731: 03/09/20: Re: ISE 6.1 and Redhat 9
    62081: 03/10/18: Re: simple project needed
    62751: 03/11/06: Re: Tools Tree
    63491: 03/11/23: Laptop without serial/parallel port
    63554: 03/11/25: Re: Laptop without serial/parallel port
    63954: 03/12/10: Re: Finding Multicyle Paths in a Design
    68092: 04/03/26: Re: about trouble with attributes in Exemplar Leonardo Spectrum 20001b
    70951: 04/07/02: Re: Running precision on Mandrake 10
    73848: 04/09/30: Re: PSL pros and cons
    72824: 04/09/03: Re: modelsim and rocketio
    72825: 04/09/03: Re: Unisim Library
    72826: 04/09/03: Re: Sentinel dongle no longer detected by Quartus
    73297: 04/09/18: Re: delivering VHDL (RTL) IP core to my customer: how ?
    74953: 04/10/22: Re: ModelSim is ungraceful with my stupidity...
    74162: 04/10/05: Re: 8086 IP-core in VHDL
    75576: 04/11/10: Re: Problem with Nios Development Board (Cyclone)
    75578: 04/11/10: Re: hostid for Actel Designer
    76143: 04/11/25: Re: 386 IP Core
    76727: 04/12/09: Re: Open source FPGA EDA Tools
    77018: 04/12/20: Re: Modelsim Segmentation faults
    78651: 05/02/04: Re: problem with Modelsim 5.8 Xilinx Edition
    83152: 05/04/25: Re: actel blockram the easy way?
    83356: 05/04/28: Re: *RANT* Ridiculous EDA software "user license agreements"?
    83408: 05/04/29: Re: *RANT* Ridiculous EDA software "user license agreements"?
    84446: 05/05/19: Re: Actel Designer on Linux
    85411: 05/06/09: Re: anyone tried the Actel ProASIC3 Starter Kit?
    86526: 05/06/29: Re: Low cost altera board
    86887: 05/07/08: Re: Actel vs. Xilinx and Altera
    86935: 05/07/10: Re: Announce: Impulse C-to-RTL Version 2 now available
    87059: 05/07/14: Re: Wanted Actel ProAsic RAM VHDL models
    89709: 05/09/23: Re: data logging via JTAG?
    89895: 05/09/29: Re: 16-bit microprocessor dore for Actel
    89920: 05/09/30: Re: 16-bit microprocessor dore for Actel
    91014: 05/10/27: Re: Cost to go from FPGA to ASIC
    91143: 05/10/31: Memory usage and ISE
    91629: 05/11/10: Re: Installing FPGA Advantage on Linux machine
    92862: 05/12/08: Re: Free x86 IP-Core is really working!
    92951: 05/12/09: Re: Securing verilog source code
    92952: 05/12/09: Re: Experiences with Actel ProAsic3E and toolchain?
    92953: 05/12/09: Re: VERIFICATION AND TESTING
    93808: 05/12/31: Re: TCL SCRIPT AND VHDL DESIGN
    93809: 05/12/31: Re: call for papers,Expresscard specification?
    93915: 06/01/03: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
    94058: 06/01/05: Re: ModelSim vsim-3601 message
    94137: 06/01/06: Re: Modelsim FLI: Accessing values from large arrays (RAM)
    94154: 06/01/06: Re: Modelsim FLI: Accessing values from large arrays (RAM)
    95176: 06/01/21: Re: Modelsim problem
    95214: 06/01/21: Re: Modelsim problem
    96059: 06/01/29: Re: Digilent FPGA & Handel-C
    96242: 06/02/01: Re: Digilent FPGA & Handel-C
    96241: 06/02/01: Re: Digilent FPGA & Handel-C
    96477: 06/02/04: Re: fpga hardware "breakpoint"
    96722: 06/02/09: Re: MicroBlaze in Spartan 3 playing tuxchess :)
    96771: 06/02/10: Re: ModelSim # Error loading design
    96782: 06/02/10: Re: ModelSim # Error loading design
    97261: 06/02/20: Re: FPGA - software or hardware?
    97494: 06/02/23: Re: Checkpointing PPC Smartmodels in ModelSim 6.0b Issues
    97584: 06/02/24: Re: project validation: best procedures?
    97622: 06/02/24: Re: implement IP TCP Layer in FPGA
    97624: 06/02/24: Re: 8051 IP core with JTAG debugger for FPGA?
    98421: 06/03/09: Re: FPGA imple. of aes
    99789: 06/03/29: Re: free synthesizer to synthesize VHDL to Actel 1280XL FPGA
    99856: 06/03/30: Re: free synthesizer to synthesize VHDL to Actel 1280XL FPGA
    100003: 06/04/01: Re: ModelSim 6.0 missing Structure
    100020: 06/04/01: Re: ModelSim Designer
    100694: 06/04/16: Re: systemc
    100978: 06/04/22: Re: Tcl used in Modelsim?
    101343: 06/04/29: Re: How to see *.vcd file outported from ChipScope from different computer
    101383: 06/04/30: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101441: 06/05/01: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    102177: 06/05/11: Re: Synplify - Not satisfactory results with re-timing option
    102976: 06/05/24: Re: Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4 V4LX25 :)
    103155: 06/05/26: Re: problem programming Altera Cyclone device
    103453: 06/06/02: Re: SystemVeriling Synthesis for Xilinx FPGAs
    104222: 06/06/21: Re: cache aware programming
    104335: 06/06/24: Re: stimulus for FPGA
    104390: 06/06/26: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
    105032: 06/07/12: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II, or any other tool
    105152: 06/07/14: Re: design partition across multiple FPGAs
    105153: 06/07/14: Re: Need for reset in FPGAs
    106071: 06/08/07: Re: Who is your favourite FPGA guru?
    106868: 06/08/21: Re: Modelsim SE Simulation
    108492: 06/09/12: Re: Simulating EDK 8.1i System using ModelSim 6.1e
    108498: 06/09/12: Re: VHDL or Verilog or SystemC?
    109136: 06/09/21: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
    109980: 06/10/09: Re: Quartus II 6.0: System clock has been set back
    110212: 06/10/12: Re: Functional Languages in Hardware
    110351: 06/10/14: Re: Scoreboard and Checker in Testbench?
    110469: 06/10/16: Re: Scoreboard and Checker in Testbench?
    111033: 06/10/27: Re: Survey: simulator usage
    111130: 06/10/30: Re: image processing
    111340: 06/11/01: Re: Rad-hard (neutron/SEU and space) tutorial?
    111978: 06/11/14: Re: Nested Generate Statement in VHDL
    112180: 06/11/17: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    112330: 06/11/20: Re: false path
    112918: 06/12/01: Re: How to save a changed *.wlf file with ModelSim
    113528: 06/12/15: Re: How does FPGA tools infer FIFO
    113886: 06/12/28: Re: What next next big thing coming for HDL?
    113954: 06/12/30: Re: Tools available to split the design into multiple FPGAs.
    114226: 07/01/08: Re: Use Multi-cycle Path or Pipeline?
    114260: 07/01/09: Re: Possibility of 80188 VHDL core
    114358: 07/01/12: Re: Stratix RAM limitations
    114437: 07/01/16: Re: Constraining Multiple clock design
    114598: 07/01/20: Re: SPARC V7 CORE
Hans (no-spam):
    82069: 05/04/06: Re: VHDL to schematic conversion
Hans Brand:
    61645: 03/10/08: Re: Implementing a fast cache in Altera Cyclone
Hans Christian Lonstad:
    12605: 98/10/20: Re: 100 MHz FPGA
    12868: 98/11/03: Re: 100 Mhz FPGA
Hans Dampf:
    136077: 08/10/30: Xilinx RapidIO 5.1
    136092: 08/10/31: Re: Xilinx RapidIO 5.1
Hans Grobler:
    4861: 96/12/20: Re: ASICs Vs. FPGA in Safety Critical Apps.
Hans Holm:
    20477: 00/02/11: XILINX JTAG ID
    21070: 00/03/06: Re: FilterExpress version 3.0 now available
    21068: 00/03/06: Re: QuickLogic programmers for sale
    21114: 00/03/07: antifuse fpga's replacing xilinx
    21141: 00/03/08: Re: antifuse fpga's replacing xilinx
    21142: 00/03/08: Re: antifuse fpga's replacing xilinx
    21369: 00/03/20: Re: Beginner's Guide
    21781: 00/03/31: RE: ANTIFUSE AND XILINX
Hans Holten-Lund:
    49255: 02/11/06: Re: WebPACK 5.1 SP2
    83220: 05/04/26: Re: DDR SODIMM on Avnet Virtex II PRO development kit
Hans Jörg Beltle:
    2072: 95/10/10: Help - Searching an PLD/FPGA Selection Software
Hans Jörg Lebert:
    1508: 95/07/05: Curious behaviour of Synopsys Simulator V3.3a
    1568: 95/07/18: HELP!! Xilinx V5.0 doesn't work correctly with Synopsys
    1570: 95/07/19: Re: ROM synthesis
Hans Kester:
    22943: 00/06/05: Re: Help for Spartan XCS10
    22945: 00/06/05: Re: CPLD: gang programming
Hans Lindkvist:
    11045: 98/07/15: Re: compile warning
    12171: 98/10/02: Re: Synthesis: Exemplar or Synopsys
    14566: 99/02/04: Re: VHDL clocked one-shot Implementation Problem
Hans Maier:
    69021: 04/04/26: CPLD input
    69068: 04/04/26: Re: CPLD input
    69120: 04/04/27: Re: CPLD input
Hans Rhein:
    104129: 06/06/19: Processor Design
Hans Summers:
    30617: 01/04/19: Re: clocking on both edges
    32605: 01/07/02: Re: Asynchronous design in Virtex FPGA => sleepless nights
    36561: 01/11/12: Re: ZX81 production run, is there any interest?
    39594: 02/02/14: Re: NT parallel port driver
    46549: 02/09/03: Re: IT consultant vs Engineer
Hans Tiggeler:
    466: 94/11/26: Viewdraw's Change Label Sense
    3231: 96/04/30: Re: FPGA from RAD-PACK ?
    4681: 96/11/29: Cypress CPLD, pASIC380 Programmer
    4771: 96/12/13: Re: XILINX TEST BOARD WITH ROUTING SOFTWARE
    5043: 97/01/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5044: 97/01/16: Re: Safety Critical Apps -> Xilinx Checker.
    5052: 97/01/17: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5627: 97/03/03: Re: Cypress says good-bye to Anti-Fuse
    5778: 97/03/14: Re: ACTEL RAM BASED FPGAs
    5848: 97/03/20: Re: Accolade
    6474: 97/05/27: Re: Best way to learn VHDL?
    6621: 97/06/06: Actel Designer Series 3.1 and NT 4.0?
Hans-Bernhard Broeker:
    56072: 03/05/28: Re: JTAG madness
    64919: 04/01/16: Re: Hardware to test (FPGA-based) prototype?
    66903: 04/02/29: Re: difference btw H/W & S/W implementations !!
    83359: 05/04/28: Re: x on ml300?
    85796: 05/06/16: Re: Idea exploration - Image stabilization by means of software.
    92095: 05/11/22: Re: How do I find the datasheet of this device "TIOPA 690 3BZL9"?
    109305: 06/09/23: Re: OT: Google display of this thread
Hans-Erik Floryd:
    11762: 98/09/08: Code coverage tools
    11780: 98/09/09: Re: Code coverage tools
Hans-Guenther Willers:
    6472: 97/05/27: I2C Interface
Hans-Juergen Dorn:
    63147: 03/11/17: SRL16 as synchronizer
    63197: 03/11/18: Re: SRL16 as synchronizer
    63200: 03/11/18: Re: SRL16 as synchronizer
Hans-Jürgen Dorn:
    45931: 02/08/11: Re: EDIF netlist from XST
Hans-Peter Diettrich:
    126783: 07/12/02: Re: lossless compression in hardware: what to do in case of uncompressibility?
<hans64@ht-lab.com>:
    120373: 07/06/06: Re: How to Find false path in a design
    120376: 07/06/06: Re: Topics and Ideas for BS Project
    120389: 07/06/06: Re: Topics and Ideas for BS Project
    125179: 07/10/17: Re: High level FPGA work flow: available tool?
<Hans>:
    15468: 99/03/25: Re: keeping an Altera EAB register in synplicity
    15487: 99/03/26: Re: keeping an Altera EAB register in synplicity
    15700: 99/04/09: Re: Best FPGA for High Speed DSP Logic?
Hansang Bae:
    135435: 08/10/01: Re: Sending UDP packets over Ethernet
Hanse Schmid:
Hansen Hong:
    11734: 98/09/04: URGENT REQUIREMENT FOR ALTERA PART
hanshu:
    30305: 01/04/02: some info. on FPGA
hansman:
    112787: 06/11/29: DVI clock generation
hanson j:
    81474: 05/03/24: using the for-loop !
hansp:
    97174: 06/02/17: Re: Communication between FPGA and PC with ethernet
<HansWernerMarschke@web.de>:
    131843: 08/05/03: FPGA Processor for Signal Processing ?
<hanumaan81@gmail.com>:
    135920: 08/10/21: Virtex 5 DSP.
hao xing:
    48514: 02/10/18: Read xilinx cpld usercode.
haowen:
    141064: 09/06/04: how to write data to a register in the FPGA
<happydude32905@gmail.com>:
    90335: 05/10/10: Xilinx Chipscope VIO Core Utilization
Harald:
    55446: 03/05/08: FPGA Design with Protel DXP
    126289: 07/11/19: Update to Xilinx ISE 9.2
    126295: 07/11/19: Re: Update to Xilinx ISE 9.2
    126305: 07/11/19: Re: Update to Xilinx ISE 9.2
    126348: 07/11/20: Re: EDK 9.2 and virtex 2 devices
    126350: 07/11/20: Re: EDK 9.2 and virtex 2 devices
    126352: 07/11/20: Re: EDK 9.2 and virtex 2 devices
    126358: 07/11/20: Re: EDK 9.2 and virtex 2 devices
    126359: 07/11/20: Re: EDK 9.2 and virtex 2 devices
    126363: 07/11/20: Re: EDK 9.2 and virtex 2 devices
Harald Bratko:
    3172: 96/04/18: Problems with XBLOX
Harald Simmler:
    18316: 99/10/14: Re: Virtex Board
    18629: 99/11/04: Re: Simulation of FPGA design. Please Help!
    20993: 00/03/02: ORCA 3T - input/output delay reduction?
    21148: 00/03/08: Re: ORCA 3T - input/output delay reduction?
Harald Vefling:
    10321: 98/05/12: Re: Low power FPGA design
    11422: 98/08/12: Re: Combinatoric Divide-by-3 Algorithm
    23281: 00/06/21: Re: How to cut the power disipation down ?
<harbinxiaoting@hit.edu.cn>:
    103043: 06/05/24: how to readback a frame
    103620: 06/06/06: Re: how to readback a frame
hardbreaker:
    136895: 08/12/11: Re: Xilinx ISE 10.1 SP3 MPMC NPI VHDL simple sample needed
hardwareengineer:
    73524: 04/09/22: using both edges of clocks in a design - effects on synthesis
    74447: 04/10/11: post place and route issues for a generic simple n input and gate
hardwire:
    46858: 02/09/10: Re: How to make Altera UPX board self bootable?
Hardy Pottinger:
    3705: 96/07/18: MUG'96 Call for Papers
HardySpicer:
    135663: 08/10/11: Re: XMOS XC-1 kits are shipping
    135666: 08/10/11: Re: XMOS XC-1 kits are shipping
Harel Ashwal:
    83488: 05/05/01: Xilinxs XCF16 PROMS Eng. Samples Bugs?
Haresh Kripalani:
    17524: 99/08/06: Re: Intel Opportunity
Harford Communications, Inc.:
    17893: 99/09/15: Re: simple VHDL?
Hari:
    53484: 03/03/13: ROM containing complex numbers
    64297: 03/12/25: Fast Fourirer Using Xilinx ISE
hari:
    85641: 05/06/13: Suche FPGA Protoboard
Hari Devanath:
    42173: 02/04/17: Re: problem installing xilinx foundation 3.1 on a P4
    42174: 02/04/17: Re: Programming for FPGA or ASIC
    42234: 02/04/18: Re: problem installing xilinx foundation 3.1 on a P4
    42396: 02/04/22: Re: INIT constrain
    45009: 02/07/09: Re: Bi-Directional Bus problem in Xilinx FPGA
Hari Kannan:
    102259: 06/05/12: ISE 7.1 synthesis problems
Hari Shankar:
    5756: 97/03/12: Development board with multiple FPGAs
Hari Vattikota:
    4661: 96/11/26: Re: How to utilize XC4000e IOB FFs in Synopsys?
    4701: 96/12/02: Re: How to utilize XC4000e IOB FFs in Synopsys?
<harikris@gmail.com>:
    101399: 06/04/30: design optimization
    101421: 06/04/30: Re: design optimization
Haris:
    140302: 09/05/08: Re: OpenCores CAN/Ethernet cores
    140359: 09/05/10: Re: Getting started with FPGA
Harish:
    76508: 04/12/04: HWICAP
    76627: 04/12/07: Xilinx Area Constraints for partial reconfiguration
    76648: 04/12/07: Re: Xilinx Read First Write First
    76665: 04/12/08: Re: Xilinx Area Constraints for partial reconfiguration
    76685: 04/12/08: Re: Xilinx Read First Write First
    76980: 04/12/17: Re: HWICAP
    77125: 04/12/23: Using EDK libraries in ISE
    77152: 04/12/25: Re: Using EDK libraries in ISE
    77347: 05/01/04: Location of Data in BRAM Configuration bit stream
    77348: 05/01/04: Re: documents on practicing microblaze ( ML310 ) ?
    77350: 05/01/04: Extracting BRAM data from configuration Bit stream
Harish Vutukuru:
    88721: 05/08/25: Issues with Synplify Pro 7.7 synthesis
Harish Y S:
    37709: 01/12/19: Re: Google Groups problems?
harishac:
    151812: 11/05/20: Verify failed between address 0x80000 and 0x8FFFF
<harisrini@gmail.com>:
    129533: 08/02/27: How to connect FPGA to a ASIC Board?
    129767: 08/03/05: Re: How to connect FPGA to a ASIC Board?
hariz:
    143119: 09/09/22: view memory contents in modelsim
Harjo Otten:
    26524: 00/10/19: Re: Spartan II ?
    26967: 00/11/06: Re: Spartan2 prototype boards
    27147: 00/11/13: Re: Spartan-II with 5V ISA bus
    29158: 01/02/08: First XILINX PCI core project
    29817: 01/03/12: Leonardo 'renames' in- and outputs.
    32728: 01/07/06: Re: Xilinx PCI development board
    34058: 01/08/13: Re: this code doesn't work properly
    34774: 01/09/07: cannot replace 'if' with 'case' ???
    34783: 01/09/07: Re: cannot replace 'if' with 'case' ???
    35215: 01/09/26: Gated clocks and shortage of clock buffers
    36860: 01/11/22: How do I.......
    39136: 02/02/01: Dual ported RAM in SpartanII, output = ?????
    39138: 02/02/01: Re: Dual ported RAM in SpartanII, output = ?????
    41056: 02/03/20: syntax problem.....
harkirat:
    43781: 02/06/02: Interfacing B5 spartan FPGA with a Motorola 68HC11
    43819: 02/06/03: Re: Interfacing B5 spartan FPGA with a Motorola 68HC11
    43941: 02/06/06: Re: Interfacing B5 spartan FPGA with a Motorola 68HC11
<harnhua@plunify.com>:
    156490: 14/04/10: Re: cloud design flow
    156507: 14/04/12: Re: cloud design flow
    156510: 14/04/13: Re: cloud design flow
    156559: 14/04/30: Synthesis / PAR options mess up design functionality
    156562: 14/04/30: Re: unclear tcl error
    156566: 14/05/01: Re: Synthesis / PAR options mess up design functionality
Harold:
    119511: 07/05/21: How to copy hex data from Quartus vwf file to text?
<harrah1@ibm.net>:
    1610: 95/07/28: Re: VHDL/FPGAs/PLDs help
Harrie Gulikers:
    4768: 96/12/13: Re: ASICs Vs. FPGA in Safety Critical Apps.
Harris Georgiou:
<harrisjd@gmail.com>:
    134971: 08/09/08: Re: Development board with SD card.
Harry:
    27082: 00/11/10: VHDL: FFS in IOBs
Harry Chung:
    33419: 01/07/25: Prom: Download problem
    33945: 01/08/09: Install : Administrative privileges in Win2K
    34652: 01/09/01: Prom : Question on Configuration
Harry Dellamano:
    87911: 05/08/03: Re: System Engineering in the R/D World
Harry Seldon:
    48218: 02/10/14: Configuring a Xilinx device with JAM player
Harry Stello:
    107928: 06/09/02: DMA on Virtex-4 using PPC
    108090: 06/09/05: sinmple DMA Example for ML403
    108109: 06/09/05: Re: sinmple DMA Example for ML403
    115751: 07/02/19: MPD Files
    115752: 07/02/19: Re: using shared vhdl code in customer ipif block
<harrytheasicguy@gmail.com>:
    132041: 08/05/11: Re: Breaking News ... Accellera Verification Working Group Forming
harsha:
    44409: 02/06/19: uart code using vhdl
Harsha Gordhan Jagasia:
    31999: 01/06/10: Teramac FPGA mapping for Pentium
Harsha Jagasia:
    31998: 01/06/10: Teramac FPGA mapping for Pentium
<harsha.s.udupa@gmail.com>:
    156576: 14/05/03: Re: Initializing color bars on CH7301
<harshada.pendse@gmail.com>:
    123511: 07/08/29: Re: VHDL core to read/write to Bram_Block.
hartenst@rhrk.uni-kl.de:
    22681: 00/05/17: FPL 2000 - Roadmap to Reconfigurable Systems
Hartmut Schaefer:
    39468: 02/02/11: XILINX Webpack 4.1 beginners question
    39481: 02/02/11: Re: XILINX Webpack 4.1 beginners question
Hartono:
    21795: 00/03/31: Modem Pooling using Fpga
<hartono.setiono@gmail.com>:
    138146: 09/02/07: PLDShell Plus V5.1
    138148: 09/02/07: Re: PLDShell Plus V5.1
    138161: 09/02/08: Re: PLDShell Plus V5.1
harvey hanig:
    6719: 97/06/19: Re: FS: CADKEY '97 (8.0)-100+ Available- Save $HUNDRED's EACH!!!
Harvey Miller:
    15983: 99/04/24: Timing Constraint
Harvey Twyman:
    30240: 01/03/29: Programmble Logic Sequencer
    31244: 01/05/16: PROGRAMMABLE LOGIC SEQUENCER CORRECTIONS
<harveytwyman@my-deja.com>:
    27793: 00/12/08: Re: Altera MAX+PlusII v.s. Xilinx Foundation
    27774: 00/12/07: Re: jtag for fpga
    27792: 00/12/08: Re-Reverse-engineering FPGA's"
    27904: 00/12/14: Re: jtag for fpga
    28059: 00/12/20: Re: jtag for fpga
    28060: 00/12/20: Re: Reverse-engineering FPGA's
    28061: 00/12/20: Hand Soldering a PQ208 - It looks tough to do
    28064: 00/12/20: Re: FPGA and Board for Microprocessor Design?
    28219: 01/01/01: How can I design FPGA based RISC processors?
hary:
    156280: 14/02/04: RE: Jobs going in New Zealand
Hasan I.:
Hasan K.:
    77188: 04/12/28: Re: USB JTAG programmers?
Hassan Atat:
    87014: 05/07/12: edif version generated by xilinx ISE 6.2
Hassan Mourad:
    42701: 02/05/01: synthesis error
    42734: 02/05/01: Re: synthesis error
Hassan rabah:
    3209: 96/04/26: run time reconfiguration
Hassane Guermoud:
    3217: 96/04/29: FPIC
hassantalal:
    144712: 09/12/27: JTAG-USB CABLE NOT DETECTED
    144968: 10/01/17: CDMA ON FPGA
    145019: 10/01/20: AWGN TESTING
hassen Karray:
    141295: 09/06/16: what is non-aligned -- memory accesses ?
<hassen.karray@gmail.com>:
    138730: 09/03/06: 2 Modules working independently but not together on FPGA
    139329: 09/03/26: Best way to export Xilinx EDK project in ISE and how to initialize
    139364: 09/03/27: Re: Best way to export Xilinx EDK project in ISE and how to
    139472: 09/03/31: Re: Best way to export Xilinx EDK project in ISE and how to
    139474: 09/03/31: Re: initialize BRAM contents
    139590: 09/04/06: Don't understand the Partialmask option for partial reconfiguration
    139654: 09/04/08: want to see and use Commands used by Xilinx ISE
    139656: 09/04/08: Re: want to see and use Commands used by Xilinx ISE
    140211: 09/05/04: Dynamic partial reconfiguration on Spartan 3 chips
    140616: 09/05/20: Re: Port assignment question
    140664: 09/05/21: Re: Port assignment question
    140736: 09/05/23: Re: Port assignment question
    140737: 09/05/23: Re: Port assignment question
    140741: 09/05/23: Re: Port assignment question
hassoo:
    151422: 11/04/06: Ethernet MAC on Virtex 4
    151627: 11/04/27: Re: Ethernet MAC on Virtex 4
    151628: 11/04/27: Re: Ethernet MAC on Virtex 4
hat:
hata:
    86760: 05/07/06: virtex4 evaluation board
    86764: 05/07/06: Re: virtex4 evaluation board
    86951: 05/07/11: Wishbone RTL simulator
    86955: 05/07/11: Re: Wishbone RTL simulator
    87571: 05/07/26: Soft IPs licensing
<hattangady@gmail.com>:
    113763: 06/12/20: Soft processor Microblaze vs embedded core PowerPC
    113794: 06/12/21: FSL feasibiliity
Hauke D:
    132982: 08/06/12: Re: FPGA to FLASH and back?
    133077: 08/06/17: Re: Virtex5 FPGA Board and USB interface
    133078: 08/06/17: Re: FPGA configuration Beginner questions...
    133079: 08/06/17: Re: FPGA configuration Beginner questions...
    133248: 08/06/22: Re: virtex-5: can't use DCM (too low input frequency)
    133254: 08/06/22: Re: virtex-5: can't use DCM (too low input frequency)
    133431: 08/06/28: Re: Still a Beginner: Accumulator has no reset
    147868: 10/05/28: Re: Programming Digilent Nexys 2 from Linux
Havatcha:
    46668: 02/09/05: Re: Neural hardware containing many neurons but very simple computation
    46702: 02/09/06: Re: Neural hardware containing many neurons but very simple computation
Hawker:
    25501: 00/09/12: ABEL trouble with XC95108 and Foundation 2.1i SPVI
    25537: 00/09/13: Re: ABEL trouble with XC95108 and Foundation 2.1i SPVI
    25538: 00/09/13: Re: MEMORY
    25539: 00/09/13: Re: Virtex 'shutdown' phenomenon
    25574: 00/09/14: Re: Virtex 'shutdown' phenomenon
    25589: 00/09/14: Re: Simon,Floating Inputs
    25612: 00/09/15: Re: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W,
    25754: 00/09/19: PCB side of this
    26225: 00/10/09: Re: Analogue FPGAs ?
    26228: 00/10/09: Re: Analogue FPGAs ?
    26975: 00/11/06: Quick Foundation SPIV install question
    27386: 00/11/20: Xilinx and Tri state I/O
    116481: 07/03/09: Any Western NC VHDL Designers?
    119401: 07/05/17: Re: Visio logic symbols
Hayden So:
    30456: 01/04/09: Spartan-II DLL question
    34277: 01/08/18: connected "not connect" pins on Xilinx
    35716: 01/10/15: Spartan2: opposite of Synch-to-DONE?
<haydenso@my-deja.com>:
    27141: 00/11/13: Spartan-II with 5V ISA bus
    27179: 00/11/14: Re: Spartan-II with 5V ISA bus
Hayder Mrabet:
    64976: 04/01/17: QUIP( Altera ) interseting But ?????
    65037: 04/01/19: QUIP ( advance)
haydin:
    147235: 10/04/20: Re: Virtex-5 FPGA PCIe card
Haytham:
    57083: 03/06/23: Programming xc95144 using parallel IV cable
HB:
    85813: 05/06/16: uart / Nios2
    85863: 05/06/17: Re: uart / Nios2
    86056: 05/06/21: nios2 / terminal
    93033: 05/12/12: 3/2 with virtex 300
    93091: 05/12/13: Re: 3/2 with virtex 300
    93137: 05/12/14: Re: 3/2 with virtex 300
hbenin:
    136429: 08/11/16: Re: Question on timing constraints
    136738: 08/12/03: Re: Question on timing constraints
Hchen:
    26137: 00/10/05: Xilinx BoardScope
<hchenry@comsoc.com>:
    27946: 00/12/16: FPGA to ASIC conversion
<hdhunter@usaor.net>:
    4101: 96/09/10: RE: FPGA DESIGNERS
HDL Conference:
    14804: 99/02/17: Announcing HDL Conference
    15066: 99/03/04: 1999 Int'l HDL Conference & Exhibition
    16101: 99/05/03: Fall VIUF Workshop Call For Papers
hdl_book_seller:
    108066: 06/09/04: Good Verilog reference book: Thomas & Moorby
<hdl_fan@my-dejanews.com>:
    15115: 99/03/08: Pin constraints of Xilinx
HDLadmirer:
    49758: 02/11/20: Re: Convert AHDL design to schematics(RTL)
<hdlnerd@gmail.com>:
    153857: 12/06/07: Re: EDK problems
    153858: 12/06/07: Re: FPGA Interconnect
HDLsRFun:
    8710: 98/01/21: Destination FPGA
    8837: 98/01/30: Re: VHDL book
<hdrbjj@nowhere.com>:
<hdunn@my-deja.com>:
    17536: 99/08/06: Intellectual Property
he:
    143551: 09/10/15: Re: What is the basis on flip-flop replaced by a latch
    145619: 10/02/16: Re: Data2Mem ? BlockRAM ? Init BMM and MEM
    145622: 10/02/16: Re: Data2Mem ? BlockRAM ? Init BMM and MEM
    145833: 10/02/25: Re: Scrubbing in Virtex-4
    146570: 10/03/23: Re: Writing Hex values to file in VHDL?
    147636: 10/05/11: Two PCIe Endpoints in one Virtex-6?
    148214: 10/06/30: Re: ML605 Dev Board Problems
    150220: 11/01/02: Re: USB Cables again
headout:
Heather Cooper:
    32613: 01/07/02: High Speed Logic Board Designer needed
    32614: 01/07/02: FPGA Design
<heatherr@london.com>:
Heavenfish:
    56063: 03/05/28: Re: Multiply 19.44MHz with Virtex-II DCM
HECTOR DAVILA:
    2641: 96/01/17: ***KEYBOARD RECORDERS**********************************************
heedaf:
    149250: 10/10/11: Xilinx SDK Debugger Problem
Heeyong:
    74551: 04/10/13: [Noise] Xilinx Evaluation Board Problem
Heiko:
    70176: 04/06/08: Hardware implementation of the Xilinx configuration CRC generator
    70198: 04/06/08: Re: Hardware implementation of the Xilinx configuration CRC generator
Heiko Ehrenberg (GOEPEL):
    151551: 11/04/18: IEEE standardization of test data register (TDR) interfaces
Heiko Kalte:
    44888: 02/07/04: Maximum frequency in Virtex and Virtex-E Devices
    44952: 02/07/08: High Performance (partial) FPGA (Re-)Configuration
    48333: 02/10/16: I need your experience, very important for me
    50471: 02/12/11: partial Bitstream Size in Virtex-II
    50480: 02/12/11: Re: partial Bitstream Size in Virtex-II
    52580: 03/02/14: Xilinx Virtex-II Pro OCM and PLB Clock Frequency
    87100: 05/07/15: Virtex-4 5V tolerance
Heiko Panther:
    60762: 03/09/22: EDK 3.2: timing constraint for CLKDLL
Heiko Timmer:
    46040: 02/08/15: Resetting Spartan II FPGA
<heiko@csse.uwa.edu.au>:
    92128: 05/11/22: Access to long lines in Virtex-II
    92129: 05/11/22: Flip-flop state extraction out of reaback stream in Virtex-II/Pro
    92141: 05/11/22: Re: Flip-flop state extraction out of reaback stream in Virtex-II/Pro
    92143: 05/11/22: Re: Flip-flop state extraction out of reaback stream in Virtex-II/Pro
<heilig@iname.com>:
    135214: 08/09/21: 50 Ohm Analog Output of FPGA
    135262: 08/09/23: Re: 50 Ohm Analog Output of FPGA
Hein Roehrig:
    78900: 05/02/09: Re: Impact with Linux Kernel 2.6.x
    78955: 05/02/10: Re: Impact with Linux Kernel 2.6.x
    79869: 05/02/25: Re: Adjustment for FPGA-FAQ 0044
Heiner Litz:
    91894: 05/11/16: XILINX BlockRAM setuphold violation (setup) problems HELP!
    133772: 08/07/14: GTP simulation problems
    133790: 08/07/14: Re: GTP simulation problems
    133808: 08/07/16: No open-drain in V5 to drive an external LED?
    135396: 08/09/30: reasonable timing analysis without mapping design to IO
    135408: 08/10/01: Re: reasonable timing analysis without mapping design to IO
    135455: 08/10/02: Re: reasonable timing analysis without mapping design to IO
    135699: 08/10/13: Re: reasonable timing analysis without mapping design to IO
    139283: 09/03/25: Transmit data with clock capable pins on Virtex5 ??
<heinerlitz@gmx.de>:
    105132: 06/07/14: Using Samsung DDR2 memory with Xilinx Memory Interface Generator (MIG)
    105284: 06/07/19: Sorting algorithm for FPGA availlable?
    105322: 06/07/20: MIG DDR2 controller does not work (reset problems?)
    105386: 06/07/21: Re: MIG DDR2 controller does not work (reset problems?)
    105391: 06/07/21: Re: MIG DDR2 controller does not work (reset problems?)
    105414: 06/07/22: Re: MIG DDR2 controller does not work (reset problems?)
    105767: 06/07/31: MIG 1.6 DDR2 testing problems (FIFO16 related?)
    105804: 06/08/01: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
    105806: 06/08/01: Re: Usage of DDR IOBs
    105824: 06/08/01: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
    106049: 06/08/07: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
    106058: 06/08/07: Re: Xilinx ISE 8.2 implementation problem
    106204: 06/08/09: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
    106261: 06/08/09: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
    106674: 06/08/17: Re: Is necessary to use Modsim on DDR Memory development?
    107565: 06/08/30: MGT Power supply
    107774: 06/09/01: Re: MGT Power supply
heinerlitz@googlemail.com:
    124546: 07/09/26: XST corrupts my state machine. Only disabling FSM encoding helps
    124548: 07/09/26: Re: XST corrupts my state machine. Only disabling FSM encoding helps
    126665: 07/11/29: Asynchronous FIFO and almost empty - bug?
    126718: 07/11/30: Re: Asynchronous FIFO and almost empty - bug?
    126805: 07/12/03: Re: Asynchronous FIFO and almost empty - bug?
Heinrich:
    133341: 08/06/25: Signal forwarding between FPGAs
    133377: 08/06/26: Re: Signal forwarding between FPGAs
    133378: 08/06/26: Re: Signal forwarding between FPGAs
    133406: 08/06/27: Re: Signal forwarding between FPGAs
    133410: 08/06/27: Re: Signal forwarding between FPGAs
Heinrich Burgsteiner:
    126066: 07/11/14: VCD Files Viewer?
    126069: 07/11/14: Re: VCD Files Viewer?
    126070: 07/11/14: grouping bits to form bus in VCD file
Heinrich Fonfara:
    16546: 99/05/27: High speed with VHDL
    17656: 99/08/19: constrain into one XC4000 CLB
    17990: 99/09/21: Re: Back engineer xc3000
    23094: 00/06/14: Req: Source for Filter Design
    29395: 01/02/19: Fine Phase Shift in VirtexII
    29446: 01/02/21: Re: Fine Phase Shift in VirtexII
    29898: 01/03/16: RAM-based Shift Register
    29938: 01/03/19: Re: RAM-based Shift Register
    32085: 01/06/13: Fifo Clock in SpartanII
Heinz Seltmann Jr:
    1271: 95/05/24: Re: PLDShell Plus
Heinz Wolter:
    29660: 01/03/04: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
Helen:
    30665: 01/04/22: Frequency of FPGA
    30666: 01/04/22: Something about the counter
    30683: 01/04/23: CarryLogic
    30684: 01/04/23: Re: Something about the counter
    44621: 02/06/24: Help with Lattice ispLSIv2192VE
    110971: 06/10/26: Jumps in FPGA implemented integrator
    110986: 06/10/26: Re: Jumps in FPGA implemented integrator
    111018: 06/10/27: Re: Jumps in FPGA implemented integrator
    111137: 06/10/30: Re: Jumps in FPGA implemented integrator
Helen Long:
    29411: 01/02/20: UCF problem "- Could not find NET "
    30383: 01/04/05: How to combine bus in schematic
    30562: 01/04/17: inout pin of DAC
    30702: 01/04/24: Re: what does it mean in fe.log?
    30703: 01/04/24: Re: Something about the counter
Heliboy:
    71024: 04/07/05: Xilinx FPGA routing question
<heliboy2003@yahoo.com.tw>:
    116016: 07/02/27: [Q] Xilinx Webpack warning message "Cannot apply TIMESPEC TS_WR_CPLD"
    116018: 07/02/27: Re: Xilinx Webpack warning message "Cannot apply TIMESPEC TS_WR_CPLD"
helix:
    97274: 06/02/20: DVI - LVDS controller
    97282: 06/02/20: Re: DVI - LVDS controller
<hell@hell.com>:
    8517: 98/01/02: *** GET MONEY POSTED TO YOUR CREDIT CARD, NO CATCH! READ!!! ***
Hello:
    7736: 97/10/09: [Fwd: [Fwd: [Fwd: [Fwd: [Fwd: READ THIS MESSAGE AND PASS IT ON....]]]]]
Helmar:
    139004: 09/03/18: Bullshit! - Re: Zero operand CPUs
    139013: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
    139017: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
    139021: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
    139023: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
    139025: 09/03/18: Re: Zero operand CPUs
Helmut:
    100312: 06/04/06: Re: RocketIO MGT Clocking Arrangement!
    114788: 07/01/24: Platform Cable USB & Windows 2003 Server
    114798: 07/01/24: Re: Platform Cable USB & Windows 2003 Server
    114806: 07/01/24: Re: Platform Cable USB & Windows 2003 Server
    115259: 07/02/05: Re: ISE 9.1 SAY YOURS OPINION
    116321: 07/03/07: Re: No Clock in ChipScope Pro Analyzer
    117237: 07/03/27: Re: Where is MIG 1.7???
    117361: 07/03/29: Re: Where is MIG 1.7???
    117831: 07/04/11: Re: Xilinx WebCase support
    123865: 07/09/06: Re: FATAL ERROR ISE9.1i
    126456: 07/11/23: Re: VHDL language is out of date! Why? I will explain.
    126591: 07/11/28: Re: DDR2 controler
    128215: 08/01/18: Chipscope Inserter to Chipscope Analyzer
    128219: 08/01/18: Re: Chipscope Inserter to Chipscope Analyzer
    130212: 08/03/18: Re: Chipscope
    130213: 08/03/18: Re: Xilinx Webcase Workflow
Helmut Juchems:
    16174: 99/05/07: Re: BGA Prototyping ?
    24345: 00/08/04: Re: 5V Lattice 1032E and 3.3V compatability
Helmut Sennewald:
    44970: 02/07/08: SpartanXL,2E: How many flipflops on one clock-net?
    44979: 02/07/09: Re: SpartanXL,2E: How many flipflops on one clock-net?
    45108: 02/07/12: Re: FPGA CPU?
    45137: 02/07/13: Re: Accurate Oscillator
    45256: 02/07/17: Re: SpartanXL,2E: How many flipflops on one clock-net?
    45883: 02/08/08: Re: Division
    46251: 02/08/22: Re: Want a most simple develop board's design example for Xilinx FPGA(SP-II)?
    46284: 02/08/24: Re: need cheap and dirty time delay for spartan2e
    46291: 02/08/24: Re: need cheap and dirty time delay for spartan2e
    46415: 02/08/29: Re: WebPack FSM woes...
    47724: 02/10/02: Re: Moving average filter
    47842: 02/10/05: Re: Low power design
    48510: 02/10/18: Re: Webpack4.2
    48533: 02/10/19: Re: Webpack4.2
    49330: 02/11/09: Re: Instruction sets to implement instruction sets
    50942: 02/12/23: Re: I didn't understand altera's max+plus2 software to setting up.
    146506: 10/03/21: Re: Finally, selling my old Xilinx/Viewlogic software package
<helmut.leonhardt@gmail.com>:
    111443: 06/11/03: Re: Scientific Computing on FPGA
    111926: 06/11/13: Re: bidirectional bus
    112028: 06/11/14: Re: sending data across a 32 bit bus
    112355: 06/11/21: Re: DDR_VDHL_models
    112722: 06/11/28: Re: problems with verilog SDRAM models
    112723: 06/11/28: Re: problems with verilog SDRAM models
    112776: 06/11/28: Re: ModelSim Xilinx edition new bug?
    113787: 06/12/21: Re: How to simulate from the xilinx ISE
Help:
    24524: 00/08/11: Easy question on programming
help me:
    47461: 02/09/26: Re: fpga comparisons???
    47462: 02/09/26: comp.arch.fpga : mapping of fpga
    47463: 02/09/26: mapping of fpga
<help@for.you>:
    17195: 99/07/08: Re: Virtex: Excessive PAR run-times without user-feedback?
Helpme:
    124457: 07/09/22: Xilinx Microblaze EDK and Virtex5/LXT TEMAC core?
    124459: 07/09/22: Does Modelsim work under Windows Vista?
    124676: 07/09/29: Re: XST corrupts my state machine. Only disabling FSM encoding helps
    126887: 07/12/05: can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation
hema:
    114780: 07/01/24: Re: FPGA damage from bad bitstream
    114781: 07/01/24: ethernet MAC and switch
Hemang Parekh:
    103458: 06/06/02: Re: Delay or latency
    113878: 06/12/27: Re: Matlab (.m) to VHDL
Hemant D. Tagare:
    8863: 98/02/02: Re: VHDL programming style (was VHDL vs schematics)
Hemanth:
    112686: 06/11/27: Re: Aurora 2.4 error
<hemulliken@aol.com>:
    128788: 08/02/06: Virtex5 not for SONET or SDH
Hendra:
    75082: 04/10/26: ModelSim Directory
    75155: 04/10/27: Re: Webpack 6.3i support for Spartan 3
    74890: 04/10/20: Webpack 6.3i support for Spartan 3
    74893: 04/10/20: Re: Async reset
    75660: 04/11/11: Re: Xilinx Tshirts in football package.....
    75813: 04/11/15: New Xilinx 6.3i from Prentice Hall ?
    76460: 04/12/02: Re: how to start with development of eda tools
    76463: 04/12/02: Re: How to subscribe to the newsgroup comp.arch.fpga
    76483: 04/12/03: Re: how to start with development of eda tools
    76491: 04/12/04: Re: how to start with development of eda tools
    76642: 04/12/07: Re: "Hello World" project for an FPGA (on a Spartan3 board)
    76651: 04/12/08: Re: Clock Gating !!!
    76652: 04/12/08: Re: Clock Gating !!!
    76695: 04/12/08: Atari 10-in-1 Joystick
    76721: 04/12/09: Re: Seeking suggestions on prototyping board
    76753: 04/12/10: Xilinx 6.3i Student Edition released today!
    76929: 04/12/15: Re: Xilinx ISE 6.3.03i service pack size
    76978: 04/12/17: Re: Xilinx Student Foundation Edition on Windows-XP ??
    78433: 05/01/31: Re: Any solution for solving setup or hold time violation?
    78495: 05/02/01: MP3 Player Project
    78538: 05/02/02: Re: MP3 Player Project
    80447: 05/03/05: Re: Newby Getting started with FPGA
    80467: 05/03/06: Re: Newby Getting started with FPGA
    80475: 05/03/06: Re: Newby Getting started with FPGA
    80672: 05/03/09: Re: Differences among the FPGA development tools.
    80673: 05/03/09: Re: Newby Getting started with FPGA
    80946: 05/03/14: Re: Question from Newbie about FPGAs
    81113: 05/03/17: Re: Beginning Xilinx FPGA Tutorials?
    81523: 05/03/26: Re: Xilinx ISE 7.1 - Can this get any worse?
    81603: 05/03/28: Re: using (verilog) reg as memory
    81691: 05/03/29: Re: using (verilog) reg as memory
    81958: 05/04/05: Structural vs Behavioral
    82092: 05/04/06: Re: VHDL to schematic conversion
    83124: 05/04/24: Re: simple delays
    83560: 05/05/03: Re: JTAG without parallel port
    83869: 05/05/08: Flagging XST to suppress the warning
    97173: 06/02/17: ISE Simulator Price
    97219: 06/02/19: Re: Xilinx ISE Simulator Arrays
    97277: 06/02/20: Re: Problem with multple clcok domains
    97332: 06/02/20: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
    97867: 06/02/28: Re: Serious problem with XST
    98101: 06/03/04: Re: why use an FPGA when a CPLD will do ??
    98113: 06/03/05: Which CPU and Screen Rez for ISE 6.3i ?
    98269: 06/03/07: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
    98290: 06/03/08: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
    98506: 06/03/11: Re: Learning new stuff about FPGA
    100576: 06/04/12: Problem with Xilinx FTP
Hendra Gunawan:
    62364: 03/10/27: Static 1 and 0 Hazards
    67369: 04/03/10: ModelSim vs HDL Bencher
    67844: 04/03/20: Re: Why It Is not Recommended to Infer latches in VLSI Design...
    67845: 04/03/20: Re: PCI Development Board
    67865: 04/03/21: Re: Why It Is not Recommended to Infer latches in VLSI Design...
    67877: 04/03/21: Re: Why It Is not Recommended to Infer latches in VLSI Design...
    67937: 04/03/22: How many times can I burn an FPGA?
    68026: 04/03/24: Re: study verilog or vhdl?
    68146: 04/03/27: Re: AHDL, VERILOG or VHDL??
    68147: 04/03/27: Re: study verilog or vhdl?
    68198: 04/03/29: Re: AHDL, VERILOG or VHDL??
    68242: 04/03/30: Re: AHDL, VERILOG or VHDL??
    68245: 04/03/30: Re: AHDL, VERILOG or VHDL??
    68344: 04/04/01: Xilinx License Question
    68348: 04/04/01: Re: AHDL, VERILOG or VHDL??
    68404: 04/04/02: The Logic Behind License Renewal
    68420: 04/04/03: Re: iMPACT "Programming Failed"
    68439: 04/04/04: Which HVL is the most popular?
    68502: 04/04/06: Re: VGA Contoller
    68634: 04/04/11: Problem downloading with parallel converter
    68651: 04/04/12: Waveform Tool
    68677: 04/04/13: Re: Problem downloading with parallel converter
    68706: 04/04/14: Re: what is a better approach to synthezise synchronous reset on FPGA?
    68732: 04/04/15: Re: PCI Express specification.
    68764: 04/04/16: Re: Problem downloading with parallel converter
    68768: 04/04/16: Re: Huh, anybody wants to play some NES???
    68821: 04/04/19: Re: Problem downloading with parallel converter
    69964: 04/05/25: Re: VHDL simple question: is 2-D array synthesizable
    69969: 04/05/25: Re: VHDL simple question: is 2-D array synthesizable
    69972: 04/05/25: Re: Xilinx training
    70048: 04/05/29: Re: Propogation delays and setup times
    70170: 04/06/07: ISE 4.2i Impact and Windows XP not working
    70172: 04/06/07: Re: comp.arch.fpga: reset strategy
    70272: 04/06/10: Re: where is ISE 6.2 SP#3 ?
    70411: 04/06/15: Re: >Math Skills = >Engineer ?
Hendrie Dorland:
    8542: 98/01/07: Re: Newbe to fpga
Hendrik:
    104367: 06/06/26: Synthesis problem with ranged integer
    142898: 09/09/07: Mac OS X support for Sigasi HDT
    146578: 10/03/23: Re: Why hardware designers should switch to Eclipse
    146582: 10/03/23: Re: Why hardware designers should switch to Eclipse
Hendrik De Vloed:
    17505: 99/08/03: Xilinx Virtex configuration in chunks
Hendrik van der Heijden:
    157860: 15/04/23: Xilinx Aurora link splitter
    157862: 15/04/23: Re: Xilinx Aurora link splitter
    157864: 15/04/24: Re: Does each core of 8-core Intel processor has an independent floating
Hendry:
    90425: 05/10/12: IOs on ML-310 Evaluation Board
Henele I Adams:
    5612: 97/02/28: help:Prog. Xilinx demo board
Heng Tan:
    61241: 03/09/30: Re: your opinion about Avnet (Silica) VirtexII Pro evaluation board
    61453: 03/10/03: Re: your opinion about Avnet (Silica) VirtexII Pro evaluation board
    75561: 04/11/09: module based partial reconfiguration questions
hengchi:
    19869: 00/01/15: fuzzy logic in FPGas
henk:
    93171: 05/12/15: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
    98770: 06/03/16: Re: spartan-3e starter kit
    98807: 06/03/16: Re: spartan-3e starter kit
    99340: 06/03/23: Re: this JTAG thing is a joke
    101568: 06/05/03: Re: 50-th Anniversary of the CORDIC Algorithm
    108336: 06/09/08: Re: Open-source CableServer for Impact on sourceforge.net
    134835: 08/09/03: Re: crazy patent
Henk Bliek:
    35792: 01/10/17: Re: open-drain bidirs in xilinx or altera
Henk Luijmes:
    10567: 98/05/31: JTAG connector
Henk van Kampen:
    53178: 03/03/05: Re: FIR Filter from Xilinx
    62298: 03/10/24: Picoblaze development tool
    62319: 03/10/26: Re: Picoblaze development tool
    62378: 03/10/28: Re: chipscope pro and jtag
    62381: 03/10/28: Re: Picoblaze development tool
    62411: 03/10/29: Re: Picoblaze development tool
    62577: 03/11/02: Re: chipscope pro and jtag
    62579: 03/11/02: Re: Picoblaze development tool
    70514: 04/06/18: Re: Is there a verilog version of PicoBlaze?
    70526: 04/06/18: Re: Is there a verilog version of PicoBlaze?
    75627: 04/11/11: Re: C Compiler for Picoblaze !!!!!
    75683: 04/11/12: Re: C Compiler for Picoblaze !!!!!
HenktenBakker:
    127390: 07/12/19: Re: Quartus and simulation libraries...
    127391: 07/12/19: Re: Spartan-3E starter kit, what's "J8" 6-pin for?
    127392: 07/12/19: Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
    127393: 07/12/19: Re: Spartan 3e and SDRAM
henn_xxx@trispel.org:
    92007: 05/11/19: Functional problems with Stratix II when configuring at higher temperatures?
    92356: 05/11/28: Re: Altera Pin not used in Quartus project but drives logic
    92611: 05/12/02: Re: Download old Quartus versions (4.0, 4.1)
Henning Bahr:
    55763: 03/05/19: FPGA: Feasibility of Memory testing
    58209: 03/07/16: Digital Design with just one clock at one edge
    64461: 04/01/05: p160 connector
    64767: 04/01/13: Error: (vsim-3341) Cannot open file
Henning E. Larsen:
    4626: 96/11/22: Re: VHDL code editor for Windows NT.
Henning Paul:
    115475: 07/02/12: Re: Building Coaxial transmission line on PCB?
Henning Trispel:
    15392: 99/03/22: Re: FLEX 10K question
    16073: 99/04/30: Altera EPC2 - Has anybody used it already?
    17042: 99/06/27: Re: Altera: Simulation results differ...
    31469: 01/05/26: Xilinx XC4010E Problem
    31480: 01/05/27: Re: Xilinx XC4010E Problem
    35289: 01/09/27: Re: Altera Quartus II: Ouput skew ;-(
Henning Zabel:
    84388: 05/05/18: Linux on Xilinx ml310
HenningB:
    46142: 02/08/20: Huge discrepanzcy between gate-array and standard cell synthesis
Henri:
    30731: 01/04/26: Re: Virtex power supplies.
    32626: 01/07/03: Re: Phase Locked loop implementation on FPGA
    32627: 01/07/03: Re: QPSK signal processing.
    133943: 08/07/20: Re: The littlest CPU
henri:
    3907: 96/08/19: Searching a good designer?
Henri Faber:
    49137: 02/11/01: Asynchronous clock enable with stable data
Henrik =?iso-8859-1?Q?S=F8rensen?=:
    27442: 00/11/22: Post synthesis pre-NGDbuid gate-level functional simulation
Henrik A. =?iso-8859-1?Q?S=F8rensen?=:
    25831: 00/09/22: Pack I/O Reg/Latches into IOBs
Henrik Douglas Green:
    53227: 03/03/07: Current Consumption/Limitation Upon Output
Henrik Eriksson:
    6379: 97/05/20: Re: VHDL or Verilog?
    6406: 97/05/22: Re: VHDL or Verilog?
Henrik Johnsson:
    13218: 98/11/20: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
Henrik Koksby Hansen:
    81145: 05/03/18: Downloading problems [Memec DS-BD-V2MB1000 Virtex-II board].
    81168: 05/03/18: Re: Downloading problems [Memec DS-BD-V2MB1000 Virtex-II board].
    81262: 05/03/20: Re: Downloading problems [Memec DS-BD-V2MB1000 Virtex-II board].
    81377: 05/03/22: Re: Downloading problems [Memec DS-BD-V2MB1000 Virtex-II board].
    83465: 05/04/30: Re: Downloading problems [Memec DS-BD-V2MB1000 Virtex-II board].
Henrik Pedersen:
    109934: 06/10/08: Re: Xilinx-Modelsim on Linux
    110014: 06/10/09: Re: Xilinx-Modelsim on Linux
    110072: 06/10/10: Re: Xilinx-Modelsim on Linux
    110490: 06/10/16: WebPack on Linux
    110553: 06/10/17: Re: WebPack on Linux
    110668: 06/10/19: Re: WebPack on Linux
    110676: 06/10/19: Re: WebPack on Linux
Henrique:
    47649: 02/10/01: Where can i buy xilinx fpga online?
    56579: 03/06/09: Where can i buy virtex II ?
<henrique.portela@gmail.com>:
    89222: 05/09/08: ML361 Documentation....
    89225: 05/09/08: Re: ML361 Documentation....
    89957: 05/09/30: PCB Software....
    89968: 05/09/30: Re: PCB Software....
    89976: 05/09/30: Re: PCB Software....
Henry:
    42732: 02/05/01: Can not get define_multicycle_path to work.
    42799: 02/05/02: Re: Can not get define_multicycle_path to work.
    46052: 02/08/15: 2 questions using Synplify Pro.
    61837: 03/10/14: Re: mp3 project
    61882: 03/10/14: Re: mp3 project
    91502: 05/11/07: Suggestions/Recommendations with CPLD's and Software
    93766: 05/12/30: Re: Brute Force Examination of a PLD
    94813: 06/01/18: Re: Attack of the clones
    94893: 06/01/18: Re: Attack of the clones
    103655: 06/06/07: Xilinx SystemACE : Flash Memory
henry:
    20935: 00/02/29: Delay Lines using FPGA ??
    21019: 00/03/03: Re: Delay Lines using FPGA ??
Henry Baker:
    2524: 95/12/27: Re: [q][Reverse Engineering Protection]
    2630: 96/01/16: Re: [q][Reverse Engineering Protection]
    2636: 96/01/17: Re: [q][Reverse Engineering Protection]
Henry Davis:
    5947: 97/03/28: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
    49266: 02/11/07: Re: Instruction sets to implement instruction sets
    49289: 02/11/07: Re: Instruction sets to implement instruction sets
Henry F Fernandes:
    6508: 97/05/29: new to FPGAs
Henry F. (Hank) McCall:
    6922: 97/07/09: Re: fast scopes: how?
    6923: 97/07/09: Re: Generating Sine/Cosine digitally
Henry Selvaraj:
    5647: 97/03/04: ICCIMA'98 Call for papers (includes a special session on Logic Synthesis and AI)
    5893: 97/03/24: ICCIMA'98 Special Sessions - First CFP
    6240: 97/05/02: Special Session on AI and Logic Synthesis: CFP
    6746: 97/06/23: Logic Synthesis and AI - Special Session - Final CFP
Henry Spencer:
    44: 94/08/03: Re: How pricey is FPGA development?
    69: 94/08/08: Re: How pricey is FPGA development?
    100: 94/08/15: Re: FPGA Hobbyist and their software/programmer/hardware
    104: 94/08/16: Re: FPGA Hobbyist and their software/programmer/hardware
    109: 94/08/16: Re: FPGA Hobbyist and their software/programmer/hardware
    128: 94/08/18: Re: FPGA Hobbyist and their software/programmer/hardware
    370: 94/10/31: Re: Metastable Immune? (Was: High Bus Drive (24mA) FPGAs/CPLDs?)
    2211: 95/11/02: Re: Xilinx Configuration Memory Hacking
    2244: 95/11/09: Re: Xilinx Configuration Memory Hacking
    2540: 95/12/29: Re: [q][Reverse Engineering Protection]
    3720: 96/07/21: Re: Hardware sort?
    3931: 96/08/21: Re: INDUSTRY GADFLY: EDA Goes OJ
    4883: 96/12/24: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4937: 97/01/02: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5010: 97/01/12: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5024: 97/01/14: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5042: 97/01/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5255: 97/02/02: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5728: 97/03/11: Re: Reverse Engineering FPGAs
    5729: 97/03/11: Re: Reverse Engineering FPGAs
    5635: 97/03/03: Re: Reverse Engineering FPGAs
    5803: 97/03/16: Re: Reverse Engineering FPGAs
    5873: 97/03/21: Re: Sole source
    5884: 97/03/23: Re: Sole source
    5885: 97/03/23: Re: Complexity of standards
    5926: 97/03/26: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
    5949: 97/03/28: Re: HELP! - peel programming?
    6051: 97/04/08: temperature (was Re: Sole source)
    6052: 97/04/08: Re: Chip Temperature (was:Re: Sole source)
    7075: 97/07/29: Re: Design Protection in FPGAs
    7220: 97/08/15: Re: Price of Serial EEPROM is Outrageous
    7503: 97/09/18: Re: 6809 discontinued
    7525: 97/09/19: Re: 6809 discontinued
    7546: 97/09/21: Re: Hacking bitstream formats
    7553: 97/09/21: Re: Hacking bitstream formats
    7552: 97/09/21: Re: Hacking bitstream formats
    7669: 97/10/01: Re: Hacking bitstream formats
Henry Styles:
    24740: 00/08/17: Re: Board suggestion for high gate count FPGA board
    28519: 01/01/16: Re: Looking for prototyping board
    41443: 02/03/28: Re: Handel-C useless.. Move to SystemC
    55379: 03/05/06: Re: Hardware acceleration for raytracing purposes
Henry Thomas:
    5602: 97/02/28: Re: Cypress says good-bye to Anti-Fuse
    5655: 97/03/04: Timing simulator for Warp 4.1 that works under Win NT 4.0
    5654: 97/03/04: Re: Cypress says good-bye to Anti-Fuse
    5727: 97/03/11: Re: Timing simulator for Warp 4.1 that works under Win NT 4.0
Henry Wong:
    87297: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    102054: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
    103021: 06/05/24: Re: Stopping Quartus using multipliers?
    103044: 06/05/25: Re: Superscalar Out-of-Order Processor on an FPGA
    110027: 06/10/09: Re: Quartus II 6.0
    110439: 06/10/15: Re: echo $LM_LICENCE_FILE not working
    132947: 08/06/11: Re: Altera Quartus Web Edition 8.0 available
    132995: 08/06/12: Re: Altera Quartus Web Edition 8.0 available
Henryk Cieslak:
    24086: 00/07/26: Re: F3.1 in Great Britain
    25363: 00/09/08: Re: 3.3/2.5 voltage regulators
<henryk.mueller@gmx.de>:
    103349: 06/05/31: Virtex-4FX12MM: Any hardware MAC address accessable?
    103352: 06/05/31: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
    103355: 06/05/31: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
    103386: 06/06/01: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
<hepmehepme@comcast.net>:
    140276: 09/05/07: Seeding random number generator
Herb T:
    81079: 05/03/17: Beginning Xilinx FPGA Tutorials?
    81159: 05/03/18: Re: Beginning Xilinx FPGA Tutorials?
    81446: 05/03/23: Re: ISE 7.1 on Fedora Core 3
    81447: 05/03/23: Re: ISE 7.1 on Fedora Core 3
    81574: 05/03/27: Spartan 3, Microblaze and FPU
    81588: 05/03/28: Re: Spartan 3, Microblaze and FPU
    81665: 05/03/29: Re: ISE
    81666: 05/03/29: Re: ISE
    82771: 05/04/17: Re: EDK:input to microblaze
    82890: 05/04/19: Re: EDK:input to microblaze
    84033: 05/05/11: Analog to Digital Converted (ADC) & Spartan 3
    84035: 05/05/11: Re: Analog to Digital Converted (ADC) & Spartan 3
    84038: 05/05/11: Re: Analog to Digital Converted (ADC) & Spartan 3
Herbert Kleebauer:
    1627: 95/08/07: Re: 16 bit computer on fpga's
    4140: 96/09/17: Re: manchester clock recovery
    6969: 97/07/17: free FPGA software from actel
    6968: 97/07/17: free FPGA software from actel
    12882: 98/11/03: Re: New free FPGA CPU
    12915: 98/11/04: Re: New free FPGA CPU
    12981: 98/11/09: Re: FPGA VGA interface
    15283: 99/03/17: 16 bit minimal processor
    24522: 00/08/11: Re: Viewlogic to Orcad conversion
    27601: 00/11/29: Re: Gates in a typical small MPU
    38461: 02/01/15: Re: Homebrew computers using FPGA?
    42464: 02/04/24: Re: Prototyping Boards for Hobbyist CPU/System Designs
    55701: 03/05/16: Re: smallest embedded cpu.
    114448: 07/01/16: Re: small, free simple state machine processor suggestions?
    116887: 07/03/20: FPGA with 5V and PLCC package
    116945: 07/03/21: Re: FPGA with 5V and PLCC package
    116946: 07/03/21: Re: FPGA with 5V and PLCC package
    116947: 07/03/21: Re: FPGA with 5V and PLCC package
    116948: 07/03/21: Re: FPGA with 5V and PLCC package
    116949: 07/03/21: Re: FPGA with 5V and PLCC package
    116950: 07/03/21: Re: FPGA with 5V and PLCC package
    117044: 07/03/22: Re: FPGA with 5V and PLCC package
    117199: 07/03/26: Re: FPGA with 5V and PLCC package
    117356: 07/03/29: Re: FPGA with 5V and PLCC package
    117371: 07/03/29: Re: FPGA with 5V and PLCC package
    117559: 07/04/04: Re: FPGA with 5V and PLCC package
    118409: 07/04/26: Re: DARNAW! - PGA Style FPGA Module
    119005: 07/05/09: Re: An Open-Source suggestion for Xilinx
    121123: 07/06/26: Re: DARNAW! - PGA Style FPGA Module
    126073: 07/11/14: FPGA for hobby use
    126132: 07/11/15: Re: FPGA for hobby use
    126133: 07/11/15: Re: FPGA for hobby use
    127766: 08/01/07: Re: Processor in CPLD
    128398: 08/01/24: Re: microblaze question
    130469: 08/03/25: Re: Designing CPU
    134309: 08/08/06: Re: Schematic Capture tutorials/books?
    134313: 08/08/06: Re: Schematic Capture tutorials/books?
    134347: 08/08/07: Re: Schematic Capture tutorials/books?
    135801: 08/10/16: Re: A couple of CPLD design challenges for the group
    135807: 08/10/16: Re: A couple of CPLD design challenges for the group
    138881: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138889: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138910: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    138927: 09/03/15: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    139027: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
    142430: 09/08/11: Re: Spartan-6 Boards - Your Wish List
    142541: 09/08/16: Re: Soft Processor IP core report
    142549: 09/08/16: Re: Soft Processor IP core report
    142550: 09/08/16: Re: Soft Processor IP core report
    142560: 09/08/17: Re: Soft Processor IP core report
    143168: 09/09/23: Re: Shift left arithmetic?
    143760: 09/10/24: Re: ISe 10.1 nightmare bug
    147786: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
    153488: 12/03/09: Re: CPU Design in Xilinx Spartan 3E
    153658: 12/04/10: Re: Data Transfer from PC to FPGA through USB
    153659: 12/04/10: Re: CPU Design in Xilinx Spartan 3E
    153913: 12/06/29: Re: Replacement for XC4005E
    154930: 13/02/19: Re: Help with .mem and .bmm file generation
    154932: 13/02/20: Re: Help with .mem and .bmm file generation
    155920: 13/10/16: Re: draw lines, circles, squares on FPGA by mouse and display on
    158821: 16/04/16: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
    158837: 16/04/26: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
Herbert Larbie:
    1062: 95/04/23: Lattice low-cost start kit
    1148: 95/05/05: Re: FPGA price trends?
    1523: 95/07/07: Abel and connectedt tri-state outputs
Herbi:
    34187: 01/08/16: Readback Xilinx Vertex FPGA
    34192: 01/08/16: Re: Help with ACEX1K100 device
    34193: 01/08/16: Re: Development boards
    34194: 01/08/16: Re: FPGA for Reconfigurable Computing
Herbie:
    41942: 02/04/11: Destroying Xilinx xc4000 etc
Herman:
    20807: 00/02/23: Re: Bit Serial Arithmetic De-mystified
    20852: 00/02/24: Re: MRP systems
    22559: 00/05/12: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
    22601: 00/05/13: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
    24597: 00/08/15: Re: Non-disclosures in job interviews
Herman Beke:
    12643: 98/10/21: Re: Fixed-point arithmetic coding
    16517: 99/05/26: Re: C to VHDL translator?
Herman Dullink:
    96867: 06/02/12: Re: which one among the available FPGAs is best for a fresher?
    103380: 06/06/01: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
Herman Oosthuysen:
    27401: 00/11/21: Re: ANNOUNCE: Checksum and CRC Code/Article
    27678: 00/12/02: Re: ANNOUNCE: Checksum and CRC Code/Article
    27701: 00/12/04: Re: ANNOUNCE: Checksum and CRC Code/Article
    43288: 02/05/17: Re: SDRAM pricing
Herman Roebbers:
    88209: 05/08/11: Call for Delegates Communicating Process Architectures 2005 at Eindhoven
    89127: 05/09/06: Final Call for Participants CPA 2005 (18-21 Sept 2005) in Eindhoven
    89148: 05/09/06: Final Call for Participants & fringe CPA 2005 (18-21 Sept 2005) in Eindhoven
Herman Rubin:
    331: 94/10/21: FPGA's to use with other devices
    4212: 96/09/27: Re: hardware implementation of permutation multiplication
    11450: 98/08/14: Re: Combinatoric Divide-by-3 Algorithm
    29347: 01/02/15: Re: double precision floating point arithmetic
    67428: 04/03/11: Re: difference btw H/W & S/W implementations !!
    67565: 04/03/14: Re: difference btw H/W & S/W implementations !!
Herman Schmit:
    1960: 95/09/25: PREP benchmarks
    2904: 96/02/27: Re: Languages for reconfigurable computing.
    2976: 96/03/07: Re: Reconfigurable Computing Languages
    3006: 96/03/12: Re: Reconfigurable Computing Languages
    3008: 96/03/13: Sq. Roots and Languages
    8642: 98/01/15: XC6200 Questions
    16426: 99/05/21: CFP: FPGA 2000
    17227: 99/07/12: CFP: FPGA 2000
    17229: 99/07/12: Re: Benchmark circuits - in VHDL for FPGA
    17690: 99/08/24: CFP: FPGA 2000
    18165: 99/10/04: FPGA 2000: Paper Deadline Extension
Hermann Winkler:
    17174: 99/07/07: Tristate Register in Xilinx 4000XLA IO block
    35544: 01/10/10: Virtex2 DCM: frequenqy synthesis
Hermann-Josef Hebbelmann:
    899: 95/03/23: Divider in Xilinx 4000
Hernan:
    15538: 99/03/29: Re: Info about FPGA/PLD
Hernan Saab:
    18543: 99/10/29: Re: Hold times for Xilinx FPGAs
    20679: 00/02/17: Re: Xilinx hold time problems...
    24365: 00/08/04: Re: Who needs all those printed ac parameters? (sw should be the data
    24486: 00/08/10: Re: 3-state busses on Virtex?
hernan saab:
    17937: 99/09/17: test
Hernan Sanchez:
    22501: 00/05/10: Re: ? economical SPROM programmer for Xilinx
Hernán Sánchez:
    65095: 04/01/20: Re: ISE 6.1 and Win2000 sp4
    65622: 04/02/03: Re: Clocking an FPGA??
    76224: 04/11/29: Re: fpga prices
Herrera, Alfredo [CAR:5T12:EXCH]:
    38265: 02/01/10: coregen in Alliance ISE v4.1i
<herry@poste.isima.fr>:
    17375: 99/07/23: Using Xilinx Foundation & Mentor Graphics
<hershkoy@gmail.com>:
    126248: 07/11/18: synthesizing vqm with parameters with quartus 7.1sp1
Hervé Echelard:
    15529: 99/03/29: Xilinx Download Serial Cable
Herwig Dietl:
    64141: 03/12/18: Re: VHDL comments in Vim?
Herwin:
    65857: 04/02/08: mixing LVDS data
    75589: 04/11/10: VirtexII-Pro MGT: 8/10 coding bypass problems
    75604: 04/11/10: Re: VirtexII-Pro MGT: 8/10 coding bypass problems
    75711: 04/11/12: Re: VirtexII-Pro MGT: 8/10 coding bypass problems
hess:
    127335: 07/12/18: Altera USB-Blaster on RHEL 5?
<hess.gremio@gmail.com>:
    157710: 15/02/10: Re: FPGA : Open core FFT
hetfield:
    89632: 05/09/21: Count "1" bit in bit stream
    89635: 05/09/21: Re: Count "1" bit in bit stream
    89640: 05/09/21: Re: Count "1" bit in bit stream
    89675: 05/09/21: Re: Count "1" bit in bit stream
heyho:
    38903: 02/01/28: Re: Pin assignment on ACEX1K
    39274: 02/02/05: Re: I want pla2tdf.exe
<heynow567@yahoo.com>:
    81393: 05/03/22: TI SN54LVT8980A JTAG TAP MASTER
<hezhikuan2007@gmail.com>:
    123717: 07/09/02: [Nios II] How Can I define the pio inputs as a interrupt?
    123720: 07/09/02: Re: How Can I define the pio inputs as a interrupt?
    123848: 07/09/05: =?gb2312?B?ob5OaW9zIElJob9Ib3cgQ2FuIEkgRmluZCBPdXQgVGhlc2UgRnVuY3Rpb25zIKO/?=
Hezi Hershkovitz:
    76124: 04/11/25: peculiar process behavioral when using modelsim se 5.8d
<hezyxf@zwallet.com>:
HG:
    9154: 98/02/25: Re: Correlation implementation...
    9160: 98/02/25: Re: PLL design with Xilinx 4kseries
hgs:
    114983: 07/01/28: Problem with pin assign using CASE
    114984: 07/01/28: Problem with pin assign using CASE
    114995: 07/01/28: Re: Problem with pin assign using CASE
HH:
    21331: 00/03/16: Re: ,,..SAY A PRAYER FOR THE INNOCENT VICTIMS OF BLACK VIOLENCE AND LAWLESSNESS!!..
    21747: 00/03/30: Re: What's so good about antifuse???
hhk:
    16152: 99/05/06: Fpga gates, PLD gates ASIC gates: Help us please.
    16156: 99/05/06: Re: Help me: What is FPGA?
Hi Tech Jobs:
    9009: 98/02/13: Digital FPGA Design requirements ==> AZ
    9096: 98/02/19: AZ - JOB => Digital FPGA Design Engineers needed...........
    9127: 98/02/22: => AZ : Digital FPGA Design/Modem Tech => AZ
    9161: 98/02/25: Digital FPGA (ASIC) -High Speed Modem Technology Designers needed.......
    9407: 98/03/10: Digital FPGA Digital Designer opportunities => AZ
    9485: 98/03/17: JOB > AZ Digital FPGA Modem Design
    9915: 98/04/13: AZ=> ASIC/FPGA Digital Designers needed.......
Hicks:
    36952: 01/11/27: Re: Device Support in Webpack
    38672: 02/01/21: Re: help me!
    38676: 02/01/21: Re: help me!
    38697: 02/01/22: effective high resolution counter using DLL clock phases
HIDDEN:
    147721: 10/05/19: sensor-FPGA-DSP image processing
    147723: 10/05/19: Re: sensor-FPGA-DSP image processing
Hideki Itoh:
    4045: 96/09/05: Re: XACT STEP 6.0.1 SETUP PROBLEM
Hidemi Ishihara:
    64803: 04/01/15: Installed Xilinx ISE6.1i on the Fedora
Hiding in Plain Sight:
    87492: 05/07/25: Re: Xilinx software update?
    88235: 05/08/12: Re: Xilinx ISE 6.3i on Gentoo Linux
    88406: 05/08/17: Re: Xilinx ISE on remtoe Display
    88940: 05/08/31: Re: Spartan 3 Serdes
    89186: 05/09/07: Re: ISE 64bit question
    89305: 05/09/12: Re: SDRAM quality
Hien Pham:
    28172: 00/12/24: Re: ActiveHDL 4.1?
    37913: 01/12/24: What the many ways to meet FPGA timing ?
<hiennguyen@my-deja.com>:
    24243: 00/07/31: Re: OT: was Re: Which one is good coding style?
HighTech:
    3754: 96/07/25: Re: Job posting
highwayismyway:
    77273: 05/01/02: Recover FPGA Verilog or VHDL source from .SOF file
<highZ>:
    113965: 06/12/31: xilinx xc9536?
    113979: 07/01/01: Re: xilinx xc9536?
    113984: 07/01/02: Re: xilinx xc9536?
HIKIMA Toshio:
    2805: 96/02/10: Xilinx is NOT specified MINIMUM delay -- is it right??
hikmetkoca:
    111381: 06/11/02: I can not simulate "pipelined divider v3.0"
    111794: 06/11/10: C3188A - 1/3"Digital Output Colour Camera Module
    111795: 06/11/10: Re: Code for Verilog 8bit * 8bit pipelined multiplier
    111824: 06/11/10: Re: C3188A - 1/3"Digital Output Colour Camera Module
<hilo_pupu@hotmail.com>:
    128720: 08/02/05: How to optimize my design area to fit?
    128843: 08/02/07: What does "Continuous Sample times are not allowed" mean in SysGen
    128872: 08/02/08: How to get Map Repoprt after System Generator postmap estimation
    128876: 08/02/08: Problem in assignment of pins in PACE
    128932: 08/02/10: Re: Downloading codes to FPGA development Board
    129451: 08/02/25: Command to unzip hardware cosim files
    129484: 08/02/26: Hardware Cosim no output
    129893: 08/03/08: Hardware Cosim one wrong output and one correct output
HiltDesign:
    6455: 97/05/25: Re: Best way to learn VHDL?
<hiluckydr@gmail.com>:
    156685: 14/06/04: Re: Partial Reconfiguration clock enable problem
Hima Bindu Yalamati:
    2789: 96/02/08: High Speed FPGA's and EPLD's
    2790: 96/02/08: Info wanted on high speed(3-5ns) FPGA's
<hima.aj@gmail.com>:
    155725: 13/08/22: Problem in Xilinx xapp1052 DMA PCIE custom flow
<himalayas-1@263.net>:
    18036: 99/09/25: Help for viewlogic73!
<himalayas@my-deja.com>:
    19790: 00/01/12: Help for EDIF format !
    19793: 00/01/12: Re: Help for EDIF format !
Himani:
    71165: 04/07/10: Nios2 on Parallax Cyclone board (SmartPack)
himanshu:
    35491: 01/10/08: Virtex-2 maximum clock speed
Himanshu Pokharna:
    12633: 98/10/20: How many ASIC per port for Switches?
himassk:
    85745: 05/06/15: VHDL Synthesis tutorial
    85923: 05/06/18: Interesting question on CPLD
    90699: 05/10/19: which is Low power FPGA?
    90703: 05/10/19: Re: which is Low power FPGA?
    91096: 05/10/29: How to reduse the logic.
    108279: 06/09/07: RTL deisgn for Blocking and Nonblocking
    108280: 06/09/07: 2 FF synchronizer
    110645: 06/10/19: How to avoid negative slack.
    111390: 06/11/02: How to avoid negative slack?
    118909: 07/05/07: FF setup and hold time.
    119269: 07/05/15: clock wide pulse transfer b/w clock domains
Himlam8484:
    115461: 07/02/12: Picobalze in the FPGA
    115515: 07/02/12: Picobalze in the FPGA
    115530: 07/02/13: Re: Picobalze in the FPGA
    115928: 07/02/26: Picobalze in the FPGA
    116019: 07/02/27: Re: Picobalze in the FPGA
    116508: 07/03/11: Comunicate FPGA to Ethernet
Hing-Fai Lee:
    1209: 95/05/14: Re: FLEXlogic opinions?
    1424: 95/06/21: Re: altera mail adress ?
    1552: 95/07/13: Re: Flex 8000: Locking down pins
    2387: 95/11/27: Re: CRC-32 implementation
    13736: 98/12/21: Re: Xilinx FlowEngine vs Batch file?
    14200: 99/01/19: Re: Ratings for Synplicity Synplify
5hinka:
    68185: 04/03/29: DPLL in FPGA's (xilinx) ??
    72931: 04/09/08: vhdl error ?? - [code included]
    72943: 04/09/08: Re: vhdl error ?? - [code included]
    73019: 04/09/10: std_logic_textio - in xilinx
    73073: 04/09/13: two questions about spartan/xilinx devices??
    75231: 04/10/30: Webpack / Multisim - jitter simulation ??
Hippolyte Lizard:
    37156: 01/12/01: XNF file gets corrupted
hirenshah.05@gmail.com:
    90875: 05/10/24: verilog code
    92123: 05/11/22: data encryption standard
    92133: 05/11/22: Re: data encryption standard
    92654: 05/12/02: internal clock
hiro:
    28113: 00/12/22: testbench generation tool
    42388: 02/04/23: INIT constrain
    48768: 02/10/24: LVDS standard
    49036: 02/10/30: Virtex2 Prototyping Board
    49295: 02/11/08: BUFT bus contention
    49799: 02/11/21: clock enable timing analysis
    64019: 03/12/12: Spartan-IIE TDO and CCLK pin status
    68803: 04/04/19: OPB bus burst transfer support?
Hiroshi Miyauchi:
    2506: 95/12/21: Re: Looking for OpenABEL
hiroyuki.kawai0914@gmail.com:
    126786: 07/12/02: XHwICAP functions on EDK
    128405: 08/01/24: XST_BUFFER_TOO_SMALL
hiroyuki.kawai@gmail.com:
    124824: 07/10/05: Re: Using PlanAhead for Partial Reconfiguration
<hirsch_yoav@hotmail.com>:
    28261: 01/01/04: Re: Question about Xilinx pins at high-frequency
    28259: 01/01/04: XILINX SRL16E - FIFO
<hirsch_yoav@my-deja.com>:
    28287: 01/01/05: Re: XILINX SRL16E - FIFO
hitajian:
    35020: 01/09/18: BUGs ?
    36057: 01/10/27: Confusion of Macro!
    36745: 01/11/19: Problems of Amplify about Modular Design
HiTech:
    84819: 05/05/28: FPGA Boards
Hitesh Brahmbhatt:
    12413: 98/10/11: Brand New Books for sale at 20% discount
    39167: 02/02/03: To Prevent Xilinx Mapper from Removing the RAMs in ISE 4.1i
Hitesh Patel:
    13757: 98/12/22: Xilinx - Viewlogic Virtex Support
hits:
    55268: 03/05/02: Carry skip adder implementation in FPGAs
hitsx@hit.edu.cn:
    94071: 06/01/05: Re: Clock generation
    94195: 06/01/07: Re: Schematic Entry, Xilinx or Altera?
    94073: 06/01/05: What kind of cpu is suit for me?
    94156: 06/01/06: Re: What kind of cpu is suit for me?
    100466: 06/04/10: How to handle the high fanout
    100537: 06/04/11: Re: How to handle the high fanout
    102803: 06/05/21: MicroBlaze as SubModule Problem
    102810: 06/05/21: Re: MicroBlaze as SubModule Problem
    102812: 06/05/21: Re: MicroBlaze as SubModule Problem
    102922: 06/05/23: Re: MicroBlaze as SubModule Problem
    118120: 07/04/17: Any recommendations for FPGA PCI development board?
    118218: 07/04/19: Re: Any recommendations for FPGA PCI development board?
    120904: 07/06/19: Interesting problems about high performance computing
    120952: 07/06/21: Re: Interesting problems about high performance computing
    120953: 07/06/21: Re: Interesting problems about high performance computing
    121015: 07/06/21: Re: Interesting problems about high performance computing
    121016: 07/06/21: Re: Interesting problems about high performance computing
    121031: 07/06/22: Re: Interesting problems about high performance computing
    121069: 07/06/24: Re: Interesting problems about high performance computing
    121070: 07/06/24: How to choose FPGA for a huge computation?
    121108: 07/06/25: Re: How to choose FPGA for a huge computation?
    121130: 07/06/26: Re: How to choose FPGA for a huge computation?
    121910: 07/07/15: Re: Interesting problems about high performance computing
Hjhke:
    33989: 01/08/09: Re: Reconfigurable Computational Accelerator
HJO:
    51548: 03/01/16: Xilinx PCI core PCI-X compatible ?
    61264: 03/10/01: Re: Implementing Bidirectional pins
hlao:
    133443: 08/06/29: Quartus-II 8.0 resource-sharing? (why inferred addsub takes 2x LUTs?)
HLD PUBLISHING:
    3677: 96/07/11: Is your computer being bugged????
<Hlebasko@t-online.de>:
    13073: 98/11/14: Low Cost FPGA Development Tools
<hmmudassir82@gmail.com>:
    133769: 08/07/14: usb core
    133840: 08/07/17: usb core
    133844: 08/07/17: usb core block diagram
    133851: 08/07/17: Re: GTP simulation problems
    133852: 08/07/17: free of bugs
    133853: 08/07/17: full timing diagram
    133854: 08/07/17: protocol layer
    133856: 08/07/17: UTMI
    133867: 08/07/17: Re: free of bugs
    133868: 08/07/17: Re: free of bugs
    133869: 08/07/17: USB 1.1 Function IP Core
    133870: 08/07/17: USB 1.1 Function IP Core
HNS:
    95155: 06/01/20: Re: Irrelevant, stupid, racist, and worse.
Ho Siu Hung:
    6701: 97/06/17: DES cracker project
    7753: 97/10/11: Re: How fast can fully pipelined XC4000 logic go?
    7951: 97/11/03: Re: Questions about FPGA hardware design
    8721: 98/01/22: XC4000E CLB utilization
    9163: 98/02/26: Re: XC4000E CLB utilization (again...)
    9588: 98/03/25: CMOS or TTL?
    9777: 98/04/05: VHDL in synopsys -> M1
    9813: 98/04/07: Re: VHDL in synopsys -> M1
    9983: 98/04/21: Re: Demonstrate the power of your FPGA system. Win $10k.
    10032: 98/04/23: Re: Synopsys FPGA compiler
Ho Voon Yee:
    9724: 98/04/02: Altera Bitblaster or Byteblaster
    10465: 98/05/20: 44 pins size fpga or cpld
Ho Wong:
    47623: 02/10/01: Rounting of non-global IO pad to a GCLKIOB site.
    47626: 02/10/01: Re: Rounting of non-global IO pad to a GCLKIOB site.
    47690: 02/10/02: Block Ram Timing Issues
    47693: 02/10/02: Whoops.. forget that last post.
Ho0gA:
    58589: 03/07/28: dataio 3900 system disk
Hoa Phan:
    29891: 01/03/15: Re: Parallel Port EPP (again)
    29894: 01/03/16: Looking for VHDL code or ABEL+schematic capture for interfacing parallel port in mode EPP
<hobin0920@gmail.com>:
    121499: 07/07/05: USB analyzer evaluation
Hobson:
    40112: 02/02/27: Re: Creation of FPGA tips and tricks forum - help required
    41024: 02/03/19: Re: Constraint File NET syntax
    41035: 02/03/19: Re: STARTUP_VIRTEX primitive
Hobson Frater:
    14159: 99/01/15: Re: Xilinx Bitstream
    14218: 99/01/20: Re: Design manager
    14984: 99/03/01: Re: Problem with xilinx M1
    15256: 99/03/16: Re: Problems with foundation
    15302: 99/03/17: Re: Xilinx Spartan configuration troubles
    15416: 99/03/23: Re: FPGA Express, STARTUPs and user clocks
    16188: 99/05/07: Re: problem with Prentice-Hall student edition Xilinx
    16735: 99/06/04: Re: Initial Values, Xilinx Virtex
    16787: 99/06/08: Re: Initial Values, Xilinx Virtex
    21409: 00/03/21: Re: FPGA openness
    30136: 01/03/24: Re: How to find out where par placed things?
<hodunov07@gmail.com>:
    156303: 14/02/13: Re: Monostable multivibrator
Hofjue:
    121368: 07/07/03: Re: Microblaze and software interrupts?
    121465: 07/07/05: Re: Microblaze and software interrupts?
    121787: 07/07/13: Re: Microblaze and software interrupts?
    121994: 07/07/16: Re: Microblaze and software interrupts?
<hofmann.juergen@pc-future.de>:
    121361: 07/07/03: Microblaze and software interrupts?
hokie03:
    138403: 09/02/19: Problem loading my bitstream into the parallel NOR flash using the
hokutoi:
    118144: 07/04/18: There is something (other) like his?
hol:
    73626: 04/09/26: AVNET's Xilinx prototyping modules (AvBus cable?!?)
    73627: 04/09/26: embedded linux on FPGA?
Holger:
    63032: 03/11/13: SystemC Implementation
Holger Azenhofer:
    20098: 00/01/27: microcontroller in vhdl
    21475: 00/03/23: DCF 77
    22720: 00/05/19: 68k - core
Holger Baxmann:
    49901: 02/11/24: picoJava & the other of Eclipse Sun
    70137: 04/06/04: IDE/ATA _device_ core availablility
    70151: 04/06/05: Re: IDE/ATA _device_ core availablility
Holger Blum:
    87304: 05/07/21: IP-cores for digital audio
    94622: 06/01/14: Mistake in Xilinx dsp-book.pdf?
    95701: 06/01/25: Re: Mistake in Xilinx dsp-book.pdf?
Holger Englert:
    44785: 02/07/01: Reconfiguring .SOF file
Holger Hellmuth:
    210: 94/09/22: Re: PLD for async state machine?
    443: 94/11/17: Re: Anybody used FPGA as Encryption Device?
    841: 95/03/10: Re: Questions of implementing asynchronous circuits using FPGAs.
Holger Kleinegraeber:
    44205: 02/06/14: must signals to ram come from a register?
    44269: 02/06/15: Re: must signals to ram come from a register?
    44400: 02/06/19: Re: ISE Webpack Basics
    44961: 02/07/08: Virtex reset signal internaly hold?
    44963: 02/07/08: Re: ModelSim License problem
    45769: 02/08/05: Re: Controller for a Architecture
    45808: 02/08/06: Re: Controller for a Architecture
Holger Kleinert:
    19163: 99/12/02: Re: data serializer/decoder FPGA solution
    19233: 99/12/07: Re: JTAG on PCI slot
    19250: 99/12/08: Re: JTAG on PCI slot
    19275: 99/12/09: Re: EEPROM for spartan xl series FPGA?
    20052: 00/01/25: Re: Xilinx Foundation: VHDL to symbol
    20156: 00/01/29: Re: Spartan XL
    20276: 00/02/03: VHDL and Xilinx Books for beginners
    20789: 00/02/22: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
    20816: 00/02/23: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
    20817: 00/02/23: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
    20968: 00/03/01: Re: Xilinx PCI pinout ?
    21118: 00/03/07: Re: Stupid Foundation question
    21410: 00/03/22: Re: How to solder FPGA in BGA package ?
    21412: 00/03/22: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
    21417: 00/03/22: Re: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
    21422: 00/03/22: How to implement STARTBUF / GSR with SpartanXL and VHDL on FNDTN 2.1i ?
    21634: 00/03/27: Re: Good book on learning FPGA/VHDL/Verilog programming
Holger Nissle:
    76313: 04/11/30: Re: Running EDK 6.2i with ISE6.3i
    85107: 05/06/04: Re: How to get *.mcs file containing both *.bit and *.elf file, to port linux on my memec virtex-ii board.
Holger Petersen:
    2507: 95/12/21: Re: UART in PLD
Holger Schmidt:
    7978: 97/11/05: Re: interface between FPGA & user?
Holger Veit:
    2560: 96/01/02: Re: Career value: VHDL or Verilog?
    2601: 96/01/10: Re: Career value: VHDL or Verilog?
    44949: 02/07/08: Re: ModelSim License problem
    47810: 02/10/04: Re: FPGA with an EPROM on it?
    47948: 02/10/08: Re: Booting a FPGA via USB
    48332: 02/10/16: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
    49693: 02/11/19: Re: What combinational logic will produce a falling edge only.
    49788: 02/11/21: Re: What combinational logic will produce a falling edge only.
    50385: 02/12/10: Re: How to assign pins in VHDL?
    57184: 03/06/25: Re: Interfacing IDE
Holger Venus:
    3912: 96/08/19: Synth. VHDL PCI Model?
    6323: 97/05/15: VHDL PCI FPGA Implementation
    12533: 98/10/15: Re: Xilinx Foundation forgets the pin assignment. Bug?
    18593: 99/11/02: Re: StateCAD versus Viewdraw
    21384: 00/03/21: Re: Actel Design with A42MX36 Help
    46070: 02/08/16: MicroBlaze processor core
    46071: 02/08/16: Re: transputers
    46509: 02/09/02: Re: Thermoelectric Controller by FPGAs
<HollyRobinson@ThisSite.net>:
    10565: 98/05/30: ! Voyeur Cams 86397
Holm M.:
    48635: 02/10/22: Re: How to read files in a CompactFlash?
<holosapien@my-deja.com>:
    18467: 99/10/26: FPGA Starter Kit
<homelab@hotmail.co.uk>:
    114036: 07/01/03: Re: OT. Re: Surface mount ic's
homeless:
    154341: 12/10/09: modelsim SE 10.0C SystemC bug about initializing sc_signal
    154354: 12/10/12: Re: modelsim SE 10.0C SystemC bug about initializing sc_signal
Homer J Simpson:
    107646: 06/08/30: Re: Performance Appraisals
    107899: 06/09/02: Re: Performance Appraisals
    107901: 06/09/02: Re: Performance Appraisals
    108034: 06/09/04: Re: Please help me with (insert task here)
    108039: 06/09/04: Re: Please help me with (insert task here)
    108223: 06/09/06: Re: Please help me with (insert task here)
    108299: 06/09/07: Re: Performance Appraisals
    108300: 06/09/07: Re: Performance Appraisals
    108453: 06/09/11: Re: Performance Appraisals
    112470: 06/11/22: Re: board - T562.jpg
    112479: 06/11/23: Re: board - T562.jpg
    112505: 06/11/23: Re: board - T562.jpg
    112511: 06/11/23: Re: board - T562.jpg
    112520: 06/11/23: Re: board - T562.jpg
    112549: 06/11/24: Re: board - T562.jpg
    112562: 06/11/24: Re: board - T562.jpg
    112567: 06/11/24: Re: board - T562.jpg
    112571: 06/11/25: Re: board - T562.jpg
    112587: 06/11/25: Re: board - T562.jpg
    112589: 06/11/25: Re: board - T562.jpg
    112594: 06/11/25: Re: board - T562.jpg
    112595: 06/11/25: Re: board - T562.jpg
    112596: 06/11/25: Re: board - T562.jpg
    112597: 06/11/25: Re: board - T562.jpg
    112602: 06/11/26: Re: board - T562.jpg
    112611: 06/11/26: Re: board - T562.jpg
    112612: 06/11/26: Re: board - T562.jpg
    112618: 06/11/26: Re: board - T562.jpg
    112627: 06/11/27: Re: board - T562.jpg
    112630: 06/11/27: Re: board - T562.jpg
    112712: 06/11/28: Re: board - T562.jpg
    112717: 06/11/28: Re: board - T562.jpg
homoalteraiensis:
    105267: 06/07/19: Synthesis Problems with Quartus II Version 6.x
    105269: 06/07/19: corrupted data when accessing dual port bram in Cyclone II
    105271: 06/07/19: Re: corrupted data when accessing dual port bram in Cyclone II
    105285: 06/07/19: Re: Sorting algorithm for FPGA availlable?
    105288: 06/07/19: Re: corrupted data when accessing dual port bram in Cyclone II
    105418: 06/07/22: Re: corrupted data when accessing dual port bram in Cyclone II
    105459: 06/07/24: Re: version control of ISE+EDK projects with CVS and/or SVN
    106024: 06/08/05: Re: FPGA interface to serial ADC
    106025: 06/08/05: Re: Cyclone I & II memory fmax
    106026: 06/08/05: Re: large data access to SDRAM at fixed frequency
    106027: 06/08/05: Re: ASIC Design Engineer Job in SHENZHEN China
    106281: 06/08/10: Re: FPGA interface to serial ADC
    106287: 06/08/10: synthesis intelligence of quartus regarding range of values
    106489: 06/08/14: Re: synthesis intelligence of quartus regarding range of values
    106490: 06/08/14: Re: Altera SOPC ModelSim question
    106492: 06/08/14: Video - DSP Eval board with Altera
    106551: 06/08/15: Re: synthesis intelligence of quartus regarding range of values
    106566: 06/08/15: Alternative for Mentor''s HDL Designer
    106909: 06/08/22: Re: Why is Spartan-3 more expensive than Cyclone?
    106910: 06/08/22: Re: Alternative for Mentor''s HDL Designer
Homuncilus:
    116768: 07/03/17: Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*
    116782: 07/03/17: Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*
    116813: 07/03/19: Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*
    140405: 09/05/12: Re: how i can use the external SRAM of FPGA
Hona:
    64001: 03/12/11: Re: Verilog-2001 `define expressions?
Honey News:
    15415: 99/03/23: HELP ME : About JTAG on Altera Flex 10k
Hong:
    33026: 01/07/15: Re: How to fan out signals to bus lines in Xilinx Foundation Schematic Editor?
    33069: 01/07/16: Re: How to fan out signals to bus lines in Xilinx Foundation Schematic Editor?
    33127: 01/07/17: Re: DDS Xilinx Core
    33287: 01/07/22: Re: Altera ISP - JTAG
    33444: 01/07/26: FPGA Advantage
    33501: 01/07/28: Re: PCI-Interface
Hong Eun Jong:
    15952: 99/04/23: on using EAB of FLEX10k
Hong Shan Neoh:
    60391: 03/09/11: Re: Compact FIR filters with multiplier blocks?
    64167: 03/12/18: Re: Help me converting Mathlab code to VHDL? DSPBuilder or SystemGenerator
    65566: 04/02/02: Re: Altera DSP builder problem with delay and Integrator
    65676: 04/02/04: Re: Altera DSP builder problem with delay and Integrator
Honghua Yang:
    27: 94/07/29: Xilinx Summer Workshops (FREE)
Honglei Chen:
    71655: 04/07/26: Re: New WinFilter Digital Filter design freeware tool release available.
Hongtu:
    74294: 04/10/07: modelsim crashs with large ram simulation model
    74336: 04/10/08: Re: modelsim crashs with large ram simulation model
    75756: 04/11/14: video camera interface to FPGA
    75840: 04/11/16: Re: video camera interface to FPGA
hongyan:
    99749: 06/03/28: Question about: Logic Levels in Critical Path
    99794: 06/03/29: Re: Question about: Logic Levels in Critical Path
hongying meng:
    92805: 05/12/07: FPGA development board with digital image camera
honio:
    147743: 10/05/21: Xilinx FIFO cannot be written
    147748: 10/05/21: Re: Xilinx FIFO cannot be written
Hooman Dadrassan:
    12787: 98/10/29: Xilinx mode pins.
<hooshaya@gmail.com>:
    134474: 08/08/12: [Xilinx]:SetClbBits() function in HWICAP
    134475: 08/08/12: Re: impact error with ISE 10.1
hoothsb:
    38549: 02/01/17: how should i change it?
horst:
    108589: 06/09/13: Problems with NIOS II PIO interrupt
    108652: 06/09/14: Re: Problems with NIOS II PIO interrupt
    108718: 06/09/15: Re: Problems with NIOS II PIO interrupt
Horst Trattnig:
    46366: 02/08/27: Re: Altera Quartus II problems
    46399: 02/08/28: Re: Altera Quartus II problems
HORSTINK_HMM:
    2231: 95/11/07: Re: FPGAs as a substitute for glue logic?
hosein nooriaan:
    57127: 03/06/24: stratix IO pins during configuration
Hot Dog:
    49111: 02/11/01: Sales News
<hotben@hotmail.fr>:
    134637: 08/08/22: missing Xilinx virtual machine Centos password
    134640: 08/08/22: Re: missing Xilinx virtual machine Centos password
    134660: 08/08/25: Re: missing Xilinx virtual machine Centos password
hotrodtodd1968:
    154626: 12/12/03: USB Cable - RHEL 6.2 and ISE 13.3
Houman:
    51929: 03/01/26: New to FPGA world...need guidline/help
houman:
    53540: 03/03/15: serial transmission between altera's fpga board and PALM?
HoustonEngineer:
    94971: 06/01/20: OT:Shooting Ourselves in the Foot
Howard Butler @ Altera:
    64069: 03/12/15: Re: Q:Altera's excalibur device
Howard Del Fava:
    2687: 96/01/24: any altera library sites
    2756: 96/02/02: Re: Xilinx or Altera for Newbie?
Howard Hu:
    11982: 98/09/22: Re: Anyone received Xilinx M1.5 yet???
    11983: 98/09/22: Programming Xilinx Spartan using JTAG cable
Howard Long:
    109186: 06/09/22: Re: Dell Laptop for Embedded Work
    109233: 06/09/22: Re: Dell Laptop for Embedded Work
    113511: 06/12/15: Re: IQ multiplier
<hoyte@ucsu.colorado.edu>:
    27992: 00/12/19: FPGA and Board for Microprocessor Design?
hpg:
    87605: 05/07/27: Xilinx Foundation ISE and WinXP/x64?
HR:
    21325: 00/03/16: Employment
    21327: 00/03/16: Re: Employment
HR Cybrarian:
    15823: 99/04/15: Wanted: 5 EE's to work on High Speed Mixed-Signal, CMOS, VLSI. See Attached HTML Description. - NPMS Jobs.htm (0/1)
    15824: 99/04/15: Wanted: 5 EE's to work on High Speed Mixed-Signal, CMOS, VLSI. See Attached HTML Description. - NPMS Jobs.htm (1/1)
    15844: 99/04/16: Benchmark Specialist Wanted For Printer/Software Solutions and Applications Testing-San Diego, CA
Hrishi:
    117592: 07/04/04: Interfacing the DAC0808 to FPGA
    118308: 07/04/23: Problem with real data type
    118309: 07/04/23: Problem with real data type
hrishi24h:
    152725: 11/10/11: Microblaze Resources such as BRAMS, LUTS
hristo:
    31764: 01/06/05: on-chip vs off-chip ram
    31765: 01/06/05: on-chip vs off-chip ram
    31841: 01/06/06: ASIC vs FPGA designer
    44154: 02/06/12: ISE4.2i patch is it the same for F4.2i
    45240: 02/07/17: Re: 6 parallel inputs to Mux? How?
    45596: 02/07/28: Bit serial arithmetic Vs Digit serial Arithmetic
    45621: 02/07/29: Re: Bit serial arithmetic Vs Digit serial Arithmetic
    45946: 02/08/12: FPGA a promising platform for hardware design...need articles
    46016: 02/08/14: routing long line ressources
    46312: 02/08/25: Virtex2 and Virtex-E speed performance
    46563: 02/09/03: why Xilinx does not make its own HDL synthesiser?
    46621: 02/09/04: why the need for HIGH speed design?
    46739: 02/09/06: Re: why the need for HIGH speed design?
    46740: 02/09/06: Re: why the need for HIGH speed design?
    46756: 02/09/07: Re: why the need for HIGH speed design?
    46757: 02/09/07: scan insertion is easily feasible
    47537: 02/09/27: Block Ram maximum speed
    49233: 02/11/05: VersaRing
    49258: 02/11/06: glue logic device
    49285: 02/11/07: Re: glue logic device
    49349: 02/11/10: Re: VersaRing
    50417: 02/12/10: FPGA startup events
    50442: 02/12/10: Re: FPGA startup events
    50468: 02/12/11: Re: FPGA startup events
    50550: 02/12/12: what makes an implementation a patent?
Hristo Stevic:
    38711: 02/01/23: input source to feed 20 filters! how to decrease the load
    38727: 02/01/23: Re: input source to feed 20 filters! how to decrease the load
    39044: 02/01/30: 9 or 8 bits for image processing ?
    39052: 02/01/30: Re: 9 or 8 bits for image processing ?
    39162: 02/02/02: BRAM, clka too short setup time
    39163: 02/02/02: Re: BRAM, clka too short setup time
    39173: 02/02/03: Re: BRAM, clka too short setup time
    39177: 02/02/03: F3.3 SP8
    39665: 02/02/15: oscillation
    40530: 02/03/09: Logic levels
    40547: 02/03/09: Re: Logic levels
    40941: 02/03/18: advance in the design of controller
    42568: 02/04/27: Controller Initial State
    42592: 02/04/28: Re: Controller Initial State
    44193: 02/06/13: compatibility between F3.1 and F4.1
    44383: 02/06/18: systolic Vs pipelined
    44405: 02/06/19: Re: systolic Vs pipelined
    45098: 02/07/12: 6 parallel inputs to Mux? How?
    45929: 02/08/11: articles about FPGA based DSP design
    50411: 02/12/10: on FPGA startup what is going on?
    55084: 03/04/25: max BlockRam speed
<hrocarina@gmail.com>:
    105173: 06/07/16: FPGA consultants
Hrvoje Niksic:
    14409: 99/01/29: Re: The development of a free FPGA synthesis tool
    14433: 99/01/29: Re: The development of a free FPGA synthesis tool
hrwieuyriwru:
    58641: 03/07/30: Re: Multi Cycle path and False paths
hrzic:
    37933: 01/12/25: Re: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
HS:
    146403: 10/03/16: ISE speed determined by console output?
<hsanchez@egresados.upb.edu.co>:
    14372: 99/01/27: Re: Free max+plus ll simulator on win95
hsdary:
    29368: 01/02/16: help
HSeldon:
    136552: 08/11/21: Accessing bottom MGT of Virtex II Pro FPGA
hsfranck@gmail.com:
    113891: 06/12/28: remove logic redundancy
hssig:
    143106: 09/09/21: timing simulation performance
    143108: 09/09/21: Re: timing simulation performance
    143110: 09/09/21: Re: timing simulation performance
    143117: 09/09/22: Re: timing simulation performance
    147794: 10/05/24: mux behavior
    147802: 10/05/25: Re: mux behavior
    148905: 10/09/09: VHDL-2008 already alive with Aldec
hswnetin:
    53581: 03/03/17: Non-integer ratio interpolation and decimation
HT Chang:
    57975: 03/07/11: resynthesize ASIC netlist
    103827: 06/06/12: Looking for patent attorney specialized in programmable logic
HT-Lab:
    114963: 07/01/28: Re: Minimal design for xilinx?
    115351: 07/02/08: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
    115538: 07/02/13: Re: Which is your favorite FPGA language?
    115754: 07/02/19: Re: ACTEL ProAsic Plus
    115780: 07/02/20: Re: ACTEL ProAsic Plus
    115898: 07/02/23: Re: SystemVerilog?
    115982: 07/02/27: Re: SystemVerilog?
    115984: 07/02/27: Re: Modelsim (errno = ENOSPC) error
    116319: 07/03/07: Re: Ideas for Masters Project.
    116624: 07/03/14: Re: qemu+ghdl or uml+ghdl hardware-software cosimulation?
    116767: 07/03/17: Re: Virtex5 LXT and synthesis..
    116876: 07/03/20: Re: ModelSim PE exit code 211
    117104: 07/03/23: Re: XST coverage
    117693: 07/04/07: Re: Transition from ASIC to FPGA
    118104: 07/04/17: Re: No Synplify evaluation?
    118110: 07/04/17: Re: 80000 Bit Shift Register
    118619: 07/05/01: Re: synthesis tools
    118721: 07/05/02: Re: prevent ROM inferration
    119396: 07/05/17: Re: SystemC and TLM
    119421: 07/05/18: Re: Precision RTL and DesignWare libraries
    119429: 07/05/18: Re: Precision RTL and DesignWare libraries
    119516: 07/05/21: Re: ModelSim version upgrade problem from 6.1c to 6.2c
    119786: 07/05/25: Re: ISE 9.1 and ModelSim XE III/Starter 6.2c: Distributed memory behaviorial simulation
    119991: 07/05/30: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
    120037: 07/05/31: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
    120338: 07/06/05: Re: Portable TCP/IP socket library
    120347: 07/06/05: Re: Topics and Ideas for BS Project
    120443: 07/06/07: Re: Topics and Ideas for BS Project
    120879: 07/06/19: Re: SystemC - Libero IDE
    120880: 07/06/19: Re: How to simulate testbenches using the ISE simulator in linux
    121205: 07/06/28: Re: Xilinx Modelsim XE-III 6.2g no more Systemverilog support?
    121247: 07/06/29: Re: modelsim search path
    121260: 07/06/29: Re: modelsim search path
    121655: 07/07/11: Re: SystemC in modeling HW/SW
    122048: 07/07/18: Re: Generating video noise.
    122593: 07/08/01: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
    123226: 07/08/20: Re: exe file in modelsim
    123425: 07/08/28: Re: Null statement in VHDL
    123808: 07/09/05: Re: Actel Designer - Specifying multicycle path constraints (via .sdc file) when using synchronous clock enables
    124222: 07/09/14: Re: Is post-place and route simulation useful?
    124230: 07/09/15: Re: Beginner Advice (Languages, tools etc.)
    124242: 07/09/16: Re: Beginner Advice (Languages, tools etc.)
    124976: 07/10/14: Re: where to download latest systemc libararies?
    125617: 07/10/30: Re: Is it possible to check how cache memories are mapped to FPGA block rams?
    126012: 07/11/12: Re: Strange VHDL Error
    126222: 07/11/17: Re: VHDL language is out of date! Why? I will explain.
    126225: 07/11/17: Re: New Laptop for work
    126285: 07/11/19: Re: New Laptop for work
    126481: 07/11/24: Re: How to simulate these example CORDIC code?
    126484: 07/11/24: Re: How to simulate these example CORDIC code?
    126930: 07/12/06: Re: Drigmorn1 - The Cheapest FPGA Development Board???
    127050: 07/12/10: Re: How to simulate these example CORDIC code?
    127318: 07/12/18: Re: Tarfessock1 - FPGA Cardbus Development Board
    127397: 07/12/20: Re: ASIC verification job info request
    127657: 08/01/04: Re: converting floating point number to integer and vice versa
    127799: 08/01/08: Re: Low Power CPU Implementation
    127838: 08/01/09: Re: Low Power CPU Implementation
    127841: 08/01/09: Re: Spartan3 vs cyclone
    128038: 08/01/14: Re: Debbuging a RISC processor on an FPGA
    128056: 08/01/14: Re: Debbuging a RISC processor on an FPGA
    128087: 08/01/15: Re: ieee_ proposed library
    128517: 08/01/29: Re: HDLC
    128577: 08/01/31: Re: PC requirements for ISE webpack
    128579: 08/01/31: Re: ROM/LUT
    130045: 08/03/13: Re: SDC of NCF?
    130156: 08/03/17: Re: Designing CPU
    130359: 08/03/21: Re: Synoplify ???
    130404: 08/03/22: Re: Viewing internal signals with ModelSim
    130963: 08/04/07: Re: system level language: why all this fuss about
    131194: 08/04/15: Re: DOS script file to synthesize a VHDL design
    131210: 08/04/15: Re: Simulation tools for Xilinx ISE
    131218: 08/04/15: Re: Simulation tools for Xilinx ISE
    131219: 08/04/15: Re: Which to learn: Verilog vs. VHDL?
    131254: 08/04/17: Re: Help, router can't rout all connections (XILINX)
    131256: 08/04/17: Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?
    131279: 08/04/17: Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?
    131281: 08/04/17: Re: XST design frequency setting
    131392: 08/04/21: Re: synchronous reset problems on FPGA
    131411: 08/04/21: Re: Celoxica RC1000
    131424: 08/04/21: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
    131467: 08/04/22: Re: Newbie: Testbench question
    131468: 08/04/22: Re: Very simple VHDL problem
    131689: 08/04/29: Re: floating point and logarithm in vhdl+xilinx
    132336: 08/05/22: Re: timing constraint is impossible to meet
    132620: 08/06/03: Re: Problem with Xilinx 9.2i and Modelsim 6.0
    132632: 08/06/04: Re: puzzling [and deceiving ?] Actel kit
    132786: 08/06/06: 1 Pin MTE Cable
    132928: 08/06/10: Re: Cheating the FPGA clock speed
    133081: 08/06/17: Re: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
    133083: 08/06/17: Re: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
    133084: 08/06/17: Re: Cadence offers to buy Mentor Graphics for $1.45B
    133106: 08/06/18: Re: Synthesis results when testing for 'X' and 'U'
    133109: 08/06/18: Re: Synthesis results when testing for 'X' and 'U'
    133115: 08/06/18: Re: Synthesis results when testing for 'X' and 'U'
    133201: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
    133286: 08/06/23: Re: Xilinx SecureIP simulation and third-party simulators?
    133521: 08/07/02: Re: VHDL code for RCOM message
    133716: 08/07/11: Re: multicyle and false path in FPGA Design
    133843: 08/07/17: Re: Xilinx/Altera gate equivalence
    133918: 08/07/19: Re: The littlest CPU
    134048: 08/07/23: Re: Modelsim Simulate INOUT port
    134226: 08/07/31: Re: Question on ModelSim wave viewer
    134278: 08/08/04: Re: Is HDL-Designer not supporting records correctly?
    135072: 08/09/13: Re: ASIC Prototyping
    135182: 08/09/19: Re: What software do use big organizations for Logic Synthesis from HDL?
    135620: 08/10/10: Re: VHDL Training Course
    135633: 08/10/10: Re: VHDL Training Course
    135649: 08/10/11: Re: Looking for a soft core 32 bit processor in VHDL
    135958: 08/10/24: Re: Hollybush2 - Soft Core Processor Board
    136319: 08/11/11: Re: request: sample vcd files for TimingAnalyzer
    136543: 08/11/21: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
    136610: 08/11/25: Re: distributed dual port RAM with asynchronous read in ACTEL Smartgen
    136962: 08/12/16: Re: Leonardo scl05u synthesis-library datasheet
    136967: 08/12/16: Re: Leonardo scl05u synthesis-library datasheet
    137205: 09/01/02: Re: Classifying different kinds of FPGA optimizations
    137216: 09/01/03: Re: time limited netlist generation
    137334: 09/01/09: Re: Linux friendly FPGA dev board
    137720: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
    137725: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
    137895: 09/02/02: Re: Selecting a starter FPGA board
    138747: 09/03/07: lunch time videos
    139965: 09/04/21: new FPGA vendor
    139968: 09/04/21: Re: new FPGA vendor
    140032: 09/04/24: Re: Modelsim GTP_DUAL not recognized
    140366: 09/05/11: Re: which low cost fpga for space?
    140610: 09/05/20: ISIM and CONV_INTEGER warnings
    140626: 09/05/20: Re: ISIM and CONV_INTEGER warnings
    140647: 09/05/21: Re: ISIM and CONV_INTEGER warnings
    140694: 09/05/22: Re: ISIM and CONV_INTEGER warnings
    140695: 09/05/22: Re: Nibz VHDL Processor (Version G-spot)
    140835: 09/05/27: Re: how i can to send a sequence of bytes to the FPGA ?
    141208: 09/06/11: Re: opencores shut down?
    141345: 09/06/19: Re: How to set environment to ModelsimXE
    141678: 09/07/03: Re: OVM compilation problem
    142459: 09/08/12: Re: algorithm implementation in IC
    142490: 09/08/13: Re: algorithm implementation in IC
    142516: 09/08/14: Re: Mixed language simulation on the cheap
    142608: 09/08/20: Re: Wildcards in Quartus TCL Scripting
    142744: 09/08/30: Re: Does ModelSim or any simulator software have a function similar to the standard function any logic analizer has?
    142746: 09/08/30: Re: low power FPGA
    142801: 09/09/02: Re: OpenSPARC T1 or T2 on Altera EP2S60 or EP2S90
    142806: 09/09/02: Re: OpenSPARC T1 or T2 on Altera EP2S60 or EP2S90
    142859: 09/09/04: Re: Choice of Language for FPGA programming
    142893: 09/09/06: Re: Choice of Language for FPGA programming
    142901: 09/09/07: Re: Choice of Language for FPGA programming
    143019: 09/09/15: Re: Does Modelsim support Xilinx .mif file for Coregen generated distribute ram?
    143087: 09/09/19: Re: Symbolic string for vector values under modelsim
    143409: 09/10/10: Re: ASIC Prototyping using FPGA
    143738: 09/10/23: Re: CPLD/FPGA with Linux
    143991: 09/11/06: Re: OK Xilinx users, it's time I was let in on the joke...
    144342: 09/11/28: Re: Going mad trying to solve PLL setup/hold timing violation issues in Quartus
    144860: 10/01/08: Re: new PC specs for Xilinx tools
    144867: 10/01/08: Re: new PC specs for Xilinx tools
    144928: 10/01/15: Re: SystemVerilog Verification Example using Quartus and ModelSim
    144929: 10/01/15: Re: SystemVerilog Verification Example using Quartus and ModelSim
    144955: 10/01/17: Re: Altera Quartus II on Debian GNU/Linux
    145018: 10/01/20: Re: IEEE fixed_pkg not recognized in ISE 11.1
    145351: 10/02/06: Re: using an FPGA to emulate a vintage computer
    146022: 10/03/04: Re: Modelsim PE vs. Aldec Active-HDL (PE)
    146121: 10/03/06: Re: Laptop for FPGA design?
    146418: 10/03/17: Re: Xilinx Spartan6 Virtex6 Rollout
    146472: 10/03/19: Re: wishbone
    146473: 10/03/19: Re: Spartan 3 Starter Kit Example
    146492: 10/03/20: Re: wishbone
    146493: 10/03/20: Re: Spartan 3 Starter Kit Example
    146999: 10/04/09: Re: Debug multiple FPGAs using ChipScope via single JTAG chain
    147072: 10/04/13: Re: How to find latches in Xilinx ISE 10.1
    147200: 10/04/18: Re: Which 32 bit cores support full Linux?
    147239: 10/04/20: Re: Developin tool for Xilinx XC2018
    147254: 10/04/21: Xilinx no longer ships with Modelsim MXE?
    147310: 10/04/22: Re: Can Altera generate EDIF
    147344: 10/04/23: Re: confusion with ADC/DAC interface implementation
    148219: 10/06/30: Re: Testbench
    148959: 10/09/15: Re: Preventing timing warnings
    148993: 10/09/20: Re: Stack Exchange site for programmable logic and FPGA design
    149019: 10/09/21: Re: Cant launch ModelSim from Xilin ISE 12.1
    149033: 10/09/23: Re: Xilinx dropping Modelsim XE
    149132: 10/10/04: Actel bought by Microsemi
    149404: 10/10/22: Re: User Constraint Files
    149685: 10/11/17: Re: fpga quickstart - best learning resource recommendations
    149700: 10/11/18: Re: What is the meaning of 'combinatorial path crossing multiple units'?
    150110: 10/12/14: Re: ISIM simulation speed
    150231: 11/01/04: Re: Error in Clock Divider!
    150453: 11/01/23: Re: Xilinx news
    150595: 11/01/27: Re: Wow! No TestbenchWow!
    150669: 11/02/02: Re: Bit-accurate C simulation
    151586: 11/04/22: Re: more precise info
    152166: 11/07/15: Re: Modelsim script to print simulation progress and a TCL question
    152669: 11/09/26: Re: Modelsim cannot run its example tcl
    152766: 11/10/20: Re: Peter Alfke has passed away
    152785: 11/10/22: Re: Peter Alfke has passed away
    152829: 11/10/26: Re: Modelsim on windoz save settings in a file rather than registry
    153685: 12/04/22: Re: VHDL syntheses timestamp
    154274: 12/09/19: Re: Querying Active-HDL from TCL
    154275: 12/09/19: Re: Global Reset using Global Buffer
    154342: 12/10/09: Re: modelsim SE 10.0C SystemC bug about initializing sc_signal
    154376: 12/10/17: Re: .do files... why?
    154487: 12/11/17: Re: Question about TCL command of modelsim
    154498: 12/11/19: Re: Question about TCL command of modelsim
    154505: 12/11/20: Re: Question about TCL command of modelsim
    154664: 12/12/14: Re: MII SFD Detection with Shematics
    154984: 13/03/15: Re: Anybody got Microsemi/Actel Libero SoC 11.0 SP1 to work on linux?
    155125: 13/04/24: Re: Modelsim ought to be cheaper
    155156: 13/05/13: Re: Any experience of Equivalence Checking tools?
    155160: 13/05/13: Re: Modelsim ought to be cheaper
    155178: 13/05/22: Re: XILINX Artix-7 DDR2-RAM-Controller
    155181: 13/05/23: Re: Linting tool setup
    155269: 13/06/20: Re: Modelsim ought to be cheaper
    155391: 13/06/25: Re: FPGA Exchange
    155757: 13/08/28: Re: Actel Designer Warning: CMP201: Net drives no load
    155877: 13/10/10: Re: Book recommendation
    155943: 13/10/18: Re: reset strategy FPGA Igloo
    155975: 13/11/01: Re: FREE download of HercuLeS high-level synthesis!
    156147: 13/12/19: Re: New Cloud Based VHDL Simulator-Tarang
    156197: 14/01/16: EDA Playground
    156328: 14/03/10: Re: license server
    156330: 14/03/10: Re: license server
    156334: 14/03/11: Re: license server
    156350: 14/03/13: Re: cloud design flow
    156365: 14/03/19: Re: license issue on synplify pro AE
    156443: 14/04/07: Re: Simulation deltas
    156480: 14/04/09: Re: [cross-post] group on systemC language
    156484: 14/04/09: Re: [cross-post] group on systemC language
    156502: 14/04/11: Re: [cross-post] group on systemC language
    156504: 14/04/11: Re: cloud design flow
    156611: 14/05/13: Re: need coding
    156730: 14/06/09: Re: Access custom VHDL types in TCL script
    156809: 14/07/03: Re: What use of Python, Perl in FPGA development?
    157091: 14/10/09: Re: looking for systemC/TLM 2.0 courses
    157097: 14/10/10: Re: looking for systemC/TLM 2.0 courses
    157142: 14/10/18: Re: Handel-C to VHDL
    157143: 14/10/18: Re: looking for systemC/TLM 2.0 courses
    157196: 14/10/30: Re: looking for dev kit for ProAsic3
    157430: 14/12/05: Re: Which Altera to buy?
    157463: 14/12/11: Re: Using FPGA to feed 80386
    157614: 15/01/06: Re: Parallel execution of Systemc code
    157620: 15/01/07: Re: Parallel execution of Systemc code
    157634: 15/01/10: Re: Name this pipelining technique
    157709: 15/02/09: Re: processor core validation
    157826: 15/04/04: Re: Intel in Talks to buy Altera
    157855: 15/04/21: Re: Choosing the right FPGA board
    158154: 15/08/23: Re: Handel-C to VHDL
    158158: 15/09/07: Re: Why is this group so quiet?
    158191: 15/09/12: Re: I am getting errors when i run a systemC Code in edaplayground
    158261: 15/09/30: Re: Automatic latency balancing in VHDL-implemented complex pipelined
    158441: 15/11/30: Re: Simulation vs Synthesis
    158824: 16/04/21: Re: VHDL Obfuscators, the Good, the Bad, and the Ugly
    159445: 16/11/14: Mentor bought by Siemens
    159628: 17/01/22: Re: VHDL, how to convert sensor data to Q15
HTD:
    6504: 97/05/29: Re: Fine Pitch PQFP : anyone any hassles?
<htj@es.lth.se>:
    77760: 05/01/16: xilinx sdram controller (xapp134)
htoerrin:
    86215: 05/06/23: Re: Minimum allowed clock frequency for Nios 2 processor (Stratix 2)
    86429: 05/06/27: Re: Cant' make SignalTap works...
    88351: 05/08/15: Re: AHDL Abandoned in Quartus?
    89389: 05/09/13: Re: Migration Altera APEX20KE to ???
    91929: 05/11/17: Re: UART CORE FOR NIOS
Hu Chen:
    32070: 01/06/12: Virtex, Routing Error
    34050: 01/08/12: FPGA or CPLD data compression
    34068: 01/08/13: Re: FPGA or CPLD data compression
Hua:
    131573: 08/04/25: Timing closure problem --- how to make the QII fitter smarter
    132375: 08/05/23: incremental compilation
    132409: 08/05/26: Incremental compilation problem
    132445: 08/05/27: Re: Incremental compilation problem
    132541: 08/05/30: DATA0 pin in Cyclone III device
    132623: 08/06/03: Re: Timing closure problem --- how to make the QII fitter smarter
    132624: 08/06/03: Re: Timing closure problem --- how to make the QII fitter smarter
Hua Ai:
    50029: 02/11/28: What HW/SW do I need to build a PowerPC system on Vertex II Pro?
    50654: 02/12/16: Internal_Error of ISE 5.1.02i xst F.25.
    50699: 02/12/17: Re: Internal_Error of ISE 5.1.02i xst F.25.
    50755: 02/12/18: Re: What's the easy way to port an ISE project
    50806: 02/12/20: Problem of ISE 5.1i installation.
HUA QIAN:
    45362: 02/07/20: How could I generated an efficient 16*16 multiplier in Vertex-II?
Hua Wang:
    38222: 02/01/09: comp.arch.fpga : Problem with modelsim and ISE4.1
Hua WANG:
    49800: 02/11/21: Open source for floorplan wanted
Huang:
    30774: 01/04/28: Internal Error of routing in iSE3.3i
    31564: 01/05/30: Help: RAM clear in one clock cycle
    31587: 01/05/31: Re: Help: RAM clear in one clock cycle
    33464: 01/07/27: SRL16
    33538: 01/07/29: Re: SRL16
Huang Qiang:
    35635: 01/10/12: Problem about Leonardo Spectrum with Altera MaxPlus II
Huang, Yueqiang:
    7897: 97/10/27: Re: All Digital DLL or PLL with less than 20ps resolution
<huang@engr.uky.edu>:
    3353: 96/05/17: A Collection of VHDL, FPGA Resources on Web
huangjie:
    88635: 05/08/24: Re: what is the difference between "configuring" and "programming"?
    88967: 05/09/01: Spartan3 PCI SSO(Simultaneously Switching Output) problem
    88991: 05/09/02: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
    89015: 05/09/02: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
    89106: 05/09/05: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
    89109: 05/09/05: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
    89110: 05/09/05: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
    92029: 05/11/20: CLK input DOES NOT use clk pin ( Altera Stratix II)
    92032: 05/11/20: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
    92034: 05/11/20: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
    92042: 05/11/21: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
    92124: 05/11/22: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
    92161: 05/11/23: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
    116074: 07/02/28: what about dma scatter /gather support in xilinx edk ipif ?
    128662: 08/02/01: spartan3a support DVI ?
    128673: 08/02/02: Re: spartan3a support DVI ?
huangjielg@gmail.com:
    88570: 05/08/23: Xilinx place and route cost table
huangjun:
Hub van de Bergh:
    97230: 06/02/19: FPGA - software or hardware?
    97330: 06/02/21: FPGA - software or hardware -2-
Hubble:
    87244: 05/07/20: Re: Using unregistered inputs in FSM
    88321: 05/08/15: Re: VHDL Array indexing Issue in Modelsim
    88324: 05/08/15: Re: How to disconnect a signal?
    90230: 05/10/06: Re: Question about metastability that's been on my mind for a while
    90264: 05/10/07: Re: Question about metastability that's been on my mind for a while
HUBERT GAGNON:
    8125: 97/11/19: PROBLEMS WITH A UART BUILD WITH A 10K20 FPGA
Hubert Gagnon:
    13623: 98/12/14: Dedicated pin in ALTERA 10K familly
Hubert Pujol:
    3489: 96/06/10: Schematic compare
Huesung Kim:
    19981: 00/01/20: [Q] Reconfigurable cache architecture
Huge:
    17262: 99/07/15: Re: Alto in an FPGA (was CPU's directly executing HLL's)
    145471: 10/02/11: Re: using an FPGA to emulate a vintage computer
    145521: 10/02/13: Re: using an FPGA to emulate a vintage computer
Hugh:
    46632: 02/09/04: xilinx PCI prototype board
Hugh Jack:
    4774: 96/12/13: Computer Engineering Faculty Position
    4775: 96/12/13: Computer Engineering Faculty Position
hugo:
    46457: 02/08/30: Max SSO in Virtex2 (Simultaneously Switching Out
    77334: 05/01/04: Synchronous Interface to XScale CPU
Hugo:
    46430: 02/08/29: Use SSTL2_I or SSTL2_II for bidir on VirtexII?
Hugo2H:
    66531: 04/02/21: Re: Dual-stack (Forth) processors
Hugohh3h:
    7554: 97/09/21: Window CE news group ? ?
Hui Li:
    63090: 03/11/14: PCI Slot Expansion
    63116: 03/11/15: Re: PCI Slot Expansion
    63278: 03/11/19: Where and How to get Nvidia Geforce 5600 public desigh graph
Hui Zhang:
    4251: 96/10/04: FPGA for Reed-Solomon Codec
<Huianx>:
    80353: 05/03/05: Newby Getting started with FPGA
huijun xie:
    48507: 02/10/18: Re: 32-bit PCI Target core
    48509: 02/10/18: Re: 32-bit PCI Target core
Hul Tytus:
    4947: 97/01/03: posting test
    8022: 97/11/08: scsi host adapter
    8061: 97/11/13: SCSI host adapter
    8485: 97/12/21: source code for autorouters
    13356: 98/11/30: serial arbitration
    14830: 99/02/19: Just Texting
    14831: 99/02/19: just testing
    16194: 99/05/08: USB standard
    18359: 99/10/19: listing of discretes and list of wafer fabs in US
    27132: 00/11/12: manchester decoder
    27340: 00/11/18: re: manchester decoder
    28127: 00/12/21: "lo profile" PLCC sockets
    46439: 02/08/29: Any FSM optimizer
    62900: 03/11/10: Re: How to create a look up table for a RAM application
    65519: 04/01/31: Re: Where to get FPGA devices for testing?
    70233: 04/06/09: Re: V4 teaser, correction
    96927: 06/02/13: Re: Altera RoHS Irony
    159290: 16/09/24: Re: Minimal-operation shift-and-add (or subtract)
hull:
    44341: 02/06/18: Initial of virtex II block ram
    45370: 02/07/20: CoreGen question of the new FFT core
Humberto Honda:
    5769: 97/03/13: Re: Place and Route on Pentium Pro Benchmark?
Hunter:
    67307: 04/03/09: long PAR run time for a v.v.small design in virtex II
    146009: 10/03/03: Xilinx IOBUF - operation Q (virtex4 chip)
Hunter Int.:
    7559: 97/09/22: Circuit Board & FPGA Designers
    7564: 97/09/22: Circuit Board & FPGA Designers
    7577: 97/09/24: Circuit Board & FPGA Designers
    7670: 97/10/01: DSP Professionals...
    7690: 97/10/02: DSP Professionals...
    7781: 97/10/14: Circuit Board & FPGA Designers
    8023: 97/11/07: Circuit Board & FPGA Designers
    8093: 97/11/17: DSP Professionals, ALL disciplines...
    8092: 97/11/17: High Speed Digital Designers...
    8296: 97/12/05: High Speed Digital Designers...
    8654: 98/01/16: High Speed Digital Designers...
    8761: 98/01/23: High Speed Digital Designers...
    9437: 98/03/13: Embedded Systems/Networking Position...
    9472: 98/03/16: High Speed Digital Designers...
    9533: 98/03/21: High Speed Digital Designers...
    9667: 98/03/29: High Speed Digital Designers...
    10716: 98/06/11: DSP Pro's, H/W, S/W, C++, ALL disciplines...
    10798: 98/06/19: High Speed Digital Designers...
    10880: 98/06/26: DSP Pro's, H/W, S/W, C++, ALL disciplines...
Hur:
    67649: 04/03/16: newsgroup on channel coding?
    77177: 04/12/28: (Q) interconnections between microblazes
    77199: 04/12/29: Q, connecting multiple microblazes
    77337: 05/01/04: documents on practicing microblaze ( ML310 ) ?
    77506: 05/01/08: error occurred when downloading in ML310 board: OPB ERR red light - microblaze EDK tutorial
    77654: 05/01/13: MHS modify and then ...?
    77731: 05/01/15: print(hello world) vs printf(hello world) / system wizard vs platform studio vs command prompt
    77879: 05/01/19: looking for test application for multi-microblaze in virtex II pro
    77969: 05/01/21: Out of memory error : XPS, microblaze, EDK
    77979: 05/01/21: Re: Out of memory error : XPS, microblaze, EDK
    78157: 05/01/25: Re: Out of memory error : XPS, microblaze, EDK
    78292: 05/01/28: MPI ? in EDK
    78336: 05/01/29: material finding, edk on Linux
    78553: 05/02/03: Q, compile option, mb-gcc
hurjy:
    66770: 04/02/26: Inquiry on configuration file analysis
    66771: 04/02/26: one more inquiry....fpga architecture
    66964: 04/03/02: frame length, frame addressing ?
    67192: 04/03/08: inquiry on document for partial configuration
hurleybp:
    121458: 07/07/04: Re: read/write in bram block
    121558: 07/07/08: Re: verilog code for read write in bram block
    122387: 07/07/26: Re: Is my microblaze cache functioning?
<HurleyBP@gmail.com>:
    120887: 07/06/19: Re: How do i add my IP to EDK?
    120890: 07/06/19: Re: Could I use the opencore ddr_sdr core (for SDRAM) in Xilinx Platform Studio (C code)?
<"HURRY !"hardware@soft.disc8.com>:
    7217: 97/08/15: COMPUTER HARDWARE / SOFTWARE
<husby@fnal.gov>:
    6214: 97/04/28: Implementing priority-select function in Xilinx X4000E
    6263: 97/05/06: Re: Announcing new division & an fpga implementation
    6372: 97/05/19: Re: Fast comparator
    6480: 97/05/27: Re: Pointer to a BER Circuits
    6816: 97/06/30: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
    8602: 98/01/12: Re: Xilinx Stock
    8603: 98/01/12: Asynchronous square root.
    8625: 98/01/14: Re: Asynchronous square root.
    8714: 98/01/21: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8730: 98/01/22: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8815: 98/01/28: Re: Opinions wanted on PLD selection
    8867: 98/02/03: Re: VHDL vs schematics, I vote for VHDL and this is why...
    8889: 98/02/05: Re: VHDL vs schematics, I vote for VHDL and this is why...
<husby@my-deja.com>:
    25349: 00/09/07: Re: floorplanning
    25354: 00/09/07: Re: floorplanning
    25535: 00/09/13: Re: MEMORY
    25536: 00/09/13: Re: virtex shape
    26150: 00/10/05: Re: Pwr/Gnd ( again)
    26275: 00/10/10: Headhunter, The Game (Re: Project Leader, Architecture Modeling)
    26577: 00/10/20: Re: Very Lucrative FPGA Jobs
    26796: 00/10/29: Re: death of rloc ?
    26797: 00/10/29: Re: Excellent Opportunity ASIC Engineers CA International Relocation
    27200: 00/11/15: Re: Job posting info
    27423: 00/11/21: Re: HELP! Lucent ORCA datasheets needed!
    27630: 00/11/30: Re: Orca 3t sram gsr question
hussnain721:
    142839: 09/09/03: Multiple Microblaze on FSL link
hutzelbutz:
    95380: 06/01/23: Re: ISE8.1 on Linux, first impressions
    95417: 06/01/23: Re: ISE8.1 on Linux, first impressions
    95667: 06/01/25: Re: ISE8.1 on Linux, first impressions
    95791: 06/01/26: Re: ISE8.1 on Linux, first impressions
    95923: 06/01/26: Re: ISE8.1 on Linux, first impressions
    95925: 06/01/27: Re: ISE8.1 on Linux, first impressions
Huub van Helvoort:
    79170: 05/02/15: Re: ATM Cell Payload Scrambler / Descrambler Process Explaination
    79195: 05/02/15: Re: ATM Cell Payload Scrambler / Descrambler Process Explaination
Huy Nguyen:
    44096: 02/06/11: LVPECL open-emitter interface to Virtex-II
    44251: 02/06/14: Re: LVPECL open-emitter interface to Virtex-II
huymEmail@gmail.com:
    102672: 06/05/18: Re: Where can i get "Quartus II Device Information for UNIX & Linux CD"
<huymEmail@gmail.com>:
    102618: 06/05/18: Where can i get "Quartus II Device Information for UNIX & Linux CD"
Huzaifa Ginwalla:
    74357: 04/10/08: PPC cores and XAUI core on Xilinx Virtex-II Pro 20
    75837: 04/11/16: Re: FPGA : configuration
hvo:
    140590: 09/05/19: How to load xilinx mfs file into spi flash?
    140877: 09/05/28: writing to reset vectors - xilinx spartan 3an
    140883: 09/05/28: Re: writing to reset vectors - xilinx spartan 3an
    141767: 09/07/07: webserver
    141782: 09/07/08: Re: webserver
    141849: 09/07/13: xilinx mfs
    143643: 09/10/19: xilinx edge trigger interrupt
    143645: 09/10/19: Re: xilinx edge trigger interrupt
    143658: 09/10/20: Re: xilinx edge trigger interrupt
    143672: 09/10/20: External IO Port without using Xilinx's GPIO IP
    143730: 09/10/22: Re: External IO Port without using Xilinx's GPIO IP
    144585: 09/12/16: Re: EDK custom IP read/write
    148667: 10/08/16: VDHL initializing
    148681: 10/08/17: Re: VDHL initializing
    148693: 10/08/17: Re: VDHL initializing
    148716: 10/08/18: Re: VDHL initializing
    148717: 10/08/18: Re: VDHL initializing
    148730: 10/08/18: Re: VDHL initializing
    157437: 14/12/09: VHDL Synchronization- two stage FF on all inputs?
    157452: 14/12/10: Re: VHDL Synchronization- two stage FF on all inputs?
    157500: 14/12/12: Re: VHDL Synchronization- two stage FF on all inputs?
Hw:
    83793: 05/05/07: Metastability / MUX question
    83808: 05/05/07: Re: Metastability / MUX question
    84750: 05/05/26: Ethernet / digital logic questions
    84790: 05/05/27: Re: Ethernet / digital logic questions
    88823: 05/08/29: Array of slope A/Ds in FPGA?
    88880: 05/08/30: Re: Array of slope A/Ds in FPGA?
<hw_designer@yahoo.com>:
    41576: 02/04/02: Re: XC9500 low temp. problem
hwguy:
    93044: 05/12/12: Xilinx for PDP
hwi-sung jung:
    30523: 01/04/12: How to use clock generator in Vertex-e?
<hyankijitu@gmail.com>:
    96645: 06/02/08: I2C timing problem
    97931: 06/03/01: i2c addressing
hyding:
    61808: 03/10/12: Re: Virtex II Pro Linux
Hydrochloric Asad:
    7080: 97/07/29: Re: PCI burst transfers
<hyhnode@ICEJPOR.EDU.HK>:
hypermodest:
    107001: 06/08/23: fastest FPGA
    107007: 06/08/23: Re: fastest FPGA
    107027: 06/08/23: Re: fastest FPGA
    107029: 06/08/23: Re: fastest FPGA
    107030: 06/08/23: Re: fastest FPGA
    107031: 06/08/23: Re: fastest FPGA
    107034: 06/08/23: Re: fastest FPGA
    107037: 06/08/23: esoteric hardware?
    107038: 06/08/23: Re: fastest FPGA
    112553: 06/11/24: logic analyzer using FPGA
    112666: 06/11/27: Altera's USB blaster
    112692: 06/11/27: Re: Altera's USB blaster
HyperOnyx:
    54698: 03/04/16: Re: Hardware acceleration for raytracing purposes
<hypi@gmx.net>:
    46012: 02/08/14: transputers
    46054: 02/08/15: Re: transputers
    46055: 02/08/15: Re: transputers
Hyun-Taek Chang:
    21659: 00/03/28: Re: Atmel censors web access
    22859: 00/05/28: Re: Q:Itegration of FPGA functionality in an ASIC?
Håkan Pettersson:
    29188: 01/02/09: Re: First XILINX PCI core project
    29887: 01/03/15: Re: Using Virtex DLLs in Leonardo
"Håkan Pettersson":
    13136: 98/11/17: Is there an alternative to Altera EPM5128 OTP?
    13194: 98/11/19: Content Addressable Memorys
    13828: 98/12/28: Circa 1994 Altera 881152GC192 FPGA
    14682: 99/02/11: Altera freecore library ?
Håkon L:
    72569: 04/08/25: Xilinx version ROM with automatic increment
    72591: 04/08/26: Re: Xilinx version ROM with automatic increment
    75424: 04/11/05: IO Timing constraints with internal clocks
    75503: 04/11/08: Re: IO Timing constraints with internal clocks
Håkon Lislebø:
    53230: 03/03/07: Re: Current Consumption/Limitation Upon Output
    53342: 03/03/11: Re: DDR example designs of xilinx or altera
    56017: 03/05/27: Re: FPGA design: firmware or hardware?
    59690: 03/08/26: Re: Why can't Xilinx DCM's regain lock without a RESET??
    59837: 03/08/29: Re: Why can't Xilinx DCM's regain lock without a RESET??
    59839: 03/08/29: Re: HDL Designer from Mentor
    59848: 03/08/29: Re: HDL Designer from Mentor


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