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Messages from 44275

Article: 44275
Subject: Re: Stupid WebPack question
From: Jim Stewart <jstewart@jkmicro.com>
Date: Sat, 15 Jun 2002 16:15:25 -0700
Links: << >>  << T >>  << A >>
cfk wrote:
> 
> My experience is based on using the previous one, foundation 1.5, but I
> suspect that if you right click in the IPAD or OPAD on your schematic, that
> you can set a property called "LOC" and that property will be the pin
> number.

I used to use Foundation and that's the first thing I tried.  Thanks
anyway.

> "Jim Stewart" <jstewart@jkmicro.com> wrote in message
> news:DBE581AC4D13488B.86DD1F2F267CB6BB.2098EC45139B163B@lp.airnews.net...
> > I'm using an XC9572XL part with Webpack schematic entry and I cannot
> > figure out how to assign specific package pins to the IBUF and OBUF
> > devices.  I've blown several hours looking for this and would greatly
> > appreciate any help.

Article: 44276
Subject: Strathnuey kit from Nallatech
From: Pat Ford <pat@istop.com>
Date: Sat, 15 Jun 2002 20:42:36 -0400
Links: << >>  << T >>  << A >>
Hi All;
 does anyone here have experience with the Strathnuey kit with the
XCV1000 fpga, any opinions on this card?
http://www.nallatech.com/products/dime_select/strathnuey/index.asp
 This is the card we are looking at to do the digiquartz counters I
mentioned in the ultrahigh speed counters thread.
 Thanks
Pat

Article: 44277
Subject: Re: Stupid WebPack question
From: Jim Stewart <jstewart@jkmicro.com>
Date: Sat, 15 Jun 2002 18:50:31 -0700
Links: << >>  << T >>  << A >>
Jim Stewart wrote:
> 
> I'm using an XC9572XL part with Webpack schematic entry and I cannot
> figure out how to assign specific package pins to the IBUF and OBUF
> devices.  I've blown several hours looking for this and would greatly
> appreciate any help.

After another hour of searching, I think I found it:

Design Entery Utilities
   User Constraints
      Assign Pins

jim

Article: 44278
Subject: Re: fpga and ultra highspeed counters
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 16 Jun 2002 03:47:04 GMT
Links: << >>  << T >>  << A >>
Paul, legally you are right. that's wat the data sheet says.
As an insider, I know how the 820 MHz number came about, and how much it is
guard-banded, since it cannot be concatenated, and thus is impossible to
measure in production. So I personally have no inhibitions violating this
particular spec, but I do not want to encourage loose habits...  :-(

Peter Alfke, Xilinx Applications

Paul Butler wrote:

> "Peter Alfke" <Peter.Alfke@xilinx.com> wrote :
> > The flip-flops in Virtex-II are very fast, but the feedback from
> > Q to D is very general, and thus relatively slow, so the loop has
> > a delay of just around one ns, which means 1 GHz is barely possible.
>
> 1 GHz is about 20% faster than possible according to the minimum pulse width
> requirements for a CLB clock listed in table 21 of this document:
>
> http://www.xilinx.com/partinfo/ds031-3.pdf
>
> So 820 MHz appears to be the fastest counter that's within the Xilinx spec.
> I don't doubt that 1 GHz is possible but is it reliable over normal process
> variations?  Is it safe for me to ship?
>
> Paul.Butler@ni.com


Article: 44279
Subject: Re: Can someone who is not a student use Xilinx Foundation 2.1i Student
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Sat, 15 Jun 2002 23:48:04 -0500
Links: << >>  << T >>  << A >>
The reason I will like to play around with Foundation 2.1i is because
ISE WebPACK doesn't support Spartan or Spartan-XL.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



Winnie Hsu wrote:
> 
> Foundation 2.1i is really old and technology is not up to date.
> Why don't you try downloading free WebPACK and use it legally.
> 
> -Winnie
> --------------------------------------------------------------
> All of my comments here represent personal opinions.
> --------------------------------------------------------------
>

Article: 44280
Subject: Re: TTL library in Xilinx?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sun, 16 Jun 2002 07:42:10 +0100
Links: << >>  << T >>  << A >>


Hal Murray wrote:

>
> [Why is the magic button always green?]
>

Comes from, I think, the push-buttons in metal bashing or heavy engineering
factories that are used to control dangerous bits of machinery. A small green one
marked "start" and a very large red one marked "STOP".

From whence comes the expression ``The Panic Button''.


Article: 44281
Subject: Re: Stupid WebPack question
From: David R Brooks <daveb@iinet.net.au>
Date: Sun, 16 Jun 2002 18:25:21 +0800
Links: << >>  << T >>  << A >>
And another WebPack question:
I'm using 4.1 (maybe I should upgrade...)

Designing in VHDL for the Vertex-II, and wanting to use the DDR data
registers. I find the blocks FDDRCPE and FDDRRSE compile up just fine,
but the other blocks (IFDDRCPE, IFDDRRSE, OFDDRCPE, OFDDRRSE,
OFDDRTCPE, OFDDRTRSE) don't appear in the VCOMPONENTS library. Nor are
they used in XAPP262, which uses the basic output blocks.
 Is there an updated library I should be using? (www.xilinx.com seems
decidedly flaky at present: keeps dropping out on me).

In the same vein, if I use the modules with in-build 3-state buffer
(ie OFDDRTCPE, OFDDRTRSE), is there a way to configure the electrical
standard, eg for SSTL2 IO porting?

TIA


Article: 44282
Subject: Re: Xilinx ISE BaseX... What is it?
From: spam_hater_7@email.com (Spam Hater)
Date: Sun, 16 Jun 2002 15:13:34 GMT
Links: << >>  << T >>  << A >>

Now that they "own" the synthesizer again, hopefully they'll go back
to the perpetual license.

I'm stuck at 1.5i because my design environment can't tolerate a
license that expires once a year.  (Long story; don't ask.)


On Sat, 15 Jun 2002 14:50:57 GMT, Troy Schultz <tschultz@canada.com>
wrote:

>
>The special offer for the Base-X tools shows that Xilinx is actually 
>trying to get people to use their parts and not really excessive on the 
>price.
>
>- Troy
>


Article: 44283
Subject: Problems programming a XCR3128XL with Webpack4.2
From: sk@glui.de (Sukandar Kartadinata)
Date: 16 Jun 2002 11:04:50 -0700
Links: << >>  << T >>  << A >>
Hi everybody,
when I tried to program a Xilinx XCR3128XL I first got the message:

ERROR: iMPACT:583 - '2' The IDCODE read from the device does not match
the IDCODE in the BSDL file

Luckily this problem is covered in the Xilinx' database, however after
I made the necessary changes to the bsdl file I got another one:

EXCEPTION iMPACT: JedecReader.c:76:1.30 - Data mismatch
followed by
ERROR:iMPACT:636 - performOperation() failed

I get the same/similar messages when performing a verify or readback
(exception in JedecWriter.c), but _can_ retrieve the device ID as well
as perform IDCODE looping, erasing, and blank-checking.

Release Version of iMPACT is 4.2WP2.x
Application Version: E.37
Windows98SE

Thanks in advance for your help.
best,
Sukandar

Article: 44284
Subject: Which is greater?
From: "Roger King" <roger@king.com>
Date: Sun, 16 Jun 2002 18:13:53 GMT
Links: << >>  << T >>  << A >>
Which has a greater number of CLBs.. gates.. or LUTs(if this is the one I
should compare by):

XC4005XL

and

XC2S50


I want to know which of these has a greater capacity for a design?

Thanks in advance



Article: 44285
Subject: Re: Xilinx ISE BaseX... What is it?
From: Troy Schultz <tschultz@canada.com>
Date: Sun, 16 Jun 2002 18:15:44 GMT
Links: << >>  << T >>  << A >>
Spam Hater wrote:
> Now that they "own" the synthesizer again, hopefully they'll go back
> to the perpetual license.
> 
> I'm stuck at 1.5i because my design environment can't tolerate a
> license that expires once a year.  (Long story; don't ask.)
> 
> 
> On Sat, 15 Jun 2002 14:50:57 GMT, Troy Schultz <tschultz@canada.com>
> wrote:
> 
> 
>>The special offer for the Base-X tools shows that Xilinx is actually 
>>trying to get people to use their parts and not really excessive on the 
>>price.
>>
>>- Troy
>>
> 
> 

It was explained to me that the software continues to run if you no 
longer wish to license it, but you will not get any new updates.  I 
asked specifically about this issue because I know of others that have 
found their software non-functional after their license expired.

- Troy


Article: 44286
Subject: core generator / where is it?
From: Wolfgang Pieper <amor@hs-bremen.de>
Date: 16 Jun 2002 21:01:09 +0200
Links: << >>  << T >>  << A >>
Hello world,


I'm using the downloaded ISEWebPack. Now I had the idea to explore the core
generator.
But, I can't find it. Does anybody has an answer which could help me?


Best greetings
Wolfgang

-- 
__________________________________________________________
News suchen, lesen, schreiben mit http://newsgroups.web.de

Article: 44287
Subject: Re: Which is greater?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 16 Jun 2002 21:06:34 +0200
Links: << >>  << T >>  << A >>
"Roger King" <roger@king.com> schrieb im Newsbeitrag
news:Bz4P8.360489$t8_.326219@news01.bloor.is.net.cable.rogers.com...
> Which has a greater number of CLBs.. gates.. or LUTs(if this is the one I
> should compare by):
>
> XC4005XL
>
> and
>
> XC2S50

Is it so hard to read datasheets? As alread said in this newsgroup, gate
count is useless, LUTs are the number to go.

A XC4005 XL has 392 LUTs (2 LUTs per CLB)

A XC2S50 has 1536 LUTs plus 6 BlockRams each 4 kbits ( 4 LUS per CLB).

So we can see, that the Spartan-II has more capacity, especially the 6
BlockRams.
For new design, th 4K series is absolutely NOT recommended.
Spartan-II(E) is much faster, cheaper, lower power.

--
MfG
Falk





Article: 44288
Subject: Re: fpga and ultra highspeed counters
From: kolja@bnl.gov (Kolja Sulimma)
Date: 16 Jun 2002 13:42:51 -0700
Links: << >>  << T >>  << A >>
This card will likely do the job for you. 
But for your simple application it is extremely overpriced.

If I understand your application correctly, 24 counters of 24 Bits
should fit into a Spartan-II 200 Device together with a PCI core and a
FIFO.

Kolja Sulimma



"Pat Ford" <pat.ford@nrc.ca> wrote in message news:<aeco9f$oi8$1@moonstone.imsb.nrc.ca>...
> They do BUT each card will only do 8 channels and the cost is high, and
> they don't support the range of OS's that we are looking at.
>  We are looking at the Nallatech
>  Strathnuey kit with the XCV1000 fpga, any have opinions on this card?
> http://www.nallatech.com/products/dime_select/strathnuey/index.asp
> thanks for your help so far
> Pat
> 
> "Jay" <kayrock66@yahoo.com> wrote in message
> news:d049f91b.0206131216.10a6fa2d@posting.google.com...
> > I don't want to spoil your fun but this sounds like something that
> > might already be available.  Look at those PC intrumentation guys like
> > National Instruments and the like, they may have something you can use
> > or that can be gated.

Article: 44289
Subject: Re: Xilinx ISE BaseX... What is it?
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Sun, 16 Jun 2002 16:31:52 -0500
Links: << >>  << T >>  << A >>
Xilinx bought PL/Synthesizer from a bankrupt company called Minc, and
now calls it XST, but . . . it has problems that needs to be fixed, but
problems I have seen as far as back in WebPACK ISE 3.3WP8.0 (XST Ver.
D.27) haven't been addressed even in the latest ISE WebPACK 4.2WP2.0
(XST Ver. E.35).
First of all, when the design hierarchy is flattened (hierarchy not
kept) and blackboxes are used, I have observed XST dropping valid FFs
being used in a design.
When the design hierarchy is kept, XST no longer drops valid FFs being
used in a design, so obviously this is a bug.
The second problem will be that when the design hierarchy is kept (In my
case to avoid the aforementioned bug.), XST cannot "bubble up" tri-state
buffers unlike other synthesis tools (I know at least LeonardoSpectrum
can "bubble up" tri-state buffers even when the design hierarchy is
kept.).
The only way to "bubble up" tri-state buffers when the design hierarchy
is kept is to use Xilinx specific library primitives like IOBUF, but
that makes the design vendor specific (I use `ifdef directives of
Verilog to disable vendor specific code when I port a design to other
architectures.).
Going back to the "valid FFs being used getting dropped when the
hierarchy is flattened" bug, it took me 2 days to figure it out, and
what made it hard to figure out the bug was that I used to believe
(Because that's what Xilinx say.) that XST since ISE 4.x can only
generate an NGC file in which the netlist is encrypted.
After some experiments, I found that even the XST since ISE 4.x can
still generate an EDIF netlist.

http://groups.google.com/groups?hl=en&lr=&frame=right&th=15d9015f1ea8f06f&seekm=aceh0t%24b12%241%40newsreader.mailgate.org#link1



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)




Spam Hater wrote:
> 
> Now that they "own" the synthesizer again, hopefully they'll go back
> to the perpetual license.
> 
> I'm stuck at 1.5i because my design environment can't tolerate a
> license that expires once a year.  (Long story; don't ask.)
> 
> On Sat, 15 Jun 2002 14:50:57 GMT, Troy Schultz <tschultz@canada.com>
> wrote:
>

Article: 44290
Subject: Re: Xilinx ISE BaseX... What is it?
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Sun, 16 Jun 2002 16:35:47 -0500
Links: << >>  << T >>  << A >>
Does Xilinx use the FLEXlm for licensing?
After the license expires, can I still run the backend tools from ISE
GUI?



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)




Troy Schultz wrote:
> 
> 
> It was explained to me that the software continues to run if you no
> longer wish to license it, but you will not get any new updates.  I
> asked specifically about this issue because I know of others that have
> found their software non-functional after their license expired.
> 
> - Troy

Article: 44291
Subject: Re: Xilinx ISE BaseX... What is it?
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Sun, 16 Jun 2002 16:38:30 -0500
Links: << >>  << T >>  << A >>


Spam Hater wrote:
> 
> Now that they "own" the synthesizer again, hopefully they'll go back
> to the perpetual license.
> 
> I'm stuck at 1.5i because my design environment can't tolerate a
> license that expires once a year.  (Long story; don't ask.)
> 


        Can Foundation 1.5 or 2.1i run without a FLEXlm license?



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 44292
Subject: Re: Which is greater?
From: Peter Alfke <Peter.Alfke@xilinx.com>
Date: Sun, 16 Jun 2002 16:01:00 -0700
Links: << >>  << T >>  << A >>
The XC4005 has 196 CLB with 2 LUTs each
= 392 LUTs/flip-flops
The XC2S50 has 384 CLBs with 4 LUTs each
=1,536  LUTs/flip-flops

So, the XC2S50 is just about four times bigger, and also has BlockRAMs.
Peter
========================
Roger King wrote:

> Which has a greater number of CLBs.. gates.. or LUTs(if this is the one I
> should compare by):
>
> XC4005XL
>
> and
>
> XC2S50
>
> I want to know which of these has a greater capacity for a design?
>
> Thanks in advance


Article: 44293
Subject: Re: core generator / where is it?
From: newman5382@aol.com (newman)
Date: 16 Jun 2002 19:51:10 -0700
Links: << >>  << T >>  << A >>
Wolfgang Pieper <amor@hs-bremen.de> wrote in message news:<3d0ce075$1@netnews.web.de>...
> Hello world,
> 
> 
> I'm using the downloaded ISEWebPack. Now I had the idea to explore the core
> generator.
> But, I can't find it. Does anybody has an answer which could help me?
> 
> 
> Best greetings
> Wolfgang

Wolfgang,
  As someone mentioned in a previous thread, and can be referenced in
the following link, core gen is not part of ISEWebPack, but is first
available at the ISE baseX level.

http://toolbox.xilinx.com/cgi-bin/xilinx.storefront/2029016183/UserTemplate/1

Newman

Article: 44294
Subject: new computer
From: "mac teh knife" <nospam@nowhere.com>
Date: Sun, 16 Jun 2002 20:52:43 -0700
Links: << >>  << T >>  << A >>
We have started development using the new fpgas. We are evaluating the
virtex 2 and stratix devices.
What I'm finding out is my 2 year old machine ain't got what it takes to
crunch the files that can fill up
these multi million gate chips. I was wondering if anybody would care to
share with us the machine (PC)
they are using. Also has anybody evaluated linux vs window performance as
far as fpga applications are concerned.

I'm looking at a P4 2.4ghz / 2 gig ram and 533 mhz front bus. I'm also
looking at a Xeon 2.4 g with 400 mhz
front bus. Does anybody know if there is a performance difference between
these two type of processors?

Mac the knife is of course not my real name, I'm just so tired of spam that
posting to use net generates.

thanks
Jerry




Article: 44295
Subject: Re: Power supply caps on PCB
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 17 Jun 2002 00:19:56 -0400
Links: << >>  << T >>  << A >>
John_H wrote:
> 
> rickman wrote:
> 
> > I won't argue that any of your recommendations are bad, but they don't
> > play together that I can tell.  In one place you say that a cap with a
> > SRF of 7 MHz is not good at 150 MHz which will require another cap with
> > an SRF of 150 MHz.  Later you say that this will cause a resonance
> > somewhere in the middle so you try to keep the SRFs within a decade.
> 
> Spot coverage without consideration for the whole picture will introduce potential problems;
> I didn't intend to recommend adding a single cap to the dozen with the low SRF.  If the SRFs
> are distributed, the coverage is superb.  I was trying to point out that a single cap can do
> the work of a dozen when you're far enough away from those dozen caps' SRF.  It could be a
> mistake to only add the one cap at the higher SRF to complement the dozen.  It would be more
> effective to have fewer caps across the frequency range than a quantity of single value caps.

But how do you deal with the anti resonance?  One of the other posts
gives a link to a lengthly discussion of power supply bypassing and
shows how using caps with different SRFs gives a HIGHER impedance at
points between the SRFs.  Seems to me that it can be very tricky to get
this right.  

The other issue I have is with the use of 1206 caps for bypassing.  Size
is one parameter that does affect impedance at high frequencies, unlike
capacitance.  So why use a 1 uF cap in a 1206 package with a low SRF
when a 0.1 uF cap in an 0603 package will work better at all frequencies
above the SRF?  I don't think the freqs much below SRF are important for
these caps.  If your clocks are above 40 MHz, for example, then your
switching noise will start at 80 MHz and go well up beyond 500 MHz.  The
lower frequency noise by contrast is small and will be dealt with by the
bulk cap, < 10 MHz.  The 0603 caps will be effective down to 10 MHz.  So
the band of interest is covered.  

Am I missing something?  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 44296
Subject: [ANN] Free SFL to Verilog converter (with 6502/z80 core)
From: nshimizu@bosei.cc.u-tokai.ac.jp (Naohiko Shimizu)
Date: 17 Jun 2002 06:16:41 GMT
Links: << >>  << T >>  << A >>
Hi,

I wrote a SFL to Verilog converter program.
The package is freely downloadable from my web site.

The package has m65(6502 compatible), mz80(
z80 semi-compatible) processors for test.
The target Verilog compiler is now Icarus Verilog.
(This is the only verilog compiler I have.)

Because I am not so familiar with Verilog,
I need people to help me testing the program with
the generated verilog file.

At now, there are some problems about bidirectional
terminal and memory.
I have the patch but I don't update the package yet.
(It is relatively a small problem for IP core design.)

Anyone who can help me, please visit:

http://shimizu-lab.dt.u-tokai.ac.jp/indexe.html

Regards,



---------------------------------->--------------------------->>
Naohiko Shimizu

Department of Communications Engineering,
School of Information Technology and Electronics, Tokai University
1117 Kitakaname Hiratsuka 259-1292 Japan
TEL.+81-463-58-1211(ext. 4084) FAX.+81-463-58-8320
http://shimizu-lab.dt.u-tokai.ac.jp/
<<--------------------------------<-----------------------------


Article: 44297
Subject: Many thanks to everyone!!
From: "H.L" <alphaboran@yahoo.no-spam.com>
Date: Mon, 17 Jun 2002 12:07:16 +0300
Links: << >>  << T >>  << A >>
Hello all,
with this post I like to thank everyone in this newsgroup for the great
help!
I just tested my first FPGA design and it is working fine!!  :)))

My desing is the MAC controller in an WDM ring, implemented in a Virtex-E
FPGA. In a few days I will start the implementation of a switch, with the
information I got from this newsgroup I think everything will be fine!

Thanks again,
Harris



Article: 44298
Subject: Xilinx System Generator FIR vs Core Generator FIR
From: "Ken Mac" <aeu96186@yahoo.co.uk>
Date: Mon, 17 Jun 2002 10:34:19 +0100
Links: << >>  << T >>  << A >>

Hello Folks,

Can anyone give me an idea on how System Generator and Core Generator
perform relative to each other in terms of slice cost/clock speed when
defining FIR filters (e.g. single-rate, interpolating and decimating).

Does either have an advantage or are they both using the same base code to
generate filters?  (I know CoreGen uses distributed arithmetic for fir
filters - does System Generator do the same?).

Thanks for your time,

Ken



Article: 44299
Subject: Re: Power supply caps on PCB
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Mon, 17 Jun 2002 10:13:03 GMT
Links: << >>  << T >>  << A >>
On Mon, 17 Jun 2002 00:19:56 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

>John_H wrote:
>> 
>> rickman wrote:
>> 
>> > I won't argue that any of your recommendations are bad, but they don't
>> > play together that I can tell.  In one place you say that a cap with a
>> > SRF of 7 MHz is not good at 150 MHz which will require another cap with
>> > an SRF of 150 MHz.  Later you say that this will cause a resonance
>> > somewhere in the middle so you try to keep the SRFs within a decade.
>> 
>> Spot coverage without consideration for the whole picture will introduce potential problems;
>> I didn't intend to recommend adding a single cap to the dozen with the low SRF.  If the SRFs
>> are distributed, the coverage is superb.  I was trying to point out that a single cap can do
>> the work of a dozen when you're far enough away from those dozen caps' SRF.  It could be a
>> mistake to only add the one cap at the higher SRF to complement the dozen.  It would be more
>> effective to have fewer caps across the frequency range than a quantity of single value caps.
>
>But how do you deal with the anti resonance?  One of the other posts
>gives a link to a lengthly discussion of power supply bypassing and
>shows how using caps with different SRFs gives a HIGHER impedance at
>points between the SRFs.  Seems to me that it can be very tricky to get
>this right.  

There are two mechanisms for reducing the impedance peak at "anti
resonance" :

1.  Have some loss.  The impedance only goes to infinity in an ideal
lossless system.  In real life you have a load (which looks a bit like
a shunt resistor) and the capacitors have ESR, so the impedance peaks
are much lower.

2.  Keep the ratio of the capacitor values down.  I have heard that
10:1 (e.g. 100n, 10n, 1n, 100p) can give adequate results.  I have
read papers that used lower ratios though (e.g. E3 series, 10, 4.7,
2.2 etc.).
A lower ratio will produce lower peaks for a given amount of loss.  (I
just said that - I don't have a proof.)

You can model both effects quite easily in Spice.  But getting
accurate values for the parasitic parameters can be tricky.

>The other issue I have is with the use of 1206 caps for bypassing.  Size
>is one parameter that does affect impedance at high frequencies, unlike
>capacitance.  So why use a 1 uF cap in a 1206 package with a low SRF
>when a 0.1 uF cap in an 0603 package will work better at all frequencies
>above the SRF?  I don't think the freqs much below SRF are important for
>these caps.  If your clocks are above 40 MHz, for example, then your
>switching noise will start at 80 MHz and go well up beyond 500 MHz.  The
>lower frequency noise by contrast is small and will be dealt with by the
>bulk cap, < 10 MHz.  The 0603 caps will be effective down to 10 MHz.  So
>the band of interest is covered.  
>
>Am I missing something?  

Most tantalums and OS-CONs that I've used havn't been effective much
above 1MHz, so you need those 1u ceramics to fill the gap.  (Either
that, or you need a lot of 100n caps - but you probably need a lot of
them anyway.)

Regards,
Allan.



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