Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Threads Starting Sep 2008

134794: 08/09/01: Antti: ED 9.2 too new cygwin error
    134795: 08/09/01: morphiend: Re: ED 9.2 too new cygwin error
        134804: 08/09/02: Brian Drummond: Re: ED 9.2 too new cygwin error
    134797: 08/09/01: Antti: Re: ED 9.2 too new cygwin error
    134800: 08/09/01: Alan Nishioka: Re: ED 9.2 too new cygwin error
    134803: 08/09/01: morphiend: Re: ED 9.2 too new cygwin error
    134805: 08/09/01: Antti: Re: ED 9.2 too new cygwin error
    134806: 08/09/01: Antti: Re: ED 9.2 too new cygwin error
134796: 08/09/01: Svenn Are Bjerkem: Is it possible to do incremental synthesis and placement?
    134822: 08/09/02: ajwitz: Re: Is it possible to do incremental synthesis and placement?
    134826: 08/09/02: Mike Treseler: Re: Is it possible to do incremental synthesis and placement?
    134849: 08/09/03: Marvin: Re: Is it possible to do incremental synthesis and placement?
    134873: 08/09/04: ajwitz: Re: Is it possible to do incremental synthesis and placement?
    135152: 08/09/18: Svenn Are Bjerkem: Re: Is it possible to do incremental synthesis and placement?
134799: 08/09/01: xenix: how to built a CCD camera + FPGA ???
    134808: 08/09/01: David M. Palmer: Re: how to built a CCD camera + FPGA ???
    134813: 08/09/02: <ales.gorkic@gmail.com>: Re: how to built a CCD camera + FPGA ???
    134825: 08/09/02: alexandre.poltorak@gmail.com: Re: how to built a CCD camera + FPGA ???
134810: 08/09/02: Antti: FPGA package size chart (smallest) Xilinx holds 8th place
    134811: 08/09/02: bommels: Re: FPGA package size chart (smallest) Xilinx holds 8th place
    134814: 08/09/02: Antti: Re: FPGA package size chart (smallest) Xilinx holds 8th place
    134815: 08/09/02: bommels: Re: FPGA package size chart (smallest) Xilinx holds 8th place
134817: 08/09/02: jack.harvard@googlemail.com: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134819: 08/09/02: John_H: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134820: 08/09/02: jack.harvard@googlemail.com: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134823: 08/09/02: John_H: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134833: 08/09/03: Brian Drummond: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
        134854: 08/09/04: Brian Drummond: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
            134879: 08/09/04: Mike Treseler: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
                134884: 08/09/04: Mike Treseler: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134836: 08/09/03: jack.harvard@googlemail.com: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134840: 08/09/03: John_H: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134841: 08/09/03: jack.harvard@googlemail.com: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134882: 08/09/04: John_H: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134984: 08/09/09: dand2k: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
    134987: 08/09/09: rickman: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
134827: 08/09/03: Qingbo: what is the maximum number of DDR controllers
    134834: 08/09/03: Brian Drummond: Re: what is the maximum number of DDR controllers
    134848: 08/09/03: Qingbo: Re: what is the maximum number of DDR controllers
    134853: 08/09/03: ghelbig: Re: what is the maximum number of DDR controllers
134828: 08/09/03: Petter Gustad: Quartus II priority 19 under Linux
    134830: 08/09/03: David Brown: Re: Quartus II priority 19 under Linux
        134871: 08/09/04: H. Peter Anvin: Re: Quartus II priority 19 under Linux
            134893: 08/09/05: David Brown: Re: Quartus II priority 19 under Linux
                134894: 08/09/05: Petter Gustad: Re: Quartus II priority 19 under Linux
134837: 08/09/03: timinganalyzer: request for beta testers -- TimingAnalyzer Program
134838: 08/09/03: tullio: XST bug on illigal states of a FSM ?
    134839: 08/09/03: Jochen: Re: XST bug on illigal states of a FSM ?
    134842: 08/09/03: Nathan Bialke: Re: XST bug on illigal states of a FSM ?
    134843: 08/09/03: Kevin Neilson: Re: XST bug on illigal states of a FSM ?
    134844: 08/09/03: Evan Lavelle: Re: XST bug on illigal states of a FSM ?
        134846: 08/09/03: Kevin Neilson: Re: XST bug on illigal states of a FSM ?
            134850: 08/09/03: Evan Lavelle: Re: XST bug on illigal states of a FSM ?
                134859: 08/09/04: Evan Lavelle: Re: XST bug on illigal states of a FSM ?
                    134868: 08/09/04: KJ: Re: XST bug on illigal states of a FSM ?
                        134874: 08/09/04: Mike Treseler: Re: XST bug on illegal states of a FSM ?
            134907: 08/09/06: KJ: Re: XST bug on illigal states of a FSM ?
    134847: 08/09/04: Jim Granville: Re: XST bug on illigal states of a FSM ?
    134857: 08/09/03: <gael.paul@gmail.com>: Re: XST bug on illigal states of a FSM ?
    134863: 08/09/04: <gael.paul@gmail.com>: Re: XST bug on illigal states of a FSM ?
    134866: 08/09/04: tullio: Re: XST bug on illigal states of a FSM ?
    134867: 08/09/04: Gael Paul: Re: XST bug on illigal states of a FSM ?
    134885: 08/09/04: Andy: Re: XST bug on illigal states of a FSM ?
    134898: 08/09/05: KJ: Re: XST bug on illigal states of a FSM ?
    134902: 08/09/05: Gael Paul: Re: XST bug on illigal states of a FSM ?
    134903: 08/09/05: KJ: Re: XST bug on illigal states of a FSM ?
    134962: 08/09/08: Andy: Re: XST bug on illigal states of a FSM ?
    134964: 08/09/08: KJ: Re: XST bug on illigal states of a FSM ?
    134968: 08/09/08: Andy: Re: XST bug on illigal states of a FSM ?
    134978: 08/09/09: KJ: Re: XST bug on illigal states of a FSM ?
134845: 08/09/03: m m: LED lights flashing while LCD shows chars, Spartan-3A
    135195: 08/09/19: Steve Knapp: Re: LED lights flashing while LCD shows chars, Spartan-3A
    135314: 08/09/25: m m: Re: LED lights flashing while LCD shows chars, Spartan-3A
134851: 08/09/03: Nico Coesel: Strange Spartan2 behaviour
    134852: 08/09/03: Mike Treseler: Re: Strange Spartan2 behaviour
    134855: 08/09/04: Brian Drummond: Re: Strange Spartan2 behaviour
        134858: 08/09/04: Jochen: Re: Strange Spartan2 behaviour
            134877: 08/09/04: Nico Coesel: Re: Strange Spartan2 behaviour
                134963: 08/09/08: Nico Coesel: Re: Strange Spartan2 behaviour
        134905: 08/09/06: Jochen: Re: Strange Spartan2 behaviour
    134861: 08/09/04: Jonathan Bromley: Re: Strange Spartan2 behaviour
        134878: 08/09/04: Nico Coesel: Re: Strange Spartan2 behaviour
    134880: 08/09/04: Ben Jackson: Re: Strange Spartan2 behaviour
        134881: 08/09/04: Nico Coesel: Re: Strange Spartan2 behaviour
134862: 08/09/04: fmostafa: EDK frequency problem
    134875: 08/09/04: Mike Treseler: Re: EDK frequency problem
134865: 08/09/04: Pablo: Hide VHDL code.
    134869: 08/09/04: Brian Drummond: Re: Hide VHDL code.
    134895: 08/09/05: Pablo: Re: Hide VHDL code.
134876: 08/09/04: aleksa: Spartan-3 -> Spartan-2 problem
134883: 08/09/04: benn: uClinux / Microblaze -- Min. Requirements
    134891: 08/09/04: Antti: Re: uClinux / Microblaze -- Min. Requirements
    134896: 08/09/05: rickman: Re: uClinux / Microblaze -- Min. Requirements
    134897: 08/09/05: Antti: Re: uClinux / Microblaze -- Min. Requirements
    134908: 08/09/06: rickman: Re: uClinux / Microblaze -- Min. Requirements
    134918: 08/09/06: LittleAlex: Re: uClinux / Microblaze -- Min. Requirements
134900: 08/09/05: <amigo65@gmail.com>: need sme help on data encryption based on fpga
    134901: 08/09/05: Jon Beniston: Re: need sme help on data encryption based on fpga
    134944: 08/09/08: Mark McDougall: Re: need sme help on data encryption based on fpga
134904: 08/09/05: ssylee: Reviewing Equation information on Altera Quartus II version 8
134906: 08/09/06: Paul Urbanus: Altera library sim question
    134914: 08/09/06: LittleAlex: Re: Altera library sim question
        135028: 08/09/11: Paul Urbanus: Re: Altera library sim question
    134986: 08/09/09: <leaver.andrew@gmail.com>: Re: Altera library sim question
    135032: 08/09/11: LittleAlex: Re: Altera library sim question
134909: 08/09/06: thutt: Are Xilinx tools that bad, or am I missing something?
    134910: 08/09/06: Rich Webb: Re: Are Xilinx tools that bad, or am I missing something?
        134911: 08/09/06: thutt: Re: Are Xilinx tools that bad, or am I missing something?
            134920: 08/09/07: Muzaffer Kal: Re: Are Xilinx tools that bad, or am I missing something?
                134926: 08/09/07: thutt: Re: Are Xilinx tools that bad, or am I missing something?
    134923: 08/09/07: Sean Durkin: Re: Are Xilinx tools that bad, or am I missing something?
        134928: 08/09/07: thutt: Re: Are Xilinx tools that bad, or am I missing something?
            134991: 08/09/09: Alessandro: Re: Are Xilinx tools that bad, or am I missing something?
                134996: 08/09/09: thutt: Re: Are Xilinx tools that bad, or am I missing something?
                    135004: 08/09/10: Brian Drummond: Re: Are Xilinx tools that bad, or am I missing something?
                    135020: 08/09/10: Alessandro: Re: Are Xilinx tools that bad, or am I missing something?
            134997: 08/09/10: Kim Enkovaara: Re: Are Xilinx tools that bad, or am I missing something?
        135003: 08/09/10: Jochen: Re: Are Xilinx tools that bad, or am I missing something?
    134925: 08/09/07: John_H: Re: Are Xilinx tools that bad, or am I missing something?
        134927: 08/09/07: thutt: Re: Are Xilinx tools that bad, or am I missing something?
134912: 08/09/06: Bob Smith: Best way to buy Xilinx FPGAs?
    134913: 08/09/06: LittleAlex: Re: Best way to buy Xilinx FPGAs?
        134915: 08/09/06: LittleAlex: Re: Best way to buy Xilinx FPGAs?
    134919: 08/09/07: rickman: Re: Best way to buy Xilinx FPGAs?
        134929: 08/09/07: Bob Smith: Re: Best way to buy Xilinx FPGAs?
            134946: 08/09/08: Brian Drummond: Re: Best way to buy Xilinx FPGAs?
        134931: 08/09/07: dalai lamah: Re: Best way to buy Xilinx FPGAs?
134916: 08/09/06: LittleAlex: Some feedback on the Xilinx web site
    134917: 08/09/06: Antti: Re: Some feedback on the Xilinx web site
    134921: 08/09/07: Bob Smith: Re: Some feedback on the Xilinx web site
    134950: 08/09/08: Gabor: Re: Some feedback on the Xilinx web site
    134959: 08/09/08: John_H: Re: Some feedback on the Xilinx web site
    134961: 08/09/08: LittleAlex: Re: Some feedback on the Xilinx web site
    134980: 08/09/09: Gabor: Re: Some feedback on the Xilinx web site
    134982: 08/09/09: rickman: Re: Some feedback on the Xilinx web site
    134983: 08/09/09: John_H: Re: Some feedback on the Xilinx web site
134922: 08/09/07: woko: LVDS Receiver in FPGA
    134941: 08/09/07: Not: Re: LVDS Receiver in FPGA
    134960: 08/09/08: Symon: Re: LVDS Receiver in FPGA
        135027: 08/09/11: Symon: Re: LVDS Receiver in FPGA
    135025: 08/09/11: woko: Re: LVDS Receiver in FPGA
134930: 08/09/07: Alessandro: Spartan 3E evaluation board manufacturers
    134932: 08/09/07: Olaf Kaluza: Re: Spartan 3E evaluation board manufacturers
        134934: 08/09/07: Frank Buss: Re: Spartan 3E evaluation board manufacturers
        134935: 08/09/07: Alessandro: Re: Spartan 3E evaluation board manufacturers
    134933: 08/09/07: Frank Buss: Re: Spartan 3E evaluation board manufacturers
        134936: 08/09/07: Olaf Kaluza: Re: Spartan 3E evaluation board manufacturers
            134937: 08/09/07: Frank Buss: Re: Spartan 3E evaluation board manufacturers
                134940: 08/09/07: Alessandro: Re: Spartan 3E evaluation board manufacturers
                    134972: 08/09/08: james: Re: Spartan 3E evaluation board manufacturers
                        134988: 08/09/09: Alessandro: Re: Spartan 3E evaluation board manufacturers
                            135006: 08/09/10: james: Re: Spartan 3E evaluation board manufacturers
        134938: 08/09/07: Alessandro: Re: Spartan 3E evaluation board manufacturers
            134939: 08/09/07: Frank Buss: Re: Spartan 3E evaluation board manufacturers
                134970: 08/09/09: Alessandro: Re: Spartan 3E evaluation board manufacturers
            134956: 08/09/08: Olaf Kaluza: Re: Spartan 3E evaluation board manufacturers
                134967: 08/09/08: Alessandro: Re: Spartan 3E evaluation board manufacturers
    134942: 08/09/08: MikeWhy: Re: Spartan 3E evaluation board manufacturers
        134969: 08/09/09: Alessandro: Re: Spartan 3E evaluation board manufacturers
            134975: 08/09/08: Alex Freed: Re: Spartan 3E evaluation board manufacturers
                134989: 08/09/09: Alessandro: Re: Spartan 3E evaluation board manufacturers
                    134993: 08/09/09: Alex Freed: Re: Spartan 3E evaluation board manufacturers
            134977: 08/09/09: MikeWhy: Re: Spartan 3E evaluation board manufacturers
                134990: 08/09/09: Alessandro: Re: Spartan 3E evaluation board manufacturers
                    135024: 08/09/10: MikeWhy: Re: Spartan 3E evaluation board manufacturers
134943: 08/09/07: knight: Signed multiplication
    134945: 08/09/08: RCIngham: Re: Signed multiplication
    134947: 08/09/08: Brian Drummond: Re: Signed multiplication
        134973: 08/09/09: Brian Drummond: Re: Signed multiplication
        135005: 08/09/10: Duane Clark: Re: Signed multiplication
    134948: 08/09/08: Jon Beniston: Re: Signed multiplication
    134953: 08/09/08: rickman: Re: Signed multiplication
    134954: 08/09/08: Gabor: Re: Signed multiplication
    134955: 08/09/08: Jon Beniston: Re: Signed multiplication
    134965: 08/09/08: Eric Smith: Re: Signed multiplication
134949: 08/09/08: Michael Dreschmann: No connect pins on xc4vfx20
    134951: 08/09/08: Gabor: Re: No connect pins on xc4vfx20
134952: 08/09/08: <weg22@drexel.edu>: IEEE 1394 interface for FPGA??
    134976: 08/09/09: Martin Thompson: Re: IEEE 1394 interface for FPGA??
    134981: 08/09/09: MM: Re: IEEE 1394 interface for FPGA??
    136489: 08/11/19: Finn Nielsen: Re: IEEE 1394 interface for FPGA??
134957: 08/09/08: laserbeak43: Vista 64: USB drivers still don't install
134958: 08/09/08: System Alchemist: Altera Serial Lite Protocol implemented on Xilinx ??
134974: 08/09/08: <bgong86@gmail.com>: Placing Verilog busses using Xilinx RPMs
    134979: 08/09/09: Gabor: Re: Placing Verilog busses using Xilinx RPMs
        135009: 08/09/10: james: Re: Placing Verilog busses using Xilinx RPMs
            135049: 08/09/12: james: Re: Placing Verilog busses using Xilinx RPMs
    134985: 08/09/09: <bgong86@gmail.com>: Re: Placing Verilog busses using Xilinx RPMs
    135022: 08/09/10: <bgong86@gmail.com>: Re: Placing Verilog busses using Xilinx RPMs
134992: 08/09/09: KJ: What version of ISE is availabe for Virtex5?
    134995: 08/09/09: jtw: Re: What version of ISE is availabe for Virtex5?
    135010: 08/09/10: james: Re: What version of ISE is availabe for Virtex5?
134994: 08/09/09: rao: IDELAYCTRL Locking problem with ISE10.1i
    134999: 08/09/10: mamu: Re: IDELAYCTRL Locking problem with ISE10.1i
    135012: 08/09/10: MM: Re: IDELAYCTRL Locking problem with ISE10.1i
        135018: 08/09/10: MM: Re: IDELAYCTRL Locking problem with ISE10.1i
    135014: 08/09/10: rao: Re: IDELAYCTRL Locking problem with ISE10.1i
134998: 08/09/09: lordsathish: Can Soft microprocessor replace DSP's
    135001: 08/09/10: Symon: Re: Can Soft microprocessor replace DSP's
        135011: 08/09/10: james: Re: Can Soft microprocessor replace DSP's
            135016: 08/09/10: Symon: Re: Can Soft microprocessor replace DSP's
        135015: 08/09/10: Symon: Re: Can Soft microprocessor replace DSP's
    135002: 08/09/10: RCIngham: Re: Can Soft microprocessor replace DSP's
    135007: 08/09/10: Jon Beniston: Re: Can Soft microprocessor replace DSP's
    135008: 08/09/10: TehPron: Re: Can Soft microprocessor replace DSP's
    135021: 08/09/10: Nico Coesel: Re: Can Soft microprocessor replace DSP's
    135023: 08/09/10: Eric Smith: Re: Can Soft microprocessor replace DSP's
    135071: 08/09/13: Lorenz Kolb: Re: Can Soft microprocessor replace DSP's
135000: 08/09/10: aleksa: Spartan-II, config pins 5V tolerant? (slave serial)
    135029: 08/09/11: aleksa: Re: Spartan-II, config pins 5V tolerant? (slave serial)
        135037: 08/09/11: Jeff Cunningham: Re: Spartan-II, config pins 5V tolerant? (slave serial)
        135050: 08/09/12: james: Re: Spartan-II, config pins 5V tolerant? (slave serial)
    135033: 08/09/11: rickman: Re: Spartan-II, config pins 5V tolerant? (slave serial)
    135034: 08/09/11: M.Randelzhofer: Re: Spartan-II, config pins 5V tolerant? (slave serial)
        135041: 08/09/12: M.Randelzhofer: Re: Spartan-II, config pins 5V tolerant? (slave serial)
    135040: 08/09/11: aleksa: Re: Spartan-II, config pins 5V tolerant? (slave serial)
135013: 08/09/10: FyberOptic: WinCupl Problem(s)
    135019: 08/09/11: Jim Granville: Re: WinCupl Problem(s)
135017: 08/09/10: Pablo: Load Application from External Memory without the use of XMD???
    135026: 08/09/11: <ales.gorkic@gmail.com>: Re: Load Application from External Memory without the use of XMD???
        135039: 08/09/11: MikeWhy: Re: Load Application from External Memory without the use of XMD???
            135059: 08/09/12: MikeWhy: Re: Load Application from External Memory without the use of XMD???
    135036: 08/09/11: Pablo: Re: Load Application from External Memory without the use of XMD???
    135045: 08/09/12: <ales.gorkic@gmail.com>: Re: Load Application from External Memory without the use of XMD???
    135046: 08/09/12: Pablo: Re: Load Application from External Memory without the use of XMD???
    135080: 08/09/15: Pablo: Re: Load Application from External Memory without the use of XMD???
135030: 08/09/11: =?ISO-8859-15?Q?Andreas_H=F6lscher?=: How to install Xilinx ISE simulator?
    135031: 08/09/11: Enes Erdin: Re: How to install Xilinx ISE simulator?
135035: 08/09/11: <sureshbabu.payauala@gmail.com>: errors in schematics
    135042: 08/09/12: Gregory C. Read: Re: errors in schematics
135038: 08/09/11: wallge: Quartus II compile speedup with New Quad Core Intel machine (compared
    135047: 08/09/12: Patrick Dubois: Re: Quartus II compile speedup with New Quad Core Intel machine
        135056: 08/09/12: <sky465nm@trline4.org>: Re: Quartus II compile speedup with New Quad Core Intel machine (compared with old dual XEON workstation)
        135069: 08/09/12: arko: Re: Quartus II compile speedup with New Quad Core Intel machine (compared with old dual XEON workstation)
    135053: 08/09/12: Jon Beniston: Re: Quartus II compile speedup with New Quad Core Intel machine
    135055: 08/09/12: <sky465nm@trline4.org>: Re: Quartus II compile speedup with New Quad Core Intel machine (compared with old dual XEON workstation)
    135057: 08/09/12: wallge: Re: Quartus II compile speedup with New Quad Core Intel machine
    135058: 08/09/12: KJ: Re: Quartus II compile speedup with New Quad Core Intel machine
    135073: 08/09/13: Patrick Dubois: Re: Quartus II compile speedup with New Quad Core Intel machine
    135074: 08/09/13: rickman: Re: Quartus II compile speedup with New Quad Core Intel machine
    135078: 08/09/14: <cs_posting@hotmail.com>: Re: Quartus II compile speedup with New Quad Core Intel machine
135048: 08/09/12: Michael Dreschmann: Ultra low power FPGAs
    135051: 08/09/12: Andy: Re: Ultra low power FPGAs
    135052: 08/09/12: rickman: Re: Ultra low power FPGAs
        135054: 08/09/12: Michael Dreschmann: Re: Ultra low power FPGAs
            135060: 08/09/12: Frank Buss: Re: Ultra low power FPGAs
                135081: 08/09/15: Michael Dreschmann: Re: Ultra low power FPGAs
            135064: 08/09/13: Jim Granville: Re: Ultra low power FPGAs
                135082: 08/09/15: Michael Dreschmann: Re: Ultra low power FPGAs
                    135085: 08/09/15: Jim Granville: Re: Ultra low power FPGAs
            135083: 08/09/15: Michael Dreschmann: Re: Ultra low power FPGAs
        135062: 08/09/12: rickman: Re: Ultra low power FPGAs
        135084: 08/09/15: Antti: Re: Ultra low power FPGAs
        135231: 08/09/22: rickman: Re: Ultra low power FPGAs
    135097: 08/09/16: jerzy.gbur@gmail.com: Re: Ultra low power FPGAs
    135118: 08/09/16: Steve Knapp: Re: Ultra low power FPGAs
135061: 08/09/12: <rganapa@gmail.com>: Interfacing external memory
135063: 08/09/12: dudesinmexico: Problem with Virtex-4 IBIS model
    135068: 08/09/12: Brian Davis: Re: Problem with Virtex-4 IBIS model
    135088: 08/09/15: Barry: Re: Problem with Virtex-4 IBIS model
    135090: 08/09/15: <dudesinmexico@yahoo.com>: Re: Problem with Virtex-4 IBIS model
    135091: 08/09/15: <dudesinmexico@yahoo.com>: Re: Problem with Virtex-4 IBIS model
    135094: 08/09/15: Brian Davis: Re: Problem with Virtex-4 IBIS model
    135095: 08/09/15: Brian Davis: Re: Problem with Virtex-4 IBIS model
    135919: 08/10/21: Brian Davis: Re: Problem with Virtex-4 IBIS model
135065: 08/09/12: whygee: Seeking several async. SRAMs at 8ns ( IS61LV51216-8T or GS74116TP-8
    135066: 08/09/13: Jim Granville: Re: Seeking several async. SRAMs at 8ns ( IS61LV51216-8T or GS74116TP-8)
        135067: 08/09/13: whygee: Re: Seeking several async. SRAMs at 8ns ( IS61LV51216-8T or GS74116TP-8)
135070: 08/09/12: <edwin.gobain@gmail.com>: ASIC Prototyping
    135072: 08/09/13: HT-Lab: Re: ASIC Prototyping
    135076: 08/09/13: Petter Gustad: Re: ASIC Prototyping
135075: 08/09/13: digital designs: Xilinx FFT core configured in natural order
    135098: 08/09/16: RCIngham: Re: Xilinx FFT core configured in natural order
135079: 08/09/15: Andreas Ehliar: Some random impressions from FPL 2008
135086: 08/09/15: m: Moving to Altera from Xilinx
    135087: 08/09/15: Jon Beniston: Re: Moving to Altera from Xilinx
        135151: 08/09/18: Mark McDougall: Re: Moving to Altera from Xilinx
            135167: 08/09/19: Mark McDougall: Re: Moving to Altera from Xilinx
    135089: 08/09/15: <jeffjcannon@gmail.com>: Re: Moving to Altera from Xilinx
    135092: 08/09/15: <cs_posting@hotmail.com>: Re: Moving to Altera from Xilinx
    135106: 08/09/16: Tommy Thorn: Re: Moving to Altera from Xilinx
    135120: 08/09/17: Colin Paul Gloster: Re: Moving to Altera from Xilinx
    135157: 08/09/18: Jochen: Re: Moving to Altera from Xilinx
    135163: 08/09/18: Dave Pollum: Re: Moving to Altera from Xilinx
    135173: 08/09/19: Colin Paul Gloster: Re: Moving to Altera from Xilinx
135093: 08/09/15: Ed McGettigan: Re: need fast FPGA suggestions
135096: 08/09/15: Surya: Ethernet and Interrupts in Virtex II pro
135099: 08/09/16: Rob: Xilinx build system
    135104: 08/09/16: LittleAlex: Re: Xilinx build system
    135109: 08/09/16: <sky465nm@trline4.org>: Re: Xilinx build system
        135112: 08/09/16: Alex Colvin: Re: Xilinx build system
            135117: 08/09/17: <sky465nm@trline4.org>: Re: Xilinx build system
    135110: 08/09/16: General Schvantzkopf: Re: Xilinx build system
    135143: 08/09/17: Nico Coesel: Re: Xilinx build system
    135158: 08/09/18: Jochen: Re: Xilinx build system
135100: 08/09/16: ALuPin@web.de: Compiler Options
    135101: 08/09/16: Jon Beniston: Re: Compiler Options
    135102: 08/09/16: ALuPin@web.de: Re: Compiler Options
    135111: 08/09/16: Jon Beniston: Re: Compiler Options
    135121: 08/09/17: ALuPin@web.de: Re: Compiler Options
    135126: 08/09/17: <pontus.stenstrom@gmail.com>: Re: Compiler Options
135103: 08/09/16: Pablo: Two JTAG Parallel IV Cable in a single PC.
    135105: 08/09/16: LittleAlex: Re: Two JTAG Parallel IV Cable in a single PC.
        135113: 08/09/16: MM: Re: Two JTAG Parallel IV Cable in a single PC.
            135132: 08/09/17: MM: Re: Two JTAG Parallel IV Cable in a single PC.
    135130: 08/09/17: Pablo: Re: Two JTAG Parallel IV Cable in a single PC.
135107: 08/09/16: <flatiron@libero.it>: Info request about Synplify and Foundation usage
    135175: 08/09/19: <flatiron@libero.it>: Re: Info request about Synplify and Foundation usage
135114: 08/09/16: pemiliv: security system password by voice recognition commands
    135156: 08/09/18: RCIngham: Re: security system password by voice recognition commands
    135159: 08/09/18: John_H: Re: security system password by voice recognition commands
135115: 08/09/16: Brad Smallridge: Xilinx Spartan E
    135116: 08/09/16: Eric Smith: Re: Xilinx Spartan E
        135136: 08/09/17: Brad Smallridge: Re: Xilinx Spartan E
            135144: 08/09/17: Brad Smallridge: Re: Xilinx Spartan E
                135147: 08/09/17: Brad Smallridge: Re: Xilinx Spartan E
                    135148: 08/09/17: John_H: Re: Xilinx Spartan E
                        135185: 08/09/19: Brad Smallridge: Re: Xilinx Spartan E
        135137: 08/09/17: John_H: Re: Xilinx Spartan E
        135145: 08/09/17: John_H: Re: Xilinx Spartan E
135119: 08/09/16: akineko: Free H/W Co-sim solution (Call for Wiki participation)
135122: 08/09/17: Klaus Niedermayer: Random Mask Generation on FPGAs
    135123: 08/09/17: Lorenz Kolb: Re: Random Mask Generation on FPGAs
        135125: 08/09/17: Klaus Niedermayer: Re: Random Mask Generation on FPGAs
            135154: 08/09/18: Alex Colvin: Re: Random Mask Generation on FPGAs
        135131: 08/09/17: <jetmarc@hotmail.com>: Re: Random Mask Generation on FPGAs
        135133: 08/09/17: Peter Alfke: Re: Random Mask Generation on FPGAs
    135139: 08/09/17: Alex Freed: Re: Random Mask Generation on FPGAs
        135155: 08/09/18: arsonperbuilding@gmail.com: Re: Random Mask Generation on FPGAs
    135140: 08/09/18: Jim Granville: Re: Random Mask Generation on FPGAs
        135153: 08/09/18: Lorenz Kolb: Re: Random Mask Generation on FPGAs
            135228: 08/09/22: Jon Elson: Re: Random Mask Generation on FPGAs
135124: 08/09/17: knight: 1QN representation
    135127: 08/09/17: Symon: Re: 1QN representation
    135223: 08/09/22: knight: Re: 1QN representation
135128: 08/09/17: osquillar: SDRAM question
    135129: 08/09/17: <jetmarc@hotmail.com>: Re: SDRAM question
    135138: 08/09/17: John_H: Re: SDRAM question
        135246: 08/09/23: Brian Drummond: Re: SDRAM question
            135284: 08/09/24: Brian Drummond: Re: SDRAM question
    135141: 08/09/17: osquillar: Re: SDRAM question
    135142: 08/09/17: osquillar: Re: SDRAM question
    135146: 08/09/17: John_H: Re: SDRAM question
    135224: 08/09/22: osquillar: Re: SDRAM question
    135225: 08/09/22: Dave: Re: SDRAM question
    135240: 08/09/23: osquillar: Re: SDRAM question
    135282: 08/09/24: osquillar: Re: SDRAM question
135135: 08/09/17: m m: Two-complement value from ADC, Spartan-3A, 3E
135149: 08/09/17: ekavirsrikanth@gmail.com: interview questions ........
    135150: 08/09/17: LittleAlex: Re: interview questions ........
    135198: 08/09/19: glen herrmannsfeldt: Re: interview questions ........
135160: 08/09/18: t.bartzick@gmx.net: Clock Enable safe?
    135161: 08/09/18: Symon: Re: Clock Enable safe?
        135164: 08/09/18: Mike Lewis: Re: Clock Enable safe?
            135169: 08/09/19: PatC: Re: Clock Enable safe?
                135197: 08/09/19: glen herrmannsfeldt: Re: Clock Enable safe?
    135162: 08/09/18: t.bartzick@gmx.net: Re: Clock Enable safe?
    135165: 08/09/18: KJ: Re: Clock Enable safe?
    135166: 08/09/18: t.bartzick@gmx.net: Re: Clock Enable safe?
    135168: 08/09/18: Thomas Stanka: Re: Clock Enable safe?
    135170: 08/09/19: t.bartzick@gmx.net: Re: Clock Enable safe?
    135177: 08/09/19: KJ: Re: Clock Enable safe?
135171: 08/09/19: KJ: Help~ How to develope with FPGA board?
    135172: 08/09/19: Colin Paul Gloster: Re: Help~ How to develope with FPGA board?
    135178: 08/09/19: Brian Drummond: Re: Help~ How to develope with FPGA board?
    135181: 08/09/20: Tony Burch: Re: Help~ How to develope with FPGA board?
        135183: 08/09/19: Krzysztof Kepa: Re: Help~ How to develope with FPGA board?
135174: 08/09/19: maxascent: usb on a spartan
135176: 08/09/19: psihodelia@googlemail.com: What software do use big organizations for Logic Synthesis from HDL?
    135179: 08/09/19: morphiend: Re: What software do use big organizations for Logic Synthesis from
    135180: 08/09/19: Jonathan Bromley: Re: What software do use big organizations for Logic Synthesis from HDL?
        135182: 08/09/19: HT-Lab: Re: What software do use big organizations for Logic Synthesis from HDL?
135184: 08/09/19: Peter Alfke: Peter says Good Bye
    135187: 08/09/19: Antonio Pasini: Re: Peter says Good Bye
    135188: 08/09/19: John_H: Re: Peter says Good Bye
    135193: 08/09/19: Kevin Neilson: Re: Peter says Good Bye
    135194: 08/09/19: Steve Knapp: Re: Peter says Good Bye
    135199: 08/09/20: Brian Drummond: Re: Peter says Good Bye
    135205: 08/09/19: <jprovidenza@yahoo.com>: Re: Peter says Good Bye
    135206: 08/09/19: Weng Tianxiang: Re: Peter says Good Bye
    135209: 08/09/20: <Maik>: Re: Peter says Good Bye
    135213: 08/09/21: Tony Burch: Re: Peter says Good Bye
    135217: 08/09/22: MM: Re: Peter says Good Bye
    135280: 08/09/24: przemek klosowski: Re: Peter says Good Bye
        135304: 08/09/25: Andreas Ehliar: Re: Peter says Good Bye
        135310: 08/09/25: Steve Knapp: Re: Peter says Good Bye
135186: 08/09/19: surendar: Synplify Pro derived clock going out as port
    135192: 08/09/19: Kevin Neilson: Re: Synplify Pro derived clock going out as port
135189: 08/09/19: Jon Elson: WebPack on CentOS 5 ?
    135191: 08/09/19: Andy Botterill: Re: WebPack on CentOS 5 ?
    135196: 08/09/19: General Schvantzkopf: Re: WebPack on CentOS 5 ?
        135203: 08/09/19: Eric Smith: Re: WebPack on CentOS 5 ?
    135200: 08/09/20: Brian Drummond: Re: WebPack on CentOS 5 ?
        135201: 08/09/19: Matthew Hicks: Re: WebPack on CentOS 5 ?
    135202: 08/09/19: Eric Smith: Re: WebPack on CentOS 5 ?
        135227: 08/09/22: Jon Elson: Re: WebPack on CentOS 5 ?
135190: 08/09/19: Marlboro: Is it hard to detect an ucf sytax error?
    135207: 08/09/19: Darol Klawetter: Re: Is it hard to detect an ucf sytax error?
        135208: 08/09/20: Nico Coesel: Re: Is it hard to detect an ucf sytax error?
    135220: 08/09/22: Rob: Re: Is it hard to detect an ucf sytax error?
135204: 08/09/19: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?=: Virtex-II Pro to Stratix GX
    135221: 08/09/22: Ed McGettigan: Re: Virtex-II Pro to Stratix GX
    135229: 08/09/22: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?=: Re: Virtex-II Pro to Stratix GX
    135237: 08/09/22: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?=: Re: Virtex-II Pro to Stratix GX
135210: 08/09/20: thutt: Is it possible to get an RTL netlist from Xilinx tools?
    135222: 08/09/22: Kevin Neilson: Re: Is it possible to get an RTL netlist from Xilinx tools?
        135233: 08/09/22: thutt: Re: Is it possible to get an RTL netlist from Xilinx tools?
            135239: 08/09/23: David R Brooks: Re: Is it possible to get an RTL netlist from Xilinx tools?
                135261: 08/09/23: doug: Re: Is it possible to get an RTL netlist from Xilinx tools?
                135341: 08/09/27: thutt: Re: Is it possible to get an RTL netlist from Xilinx tools?
                    135345: 08/09/27: doug: Re: Is it possible to get an RTL netlist from Xilinx tools?
                        135346: 08/09/27: thutt: Re: Is it possible to get an RTL netlist from Xilinx tools?
                            135349: 08/09/27: Muzaffer Kal: Re: Is it possible to get an RTL netlist from Xilinx tools?
                            135351: 08/09/27: doug: Re: Is it possible to get an RTL netlist from Xilinx tools?
            135264: 08/09/23: Ed McGettigan: Re: Is it possible to get an RTL netlist from Xilinx tools?
            135268: 08/09/23: Kevin Neilson: Re: Is it possible to get an RTL netlist from Xilinx tools?
                135342: 08/09/27: thutt: Re: Is it possible to get an RTL netlist from Xilinx tools?
                    135398: 08/09/30: Eric Smith: Re: Is it possible to get an RTL netlist from Xilinx tools?
                        135467: 08/10/02: thutt: Re: Is it possible to get an RTL netlist from Xilinx tools?
    135247: 08/09/23: Brian Drummond: Re: Is it possible to get an RTL netlist from Xilinx tools?
        135248: 08/09/23: thutt: Re: Is it possible to get an RTL netlist from Xilinx tools?
            135279: 08/09/24: Brian Drummond: Re: Is it possible to get an RTL netlist from Xilinx tools?
        135269: 08/09/23: Kevin Neilson: Re: Is it possible to get an RTL netlist from Xilinx tools?
            135343: 08/09/27: thutt: Re: Is it possible to get an RTL netlist from Xilinx tools?
135211: 08/09/20: m: Altera and DDR3
    135212: 08/09/20: Sean Durkin: Re: Altera and DDR3
    135219: 08/09/22: Rob: Re: Altera and DDR3
    135234: 08/09/22: <vaughnbetz@gmail.com>: Re: Altera and DDR3
    135238: 08/09/23: Rob: Re: Altera and DDR3
    135256: 08/09/23: m: Re: Altera and DDR3
    135758: 08/10/14: <vaughnbetz@gmail.com>: Re: Altera and DDR3
135214: 08/09/21: <heilig@iname.com>: 50 Ohm Analog Output of FPGA
    135215: 08/09/21: Joseph H Allen: Re: 50 Ohm Analog Output of FPGA
    135232: 08/09/22: rickman: Re: 50 Ohm Analog Output of FPGA
        135352: 08/09/27: KJ: Re: 50 Ohm Analog Output of FPGA
            135358: 08/09/28: Allan Herriman: Re: 50 Ohm Analog Output of FPGA
        135359: 08/09/28: David Tweed: Re: 50 Ohm Analog Output of FPGA
            135360: 08/09/28: Muzaffer Kal: Re: 50 Ohm Analog Output of FPGA
                135362: 08/09/28: David Tweed: Re: 50 Ohm Analog Output of FPGA
    135262: 08/09/23: <heilig@iname.com>: Re: 50 Ohm Analog Output of FPGA
    135344: 08/09/27: rickman: Re: 50 Ohm Analog Output of FPGA
    135350: 08/09/27: langwadt@fonz.dk: Re: 50 Ohm Analog Output of FPGA
135216: 08/09/21: robj: HDL Companion
135218: 08/09/22: Rob: Xilinx Timing constraint problems
    135243: 08/09/23: vasu: Re: Xilinx Timing constraint problems
    135286: 08/09/24: Rob: Re: Xilinx Timing constraint problems
    135433: 08/10/01: Greg Daughtry: Re: Xilinx Timing constraint problems
    135472: 08/10/03: Rob: Re: Xilinx Timing constraint problems
135226: 08/09/22: Roger: Ethernet MDI termination
    135270: 08/09/23: MM: Re: Ethernet MDI termination
        135283: 08/09/24: Roger: Re: Ethernet MDI termination
            135291: 08/09/24: MM: Re: Ethernet MDI termination
                135295: 08/09/24: Roger: Re: Ethernet MDI termination
                    135297: 08/09/24: MM: Re: Ethernet MDI termination
135230: 08/09/22: Stephen: Avalda's Parallel F# to RTL FPGA Compiler
    135290: 08/09/24: Benjamin Couillard: Re: Avalda's Parallel F# to RTL FPGA Compiler
    135298: 08/09/24: <ljung@codetronix.com>: Re: Avalda's Parallel F# to RTL FPGA Compiler
135235: 08/09/22: mkr: duty cycle significance
    135236: 08/09/23: Matthew Hicks: Re: duty cycle significance
    135241: 08/09/23: Muzaffer Kal: Re: duty cycle significance
    135252: 08/09/23: KJ: Re: duty cycle significance
        135274: 08/09/23: glen herrmannsfeldt: Re: duty cycle significance
            135281: 08/09/24: Andreas Ehliar: Re: duty cycle significance
                135318: 08/09/25: glen herrmannsfeldt: Re: duty cycle significance
    135255: 08/09/23: John_H: Re: duty cycle significance
135242: 08/09/23: Svenn Are Bjerkem: Use of divided clocks inside modules
    135245: 08/09/23: Rob: Re: Use of divided clocks inside modules
    135249: 08/09/23: Brian Drummond: Re: Use of divided clocks inside modules
        135266: 08/09/23: doug: Re: Use of divided clocks inside modules
            135323: 08/09/26: Symon: Re: Use of divided clocks inside modules
                135327: 08/09/26: Symon: Re: Use of divided clocks inside modules
                135328: 08/09/26: Symon: Re: Use of divided clocks inside modules
                    135339: 08/09/27: Symon: Re: Use of divided clocks inside modules
                        135353: 08/09/28: Symon: Re: Use of divided clocks inside modules
    135250: 08/09/23: Svenn Are Bjerkem: Re: Use of divided clocks inside modules
    135251: 08/09/23: KJ: Re: Use of divided clocks inside modules
    135253: 08/09/23: Rob: Re: Use of divided clocks inside modules
    135254: 08/09/23: Andy: Re: Use of divided clocks inside modules
    135257: 08/09/23: KJ: Re: Use of divided clocks inside modules
    135258: 08/09/23: Svenn Are Bjerkem: Re: Use of divided clocks inside modules
    135260: 08/09/23: doug: Re: Use of divided clocks inside modules
    135263: 08/09/23: KJ: Re: Use of divided clocks inside modules
    135265: 08/09/23: Svenn Are Bjerkem: Re: Use of divided clocks inside modules
    135267: 08/09/23: Gael Paul: Re: Use of divided clocks inside modules
    135276: 08/09/23: Andy: Re: Use of divided clocks inside modules
    135277: 08/09/23: Andy: Re: Use of divided clocks inside modules
    135325: 08/09/26: Gael Paul: Re: Use of divided clocks inside modules
    135326: 08/09/26: Andy: Re: Use of divided clocks inside modules
    135330: 08/09/26: Gael Paul: Re: Use of divided clocks inside modules
135244: 08/09/23: <secureasm@gmail.com>: OFDM band switch ...
    135288: 08/09/24: jerzy.gbur@gmail.com: Re: OFDM band switch ...
        135302: 08/09/25: Kappasm: Re: OFDM band switch ...
            135348: 08/09/27: Kappa: Re: OFDM band switch ...
                135405: 08/10/01: Kappasm: Re: OFDM band switch ...
    135322: 08/09/26: jerzy.gbur@gmail.com: Re: OFDM band switch ...
    135368: 08/09/29: jerzy.gbur@gmail.com: Re: OFDM band switch ...
135259: 08/09/23: maxascent: Xilinx Mode Select Pins
    135271: 08/09/23: LittleAlex: Re: Xilinx Mode Select Pins
        135273: 08/09/23: Andy: Re: Xilinx Mode Select Pins
    135272: 08/09/23: Benjamin Krill: Re: Xilinx Mode Select Pins
    135278: 08/09/23: Steve Knapp: Re: Xilinx Mode Select Pins
        135285: 08/09/24: Andy: Re: Xilinx Mode Select Pins
        135293: 08/09/24: emeb: Re: Xilinx Mode Select Pins
        135306: 08/09/25: Barry: Re: Xilinx Mode Select Pins
        135307: 08/09/25: emeb: Re: Xilinx Mode Select Pins
    135294: 08/09/24: Benjamin Krill: Re: Xilinx Mode Select Pins
135275: 08/09/23: argee: Simulating BRAMs using ISE simulator?
135287: 08/09/24: jack.harvard@googlemail.com: decimal to ieee 754 single precision floating point
    135312: 08/09/25: Kevin Neilson: Re: decimal to ieee 754 single precision floating point
    135324: 08/09/26: Gabor: Re: decimal to ieee 754 single precision floating point
135289: 08/09/24: Benjamin Couillard: Weird DCM problem with external deskew
    135292: 08/09/24: Ed McGettigan: Re: Weird DCM problem with external deskew
    135296: 08/09/24: Benjamin Couillard: Re: Weird DCM problem with external deskew
    135300: 08/09/25: Brian Drummond: Re: Weird DCM problem with external deskew
        135309: 08/09/25: Ed McGettigan: Re: Weird DCM problem with external deskew
    135301: 08/09/24: Benjamin Couillard: Re: Weird DCM problem with external deskew
    135311: 08/09/25: Benjamin Couillard: Re: Weird DCM problem with external deskew
135299: 08/09/25: Tony Burch: FPGA Lab Liquidation Sale
    135308: 08/09/25: John_H: Re: FPGA Lab Liquidation Sale
135303: 08/09/25: mkr: wishbone interface
    135305: 08/09/25: argee: Re: wishbone interface
        135320: 08/09/26: Martin Thompson: Re: wishbone interface
    135319: 08/09/25: mkr: Re: wishbone interface
135313: 08/09/25: KJ: Please recommend good textbook or technical report about FPGA
    135315: 08/09/26: Andreas Ehliar: Re: Please recommend good textbook or technical report about FPGA coprocessor
    135316: 08/09/26: Mark McDougall: Re: Please recommend good textbook or technical report about FPGA
135317: 08/09/25: Goli: Having problems with using flash in EDK
    135329: 08/09/26: MM: Re: Having problems with using flash in EDK
135321: 08/09/26: Pablo H: MicroBlaze SMP system DEMO
135331: 08/09/26: Tommy Thorn: Clocking Sync Burst SRAM
    135334: 08/09/26: KJ: Re: Clocking Sync Burst SRAM
    135335: 08/09/26: Joseph H Allen: Re: Clocking Sync Burst SRAM
        135363: 08/09/28: Nico Coesel: Re: Clocking Sync Burst SRAM
            135364: 08/09/28: KJ: Re: Clocking Sync Burst SRAM
                135379: 08/09/29: Nico Coesel: Re: Clocking Sync Burst SRAM
    135354: 08/09/27: Tommy Thorn: Re: Clocking Sync Burst SRAM
    135357: 08/09/27: Tommy Thorn: Re: Clocking Sync Burst SRAM
    135361: 08/09/28: KJ: Re: Clocking Sync Burst SRAM
    135380: 08/09/29: KJ: Re: Clocking Sync Burst SRAM
135332: 08/09/26: <uraniumore238@gmail.com>: maximum clock rating
    135333: 08/09/26: Tommy Thorn: Re: maximum clock rating
    135347: 08/09/27: Nico Coesel: Re: maximum clock rating
135336: 08/09/26: EM: Does XST support global signals?
    135337: 08/09/26: Brian Davis: Re: Does XST support global signals?
    135549: 08/10/07: EM: Re: Does XST support global signals?
    135582: 08/10/08: Brian Davis: Re: Does XST support global signals?
    135921: 08/10/21: Brian Davis: Re: Does XST support global signals?
135338: 08/09/27: nezhate: Open source IP core development with configuration GUI
    135340: 08/09/27: Brian Drummond: Re: Open source IP core development with configuration GUI
135355: 08/09/27: Totally_Lost: Looking for Insight S2-PCI w/XC2S150 board documentation/manual
    135356: 08/09/27: Totally_Lost: Re: Looking for Insight S2-PCI w/XC2S150 board documentation/manual
135365: 08/09/28: <onwuka.arisa@gmail.com>: Difference between PLD and General purpose CPU`
    135369: 08/09/29: Kolja Sulimma: Re: Difference between PLD and General purpose CPU`
    135400: 08/09/30: <cs_posting@hotmail.com>: Re: Difference between PLD and General purpose CPU`
    135407: 08/10/01: Kolja Sulimma: Re: Difference between PLD and General purpose CPU`
135366: 08/09/28: <vlodiya@gmail.com>: Low frequency clock generation - need help
    135367: 08/09/28: Peter Alfke: Re: Low frequency clock generation - need help
    135370: 08/09/29: Symon: Re: Low frequency clock generation - need help
    135389: 08/09/29: thutt: Re: Low frequency clock generation - need help
        135442: 08/10/02: Symon: Re: Low frequency clock generation - need help
            135448: 08/10/02: Brian Drummond: Re: Low frequency clock generation - need help
        135469: 08/10/02: thutt: Re: Low frequency clock generation - need help
            135477: 08/10/03: kadhiem_ayob: Re: Low frequency clock generation - need help
                135479: 08/10/03: thutt: Re: Low frequency clock generation - need help
                    135480: 08/10/03: kadhiem_ayob: Re: Low frequency clock generation - need help
                        135482: 08/10/04: thutt: Re: Low frequency clock generation - need help
                            135485: 08/10/04: kadhiem_ayob: Re: Low frequency clock generation - need help
        135538: 08/10/07: Brian Drummond: Re: Low frequency clock generation - need help
        135539: 08/10/07: Brian Drummond: Re: Low frequency clock generation - need help
    135425: 08/10/01: Svenn Are Bjerkem: Re: Low frequency clock generation - need help
    135445: 08/10/02: KJ: Re: Low frequency clock generation - need help
    135515: 08/10/06: Svenn Are Bjerkem: Re: Low frequency clock generation - need help
    135522: 08/10/06: KJ: Re: Low frequency clock generation - need help
    135533: 08/10/06: Svenn Are Bjerkem: Re: Low frequency clock generation - need help
135371: 08/09/29: Fred: Sending UDP packets over Ethernet
    135373: 08/09/29: Symon: Re: Sending UDP packets over Ethernet
    135383: 08/09/29: glen herrmannsfeldt: Re: Sending UDP packets over Ethernet
        135384: 08/09/29: Rick Jones: Re: Sending UDP packets over Ethernet
            135386: 08/09/29: glen herrmannsfeldt: Re: Sending UDP packets over Ethernet
            135388: 08/09/30: Vernon Schryver: Re: Sending UDP packets over Ethernet
                135401: 08/09/30: Vernon Schryver: Re: Sending UDP packets over Ethernet
                    135404: 08/09/30: glen herrmannsfeldt: Re: Sending UDP packets over Ethernet
                        135435: 08/10/01: Hansang Bae: Re: Sending UDP packets over Ethernet
                135402: 08/09/30: glen herrmannsfeldt: Re: Sending UDP packets over Ethernet
135372: 08/09/29: Benjamin Krill: Re: Sending UDP packets over Ethernet
    135374: 08/09/29: <cs_posting@hotmail.com>: Re: Sending UDP packets over Ethernet
        135375: 08/09/29: Fred: Re: Sending UDP packets over Ethernet
        135378: 08/09/29: Nico Coesel: Re: Sending UDP packets over Ethernet
    135376: 08/09/29: Benjamin Krill: Re: Sending UDP packets over Ethernet
    135377: 08/09/29: Nico Coesel: Re: Sending UDP packets over Ethernet
135381: 08/09/29: cwoodring: pciAutoConfiguration on MVME5500
    135434: 08/10/01: cwoodring: Re: pciAutoConfiguration on MVME5500
135382: 08/09/29: rao: Problem with mpmc(4.02.a) simulation -- DDR never initializes
    135385: 08/09/30: Brian Drummond: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
        135393: 08/09/30: Brian Drummond: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
            135432: 08/10/02: Brian Drummond: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
    135387: 08/09/29: rao: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
    135416: 08/10/01: Gabor: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
135390: 08/09/29: ekavirsrikanth@gmail.com: if data moves faster faster than the Clock....
    135391: 08/09/29: Thomas Stanka: Re: if data moves faster faster than the Clock....
    135395: 08/09/30: RCIngham: Re: if data moves faster faster than the Clock....
    135423: 08/10/01: Kolja Sulimma: Re: if data moves faster faster than the Clock....
135392: 08/09/30: Leon: $99 XMOS Dev kit
    135409: 08/10/01: James Harris: Re: $99 XMOS Dev kit
        135410: 08/10/01: 42Bastian Schick: Re: $99 XMOS Dev kit
    135413: 08/10/01: Leon: Re: $99 XMOS Dev kit
    135417: 08/10/01: Anthony Fremont: Re: $99 XMOS Dev kit
        135450: 08/10/02: Anthony Fremont: Re: $99 XMOS Dev kit
    135420: 08/10/01: Leon: Re: $99 XMOS Dev kit
    135422: 08/10/01: Leon: Re: $99 XMOS Dev kit
    135452: 08/10/02: Leon: Re: $99 XMOS Dev kit
135394: 08/09/30: msfarooq87@gmail.com: Interfacing DDR RAM
    135406: 08/10/01: Rob: Re: Interfacing DDR RAM
    135414: 08/10/01: Gabor: Re: Interfacing DDR RAM
    135436: 08/10/02: msfarooq87@gmail.com: Re: Interfacing DDR RAM
    135437: 08/10/02: msfarooq87@gmail.com: Re: Interfacing DDR RAM
    135438: 08/10/02: msfarooq87@gmail.com: Re: Interfacing DDR RAM
135396: 08/09/30: Heiner Litz: reasonable timing analysis without mapping design to IO
    135397: 08/09/30: KJ: Re: reasonable timing analysis without mapping design to IO
    135399: 08/09/30: Kevin Neilson: Re: reasonable timing analysis without mapping design to IO
        135440: 08/10/02: Markus: Re: reasonable timing analysis without mapping design to IO
    135403: 08/09/30: Andy: Re: reasonable timing analysis without mapping design to IO
    135408: 08/10/01: Heiner Litz: Re: reasonable timing analysis without mapping design to IO
    135455: 08/10/02: Heiner Litz: Re: reasonable timing analysis without mapping design to IO
    135456: 08/10/02: Mike Treseler: Re: reasonable timing analysis without mapping design to IO
    135699: 08/10/13: Heiner Litz: Re: reasonable timing analysis without mapping design to IO


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search