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Messages from 135150

Article: 135150
Subject: Re: interview questions ........
From: LittleAlex <alex.louie@email.com>
Date: Wed, 17 Sep 2008 23:24:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 17, 8:27 pm, "ekavirsrika...@gmail.com"
<ekavirsrika...@gmail.com> wrote:
> Hi all,
>
> 1. I have a not gate of TTL logic it has 20ns delay to the input i
> have given the square wave of 5nsec what will be the output. will the
> output be the square wave since the delayof the logic is more than the
> freq of operation doe the not gate work? and if it works upto what
> freq i can work...... for the same question what will be the output if
> the input is a sine wave instead of square wave.
>
> 2. max how many fanouts can we have for 2 input and gate. On what
> factors the fanout of a design depends. I think it depends on the
> voltage the output is driving.
>
> 3. for a single Dff (with D as input and Q as outpu and Clk as clock
> in) what will be the max Freqency it can operate.... i feel the min
> Time period req is only the tC-Q dealy (Propagation delay of the FF no
> need to consider the Tsetup time as only One FF is available for Time
> calculation).
>
> Thanks & Regards
> kil

Interesting questions, but sorry to say you're on the wrong track with
your answers.

In #1, you're supposed to be thinking about the output transistor
geometry.  (Delay is FROM the input, not TO the input, so you already
got off to a bad start.)

In #2, fanouts are on the OUTPUT, so knowing that it's a 2-input gate
is pointless.  And no, the voltage it's driving is not the answer.
(You got #1 wrong, so it's expected that you would get this one wrong
too.)

In #3, sorry, wrong.

Better luck on your next interview!

Hey, better luck on your next interview.

Article: 135151
Subject: Re: Moving to Altera from Xilinx
From: Mark McDougall <markm@vl.com.au>
Date: Thu, 18 Sep 2008 17:52:44 +1000
Links: << >>  << T >>  << A >>
Colin Paul Gloster wrote:

> Fortunately I started
> another webcase on exactly the same complaint and was assigned a
> different field application engineer, this time one who could
> think. Unfortunately this incompetence of Xilinx's adversely delayed
> me by weeks.

Unfortunately, that sort of problem is not restricted to Xilinx.

I had a question to do with Quartus service packs and patches. I opened a
service request with Altera and got a 'read the doco' response. I
re-iterated the question, trying to explain the doco was ambiguous. The
exchange went back and forth several times - the "robot" on the other end
was clearly not interested in finding the answer for me - merely throwing
more links at me to try to find the answer myself.

Eventually I mentioned it in passing to a local FAE, and he found the
answer for me almost immediately.

I think Xilinx/Altera farm out the web support to the same people that
handle telephone contract cold-calling and credit card enquiries.

I can just imagine some student/backpacker with a phone on his/her desk
and three lights on it...

* FPGA support
* Credit Card Query
* Phone bill query

:(

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 135152
Subject: Re: Is it possible to do incremental synthesis and placement?
From: Svenn Are Bjerkem <svenn.bjerkem@googlemail.com>
Date: Thu, 18 Sep 2008 00:59:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 2, 7:09 pm, Mike Treseler <mtrese...@gmail.com> wrote:
> Svenn Are Bjerkem wrote:
> > In a fairly large design I am doing some debugging on the system board
> > directly. When I discover a mistake and modify the vhdl code, the
> > whole design goes through synthesis and place-and-route. Many parts of
> > the design are never touched by my modifications, and I wonder if it
> > is possible to speed up the debug-modify-compile
>
> I finish the debug-modify-compile loop in simulation.
> Even though simulation requires significant time on the front end,
> debugging typos and changes is quick and straightforward.
>
>        -- Mike Treseler

I do most of the work up ahead in the simulator, but since the fpga is
communicating with external components via SPI, and there are many of
them, I have to verify in the lab that the code is actually working.
The timing of the external SPIs that we use are all different and I
discovered some timing errors that my simple model of the exernal
component didn't catch. Using partitions helped me speed up a little
bit, and I also discovered some pieces of code that need clean-up for
partitioning to work.

--
Svenn

Article: 135153
Subject: Re: Random Mask Generation on FPGAs
From: Lorenz Kolb <lorenz.kolb@uni-ulm.de>
Date: Thu, 18 Sep 2008 10:03:46 +0200
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> Klaus Niedermayer wrote:
>> Hi
>>
>> I would like to implement an encryption algorithm on my FPGA. The 
>> problem that I face here is that I need to generate each time I run
>> the algorithms 6 different random masks with 32-bits each. So I am 
>> wondering if anyone has a suggestion how to do that best? Until now I 
>> used LFSR to generate some single bits randomly, however now I should 
>> have in some way "independed" masks for 50.000 different runs.
> 
>  I saw recent news of a startup offering IP, but that's unlikely to be
> on real FPGA silicon yet :)
> 
>  All you can get on a FPGA is quasi-random, but you can push the
> 'quasi' to make attack harder.

Well not exactly, I'd say that if some microphone amplifier etc. is 
connected to the FPGA in some way (and no microphone is connected) the 
LSB of samples aquired (assuming some reasonable temperature-range) will 
be quite random (and equally distributed).
That could be quite a good source for initiallly feeding some shifting 
registers...

Regards,

Lorenz

Article: 135154
Subject: Re: Random Mask Generation on FPGAs
From: Alex Colvin <alexc@TheWorld.com>
Date: Thu, 18 Sep 2008 12:15:10 +0000 (UTC)
Links: << >>  << T >>  << A >>
>50 000 is really a small number, typical for a 16-bit LFSR. Nothing
>stops you from making the LFSR much longer, like 40 to 100 bits, which
>pushes the repetition out millions and trillions of times.
>Peter Alfke

Try the Mersenne Twistor for a really long LFSR-type sequence.

Note that such pseudo-randum number generators are not, in fact, random. 
And not suitable for use in cryptography.

-- 
	mac the naf

Article: 135155
Subject: Re: Random Mask Generation on FPGAs
From: "arsonperbuilding@gmail.com" <arsonperbuilding@gmail.com>
Date: Thu, 18 Sep 2008 05:35:22 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 17, 5:23=A0pm, Alex Freed <alex_n...@mirrow.com> wrote:

>
> The big question is: just random or secret?
>

Trying not to get too off topic, but has anyone tried the R300-SMT
from protego.se?  http://www.protego.se/r300a.htm
Its a hardware random number generator, with an SPI interface, so it
should be relatively straightforward to use with an FPGA.

-William Gibb

Article: 135156
Subject: Re: security system password by voice recognition commands
From: "RCIngham" <robert.ingham@gmail.com>
Date: Thu, 18 Sep 2008 09:22:40 -0500
Links: << >>  << T >>  << A >>
>HI everyone, i'm starting in the world of DSP, i have a project its a
>security system by voice patter recognition, and i have used
>pic16f877a in others projects, but it seems not enough for dsp, thou
>it has a ADC converter 10 bit - fmax = 20mhz, and i was thinking to
>combine with fpga spartan 3a (sending the digital signal to spartan
>and then maybe do some fft and filter processing ) ... but i friend of
>mine has a  TMS320 C6713 dsk and he told to me that is better with it,
>i new in all of this, i dont know how to use C6713 dsk ...so i need
>some advice, baby steps that i could take to do this project, please
>someone...
>

Have you tried asking on an appropriate forum, such as 'comp.dsp'?

http://www.dsprelated.com/compdsp.php


Article: 135157
Subject: Re: Moving to Altera from Xilinx
From: Jochen <JFrensch@harmanbecker.com>
Date: Thu, 18 Sep 2008 08:00:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
agreed 100%

http://www.callcentermovie.com/


Article: 135158
Subject: Re: Xilinx build system
From: Jochen <JFrensch@harmanbecker.com>
Date: Thu, 18 Sep 2008 08:19:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
yes !

using WinXP, apply settings explained by "LittleAlex" above, and
call the Xilinx-Tools as "General Schvantzkopf" does...

(That's how we do it)




Article: 135159
Subject: Re: security system password by voice recognition commands
From: John_H <newsgroup@johnhandwork.com>
Date: Thu, 18 Sep 2008 09:10:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 16, 1:55=A0pm, pemiliv <emr...@gmail.com> wrote:
> HI everyone, i'm starting in the world of DSP, i have a project its a
> security system by voice patter recognition, and i have used
> pic16f877a in others projects, but it seems not enough for dsp, thou
> it has a ADC converter 10 bit - fmax =3D 20mhz, and i was thinking to
> combine with fpga spartan 3a (sending the digital signal to spartan
> and then maybe do some fft and filter processing ) ... but i friend of
> mine has a =A0TMS320 C6713 dsk and he told to me that is better with it,
> i new in all of this, i dont know how to use C6713 dsk ...so i need
> some advice, baby steps that i could take to do this project, please
> someone...

It would be quicker to develop this algorithm for a DSP dsk rather
than an FPGA in my opinion.  It would possibly be cheaper to
manufacture in an FPGA especially if you need an FPGA anyway in the
overall design (Xilinx S3A-DSP, for instance).  The algorithm
development would probably be the bulk of your design "IP" yet going
to an FPGA would make transcribing that algorithm to the hardware -
even dedicated DSP48 blocks (or similar) - the largest part of your
development.

FPGAs are fantastic vehicles for getting fast custom logic into a
small footprint, both mechanical and cost.  But for a single project?
Not so helpful when the algorithm gets complex.  At least that's my
experience.

- John_H

Article: 135160
Subject: Clock Enable safe?
From: "t.bartzick@gmx.net" <t.bartzick@gmx.net>
Date: Thu, 18 Sep 2008 09:14:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello everybody!

As I could read, clock enables are pretty to avoid glitches on FFs or
counters. I hope, so does mine. My problem:

A counter, triggered by a master-clock is enabled by a signal which
might be "glitchy" on some occasions, because the enable itself is
generated by an edge-detector, which gets an asynchrounous signal for
detection:

Slow-Encoder-Signal -> FF-BASED-EDGE-DETECTOR -> CE of COUNTER.

What would be the behavior of the counter, if CE is too short and too
near to the clock? It would be o.k., if the counter simply wouldn't
count, but is it possible, that the counter sets into metastate?

Regards,

Thomas.

Article: 135161
Subject: Re: Clock Enable safe?
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 18 Sep 2008 17:45:55 +0100
Links: << >>  << T >>  << A >>

<t.bartzick@gmx.net> wrote in message 
news:b21088bb-cb93-4e0a-8789-934157d6aa62@k7g2000hsd.googlegroups.com...
>
> Slow-Encoder-Signal -> FF-BASED-EDGE-DETECTOR -> CE of COUNTER.
>
                          ^                           ^
----Is the clock for this ^ FF the same clock as this ^ counter?

Cheers, Syms.




Article: 135162
Subject: Re: Clock Enable safe?
From: "t.bartzick@gmx.net" <t.bartzick@gmx.net>
Date: Thu, 18 Sep 2008 09:52:25 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 18 Sep., 18:45, "Symon" <symon_bre...@hotmail.com> wrote:
> <t.bartz...@gmx.net> wrote in message
>
> news:b21088bb-cb93-4e0a-8789-934157d6aa62@k7g2000hsd.googlegroups.com...
>
> > Slow-Encoder-Signal -> FF-BASED-EDGE-DETECTOR -> CE of COUNTER.
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ^ =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ^
> ----Is the clock for this ^ FF the same clock as this ^ counter?
>
> Cheers, Syms.

Hi!

Yes, it is!

Thomas.

Article: 135163
Subject: Re: Moving to Altera from Xilinx
From: Dave Pollum <vze24h5m@verizon.net>
Date: Thu, 18 Sep 2008 10:30:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 18, 11:00=A0am, Jochen <JFren...@harmanbecker.com> wrote:
> agreed 100%
>
> http://www.callcentermovie.com/

R O F L !
I especially like the part where the call center guys had to call tech
support.

-Dave Pollum

Article: 135164
Subject: Re: Clock Enable safe?
From: "Mike Lewis" <someone@micrsoft.com>
Date: Thu, 18 Sep 2008 15:15:48 -0400
Links: << >>  << T >>  << A >>

<t.bartzick@gmx.net> wrote in message 
news:9094dad7-fac6-47f8-b672-a12038d33355@59g2000hsb.googlegroups.com...
On 18 Sep., 18:45, "Symon" <symon_bre...@hotmail.com> wrote:
> <t.bartz...@gmx.net> wrote in message
>
> news:b21088bb-cb93-4e0a-8789-934157d6aa62@k7g2000hsd.googlegroups.com...
>
> > Slow-Encoder-Signal -> FF-BASED-EDGE-DETECTOR -> CE of COUNTER.
>
> ^ ^
> ----Is the clock for this ^ FF the same clock as this ^ counter?
>
> Cheers, Syms.

Hi!

Yes, it is!

Thomas.



Then it won't be glitchy when it matters.
Mike 



Article: 135165
Subject: Re: Clock Enable safe?
From: KJ <kkjennings@sbcglobal.net>
Date: Thu, 18 Sep 2008 13:43:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 18, 3:15=A0pm, "Mike Lewis" <some...@micrsoft.com> wrote:
> <t.bartz...@gmx.net> wrote in message
>
> news:9094dad7-fac6-47f8-b672-a12038d33355@59g2000hsb.googlegroups.com...
> On 18 Sep., 18:45, "Symon" <symon_bre...@hotmail.com> wrote:
>
> > <t.bartz...@gmx.net> wrote in message
>
> >news:b21088bb-cb93-4e0a-8789-934157d6aa62@k7g2000hsd.googlegroups.com...
>
> > > Slow-Encoder-Signal -> FF-BASED-EDGE-DETECTOR -> CE of COUNTER.
>
> > ^ ^
> > ----Is the clock for this ^ FF the same clock as this ^ counter?
>
> > Cheers, Syms.
>
> Hi!
>
> Yes, it is!
>
> Thomas.
>
> Then it won't be glitchy when it matters.
> Mike

That would only be true if the output CE of 'FF-BASED-EDGE-DETECTOR'
is the output of a flip flop.  The OP was wondering what would happen
if "if CE is too short and too near to the clock".  The only way to
get that situation would be if CE is NOT the output of a flip flop (or
a metastable event).  While he also said that the same clock is used
to clock the ''FF-BASED-EDGE-DETECTOR' it doesn't necessarily follow
that the final output is a flop.  If that output is from logic that
depends on an asynchronous input than all bets are off.

If the output is a flop, then perhaps the OP needs to explain just
what situation he envisions where the output of such a flop could ever
be 'too short' or 'too near the clock' since that would make
absolutely no sense.

KJ

Article: 135166
Subject: Re: Clock Enable safe?
From: "t.bartzick@gmx.net" <t.bartzick@gmx.net>
Date: Thu, 18 Sep 2008 14:56:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi!

First: Thank you all for fast answers!

The edge-detection is done via two D-FFs connected serially and by an
AND-gate with one negated input,
so the output of the first FF goes into the non-negated and the output
of the second into the negated.
The corresponding VHDL code is as follows:

proc_FF1 : process (osc)
begin
   if (rising_edge(osc)) then
      ff1_out <=3D ENCODER_SIGNAL;
   end if;
end process;

proc_FF2 : process (osc)
begin
   if (rising_edge(osc)) then
      ff2_out <=3D ff1_out;
   end if;
end process;

edge_detected_pulse <=3D ff1_out and (not ff2_out);

proc_CNTR : process (osc)
begin
   if (rising_edge(osc)) then
      if (R =3D '1') then
         cntr <=3D (others =3D> '0');
      else if (edge_detected_pulse =3D '1') then
         cntr <=3D cntr + 1;
      end if;
   end if;
end process;

So as you can see, 'edge_detected_pulse' is my 'CE' for the counter.

Please be free to comment!
Thanks!

Thomas.


KJ schrieb:
> On Sep 18, 3:15=EF=BF=BDpm, "Mike Lewis" <some...@micrsoft.com> wrote:
> > <t.bartz...@gmx.net> wrote in message
> >
> > news:9094dad7-fac6-47f8-b672-a12038d33355@59g2000hsb.googlegroups.com..=
.
> > On 18 Sep., 18:45, "Symon" <symon_bre...@hotmail.com> wrote:
> >
> > > <t.bartz...@gmx.net> wrote in message
> >
> > >news:b21088bb-cb93-4e0a-8789-934157d6aa62@k7g2000hsd.googlegroups.com.=
..
> >
> > > > Slow-Encoder-Signal -> FF-BASED-EDGE-DETECTOR -> CE of COUNTER.
> >
> > > ^ ^
> > > ----Is the clock for this ^ FF the same clock as this ^ counter?
> >
> > > Cheers, Syms.
> >
> > Hi!
> >
> > Yes, it is!
> >
> > Thomas.
> >
> > Then it won't be glitchy when it matters.
> > Mike
>
> That would only be true if the output CE of 'FF-BASED-EDGE-DETECTOR'
> is the output of a flip flop.  The OP was wondering what would happen
> if "if CE is too short and too near to the clock".  The only way to
> get that situation would be if CE is NOT the output of a flip flop (or
> a metastable event).  While he also said that the same clock is used
> to clock the ''FF-BASED-EDGE-DETECTOR' it doesn't necessarily follow
> that the final output is a flop.  If that output is from logic that
> depends on an asynchronous input than all bets are off.
>
> If the output is a flop, then perhaps the OP needs to explain just
> what situation he envisions where the output of such a flop could ever
> be 'too short' or 'too near the clock' since that would make
> absolutely no sense.
>
> KJ

Article: 135167
Subject: Re: Moving to Altera from Xilinx
From: Mark McDougall <markm@vl.com.au>
Date: Fri, 19 Sep 2008 09:38:08 +1000
Links: << >>  << T >>  << A >>
Jochen wrote:

> http://www.callcentermovie.com/

LOL! Yeah, that about nails it! :)

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 135168
Subject: Re: Clock Enable safe?
From: Thomas Stanka <usenet_nospam_valid@stanka-web.de>
Date: Thu, 18 Sep 2008 22:25:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
first of all, try to avoid a full quote, as long as not necessary.

On 18 Sep., 23:56, "t.bartz...@gmx.net" <t.bartz...@gmx.net> wrote:
> So as you can see, 'edge_detected_pulse' is my 'CE' for the counter.
>
> Please be free to comment!

Your enable could be considered glitchfree with respect to the next FF
stage iff you use the same clock and handle the clock skew properly.
In fact it is no special glitch problem, but you have an enable signal
that is valid at the usual timing points (between signal delay on
longest path until signal delay on fastest path from all inputs to the
end).
You should always inspect the timing from primary inputs or FF outputs
to the input of the next ff stage with static timing analyses.

For an enable with high fan out it is always a good idea to use only
one FF as source for this enable.

regards Thomas

Article: 135169
Subject: Re: Clock Enable safe?
From: PatC <pato@REMOVETHISpatocarr.com>
Date: Fri, 19 Sep 2008 00:22:04 -0700
Links: << >>  << T >>  << A >>
t.bartzick@gmx.net wrote:
> The edge-detection is done via two D-FFs connected serially and by an
> AND-gate with one negated input,
> so the output of the first FF goes into the non-negated and the output
> of the second into the negated.
> The corresponding VHDL code is as follows:

   If you want to be absolutely sure that this circuit won't go 
metastable, I'd use three FFs instead of two, and use the last two to 
generate the enable. The first FF may go metastable, but the other two 
will be safe.

proc_FF1 : process (osc)
begin
    if (rising_edge(osc)) then
       ff1_out <= ENCODER_SIGNAL;
       ff2_demet <= ff1_out;
       ff3_demet <= ff2_demet;
    end if;
end process;

edge_detected_pulse <= ff2_demet and (not ff3_demet);

> proc_CNTR : process (osc)
> begin
>    if (rising_edge(osc)) then
>       if (R = '1') then
>          cntr <= (others => '0');
>       else if (edge_detected_pulse = '1') then
>          cntr <= cntr + 1;
>       end if;
>    end if;
> end process;
> 
> So as you can see, 'edge_detected_pulse' is my 'CE' for the counter.
> 
> Please be free to comment!
> Thanks!
> 
> Thomas.
> 
> 
> KJ schrieb:
>> On Sep 18, 3:15�pm, "Mike Lewis" <some...@micrsoft.com> wrote:
>>> <t.bartz...@gmx.net> wrote in message
>>>
>>> news:9094dad7-fac6-47f8-b672-a12038d33355@59g2000hsb.googlegroups.com...
>>> On 18 Sep., 18:45, "Symon" <symon_bre...@hotmail.com> wrote:
>>>
>>>> <t.bartz...@gmx.net> wrote in message
>>>> news:b21088bb-cb93-4e0a-8789-934157d6aa62@k7g2000hsd.googlegroups.com...
>>>>> Slow-Encoder-Signal -> FF-BASED-EDGE-DETECTOR -> CE of COUNTER.
>>>> ^ ^
>>>> ----Is the clock for this ^ FF the same clock as this ^ counter?
>>>> Cheers, Syms.
>>> Hi!
>>>
>>> Yes, it is!
>>>
>>> Thomas.
>>>
>>> Then it won't be glitchy when it matters.
>>> Mike
>> That would only be true if the output CE of 'FF-BASED-EDGE-DETECTOR'
>> is the output of a flip flop.  The OP was wondering what would happen
>> if "if CE is too short and too near to the clock".  The only way to
>> get that situation would be if CE is NOT the output of a flip flop (or
>> a metastable event).  While he also said that the same clock is used
>> to clock the ''FF-BASED-EDGE-DETECTOR' it doesn't necessarily follow
>> that the final output is a flop.  If that output is from logic that
>> depends on an asynchronous input than all bets are off.
>>
>> If the output is a flop, then perhaps the OP needs to explain just
>> what situation he envisions where the output of such a flop could ever
>> be 'too short' or 'too near the clock' since that would make
>> absolutely no sense.
>>
>> KJ

Article: 135170
Subject: Re: Clock Enable safe?
From: "t.bartzick@gmx.net" <t.bartzick@gmx.net>
Date: Fri, 19 Sep 2008 01:10:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 19, 9:22=A0am, PatC <p...@REMOVETHISpatocarr.com> wrote:
> t.bartz...@gmx.net wrote:
> > The edge-detection is done via two D-FFs connected serially and by an
> > AND-gate with one negated input,
> > so the output of the first FF goes into the non-negated and the output
> > of the second into the negated.
> > The corresponding VHDL code is as follows:
>
> =A0 =A0If you want to be absolutely sure that this circuit won't go
> metastable, I'd use three FFs instead of two, and use the last two to
> generate the enable. The first FF may go metastable, but the other two
> will be safe.
>
> proc_FF1 : process (osc)
> begin
> =A0 =A0 if (rising_edge(osc)) then
> =A0 =A0 =A0 =A0ff1_out <=3D ENCODER_SIGNAL;
> =A0 =A0 =A0 =A0ff2_demet <=3D ff1_out;
> =A0 =A0 =A0 =A0ff3_demet <=3D ff2_demet;
> =A0 =A0 end if;
> end process;
>
> edge_detected_pulse <=3D ff2_demet and (not ff3_demet);
>
>

Hi!

That's what I've feared!
Ergo: My actual design in fact contains metastability of a certain
probability. I've also thought about the idea of insertion of a
further FFs but I've wanted to get shure... Thank you for support!

Thomas.

Article: 135171
Subject: Help~ How to develope with FPGA board?
From: KJ <lkjrsy@gmail.com>
Date: Fri, 19 Sep 2008 01:22:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello everyone.

I'm a very beginner wiht FPGA board like following.
http://hitechglobal.com/catalog/product_info.php?cPath=1&products_id=199

This board contains Virtex5 FXT. I think that I need a ISE 10.1 to
support it.
Following is what I'm think of the development procedure.

(1) Make VHDL codes for Virtex5 FXT in ISE 10.1 (?)
(2) Synthesis/Translate/Palce&Part and Simulation
(3) Download bitstream into the Chip (?)
(4) Testing

In (1), someone told me that I don't need ISE and usually if I
purchase the FPGA board, software comes along with that. is this
right?

In (3), How to configure the chip? I have never done this before.
Could you explanin the procedure of configuration?
                                                 This board has the
flash memory for FPGA configuration and storage.
                                                  But, I don't know
how to use it.

Article: 135172
Subject: Re: Help~ How to develope with FPGA board?
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: Fri, 19 Sep 2008 10:40:35 +0100
Links: << >>  << T >>  << A >>
On Fri, 19 Sep 2008, KJ (not the veteran Kevin Jennings) wrote:

|------------------------------------------------------------------------|
|"I'm a very beginner wiht FPGA board like following.                    |
|http://hitechglobal.com/catalog/product_info.php?cPath=1&products_id=199|
|                                                                        |
|This board contains Virtex5 FXT. I think that I need a ISE 10.1 to      |
|support it."                                                            |
|------------------------------------------------------------------------|

Hello,

Instead of ISE, the gratis WebPACK program from
WWW.Xilinx.com/ise/logic_design_prod/webpack.htm
should be sufficient according to that Xilinx webpage and
WWW.Xilinx.com/onlinestore/silicon/online_store_v5.htm
.

|------------------------------------------------------------------------|
|"Following is what I'm think of the development procedure.              |
|                                                                        |
|(1) Make VHDL codes for Virtex5 FXT in ISE 10.1 (?)                     |
|(2) Synthesis/Translate/Palce&Part and Simulation                       |
|(3) Download bitstream into the Chip (?)                                |
|(4) Testing                                                             |
|                                                                        |
|In (1), someone told me that I don't need ISE and usually if I          |
|purchase the FPGA board, software comes along with that. is this        |
|right?                                                                  |
|                                                                        |
|In (3), How to configure the chip? I have never done this before.       |
|Could you explanin the procedure of configuration?                      |
|                                                 This board has the     |
|flash memory for FPGA configuration and storage.                        |
|                                                  But, I don't know     |
|how to use it."                                                         |
|------------------------------------------------------------------------|

Read the documentation which comes with the board; and the
documentation from the Xilinx website.

Regards,
Colin Paul Gloster

Article: 135173
Subject: Re: Moving to Altera from Xilinx
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: Fri, 19 Sep 2008 10:45:15 +0100
Links: << >>  << T >>  << A >>
On Thu, 18 Sep 2008, Mark McDougall wrote:

|-------------------------------------------------------------------------|
|"Colin Paul Gloster wrote:                                               |
|                                                                         |
|> Fortunately I started                                                  |
|> another webcase on exactly the same complaint and was assigned a       |
|> different field application engineer, this time one who could          |
|> think. Unfortunately this incompetence of Xilinx's adversely delayed   |
|> me by weeks.                                                           |
|                                                                         |
|Unfortunately, that sort of problem is not restricted to Xilinx.         |
|                                                                         |
|[..]"                                                                    |
|-------------------------------------------------------------------------|

True, but I have not experienced this problem with Aeroflex.

Article: 135174
Subject: usb on a spartan
From: "maxascent" <maxascent@yahoo.co.uk>
Date: Fri, 19 Sep 2008 05:57:30 -0500
Links: << >>  << T >>  << A >>

Hi

I would like to have usb on a spartan 3 device. I would like the high
speed version (480 Mb/s). What I would like to do is have all the logic
internal to the fpga (controller and phy) and just have an external ic to
do the voltage conversion. Does anyone know of an external ic that supports
the high speed spec. To be clear I dont want an external phy just a level
shifting ic.

Cheers

Jon



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