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Threads Starting Jul 2005

86617: 05/07/01: Keith Williams: Cyclone Board with // LVDS lines
    86657: 05/07/02: Rob: Re: Cyclone Board with // LVDS lines
86632: 05/07/01: des00: Avnet V4 - XC4VLX25
    86635: 05/07/01: Antti Lukats: Re: Avnet V4 - XC4VLX25
86634: 05/07/01: amko: interpolation in FPGA
    86636: 05/07/01: jerzy.gbur@gmail.com: Re: interpolation in FPGA
    86677: 05/07/03: <peter@geckoaudio.com>: Re: interpolation in FPGA
    86747: 05/07/05: jimgeorge at gmail dot com: Re: interpolation in FPGA
86638: 05/07/01: damidar: re:Problem for xilinx!!!
86641: 05/07/01: geoffrey wall: vhdl source code cross reference tool
    86649: 05/07/01: Jim Wu: Re: vhdl source code cross reference tool
    86682: 05/07/04: Martin Thompson: Re: vhdl source code cross reference tool
86644: 05/07/01: Tony: Foundation 3.1 in WinXP machine Problems!
    86645: 05/07/01: Falk Brunner: Re: Foundation 3.1 in WinXP machine Problems!
    86646: 05/07/01: Gabor: Re: Foundation 3.1 in WinXP machine Problems!
    86655: 05/07/01: Tony: Re: Foundation 3.1 in WinXP machine Problems!
    86660: 05/07/03: fred: Re: Foundation 3.1 in WinXP machine Problems!
86650: 05/07/01: Doug Jones: FPGA system RAM
    86651: 05/07/01: Peter Alfke: Re: FPGA system RAM
    86652: 05/07/01: Doug Jones: Re: FPGA system RAM
    86653: 05/07/01: Peter Alfke: Re: FPGA system RAM
    86654: 05/07/01: Doug Jones: Re: FPGA system RAM
    86656: 05/07/01: Peter Alfke: Re: FPGA system RAM
86658: 05/07/02: damidar: re:Problem for xilinx!!!
86659: 05/07/02: Peter Alfke: Re: Problem for xilinx!!!
86665: 05/07/03: Sidney Cadot: Xilinx: XST synchronous FIFO using BRAMs
    86666: 05/07/03: Peter Alfke: Re: Xilinx: XST synchronous FIFO using BRAMs
    86667: 05/07/03: Mike Treseler: Re: Xilinx: XST synchronous FIFO using BRAMs
        86672: 05/07/03: Mike Treseler: Re: Xilinx: XST synchronous FIFO using BRAMs
    86668: 05/07/03: <sidney@jigsaw.nl>: Re: Xilinx: XST synchronous FIFO using BRAMs
    86669: 05/07/03: <sidney@jigsaw.nl>: Re: Xilinx: XST synchronous FIFO using BRAMs
    86670: 05/07/03: Peter Alfke: Re: Xilinx: XST synchronous FIFO using BRAMs
    86671: 05/07/03: <sidney@jigsaw.nl>: Re: Xilinx: XST synchronous FIFO using BRAMs
    86673: 05/07/03: Peter Alfke: Re: Xilinx: XST synchronous FIFO using BRAMs
    86685: 05/07/04: =?ISO-8859-1?Q?G=F6ran_Bilski?=: Re: Xilinx: XST synchronous FIFO using BRAMs
    86690: 05/07/05: Unbeliever: Re: Xilinx: XST synchronous FIFO using BRAMs
    86693: 05/07/05: Alvin Andries: Re: Xilinx: XST synchronous FIFO using BRAMs
        86694: 05/07/05: Alvin Andries: Re: Xilinx: XST synchronous FIFO using BRAMs
            86701: 05/07/05: Alvin Andries: Re: Xilinx: XST synchronous FIFO using BRAMs
        86699: 05/07/05: Alvin Andries: Re: Xilinx: XST synchronous FIFO using BRAMs
            86739: 05/07/05: Alvin Andries: Re: Xilinx: XST synchronous FIFO using BRAMs
            86759: 05/07/06: Martin Thompson: Re: Xilinx: XST synchronous FIFO using BRAMs
    86695: 05/07/04: <sidney@jigsaw.nl>: Re: Xilinx: XST synchronous FIFO using BRAMs
    86696: 05/07/04: <sidney@jigsaw.nl>: Re: Xilinx: XST synchronous FIFO using BRAMs
    86697: 05/07/04: <sidney@jigsaw.nl>: Re: Xilinx: XST synchronous FIFO using BRAMs
    86698: 05/07/04: <sidney@jigsaw.nl>: Re: Xilinx: XST synchronous FIFO using BRAMs
    86704: 05/07/04: Peter Alfke: Re: Xilinx: XST synchronous FIFO using BRAMs
    86711: 05/07/05: <sidney@jigsaw.nl>: Re: Xilinx: XST synchronous FIFO using BRAMs
    86724: 05/07/05: Peter Alfke: Re: Xilinx: XST synchronous FIFO using BRAMs
    86726: 05/07/05: Vladislav Muravin: Re: Xilinx: XST synchronous FIFO using BRAMs
    86732: 05/07/05: Andy Peters: Re: Xilinx: XST synchronous FIFO using BRAMs
    86740: 05/07/05: Peter Alfke: Re: Xilinx: XST synchronous FIFO using BRAMs
86674: 05/07/03: damidar: Re: Problem for xilinx!!!
86676: 05/07/03: <peter@geckoaudio.com>: ModelSim Timing Simulation Signal Names
    86681: 05/07/04: Jonathan Bromley: Re: ModelSim Timing Simulation Signal Names
        86705: 05/07/04: Phil Hays: Re: ModelSim Timing Simulation Signal Names
            86750: 05/07/05: Phil Hays: Re: ModelSim Timing Simulation Signal Names
    86703: 05/07/04: PeterC: Re: ModelSim Timing Simulation Signal Names
    86706: 05/07/04: PeterC: Re: ModelSim Timing Simulation Signal Names
    86741: 05/07/05: Brian Philofsky: Re: ModelSim Timing Simulation Signal Names
    86806: 05/07/06: PeterC: Re: ModelSim Timing Simulation Signal Names
86678: 05/07/03: im.de: xapp 482 and add custom function
86680: 05/07/04: virtex II pro ddr controller(xapp608): DDR controller : problems about burst access
86687: 05/07/04: schellho: Xilinx IOB flop mapping vs. -bp switch
    86781: 05/07/06: Bret Wade: Re: Xilinx IOB flop mapping vs. -bp switch
86689: 05/07/04: <david@fpgaworld.com>: Call for FPGAworld 2005
86691: 05/07/04: Allan Willcox: EDK 6.3, Xilinx ML40x ML402, XBD files
    86819: 05/07/07: <abgoyal@gmail.com>: Re: EDK 6.3, Xilinx ML40x ML402, XBD files
        86824: 05/07/07: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: EDK 6.3, Xilinx ML40x ML402, XBD files
    86892: 05/07/08: Allan Willcox: Re: EDK 6.3, Xilinx ML40x ML402, XBD files
86692: 05/07/04: Jedi: nios2 toolchain sources...
    86702: 05/07/05: Ben Twijnstra: Re: nios2 toolchain sources...
        86714: 05/07/05: Jedi: Re: nios2 toolchain sources...
            86720: 05/07/05: Jedi: Re: nios2 toolchain sources...
                86721: 05/07/05: Antti Lukats: Re: nios2 toolchain sources...
                    86728: 05/07/05: Ben Twijnstra: Re: nios2 toolchain sources...
                        86729: 05/07/05: Jedi: Re: nios2 toolchain sources...
    86713: 05/07/05: Jon Beniston: Re: nios2 toolchain sources...
    86754: 05/07/06: Jon Beniston: Re: nios2 toolchain sources...
86707: 05/07/04: jai.dhar@gmail.com: Ethernet FPGA development board
    86746: 05/07/05: jimgeorge at gmail dot com: Re: Ethernet FPGA development board
    86771: 05/07/06: jai.dhar@gmail.com: Re: Ethernet FPGA development board
86709: 05/07/04: Peter Alfke: Re: Problem for xilinx!!!
86712: 05/07/05: Sven: Virtex-2 Pro: Configuration Frames
    87127: 05/07/15: praetorian: Re: Virtex-2 Pro: Configuration Frames
        88335: 05/08/16: John Williams: Re: Virtex-2 Pro: Configuration Frames
86717: 05/07/05: Marco: Connecting ADC to Opb_Spi core
    86718: 05/07/05: Antti Lukats: Re: Connecting ADC to Opb_Spi core
        86722: 05/07/05: Marco: Re: Connecting ADC to Opb_Spi core
            86723: 05/07/05: Antti Lukats: Re: Connecting ADC to Opb_Spi core
                86730: 05/07/05: Antti Lukats: Re: Connecting ADC to Opb_Spi core
                    86733: 05/07/05: Marco: Re: Connecting ADC to Opb_Spi core
                86731: 05/07/05: Marco: Re: Connecting ADC to Opb_Spi core
            86727: 05/07/05: Sylvain Munaut: Re: Connecting ADC to Opb_Spi core
86719: 05/07/05: greenplanet: PS/2 interface
    86735: 05/07/05: =?iso-8859-1?B?SGVybuFuIFPhbmNoZXo=?=: Re: PS/2 interface
        86867: 05/07/07: Dave Vanden Bout: Re: PS/2 interface
    86811: 05/07/06: greenplanet: Re: PS/2 interface
    86873: 05/07/07: greenplanet: Re: PS/2 interface
86725: 05/07/05: junaid: VPR fundaes
    86763: 05/07/06: Paul Leventis (at home): Re: VPR fundaes
    87149: 05/07/17: Vaughn Betz: Re: VPR fundaes
    87158: 05/07/18: junaid: Re: VPR fundaes
86734: 05/07/05: Antti Lukats: Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion problem)
    86921: 05/07/09: elcielo: re:Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion pro
        86924: 05/07/09: Antti Lukats: Re: re:Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion pro
86742: 05/07/05: ernie: Stratix open-drain pins
    86743: 05/07/06: Sylvain Munaut: Re: Stratix open-drain pins
    86745: 05/07/06: Rob: Re: Stratix open-drain pins
        86786: 05/07/06: Mike Treseler: Re: Stratix open-drain pins
    86784: 05/07/06: ernie: Re: Stratix open-drain pins
    86789: 05/07/06: ernie: Re: Stratix open-drain pins
86744: 05/07/05: Brad Smallridge: VHDL Clock Domains
    86768: 05/07/06: Vladislav Muravin: Re: VHDL Clock Domains
        86779: 05/07/06: Mike Treseler: Re: VHDL Clock Domains
        86780: 05/07/06: Duane Clark: Re: VHDL Clock Domains
            86791: 05/07/06: Duane Clark: Re: VHDL Clock Domains
    86769: 05/07/06: <ALuPin@web.de>: Re: VHDL Clock Domains
    86829: 05/07/07: Paul Leventis (at home): Re: VHDL Clock Domains
86748: 05/07/05: Dave: fastest FPGA speed grade?
    86752: 05/07/06: Antti Lukats: Re: fastest FPGA speed grade?
    86753: 05/07/06: Jon Beniston: Re: fastest FPGA speed grade?
    86762: 05/07/06: Paul Leventis (at home): Re: fastest FPGA speed grade?
        86777: 05/07/06: Nicholas Weaver: Re: fastest FPGA speed grade?
        86787: 05/07/06: Falk Brunner: Re: fastest FPGA speed grade?
            86788: 05/07/06: Nicholas Weaver: Re: fastest FPGA speed grade?
                86793: 05/07/06: Falk Brunner: Re: fastest FPGA speed grade?
        86866: 05/07/07: Ray Andraka: Re: fastest FPGA speed grade?
            86899: 05/07/08: Falk Brunner: Re: fastest FPGA speed grade?
    86767: 05/07/06: Jon Beniston: Re: fastest FPGA speed grade?
    86776: 05/07/06: Austin Lesea: Re: fastest FPGA speed grade? Not the only measure, but ...
        86814: 05/07/07: Martin Thompson: Re: fastest FPGA speed grade? Not the only measure, but ...
            86851: 05/07/07: Austin Lesea: Re: fastest FPGA speed grade? Not the only measure, but ...
            86872: 05/07/07: sean: Re: fastest FPGA speed grade? Not the only measure, but ...
                86877: 05/07/07: Paul Leventis (at home): Re: fastest FPGA speed grade? Not the only measure, but ...
    86782: 05/07/06: Peter Alfke: Re: fastest FPGA speed grade?
    86800: 05/07/06: B. Joshua Rosen: Re: fastest FPGA speed grade?
    86804: 05/07/06: Dave: Re: fastest FPGA speed grade?
    86903: 05/07/08: Andy Peters: Re: fastest FPGA speed grade?
86749: 05/07/05: Nju Njoroge: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
    86751: 05/07/06: <ALuPin@web.de>: Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
    86775: 05/07/06: 00andiweb.de: Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
    86778: 05/07/06: Duane Clark: Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
    86790: 05/07/06: Nju Njoroge: Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
    86803: 05/07/06: Nju Njoroge: Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
86755: 05/07/06: Joey: PowerPC interrupt
    86773: 05/07/06: 00andiweb.de: Re: PowerPC interrupt
        86783: 05/07/06: Joey: Re: PowerPC interrupt
    86820: 05/07/07: Andi: Re: PowerPC interrupt
        86833: 05/07/07: Joey: Re: PowerPC interrupt
86756: 05/07/06: Joey: Program from external memory
    86757: 05/07/06: Joey: Re: Program from external memory
    86758: 05/07/06: Andi: Re: Program from external memory
        86766: 05/07/06: Joey: Re: Program from external memory
        86785: 05/07/06: Peter Ryser: Re: Program from external memory
            86823: 05/07/07: Joey: Re: Program from external memory
            86888: 05/07/08: Joey: Re: Program from external memory
    86774: 05/07/06: 00andiweb.de: Re: Program from external memory
86760: 05/07/06: hata: virtex4 evaluation board
    86761: 05/07/06: Antti Lukats: Re: virtex4 evaluation board
    86764: 05/07/06: hata: Re: virtex4 evaluation board
86770: 05/07/06: vssumesh: Triggering and reseting FF
    86792: 05/07/06: Vladislav Muravin: Re: Triggering and reseting FF
    87746: 05/07/30: vssumesh: Re: Triggering and reseting FF
86772: 05/07/06: stbcasa: Spartan II 2s200 PCI Board
    86795: 05/07/06: Eric Smith: Re: Spartan II 2s200 PCI Board
    86796: 05/07/06: Gabor: Re: Spartan II 2s200 PCI Board
86794: 05/07/06: RobJ: Spartan3 pci above 33MHz
    86832: 05/07/07: colin: Re: Spartan3 pci above 33MHz
86797: 05/07/06: Sewook Wee: Cheking out Linux Kernel Source
    86805: 05/07/06: praetorian: Re: Cheking out Linux Kernel Source
    86810: 05/07/06: Peter Ryser: Re: Cheking out Linux Kernel Source
86798: 05/07/06: amko: PC104 (ISA) bus in FPGA (Spatan 2E)
    86799: 05/07/06: Gabor: Re: PC104 (ISA) bus in FPGA (Spatan 2E)
    86812: 05/07/07: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: PC104 (ISA) bus in FPGA (Spatan 2E)
    86849: 05/07/07: Peter Wallace: Re: PC104 (ISA) bus in FPGA (Spatan 2E)
86801: 05/07/06: Adam Megacz: for sale: two spartan-3 dev boards, $50 each (normally $100)
86802: 05/07/06: azam: Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?
    86835: 05/07/07: Jim Wu: Re: Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?
    86852: 05/07/07: Austin Lesea: Re: Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?
86807: 05/07/06: Joel Kolstad: Actel vs. Xilinx and Altera
    86843: 05/07/07: Ed McGettigan: Re: Actel vs. Xilinx and Altera
    86887: 05/07/08: Hans: Re: Actel vs. Xilinx and Altera
        86900: 05/07/08: Joel Kolstad: Re: Actel vs. Xilinx and Altera
86813: 05/07/07: Giox: about fast adder
    86825: 05/07/07: Sylvain Munaut: Re: about fast adder
        86834: 05/07/07: John_H: Re: about fast adder
        86841: 05/07/07: Sylvain Munaut: Re: about fast adder
        86883: 05/07/07: Marko: Re: about fast adder
    86826: 05/07/07: Giox: Re: about fast adder
    86827: 05/07/07: des00: Re: about fast adder
    86831: 05/07/07: Giox: Re: about fast adder
    86836: 05/07/07: des00: Re: about fast adder
    86839: 05/07/07: Giox: Re: about fast adder
    86842: 05/07/07: Giox: Re: about fast adder
    86847: 05/07/07: JJ: Re: about fast adder
86817: 05/07/07: <ALuPin@web.de>: Problems with Timing Simulation
    86822: 05/07/07: Ben Jones: Re: Problems with Timing Simulation
        86838: 05/07/07: Ben Jones: Re: Problems with Timing Simulation
        86840: 05/07/07: Ben Jones: Re: Problems with Timing Simulation
    86828: 05/07/07: <ALuPin@web.de>: Re: Problems with Timing Simulation
    86837: 05/07/07: <ALuPin@web.de>: Re: Problems with Timing Simulation
    86886: 05/07/08: <ALuPin@web.de>: Re: Problems with Timing Simulation
86818: 05/07/07: vssumesh: SELV - power supply specification
    86821: 05/07/07: fred: Re: SELV - power supply specification
    86844: 05/07/07: vssumesh: Re: SELV - power supply specification
    86845: 05/07/07: fred: Re: SELV - power supply specification
    86869: 05/07/08: David R Brooks: Re: SELV - power supply specification
86830: 05/07/07: katherine: aurora reliability
    86846: 05/07/07: Duane Clark: Re: aurora reliability
        86855: 05/07/07: Austin Lesea: Re: aurora reliability
            86894: 05/07/08: Martin Thompson: Re: aurora reliability
    86850: 05/07/07: katherine: Re: aurora reliability
    86896: 05/07/08: katherine: Re: aurora reliability
86848: 05/07/07: Elektro: Bit serial, book, other info???
    86859: 05/07/07: Philip Freidin: Re: Bit serial, book, other info???
    86860: 05/07/07: Ray Andraka: Re: Bit serial, book, other info???
        86904: 05/07/08: Elektro: Re: Bit serial, book, other info???
            86923: 05/07/09: temp: Re: Bit serial, book, other info???
86853: 05/07/07: Kaalia Anthony: QAM 64 implementation on a FPGA board
86856: 05/07/07: Pistony2k: Verilog Coding Guidelines
86857: 05/07/07: jjlindula@hotmail.com: Max Sample Rate for Signal Tap in Altera Quartus?
    86868: 05/07/07: Peter Sommerfeld: Re: Max Sample Rate for Signal Tap in Altera Quartus?
        86909: 05/07/08: Thomas Entner: Re: Max Sample Rate for Signal Tap in Altera Quartus?
            87148: 05/07/17: Vaughn Betz: Re: Max Sample Rate for Signal Tap in Altera Quartus?
    86902: 05/07/08: jjlindula@hotmail.com: Re: Max Sample Rate for Signal Tap in Altera Quartus?
    86941: 05/07/10: jjlindula@hotmail.com: Re: Max Sample Rate for Signal Tap in Altera Quartus?
86861: 05/07/07: <bgaughan@airnetcom.com>: Resampling in FPGA with irrational or large rational ratios
    86864: 05/07/07: Greg Berchin: Re: Resampling in FPGA with irrational or large rational ratios
86870: 05/07/07: Nju Njoroge: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
    86871: 05/07/07: Jason Zheng: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3
    86874: 05/07/07: Nju Njoroge: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
    86875: 05/07/07: Nju: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
    86882: 05/07/07: Marko: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
    86965: 05/07/11: Andy Peters: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
    87004: 05/07/12: Andy Peters: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
86878: 05/07/08: Jim Granville: Stacked Die devices
86879: 05/07/07: <stud_lang_jap@yahoo.com>: Ray Andraka when will your book be on store???
    86880: 05/07/08: Ray Andraka: Re: Ray Andraka when will your book be on store???
        86905: 05/07/08: Yttrium: Re: Ray Andraka when will your book be on store???
    86881: 05/07/07: <stud_lang_jap@yahoo.com>: Re: Ray Andraka when will your book be on store???
86884: 05/07/07: Sven: Xilinx V2Pro reconfiguration
86885: 05/07/07: <shuo.huang@fibre.com>: Possible bug in Vertex-4 Rocket-IO?
    86897: 05/07/08: Marko: Re: Possible bug in Vertex-4 Rocket-IO?
        86919: 05/07/08: Marko: Re: Possible bug in Vertex-4 Rocket-IO?
            86929: 05/07/09: Marko: Re: Possible bug in Vertex-4 Rocket-IO?
                86943: 05/07/10: Marko: Re: Possible bug in Vertex-4 Rocket-IO?
    86901: 05/07/08: <shuo.huang@fibre.com>: Re: Possible bug in Vertex-4 Rocket-IO?
    86926: 05/07/09: <shuo.huang@fibre.com>: Re: Possible bug in Vertex-4 Rocket-IO?
    86931: 05/07/09: <shuo.huang@fibre.com>: Re: Possible bug in Vertex-4 Rocket-IO?
    86932: 05/07/09: <shuo.huang@fibre.com>: Re: Possible bug in Vertex-4 Rocket-IO?
    86944: 05/07/10: <shuo.huang@fibre.com>: Re: Possible bug in Vertex-4 Rocket-IO?
86889: 05/07/08: Joey: Running prog from PROM
    86890: 05/07/08: John Adair: Re: Running prog from PROM
    86891: 05/07/08: Michael Bodenbach: Re: Running prog from PROM
        86898: 05/07/08: Joey: Re: Running prog from PROM
            86958: 05/07/11: Joey: Re: Running prog from PROM
    86893: 05/07/08: Antti Lukats: ISE 7.1 SP3, Spartan3-E readiness ??
        86895: 05/07/08: Antti Lukats: Re: ISE 7.1 SP3, Spartan3-E readiness ??
    86939: 05/07/10: <m.bodenbach@ifen.com>: Re: Running prog from PROM
86906: 05/07/08: Paul Boven: Timespec for DCM outputs (Spartan 3) ?
    86908: 05/07/08: Falk Brunner: Re: Timespec for DCM outputs (Spartan 3) ?
        86914: 05/07/08: Paul Boven: Re: Timespec for DCM outputs (Spartan 3) ?
    86912: 05/07/08: Vladislav Muravin: Re: Timespec for DCM outputs (Spartan 3) ?
        86916: 05/07/09: Paul Boven: Re: Timespec for DCM outputs (Spartan 3) ?
            86918: 05/07/09: Philip Freidin: Re: Timespec for DCM outputs (Spartan 3) ?
            86925: 05/07/09: Dave: Re: Timespec for DCM outputs (Spartan 3) ?
            86953: 05/07/11: Symon: Re: Timespec for DCM outputs (Spartan 3) ?
86907: 05/07/08: PL: Xilinx ISE 7.1 : Macro search path in Transalate
    86910: 05/07/08: Duane Clark: Re: Xilinx ISE 7.1 : Macro search path in Transalate
86911: 05/07/08: Joseph: Ethernet reference design for ML310?
    86915: 05/07/08: Joseph: Re: Ethernet reference design for ML310?
        86927: 05/07/09: Mike Treseler: Re: Ethernet reference design for ML310?
    86977: 05/07/11: Joseph: Re: Ethernet reference design for ML310?
86917: 05/07/08: tony.p.lee@gmail.com: Rocket IO failure after power cycle.
    86920: 05/07/08: Marko: Re: Rocket IO failure after power cycle.
        86922: 05/07/09: Jerzy Gbur: Re: Rocket IO failure after power cycle.
86928: 05/07/09: Mike Treseler: Re: Announce: Impulse C-to-RTL Version 2 now available
86930: 05/07/09: JJ: Re: Announce: Impulse C-to-RTL Version 2 now available
    86935: 05/07/10: Hans: Re: Announce: Impulse C-to-RTL Version 2 now available
        86975: 05/07/11: David Pellerin: Re: Announce: Impulse C-to-RTL Version 2 now available
86933: 05/07/09: farnel: Altera QII WE Tutorials
    86934: 05/07/10: Jim Granville: Re: Altera QII WE Tutorials
    87151: 05/07/17: Vaughn Betz: Re: Altera QII WE Tutorials
86936: 05/07/10: <nahum_barnea@yahoo.com>: design does not fit in device
    86937: 05/07/10: Falk Brunner: Re: design does not fit in device
        86959: 05/07/11: Nahum Barnea: Re: design does not fit in device
    86950: 05/07/11: John Adair: Re: design does not fit in device
86938: 05/07/10: Paul Solomon: Quartus Timing Issues
    86940: 05/07/10: Mike Treseler: Re: Quartus Timing Issues
        86942: 05/07/11: Paul Solomon: Re: Quartus Timing Issues
            87020: 05/07/13: Vaughn Betz: Re: Quartus Timing Issues
86945: 05/07/11: Thomas Reinemann: Search for FPGA
    86947: 05/07/11: Antti Lukats: Re: Search for FPGA
        86985: 05/07/11: Thomas Stanka: Re: Search for FPGA
    86948: 05/07/11: Michael Bodenbach: Re: Search for FPGA
    86949: 05/07/11: John Adair: Re: Search for FPGA
        86963: 05/07/11: John Adair: Re: Search for FPGA
    86960: 05/07/11: Gabor: Re: Search for FPGA
86946: 05/07/11: Antti Lukats: new PLD and FPGA devices from Lattice
    86954: 05/07/11: Thomas Entner: Re: new PLD and FPGA devices from Lattice
86951: 05/07/11: hata: Wishbone RTL simulator
    86952: 05/07/11: Antti Lukats: Re: Wishbone RTL simulator
        86964: 05/07/11: Rudolf Usselmann: Re: Wishbone RTL simulator
    86955: 05/07/11: hata: Re: Wishbone RTL simulator
86956: 05/07/11: zoinks@mytrashmail.com: stupid question about XPS peripheral filenames
    86957: 05/07/11: Antti Lukats: Re: stupid question about XPS peripheral filenames
86961: 05/07/11: Manfred Balik: output-value isn't stored
    86962: 05/07/11: Gabor: Re: output-value isn't stored
    86967: 05/07/11: Sean Durkin: Re: output-value isn't stored
        87036: 05/07/13: Sean Durkin: Re: output-value isn't stored
    87003: 05/07/12: Andy Peters: Re: output-value isn't stored
86968: 05/07/11: <tony.p.lee@gmail.com>: Any Scope/LogicAnalyzer that can decode 8b/10b signals in the Rocket IO?
    86969: 05/07/11: Antti Lukats: Re: Any Scope/LogicAnalyzer that can decode 8b/10b signals in the Rocket IO?
86970: 05/07/11: Elder Costa: Connecting TigerSharc TS201 EzKIT to PCI with Spartan 3
    86987: 05/07/12: katherine: Re: Connecting TigerSharc TS201 EzKIT to PCI with Spartan 3
86971: 05/07/11: Sander Zuidema: Bazix introduce FPGA based One Chip computer system
    86972: 05/07/11: Jedi: Re: Bazix introduce FPGA based One Chip computer system
        86973: 05/07/11: Sander Zuidema: Re: Bazix introduce FPGA based One Chip computer system
            86974: 05/07/11: Antti Lukats: Re: Bazix introduce FPGA based One Chip computer system
                86998: 05/07/12: Sander Zuidema: Re: Bazix introduce FPGA based One Chip computer system
                    86999: 05/07/12: Antti Lukats: Re: Bazix introduce FPGA based One Chip computer system
86976: 05/07/12: Paul Solomon: Testbenching and verification
    87000: 05/07/12: Andy Peters: Re: Testbenching and verification
    87027: 05/07/13: Arash Salarian: Re: Testbenching and verification
        87150: 05/07/17: Vaughn Betz: Re: Testbenching and verification
86978: 05/07/11: tns1: QII simulation annoyance
    86986: 05/07/12: <ALuPin@web.de>: Re: QII simulation annoyance
        86994: 05/07/12: tns: Re: QII simulation annoyance
    86997: 05/07/12: Mike Treseler: Re: QII simulation annoyance
        87005: 05/07/12: tns: Re: QII simulation annoyance
    87011: 05/07/12: GMM50: Re: QII simulation annoyance
        87016: 05/07/12: tns1: Re: QII simulation annoyance
            87053: 05/07/13: tns: Re: QII simulation annoyance
        87029: 05/07/13: Markus Knauss: Re: QII simulation annoyance
    87018: 05/07/12: Vaughn Betz: Re: QII simulation annoyance
        87021: 05/07/13: tns: Re: QII simulation annoyance
            87152: 05/07/18: Vaughn Betz: Re: QII simulation annoyance
    87049: 05/07/13: Andy Peters: Re: QII simulation annoyance
86979: 05/07/12: Paul Solomon: Unrolled Pipeline Implementation
    86980: 05/07/11: Ray Andraka: Re: Unrolled Pipeline Implementation
    86996: 05/07/12: John_H: Re: Unrolled Pipeline Implementation
    87025: 05/07/13: Arash Salarian: Re: Unrolled Pipeline Implementation
86981: 05/07/11: gallen: Re: Announce: Impulse C-to-RTL Version 2 now available
86982: 05/07/12: Tommy Thorn: Quartus 5.0sp1 -- Error: Unexpected error in JTAG server -- error
    86983: 05/07/12: Antti Lukats: Re: Quartus 5.0sp1 -- Error: Unexpected error in JTAG server -- error code 33
86984: 05/07/11: <praveen.kantharajapura@gmail.com>: Clock recovery in FPGA at 300 MHZ
    86990: 05/07/12: Ben Twijnstra: Re: Clock recovery in FPGA at 300 MHZ
        87019: 05/07/12: Vaughn Betz: Re: Clock recovery in FPGA at 300 MHZ
    87055: 05/07/13: <praveen.kantharajapura@gmail.com>: Re: Clock recovery in FPGA at 300 MHZ
86989: 05/07/12: Laurent Gauch: FPGA to ASIC + JTAG chain insertion
86991: 05/07/12: Antti Lukats: Xilinx PLEASE HELP
    87031: 05/07/13: Antti Lukats: Re: Xilinx PLEASE HELP
        87032: 05/07/13: Antti Lukats: Re: Xilinx PLEASE HELP
            87035: 05/07/13: Antti Lukats: Re: Xilinx PLEASE HELP, thanks issue solved by reverse engineering...
86992: 05/07/12: Max: Xilinx Conversion 3.1 --> 6.1
    86993: 05/07/12: Gabor: Re: Xilinx Conversion 3.1 --> 6.1
        87008: 05/07/12: Max: Re: Xilinx Conversion 3.1 --> 6.1
            87015: 05/07/13: Alex Gibson: Re: Xilinx Conversion 3.1 --> 6.1
    86995: 05/07/12: John Adair: Re: Xilinx Conversion 3.1 --> 6.1
    87010: 05/07/12: Gabor: Re: Xilinx Conversion 3.1 --> 6.1
87001: 05/07/12: amko: 16-bit Acesses on ISA bus
    87006: 05/07/12: Peter C. Wallace: Re: 16-bit Acesses on ISA bus
    87024: 05/07/13: Arash Salarian: Re: 16-bit Acesses on ISA bus
87007: 05/07/12: Aj: Observations on passing clock constraints through DCM in Synplify 8.1
87009: 05/07/12: Aj: Observations on passing clock constraints through DCM in Synplify 8.1
87012: 05/07/12: jjlindula@hotmail.com: Safe State Machine Design in AHDL
    87026: 05/07/13: Arash Salarian: Re: Safe State Machine Design in AHDL
87013: 05/07/12: Richard B. Katz: MAPLD 2005: Program Announced and Registration Open
87014: 05/07/12: Hassan Atat: edif version generated by xilinx ISE 6.2
    87030: 05/07/13: Jon Beniston: Re: edif version generated by xilinx ISE 6.2
87017: 05/07/12: Daniel Leu: Re: Announce: Impulse C-to-RTL Version 2 now available
87022: 05/07/13: Jedi: NIOS2 toolchain sources...
    87023: 05/07/13: Antti Lukats: Re: NIOS2 toolchain sources...
        87028: 05/07/13: Jedi: Re: NIOS2 toolchain sources...
87033: 05/07/13: irish: Implement a JTAG controller in an FPGA
    87034: 05/07/13: Antti Lukats: Re: Implement a JTAG controller in an FPGA
    87042: 05/07/13: Luc: Re: Implement a JTAG controller in an FPGA
        87044: 05/07/13: Antti Lukats: Re: Implement a JTAG controller in an FPGA
87037: 05/07/13: Shai: Problems programing FPGAs..
    87038: 05/07/13: Antti Lukats: Re: Problems programing FPGAs..
    87057: 05/07/14: Rene Tschaggelar: Re: Problems programing FPGAs..
87039: 05/07/13: jeff murphy: ise 7.1 Input clk is never used.
    87040: 05/07/13: Antti Lukats: Re: ise 7.1 Input clk is never used.
    87046: 05/07/13: Andy Peters: Re: ise 7.1 Input clk is never used.
    87067: 05/07/14: <raghurash@rediffmail.com>: Re: ise 7.1 Input clk is never used.
    87071: 05/07/14: <ALuPin@web.de>: Re: ise 7.1 Input clk is never used.
        87106: 05/07/15: Martin Thompson: Re: ise 7.1 Input clk is never used.
    87079: 05/07/14: jeff murphy: Re: ise 7.1 Input clk is never used.
87041: 05/07/13: Antti Lukats: IEEE1532 question, with Xilinx devices
87043: 05/07/13: <linq936@hotmail.com>: virtex 4 : how can I know the clock region coverage?
    87045: 05/07/13: Antti Lukats: Re: virtex 4 : how can I know the clock region coverage?
    87056: 05/07/14: Antti Lukats: Re: virtex 4 : how can I know the clock region coverage?
    88068: 05/08/08: google_comp.arch.fpga@47110815.com: Re: virtex 4 : how can I know the clock region coverage?
87047: 05/07/13: Antti Lukats: MachXO - not released, but already supported by Aldec !!
87048: 05/07/13: Andy Peters: Re: QII simulation annoyance
87050: 05/07/13: Bob Myers: Virtex 300: what could cause pin to short?
    87051: 05/07/13: Peter Alfke: Re: Virtex 300: what could cause pin to short?
    87052: 05/07/13: Marc: Re: Virtex 300: what could cause pin to short?
    87087: 05/07/14: John_H: Re: Virtex 300: what could cause pin to short?
    87092: 05/07/14: Jon Elson: Re: Virtex 300: what could cause pin to short?
87054: 05/07/13: greenplanet: Reading a PS/2 mouse
    87073: 05/07/14: greenplanet: Re: Reading a PS/2 mouse
        87093: 05/07/15: Jeremy Stringer: Re: Reading a PS/2 mouse
            87187: 05/07/19: Jeremy Stringer: Re: Reading a PS/2 mouse
    87099: 05/07/14: greenplanet: Re: Reading a PS/2 mouse
    87125: 05/07/15: Big Boy: re:Reading a PS/2 mouse
    87131: 05/07/16: greenplanet: Re: Reading a PS/2 mouse
87058: 05/07/14: scd: Wanted Actel ProAsic RAM VHDL models
    87059: 05/07/14: Hans: Re: Wanted Actel ProAsic RAM VHDL models
87060: 05/07/14: Paul Solomon: Modulo division in Verilog
    87062: 05/07/14: mk: Re: Modulo division in Verilog
        87063: 05/07/14: Paul Solomon: Re: Modulo division in Verilog
    87086: 05/07/14: John_H: Re: Modulo division in Verilog
        87091: 05/07/15: Paul Solomon: Re: Modulo division in Verilog
            87096: 05/07/15: John_H: Re: Modulo division in Verilog
                87097: 05/07/15: Paul Solomon: Re: Modulo division in Verilog
                    87114: 05/07/15: John_H: Re: Modulo division in Verilog
                    87358: 05/07/22: Vaughn Betz: Re: Modulo division in Verilog
87061: 05/07/14: scd: Wanted: I2C RAM pre-loader VHDL module
    87065: 05/07/14: Antti Lukats: Re: Wanted: I2C RAM pre-loader VHDL module
        87072: 05/07/14: Kryten: Re: Wanted: I2C RAM pre-loader VHDL module
87064: 05/07/14: <mlpei279@gmail.com>: why my programm has no response after i added some opb_bram_if_ctrl core my project?
    87066: 05/07/14: Antti Lukats: Re: why my programm has no response after i added some opb_bram_if_ctrl core my project?
87069: 05/07/14: Chinix: Why cann't this block be synthesized in top level
    87070: 05/07/14: <ALuPin@web.de>: Re: Why cann't this block be synthesized in top level
    87075: 05/07/14: Chinix: Re: Why cann't this block be synthesized in top level
    87076: 05/07/14: Chinix: Re: Why cann't this block be synthesized in top level
    87077: 05/07/14: Gabor: Re: Why cann't this block be synthesized in top level
    87080: 05/07/14: Chinix: Re: Why cann't this block be synthesized in top level
    87129: 05/07/15: RaKa: Re: Why cann't this block be synthesized in top level
87074: 05/07/14: vssumesh: Doubts on Xilinx FPGA
    87078: 05/07/14: Gabor: Re: Doubts on Xilinx FPGA
    87085: 05/07/14: John_H: Re: Doubts on Xilinx FPGA
        87113: 05/07/15: John_H: Re: Doubts on Xilinx FPGA
        87136: 05/07/16: John_H: Re: Doubts on Xilinx FPGA
        87913: 05/08/03: John_H: Re: Doubts on Xilinx FPGA
    87108: 05/07/15: vssumesh: Re: Doubts on Xilinx FPGA
    87109: 05/07/15: vssumesh: Re: Doubts on Xilinx FPGA
    87130: 05/07/16: vssumesh: Re: Doubts on Xilinx FPGA
    87137: 05/07/16: Andy Peters: Re: Doubts on Xilinx FPGA
    87160: 05/07/18: Gabor: Re: Doubts on Xilinx FPGA
    87783: 05/08/01: vssumesh: Re: Doubts on Xilinx FPGA
87083: 05/07/14: Joey Martin: Reciprocal of improper fraction by using Divider ipcore
87088: 05/07/14: <jjohnson@cs.ucf.edu>: Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
    87090: 05/07/14: Mike Treseler: Re: Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
        87112: 05/07/15: Anton Erasmus: Re: Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
        87300: 05/07/21: Jahagirdar Vijayvithal S: Re: Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
    87094: 05/07/15: Colin Marquardt: Re: Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
87089: 05/07/14: praetorian: Bus Macros
    87105: 05/07/15: Gabor: Re: Bus Macros
        87115: 05/07/15: praetorian: Re: Bus Macros
            87174: 05/07/18: praetorian: Re: Bus Macros
    87120: 05/07/15: Gabor: Re: Bus Macros
    87141: 05/07/16: Correlious: Re: Bus Macros
87095: 05/07/14: fahadislam2002: How to Interface External Ram with FPGA
    87140: 05/07/16: Correlious: Re: How to Interface External Ram with FPGA
87098: 05/07/14: <bjskill@rocketmail.com>: NIOS II + USB 2.0 host
    87101: 05/07/15: Antti Lukats: Re: NIOS II + USB 2.0 host
        87118: 05/07/15: Antonio Pasini: Re: NIOS II + USB 2.0 host
            87119: 05/07/15: Antti Lukats: Re: NIOS II + USB 2.0 host
    87124: 05/07/15: <bjskill@rocketmail.com>: Re: NIOS II + USB 2.0 host
    87146: 05/07/18: Rudolf Usselmann: Re: NIOS II + USB 2.0 host
    87147: 05/07/17: <bjskill@rocketmail.com>: Re: NIOS II + USB 2.0 host
87100: 05/07/15: Heiko Kalte: Virtex-4 5V tolerance
    87161: 05/07/18: Antti Lukats: Re: Virtex-4 5V tolerance
    87184: 05/07/18: austin: Re: Virtex-4 5V tolerance
    87186: 05/07/18: Peter Alfke: Re: Virtex-4 5V tolerance
    87212: 05/07/19: Big Boy: re:Virtex-4 5V tolerance
87102: 05/07/15: Johan Riesbeck: Xilinx MPEG
87104: 05/07/15: Antti Lukats: Xilinx: Clock speeds 420MHz+ tested in Spartan-3
    87107: 05/07/15: Unbeliever: Re: Xilinx: Clock speeds 420MHz+ tested in Spartan-3
        87122: 05/07/15: Antti Lukats: Re: Xilinx: Clock speeds 420MHz+ tested in Spartan-3
87110: 05/07/15: Marco: Linux Fedora and Xilinx ISE
    87116: 05/07/15: jeff murphy: Re: Linux Fedora and Xilinx ISE
    87123: 05/07/15: Marco: Re: Linux Fedora and Xilinx ISE
87111: 05/07/15: <muthusnv@rediffmail.com>: Compilation error with Synplify attribute
    87126: 05/07/15: Ken McElvain: Re: Compilation error with Synplify attribute
        87128: 05/07/16: jtw: Re: Compilation error with Synplify attribute
87117: 05/07/15: Guy Lemieux: FPGA2006 Call for Papers -- ACM/SIGDA International Symposium on FPGAs
87121: 05/07/15: Gabster: Interface Wi-Fi with FPGA
87132: 05/07/16: <abgoyal@gmail.com>: virtex 4 configuration error
87133: 05/07/16: B. Joshua Rosen: Can't run Xilinx 7.1SP3 on FC3
    87138: 05/07/16: Paul Hartke: Re: Can't run Xilinx 7.1SP3 on FC3
        87139: 05/07/16: B. Joshua Rosen: Re: Can't run Xilinx 7.1SP3 on FC3
87134: 05/07/16: <coshzz@gmail.com>: post-place & route simulation of simple project problem.
    87135: 05/07/16: <coshzz@gmail.com>: Re: post-place & route simulation of simple project problem.
    87167: 05/07/18: Brijesh: Re: post-place & route simulation of simple project problem.
    87357: 05/07/21: <coshzz@gmail.com>: Re: post-place & route simulation of simple project problem.
87142: 05/07/17: pasacco: Serial vs Chipscope
    87143: 05/07/17: Antti Lukats: Re: Serial vs Chipscope
    87144: 05/07/17: Mike Treseler: Re: Serial vs Chipscope
    87145: 05/07/17: pasacco: Re: Serial vs Chipscope
87153: 05/07/18: Jack Falk: chips with partial reconfig other than atmel & xilinx?
    87156: 05/07/18: Antti Lukats: Re: chips with partial reconfig other than atmel & xilinx?
87154: 05/07/18: Jack Falk: "Tbufs don't exist"
    87155: 05/07/18: Antti Lukats: Re: "Tbufs don't exist"
        87157: 05/07/18: Bob Perlman: Re: "Tbufs don't exist"
            87210: 05/07/19: Joseph H Allen: Re: "Tbufs don't exist"
    88695: 05/08/25: glen herrmannsfeldt: Re: "Tbufs don't exist"
87159: 05/07/18: Antti Lukats: Sparan S3E availability update
    87827: 05/08/02: <oen_no_spam@yahoo.com.br>: Re: Sparan S3E availability update
        87837: 05/08/02: Antti Lukats: Re: Sparan S3E availability update
            87871: 05/08/03: Antti Lukats: Re: Sparan S3E availability update
    87854: 05/08/02: <oen_no_spam@yahoo.com.br>: Re: Sparan S3E availability update
    87975: 05/08/04: Peter Alfke: Re: Sparan S3E availability update
    87984: 05/08/04: <oen_no_spam@yahoo.com.br>: Re: Sparan S3E availability update
87162: 05/07/18: Mancini Stephane: EDK and powerpc-eabi compiler
87163: 05/07/18: Michael Dales: Lab machine xmd/debugger install?
    87165: 05/07/18: John Adair: Re: Lab machine xmd/debugger install?
    87168: 05/07/18: Michael Dales: Re: Lab machine xmd/debugger install?
87164: 05/07/18: <elinore2005@yahoo.fr>: setting XUP new board
    87180: 05/07/18: Paul Hartke: Re: setting XUP new board
    87193: 05/07/19: Alex Gibson: Re: setting XUP new board
    87202: 05/07/19: <elinore2005@yahoo.fr>: Re: setting XUP new board
    87298: 05/07/20: el231bat: Re: setting XUP new board
87166: 05/07/18: Antti Lukats: Lattice MachXO is LAUNCHED NOW!
    87196: 05/07/19: Unbeliever: Re: Lattice MachXO is LAUNCHED NOW!
        87197: 05/07/19: Antti Lukats: Re: Lattice MachXO is LAUNCHED NOW!
        87198: 05/07/19: Luc: Re: Lattice MachXO is LAUNCHED NOW!
            87204: 05/07/19: Unbeliever: Re: Lattice MachXO is LAUNCHED NOW!
                87223: 05/07/19: Luc: Re: Lattice MachXO is LAUNCHED NOW!
87169: 05/07/18: Marco: Red Hat Enterprise 64 bit and ISE WebPack
87170: 05/07/18: Vladislav Muravin: pricing of Virtex-4
    87172: 05/07/18: Antti Lukats: Re: pricing of Virtex-4
        87173: 05/07/18: Vladislav Muravin: Re: pricing of Virtex-4
            87177: 05/07/18: Vladislav Muravin: Re: pricing of Virtex-4
                87200: 05/07/19: John Adair: Re: pricing of Virtex-4
                    87222: 05/07/19: Vladislav Muravin: Re: pricing of Virtex-4
    87176: 05/07/18: Peter Alfke: Re: pricing of Virtex-4
87175: 05/07/18: Antti Lukats: Virtex-4 breaking the 1GHz clocking barrier in general purpose FPGA fabric (e.g non dedicated circuits)
    87179: 05/07/18: austin: Re: Virtex-4 breaking the 1GHz clocking barrier in general purpose FPGA fabric (e.g non dedicated circuits)
87178: 05/07/18: chat: sample for virtex4
87181: 05/07/18: Brannon: EHLO, board designers
    87182: 05/07/18: Antti Lukats: Re: EHLO, board designers
        87183: 05/07/18: Ben Twijnstra: Re: EHLO, board designers
    87185: 05/07/18: Joel Kolstad: Re: EHLO, board designers
    87195: 05/07/19: Arash Salarian: Re: EHLO, board designers
        87207: 05/07/19: Ray Andraka: Re: EHLO, board designers
    87199: 05/07/19: John Adair: Re: EHLO, board designers
87188: 05/07/18: Pete Fraser: EDK 7.1 with ML401 (paging Antti)
    87190: 05/07/19: John Williams: Re: EDK 7.1 with ML401 (paging Antti)
    87194: 05/07/19: Antti Lukats: Re: EDK 7.1 with ML401 (paging Antti)
    87340: 05/07/21: joe4702: Re: EDK 7.1 with ML401 (paging Antti)
87189: 05/07/18: kurapati: ethernet EMAC cores available for Microblaze
87191: 05/07/18: vssumesh: Driving the FPGA output.
    87192: 05/07/19: Antti Lukats: Re: Driving the FPGA output.
        87205: 05/07/19: Kolja Sulimma: Re: Driving the FPGA output.
87201: 05/07/19: zoinks@mytrashmail.com: simulation troubles
87203: 05/07/19: Paul Leventis (at home): July 20th Altera Net Seminar: Stratix II Logic Density
    87211: 05/07/19: Peter Alfke: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87218: 05/07/19: tim: Re: July 20th Altera Net Seminar: Stratix II Logic Density
        87219: 05/07/19: Antti Lukats: Re: July 20th Altera Net Seminar: Stratix II Logic Density
        87235: 05/07/19: Vaughn Betz: Re: July 20th Altera Net Seminar: Stratix II Logic Density
            87242: 05/07/20: Paul Leventis (at home): Re: July 20th Altera Net Seminar: Stratix II Logic Density
                87307: 05/07/21: Paul Leventis (at home): Re: July 20th Altera Net Seminar: Stratix II Logic Density
            87277: 05/07/20: Ray Andraka: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                87287: 05/07/20: Ray Andraka: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                    87309: 05/07/21: Paul Leventis (at home): Re: July 20th Altera Net Seminar: Stratix II Logic Density
                        87315: 05/07/21: Ray Andraka: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                    87353: 05/07/21: Vaughn Betz: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                87294: 05/07/20: Philip Freidin: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                    87318: 05/07/21: Ray Andraka: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                        87355: 05/07/21: Vaughn Betz: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                            87484: 05/07/25: Kolja Sulimma: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                                87519: 05/07/25: Antti Lukats: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                                    87553: 05/07/25: Paul Leventis (at home): Re: July 20th Altera Net Seminar: Stratix II Logic Density
                87310: 05/07/21: Paul Leventis (at home): Re: July 20th Altera Net Seminar: Stratix II Logic Density
                87441: 05/07/24: Kees van Reeuwijk: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                    87466: 05/07/24: Mike Treseler: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                    87482: 05/07/25: mk: Re: July 20th Altera Net Seminar: Stratix II Logic Density
                87487: 05/07/25: Thomas Entner: Re: July 20th Altera Net Seminar: Stratix II Logic Density
            87297: 05/07/21: Henry Wong: Re: July 20th Altera Net Seminar: Stratix II Logic Density
            87308: 05/07/21: Paul Leventis (at home): Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87236: 05/07/19: Marc Randolph: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87246: 05/07/20: Marc Randolph: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87256: 05/07/20: tim: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87257: 05/07/20: tim: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87283: 05/07/20: Peter Alfke: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87364: 05/07/21: <seannstifler69@hotmail.com>: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87365: 05/07/21: Marc Randolph: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87405: 05/07/22: Paul Leventis: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87425: 05/07/23: austin: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87434: 05/07/23: Peter Alfke: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87464: 05/07/24: Peter Alfke: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87467: 05/07/24: austin: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87518: 05/07/25: Paul Leventis: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87590: 05/07/26: Andy Peters: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87206: 05/07/19: Vaggelis: Power PC Stall ??
87208: 05/07/19: Jens: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
    87209: 05/07/19: Antti Lukats: Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
    87213: 05/07/19: pasacco: Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
    87221: 05/07/19: Vladislav Muravin: Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
    87238: 05/07/20: zeeman_be: Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
87214: 05/07/19: vssumesh: Xilinx equivalent of simplify constrains.
    87216: 05/07/19: Antti Lukats: Re: Xilinx equivalent of simplify constrains.
    87220: 05/07/19: Vladislav Muravin: Re: Xilinx equivalent of simplify constrains.
87215: 05/07/19: pasacco: ChipScope Pro : how to set up trigger
    87217: 05/07/19: Antti Lukats: Re: ChipScope Pro : how to set up trigger
    87245: 05/07/20: pasacco: Re: ChipScope Pro : how to set up trigger
    87260: 05/07/20: Nenad: Re: ChipScope Pro : how to set up trigger
    87317: 05/07/21: pasacco: Re: ChipScope Pro : how to set up trigger
    87326: 05/07/21: pasacco: Re: ChipScope Pro : how to set up trigger
    87327: 05/07/21: Nenad: Re: ChipScope Pro : how to set up trigger
    87691: 05/07/28: pasacco: Re: ChipScope Pro : how to set up trigger
    87700: 05/07/28: Nenad: Re: ChipScope Pro : how to set up trigger
    87722: 05/07/29: pasacco: Re: ChipScope Pro : how to set up trigger
    87727: 05/07/29: pasacco: Re: ChipScope Pro : how to set up trigger
    87734: 05/07/29: Nenad: Re: ChipScope Pro : how to set up trigger
    87757: 05/07/31: pasacco: Re: ChipScope Pro : how to set up trigger
    87782: 05/08/01: Nenad: Re: ChipScope Pro : how to set up trigger
    87790: 05/08/01: pasacco: Re: ChipScope Pro : how to set up trigger
87224: 05/07/19: tony.p.lee@gmail.com: Xilinx sysace + xmd -jprog options.
    87319: 05/07/21: tony.p.lee@gmail.com: Re: Xilinx sysace + xmd -jprog options.
87225: 05/07/19: Brad Smallridge: Ones Count 64 bit on Xilinx in VHDL
    87226: 05/07/19: John_H: Re: Ones Count 64 bit on Xilinx in VHDL
        87227: 05/07/19: Brad Smallridge: Re: Ones Count 64 bit on Xilinx in VHDL
            87262: 05/07/20: John_H: Re: Ones Count 64 bit on Xilinx in VHDL
                87271: 05/07/20: Brad Smallridge: Re: Ones Count 64 bit on Xilinx in VHDL
                    87293: 05/07/20: John_H: Re: Ones Count 64 bit on Xilinx in VHDL
        87229: 05/07/19: Brad Smallridge: Re: Ones Count 64 bit on Xilinx in VHDL
    87230: 05/07/19: Peter Alfke: Re: Ones Count 64 bit on Xilinx in VHDL
    87231: 05/07/19: JJ: Re: Ones Count 64 bit on Xilinx in VHDL
    87232: 05/07/19: Peter Alfke: Re: Ones Count 64 bit on Xilinx in VHDL
    87234: 05/07/19: Ray Andraka: Re: Ones Count 64 bit on Xilinx in VHDL
        88701: 05/08/25: glen herrmannsfeldt: Re: Ones Count 64 bit on Xilinx in VHDL
    87264: 05/07/20: Vladislav Muravin: Re: Ones Count 64 bit on Xilinx in VHDL
        87284: 05/07/20: Ben Twijnstra: Re: Ones Count 64 bit on Xilinx in VHDL
            87288: 05/07/20: Ray Andraka: Re: Ones Count 64 bit on Xilinx in VHDL
    87281: 05/07/20: Peter Alfke: Re: Ones Count 64 bit on Xilinx in VHDL
    87296: 05/07/20: JJ: Re: Ones Count 64 bit on Xilinx in VHDL
    87339: 05/07/21: JustJohn: Re: Ones Count 64 bit on Xilinx in VHDL
    87347: 05/07/21: Peter Alfke: Re: Ones Count 64 bit on Xilinx in VHDL
    87362: 05/07/21: Brad Smallridge: Re: Ones Count 64 bit on Xilinx in VHDL
    87369: 05/07/22: JJ: Re: Ones Count 64 bit on Xilinx in VHDL
    87372: 05/07/22: JJ: Re: Ones Count 64 bit on Xilinx in VHDL
    88714: 05/08/25: Paul Marciano: Re: Ones Count 64 bit on Xilinx in VHDL
87228: 05/07/19: JD_Design: Virtex-4 hot-swappable?
    87247: 05/07/20: austin: Re: Virtex-4 hot-swappable?
    87859: 05/08/02: JD_Design: Re: Virtex-4 hot-swappable?
    88108: 05/08/09: JD_Design: Re: Virtex-4 hot-swappable?
    88121: 05/08/09: austin: Re: Virtex-4 hot-swappable?
87233: 05/07/20: Alex Rast: General-purpose STAPL Composer?
    87239: 05/07/20: Laurent Gauch: Re: General-purpose STAPL Composer?
    87270: 05/07/20: Daniel Leu: Re: General-purpose STAPL Composer?
        87303: 05/07/21: Alex Rast: Re: General-purpose STAPL Composer?
            87335: 05/07/21: Ralph Friedrich: Re: General-purpose STAPL Composer?
                87408: 05/07/22: Alex Rast: Re: General-purpose STAPL Composer?
87237: 05/07/20: <ALuPin@web.de>: Using unregistered inputs in FSM
    87240: 05/07/20: <ALuPin@web.de>: Re: Using unregistered inputs in FSM
        87253: 05/07/20: Mike Treseler: Re: Using unregistered inputs in FSM
    87241: 05/07/20: John Adair: Re: Using unregistered inputs in FSM
    87244: 05/07/20: Hubble: Re: Using unregistered inputs in FSM
        87255: 05/07/20: Mike Treseler: Re: Using unregistered inputs in FSM
    87248: 05/07/20: <ALuPin@web.de>: Re: Using unregistered inputs in FSM
    87250: 05/07/20: <ALuPin@web.de>: Re: Using unregistered inputs in FSM
    87252: 05/07/20: Mike Treseler: Re: Using unregistered inputs in FSM
    87254: 05/07/20: Peter Alfke: Re: Using unregistered inputs in FSM
    87258: 05/07/20: Vladislav Muravin: Re: Using unregistered inputs in FSM
        87322: 05/07/21: Mike Treseler: Re: Using unregistered inputs in FSM
        87324: 05/07/21: Vladislav Muravin: Re: Using unregistered inputs in FSM
            87380: 05/07/22: Vladislav Muravin: Re: Using unregistered inputs in FSM
                87385: 05/07/22: Mike Treseler: Re: Using unregistered inputs in FSM
                    87388: 05/07/22: Vladislav Muravin: Re: Using unregistered inputs in FSM
                    87502: 05/07/25: Vladislav Muravin: Re: Using unregistered inputs in FSM
            87383: 05/07/22: Mike Treseler: Re: Using unregistered inputs in FSM
                87718: 05/07/29: Martin Thompson: Re: Using unregistered inputs in FSM
                87723: 05/07/29: Mike Treseler: Re: Using unregistered inputs in FSM
    87301: 05/07/21: <ALuPin@web.de>: Re: Using unregistered inputs in FSM
    87366: 05/07/22: <ALuPin@web.de>: Re: Using unregistered inputs in FSM
    87368: 05/07/22: <ALuPin@web.de>: Re: Using unregistered inputs in FSM
    87488: 05/07/25: <ALuPin@web.de>: Re: Using unregistered inputs in FSM
    87511: 05/07/25: <ALuPin@web.de>: Re: Using unregistered inputs in FSM
    87715: 05/07/29: <ALuPin@web.de>: Re: Using unregistered inputs in FSM
87243: 05/07/20: <sarath1111@gmail.com>: Softcore based Rapid Protyping?
87249: 05/07/20: <ALuPin@web.de>: DDR SDRAM configuration
87251: 05/07/20: Brandon: Generics of type time and XST synthesis
    87345: 05/07/21: Andy Peters: Re: Generics of type time and XST synthesis
87259: 05/07/20: methi: Design is too large for the device! xc3s400
    87261: 05/07/20: John_H: Re: Design is too large for the device! xc3s400
        87275: 05/07/20: Ray Andraka: Re: Design is too large for the device! xc3s400
            87280: 05/07/20: Ray Andraka: Re: Design is too large for the device! xc3s400
        87305: 05/07/21: Kolja Sulimma: Re: Design is too large for the device! xc3s400
    87263: 05/07/20: methi: Re: Design is too large for the device! xc3s400
    87265: 05/07/20: Vladislav Muravin: Re: Design is too large for the device! xc3s400
        87282: 05/07/20: Mike Treseler: Re: Design is too large for the device! xc3s400
            87290: 05/07/20: Ray Andraka: Re: Design is too large for the device! xc3s400
                87306: 05/07/21: Kolja Sulimma: Re: Design is too large for the device! xc3s400
        87289: 05/07/20: Ray Andraka: Re: Design is too large for the device! xc3s400
            87332: 05/07/21: Ray Andraka: Re: Design is too large for the device! xc3s400
                88699: 05/08/25: glen herrmannsfeldt: Re: Design is too large for the device! xc3s400
            88698: 05/08/25: glen herrmannsfeldt: Re: Design is too large for the device! xc3s400
    87266: 05/07/20: Peter Alfke: Re: Design is too large for the device! xc3s400
    87272: 05/07/20: methi: Re: Design is too large for the device! xc3s400
    87273: 05/07/20: methi: Re: Design is too large for the device! xc3s400
    87274: 05/07/20: methi: Re: Design is too large for the device! xc3s400
    87278: 05/07/20: methi: Re: Design is too large for the device! xc3s400
    87285: 05/07/20: Peter Alfke: Re: Design is too large for the device! xc3s400
    87286: 05/07/20: Andy Peters: Re: Design is too large for the device! xc3s400
    87291: 05/07/20: methi: Re: Design is too large for the device! xc3s400
    87292: 05/07/20: Peter Alfke: Re: Design is too large for the device! xc3s400
    87343: 05/07/21: Andy Peters: Re: Design is too large for the device! xc3s400
    87348: 05/07/21: Peter Alfke: Re: Design is too large for the device! xc3s400
    87576: 05/07/26: methi: Re: Design is too large for the device! xc3s400
    87587: 05/07/26: Andy Peters: Re: Design is too large for the device! xc3s400
    87656: 05/07/27: methi: Re: Design is too large for the device! xc3s400
    87666: 05/07/27: Peter Alfke: Re: Design is too large for the device! xc3s400
    87703: 05/07/28: methi: Re: Design is too large for the device! xc3s400
87267: 05/07/20: azam: All of the design is being optimized away and logic removed
87268: 05/07/20: Nick: FPGA + DIMM SDRAM
87269: 05/07/20: Vladislav Muravin: Re: All of the design is being optimized away and logic removed
    87276: 05/07/20: Ray Andraka: Re: All of the design is being optimized away and logic removed
    87313: 05/07/21: Vladislav Muravin: Re: All of the design is being optimized away and logic removed
87279: 05/07/20: azam: Re: All of the design is being optimized away and logic removed
87295: 05/07/20: John D. Davis: Creating Variable Delay for output signals in an XCV1000
    87320: 05/07/21: austin: Re: Creating Variable Delay for output signals in an XCV1000
    87336: 05/07/21: John D. Davis: Re: Creating Variable Delay for output signals in an XCV1000
    87346: 05/07/21: Peter Alfke: Re: Creating Variable Delay for output signals in an XCV1000
    88074: 05/08/08: John D. Davis: Re: Creating Variable Delay for output signals in an XCV1000
87299: 05/07/20: Shanon Fernald: Optimizing out a divide on altera cyclone fpga
    87311: 05/07/21: Gary Pace: Re: Optimizing out a divide on altera cyclone fpga
        87351: 05/07/21: Ray Andraka: Re: Optimizing out a divide on altera cyclone fpga
    87316: 05/07/21: <allanherriman@hotmail.com>: Re: Optimizing out a divide on altera cyclone fpga
    87329: 05/07/21: Shanon Fernald: Re: Optimizing out a divide on altera cyclone fpga
    87349: 05/07/21: Shanon Fernald: Re: Optimizing out a divide on altera cyclone fpga
    87360: 05/07/21: Shanon Fernald: Re: Optimizing out a divide on altera cyclone fpga
    87375: 05/07/22: <allanherriman@hotmail.com>: Re: Optimizing out a divide on altera cyclone fpga
87302: 05/07/21: Love Singhal: Re: All of the design is being optimized away and logic removed
87304: 05/07/21: Holger Blum: IP-cores for digital audio
    87312: 05/07/21: Al Clark: Re: IP-cores for digital audio
    87400: 05/07/22: <amyler@eircom.net>: Re: IP-cores for digital audio
87314: 05/07/21: Patrick: Heat Sink for Stratix
87321: 05/07/21: <brentkucera@gmail.com>: Does anyone have a NIOS Ethernet Development Kit?
    87323: 05/07/21: Mike Treseler: Re: Does anyone have a NIOS Ethernet Development Kit?
    87325: 05/07/21: Brent Kucera: Re: Does anyone have a NIOS Ethernet Development Kit?
    87642: 05/07/27: Brent Kucera: Re: Does anyone have a NIOS Ethernet Development Kit?
87328: 05/07/21: Nenad: DDR SDRAM on ML401
    87374: 05/07/22: Jim Wu: Re: DDR SDRAM on ML401
    87379: 05/07/22: Nenad: Re: DDR SDRAM on ML401
    87401: 05/07/22: jimwu88NOOOSPAM@yahoo.com: Re: DDR SDRAM on ML401
87330: 05/07/21: jjlindula@hotmail.com: Best Practices to Manage Complexity in Hardward/Software Design?
    87331: 05/07/21: Bhaskar Thiagarajan: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87333: 05/07/21: Ray Andraka: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87392: 05/07/22: Tim Wescott: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87334: 05/07/21: Phlip: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87359: 05/07/21: John Larkin: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87363: 05/07/22: Al Clark: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87370: 05/07/22: Steve Underwood: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87483: 05/07/25: Eric DELAGE: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                    87485: 05/07/25: Steve Underwood: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87381: 05/07/22: Phlip: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87395: 05/07/22: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87478: 05/07/24: John Larkin: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87496: 05/07/25: Bob Perlman: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                    87509: 05/07/25: John Larkin: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87508: 05/07/25: Baxter: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87337: 05/07/21: Mike Treseler: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87342: 05/07/21: Marc Randolph: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87354: 05/07/21: Fred Marshall: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87410: 05/07/22: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87422: 05/07/23: Fred Marshall: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87436: 05/07/23: Fred Marshall: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                    87448: 05/07/24: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87417: 05/07/23: Jacob Sparre Andersen: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87426: 05/07/23: xpyttl: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87438: 05/07/23: Fred Marshall: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87427: 05/07/23: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87429: 05/07/23: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87449: 05/07/24: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87430: 05/07/23: Matt Timmermans: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87444: 05/07/24: Steve Underwood: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87450: 05/07/24: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87470: 05/07/24: Matt Timmermans: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                    87474: 05/07/24: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                        87507: 05/07/25: Baxter: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                        87552: 05/07/25: Matt Timmermans: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                        87559: 05/07/26: Jon Harris: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                            87564: 05/07/26: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                        87563: 05/07/26: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                    87499: 05/07/25: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87471: 05/07/24: Matt Timmermans: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                    87473: 05/07/24: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87439: 05/07/23: Fred Marshall: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87454: 05/07/24: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                    87468: 05/07/24: Fred Marshall: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                        87503: 05/07/25: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                            87532: 05/07/25: Fred Marshall: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                                87548: 05/07/25: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87356: 05/07/22: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87367: 05/07/22: colin: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87371: 05/07/22: <ytregubov@yahoo.com>: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87390: 05/07/22: Joel Kolstad: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87377: 05/07/22: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87391: 05/07/22: Tim Wescott: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87378: 05/07/22: steve: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87386: 05/07/22: Phil Hays: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87393: 05/07/22: Thomas Magma: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87394: 05/07/22: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87409: 05/07/22: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87411: 05/07/22: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87412: 05/07/23: Ben Bradley: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87413: 05/07/23: Erik de Castro Lopo: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87415: 05/07/23: Steve Underwood: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87416: 05/07/23: Erik de Castro Lopo: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87420: 05/07/23: glen herrmannsfeldt: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87414: 05/07/22: Matt Timmermans: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87419: 05/07/23: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87423: 05/07/23: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87428: 05/07/23: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87435: 05/07/23: steve: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87440: 05/07/24: Randy Yates: Re: Best Practices to Manage Complexity in Hardward/Software
        87455: 05/07/24: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87460: 05/07/24: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87472: 05/07/25: Steve Underwood: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                    87475: 05/07/24: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                    87486: 05/07/25: Jan Panteltje: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                        87560: 05/07/26: Jon Harris: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87461: 05/07/24: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87465: 05/07/25: Randy Yates: Re: Best Practices to Manage Complexity in Hardward/Software
        87535: 05/07/25: Fred Marshall: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87561: 05/07/26: Jon Harris: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87545: 05/07/26: Randy Yates: Re: Best Practices to Manage Complexity in Hardward/Software
            87557: 05/07/26: Steve Underwood: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87602: 05/07/27: Al Clark: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                    87603: 05/07/26: Fred Marshall: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87584: 05/07/26: Al Clark: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87556: 05/07/26: Steve Underwood: Re: Best Practices to Manage Complexity in Hardward/Software Design?
        87601: 05/07/27: Randy Yates: Re: Best Practices to Manage Complexity in Hardward/Software
        87668: 05/07/28: Randy Yates: Re: Best Practices to Manage Complexity in Hardward/Software
        87708: 05/07/29: Randy Yates: Re: Best Practices to Manage Complexity in Hardward/Software
        87739: 05/07/30: Randy Yates: Re: Best Practices to Manage Complexity in Hardward/Software
            87758: 05/07/31: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
            87777: 05/08/01: Steve Underwood: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87787: 05/08/01: Jerry Avins: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                    87793: 05/08/01: Tim Wescott: Re: Best Practices to Manage Complexity in Hardward/Software Design?
                87789: 05/08/01: David: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87442: 05/07/24: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87443: 05/07/24: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87445: 05/07/24: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87446: 05/07/24: Peter K.: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87456: 05/07/24: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87457: 05/07/24: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87458: 05/07/24: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87462: 05/07/24: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87491: 05/07/25: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87494: 05/07/25: Peter K.: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87495: 05/07/25: Peter K.: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87510: 05/07/25: bill turner: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87514: 05/07/25: scottfrye: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87549: 05/07/25: Peter K.: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87572: 05/07/26: Peter K.: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87573: 05/07/26: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87574: 05/07/26: scottfrye: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87575: 05/07/26: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87595: 05/07/26: jjlindula@hotmail.com: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87613: 05/07/27: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87620: 05/07/27: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87622: 05/07/27: Peter K.: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87623: 05/07/27: Peter K.: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87630: 05/07/27: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87644: 05/07/27: Peter K.: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87662: 05/07/27: Rune Allnor: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87687: 05/07/28: Peter K.: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87725: 05/07/29: <scottf3095@aol.com>: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87736: 05/07/29: steve: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87737: 05/07/29: Peter K.: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87755: 05/07/30: Peter K.: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87775: 05/08/01: scott frye: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87776: 05/08/01: scott frye: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87338: 05/07/21: Martin: Xilinx software update?
    87341: 05/07/21: austin: Re: Xilinx software update?
        87350: 05/07/22: Martin: Re: Xilinx software update?
    87344: 05/07/21: Marc Randolph: Re: Xilinx software update?
    87352: 05/07/22: Bob Perlman: Re: Xilinx software update?
        87463: 05/07/24: Martin: Re: Xilinx software update?
    87477: 05/07/24: Gladiator: Re: Xilinx software update?
    87492: 05/07/25: Hiding in Plain Sight: Re: Xilinx software update?
87361: 05/07/22: uuyu: (x86 linux) SSE2 usage by simulation applications?
    87376: 05/07/22: Jason Ozolins: Re: (x86 linux) SSE2 usage by simulation applications?
87373: 05/07/22: junaid: verilog to blif(lut)
    87397: 05/07/22: Andy Peters: Re: verilog to blif(lut)
    87403: 05/07/22: Vladislav Muravin: Re: verilog to blif(lut)
        87498: 05/07/25: Antti Lukats: Re: verilog to blif(lut)
    87500: 05/07/25: <jacob.bower@gmail.com>: Re: verilog to blif(lut)
        87551: 05/07/25: Paul Leventis (at home): Re: verilog to blif(lut)
    87670: 05/07/27: Vaughn Betz: Re: verilog to blif(lut)
    87771: 05/08/01: junaid: Re: verilog to blif(lut)
    88895: 05/08/30: <vbetz@altera.com>: Re: verilog to blif(lut)
87382: 05/07/22: ituspam@yahoo.com: What a nice day for XLNX
    87396: 05/07/22: Andy Peters: Re: What a nice day for XLNX
87384: 05/07/22: stbcasa: Place Error
    87389: 05/07/22: Gabor: Re: Place Error
87387: 05/07/22: Stefan: Overmapped
    87432: 05/07/24: Philip Freidin: Re: Overmapped
87398: 05/07/22: azam: Re: All of the design is being optimized away and logic removed
87399: 05/07/22: Tullio Grassi: parallel optic availability
    87402: 05/07/22: Falk Brunner: Re: parallel optic availability
    87406: 05/07/22: Tullio Grassi: Re: parallel optic availability
    87437: 05/07/23: Franklin: Re: parallel optic availability
87404: 05/07/22: <jacques77@gmail.com>: Transfert data to Memec Virtex II Pro Card from PC
    87407: 05/07/22: praetorian: Re: Transfert data to Memec Virtex II Pro Card from PC
    87433: 05/07/23: Correlious: Re: Transfert data to Memec Virtex II Pro Card from PC
87418: 05/07/23: Jedi: Update contacts at Altera
    87489: 05/07/25: Jedi: Re: Update contacts at Altera
        87490: 05/07/25: Antti Lukats: Re: Update contacts at Altera
            87592: 05/07/26: Jedi: Re: Update contacts at Altera
                87673: 05/07/27: Vaughn Betz: Re: Update contacts at Altera
87421: 05/07/23: Marc Battyani: Fastest way to compute floating point log and exp
    87424: 05/07/23: Ray Andraka: Re: Fastest way to compute floating point log and exp
        87452: 05/07/24: Marc Battyani: Re: Fastest way to compute floating point log and exp
    87431: 05/07/24: Philip Freidin: Re: Fastest way to compute floating point log and exp
        87453: 05/07/24: Marc Battyani: Re: Fastest way to compute floating point log and exp
        87476: 05/07/25: Ray Andraka: Re: Fastest way to compute floating point log and exp
    87447: 05/07/24: GMM50: Re: Fastest way to compute floating point log and exp
    87451: 05/07/24: Kolja Sulimma: Re: Fastest way to compute floating point log and exp
        88425: 05/08/17: Eric Smith: Re: Fastest way to compute floating point log and exp
87459: 05/07/24: <SantaBarbara350Z@gmail.com>: Problems installing windrvr.o in Red Hat EL3...
    87504: 05/07/25: Martin Thompson: Re: Problems installing windrvr.o in Red Hat EL3...
    87538: 05/07/25: SantaBarbara350Z@gmail.com: Re: Problems installing windrvr.o in Red Hat EL3...
87469: 05/07/24: im.de: DCM.
    87480: 05/07/25: Antti Lukats: Re: DCM.
    87481: 05/07/25: Jerzy Gbur: Re: DCM.
    87497: 05/07/25: dexue: Re: DCM.
    87501: 05/07/25: Vladislav Muravin: Re: DCM.
    87505: 05/07/25: austin: Re: DCM.
87479: 05/07/24: arie: Excalibur full strip simulation on solaris.
    87493: 05/07/25: Antti Lukats: Re: Excalibur full strip simulation on solaris.
        87513: 05/07/25: Phil Hays: Re: Excalibur full strip simulation on solaris.
            87515: 05/07/25: Antti Lukats: Re: Excalibur full strip simulation on solaris.
                87520: 05/07/25: Phil Hays: Re: Excalibur full strip simulation on solaris.
                    87521: 05/07/25: Antti Lukats: Re: Excalibur full strip simulation on solaris.
                        87540: 05/07/26: Antti Lukats: Re: Excalibur full strip simulation on solaris.
    87536: 05/07/25: arie: Re: Excalibur full strip simulation on solaris.
    87594: 05/07/26: arie: Re: Excalibur full strip simulation on solaris.
87506: 05/07/25: Giox: How to look inside a RAM memory
    87512: 05/07/25: <ALuPin@web.de>: Re: How to look inside a RAM memory
    87522: 05/07/25: jimwu88NOOOSPAM@yahoo.com: Re: How to look inside a RAM memory
    87565: 05/07/25: Giox: Re: How to look inside a RAM memory
87516: 05/07/25: Amr Ahmadain: Exact time-to-Failure data for FPGA devices
    87517: 05/07/25: Peter Alfke: Re: Exact time-to-Failure data for FPGA devices
    87529: 05/07/25: austin: Re: Exact time-to-Failure data for FPGA devices
    87547: 05/07/25: Amr Ahmadain: Re: Exact time-to-Failure data for FPGA devices
    87555: 05/07/25: Peter Alfke: Re: Exact time-to-Failure data for FPGA devices
    87558: 05/07/25: Amr Ahmadain: Re: Exact time-to-Failure data for FPGA devices
    87562: 05/07/25: Peter Alfke: Re: Exact time-to-Failure data for FPGA devices
87523: 05/07/25: Antti Lukats: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
    87525: 05/07/25: Martin Schoeberl: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
        87530: 05/07/25: Antti Lukats: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
            87546: 05/07/26: Jim Granville: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
                87566: 05/07/26: Antti Lukats: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
                    87596: 05/07/27: Jim Granville: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
                        87597: 05/07/26: Antti Lukats: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
                            87598: 05/07/27: Jim Granville: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
                                87599: 05/07/26: Antti Lukats: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
    87604: 05/07/26: Franklin: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
        87612: 05/07/27: Antti Lukats: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
            87616: 05/07/27: Jim Granville: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
            87811: 05/08/01: Ray Andraka: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
87524: 05/07/25: <apsolar@rediffmail.com>: How to implement Evolvable Hardware ?
87526: 05/07/25: Teo: Free 8 bit micro for fpga
    87528: 05/07/25: austin: Re: Free 8 bit micro for fpga
        87534: 05/07/25: Antti Lukats: Re: Free 8 bit micro for fpga
            88027: 05/08/06: dave: Re: Free 8 bit micro for fpga
        87544: 05/07/26: Antti Lukats: Re: Free 8 bit micro for fpga
            87550: 05/07/26: Jim Granville: Re: Free 8 bit micro for fpga
    87531: 05/07/25: Gabor: Re: Free 8 bit micro for fpga
    87569: 05/07/26: Jon Beniston: Re: Free 8 bit micro for fpga
    87580: 05/07/26: uxello: Re: Free 8 bit micro for fpga
87527: 05/07/25: praetorian: Virtex 2 Pro Routing Constraints
    87567: 05/07/26: Antti Lukats: Re: Virtex 2 Pro Routing Constraints
    87568: 05/07/26: Sven: Re: Virtex 2 Pro Routing Constraints
87533: 05/07/25: Yaju Nagaonkar: VHDL soft-core portability to Xilinx, Altera, Atmel....
    87537: 05/07/25: Mike Treseler: Re: VHDL soft-core portability to Xilinx, Altera, Atmel....
        87539: 05/07/25: Antti Lukats: Re: VHDL soft-core portability to Xilinx, Altera, Atmel....
            87542: 05/07/26: Antti Lukats: Re: VHDL soft-core portability to Xilinx, Altera, Atmel....
                87713: 05/07/29: Ben Popoola: Re: VHDL soft-core portability to Xilinx, Altera, Atmel....
    87541: 05/07/25: Yaju Nagaonkar: Re: VHDL soft-core portability to Xilinx, Altera, Atmel....
87543: 05/07/25: johnp: Virtex4 local clock timing
    87710: 05/07/28: Marc Randolph: Re: Virtex4 local clock timing
    87733: 05/07/29: johnp: Re: Virtex4 local clock timing
87554: 05/07/25: Andrew FPGA: Distributed Arithmetic Architecture - LUT Contents
    87810: 05/08/01: Ray Andraka: Re: Distributed Arithmetic Architecture - LUT Contents
87570: 05/07/26: mike: comprehension of clck to pad,clock to setup,etc
    87585: 05/07/26: Vladislav Muravin: Re: comprehension of clck to pad,clock to setup,etc
87571: 05/07/26: hata: Soft IPs licensing
    87593: 05/07/26: Antti Lukats: Re: Soft IPs licensing
    87707: 05/07/29: James Harry: Re: Soft IPs licensing -gpl
87577: 05/07/26: Confused Frank (Remove the dots): Confused with "task" keyword.
87578: 05/07/26: uxello: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG
    87579: 05/07/26: Antti Lukats: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
        87581: 05/07/26: uxello: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with
        87631: 05/07/27: MM: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
            87633: 05/07/27: Antti Lukats: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
                87695: 05/07/28: MM: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
                    87697: 05/07/28: Antti Lukats: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
                    87748: 05/07/30: Kissingers: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
87582: 05/07/26: <bazogec@hotmail.com>: chipscope on opb bus
    87583: 05/07/26: Antti Lukats: Re: chipscope on opb bus
87586: 05/07/26: <llabakdas@gmail.com>: Asynchronous Priority comparator
    87818: 05/08/02: backhus: Re: Asynchronous Priority comparator
    87857: 05/08/02: Andrew FPGA: Re: Asynchronous Priority comparator
    88247: 05/08/12: <llabakdas@gmail.com>: Re: Asynchronous Priority comparator
87588: 05/07/26: George Mercury: The new IOBUF in Spartan-3E
    87609: 05/07/27: Daniel Koethe: Re: The new IOBUF in Spartan-3E
87589: 05/07/26: Yttrium: LVDS problem/chipscope VIRTEX4
87591: 05/07/26: <skatoulas@hotmail.com>: ISE makes a mistake
    87600: 05/07/26: Mike Treseler: Re: ISE makes a mistake
87605: 05/07/27: hpg: Xilinx Foundation ISE and WinXP/x64?
    87606: 05/07/27: Keith So: Re: Xilinx Foundation ISE and WinXP/x64?
        87614: 05/07/27: Jim Wu: Re: Xilinx Foundation ISE and WinXP/x64?
87607: 05/07/26: sarath: Conversion of ASIC RTL to FPGA RTL
    87611: 05/07/27: <usenet_10@stanka-web.de>: Re: Conversion of ASIC RTL to FPGA RTL
    87626: 05/07/27: Vladislav Muravin: Re: Conversion of ASIC RTL to FPGA RTL
    87641: 05/07/27: Ben Twijnstra: Re: Conversion of ASIC RTL to FPGA RTL
    87685: 05/07/28: <neeraj_varma@yahoo.com>: Re: Conversion of ASIC RTL to FPGA RTL
87608: 05/07/26: Jack: how to measure number of cycles in ISE6.3
    87646: 05/07/27: Martin Thompson: Re: how to measure number of cycles in ISE6.3
87610: 05/07/27: efim: WEB Pack 7.1 and registry access
87615: 05/07/27: Rene Tschaggelar: Datasheet error in the Altera Cyclone 2C8F256 pindescription
    87619: 05/07/27: Karl: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
    87621: 05/07/27: Ben Twijnstra: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
        87624: 05/07/27: Rene Tschaggelar: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
            87635: 05/07/27: Thomas Entner: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
                87639: 05/07/27: Ben Twijnstra: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
                    87672: 05/07/27: Vaughn Betz: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
                        87678: 05/07/28: Ben Twijnstra: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
    87629: 05/07/27: Karl: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
    88383: 05/08/16: Albert Chang: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
87617: 05/07/27: Monica: QuartusII 4.2 problem
    87618: 05/07/27: Paul Solomon: Re: QuartusII 4.2 problem
    87625: 05/07/27: <skatoulas@hotmail.com>: Re: QuartusII 4.2 problem
87627: 05/07/27: Strelnikov: isplever and GAL
    87637: 05/07/27: Teo: Re: isplever and GAL
        87658: 05/07/28: Jim Granville: Re: isplever and GAL
            87659: 05/07/27: Antti Lukats: Re: isplever and GAL
        87675: 05/07/28: Strelnikov: Re: isplever and GAL
87628: 05/07/27: Vladislav Muravin: question for Xilinx ppl
    87677: 05/07/28: zeeman_be: Re: question for Xilinx ppl
        87689: 05/07/28: Vladislav Muravin: Re: question for Xilinx ppl
87632: 05/07/27: Matthew Plante: bmm file and ramb16
    87634: 05/07/27: Antti Lukats: Re: bmm file and ramb16
        87636: 05/07/27: Matthew Plante: Re: bmm file and ramb16
            87638: 05/07/27: Antti Lukats: Re: bmm file and ramb16
87640: 05/07/27: Pablo Alvarez Sanchez: Reset and Power-On Reset Activation XCFxxP PROMs
    87653: 05/07/27: austin: Re: Reset and Power-On Reset Activation XCFxxP PROMs
        87681: 05/07/28: Pablo Alvarez Sanchez: Re: Reset and Power-On Reset Activation XCFxxP PROMs
87643: 05/07/27: pasacco: simulatable but not synthesizable (verifiable)
    87645: 05/07/27: Jonathan Bromley: Re: simulatable but not synthesizable (verifiable)
        87647: 05/07/27: Gunther Mannigel: Re: simulatable but not synthesizable (verifiable)
    87648: 05/07/27: pasacco: Re: simulatable but not synthesizable (verifiable)
87649: 05/07/27: <mwiesbock@gmail.com>: wishbone core with ethernet, hierarchy / architecture
87650: 05/07/27: Kaalia Anthony: stratix gx query
    87663: 05/07/27: Ben Twijnstra: Re: stratix gx query
87651: 05/07/27: Tim Verstraete: chipscope/impact Virtex4 problem
    87652: 05/07/27: Antti Lukats: Re: chipscope/impact Virtex4 problem
    87669: 05/07/27: Jim Wu: Re: chipscope/impact Virtex4 problem
    87680: 05/07/28: Tim Verstraete: Re: chipscope/impact Virtex4 problem
    87684: 05/07/28: Tim Verstraete: Re: chipscope/impact Virtex4 problem
87654: 05/07/27: geoffrey wall: No clock signals found in this design... XST V2P
    87657: 05/07/27: Vladislav Muravin: Re: No clock signals found in this design... XST V2P
87655: 05/07/27: Chris Carlen: Delay Generators in FPGAs
    87661: 05/07/27: Antti Lukats: Re: Delay Generators in FPGAs
    87664: 05/07/27: John Larkin: Re: Delay Generators in FPGAs
        87699: 05/07/29: Jim Granville: Re: Delay Generators in FPGAs
    87665: 05/07/27: Peter Alfke: Re: Delay Generators in FPGAs
    87671: 05/07/27: Marc Randolph: Re: Delay Generators in FPGAs
    87692: 05/07/28: austin: Re: Delay Generators in FPGAs
    87709: 05/07/28: Marc Randolph: Re: Delay Generators in FPGAs
87660: 05/07/27: Matthew Plante: dual port ram
87667: 05/07/27: <ckpun1978@gmail.com>: How to pass parameters to do file in commandline when running vsim?
    87679: 05/07/28: Jonathan Bromley: Re: How to pass parameters to do file in commandline when running vsim?
    87701: 05/07/28: <ckpun1978@gmail.com>: Re: How to pass parameters to do file in commandline when running vsim?
87674: 05/07/27: beeraka@gmail.com: How to import a netlist in VHDL
    87756: 05/07/30: Gladiator: Re: How to import a netlist in VHDL
87682: 05/07/28: <ALuPin@web.de>: Remove Duplicate Registers / Logic
    87711: 05/07/28: Alex: Re: Remove Duplicate Registers / Logic
    87714: 05/07/29: <ALuPin@web.de>: Re: Remove Duplicate Registers / Logic
87683: 05/07/28: Stefan: GLCKs on Spartan3
    87688: 05/07/28: Vladislav Muravin: Re: GLCKs on Spartan3
        87719: 05/07/29: Stefan: Re: GLCKs on Spartan3
    87729: 05/07/29: jimwu88NOOOSPAM@yahoo.com: Re: GLCKs on Spartan3
87690: 05/07/28: Hagen2: Synplify 8.1 - View Synthesis Report
    87717: 05/07/29: Hagen2: re:Synplify 8.1 - View Synthesis Report
87694: 05/07/28: Brandon: XST and TCL support?
    87704: 05/07/28: Andy Peters: Re: XST and TCL support?
        87706: 05/07/28: Jim Wu: Re: XST and TCL support?
    87720: 05/07/29: Guenter: Re: XST and TCL support?
    87721: 05/07/29: Ben Twijnstra: Re: XST and TCL support?
    87886: 05/08/03: Brandon: Re: XST and TCL support?
    87891: 05/08/03: gallen: Re: XST and TCL support?
87696: 05/07/28: geoffrey wall: chipscope and V2P problems
    89189: 05/09/07: Gardovan: re:chipscope and V2P problems
87698: 05/07/28: <geert@user1.be>: Logic lab programmer
87702: 05/07/28: <do_not_reply_to_this_addr@yahoo.com>: Digilent's JTAG-USB cable with chipscope
    87705: 05/07/28: Paul Hartke: Re: Digilent's JTAG-USB cable with chipscope
    87766: 05/08/01: Antti Lukats: Re: Digilent's JTAG-USB cable with chipscope
        87819: 05/08/02: Antti Lukats: Re: Digilent's JTAG-USB cable with chipscope
            87872: 05/08/03: Antti Lukats: Re: Digilent's JTAG-USB cable with chipscope
            88427: 05/08/17: Eric Smith: Re: Digilent's JTAG-USB cable with chipscope
                89032: 05/09/03: James Horn: Re: Digilent's JTAG-USB cable with chipscope
    87803: 05/08/01: <do_not_reply_to_this_addr@yahoo.com>: Re: Digilent's JTAG-USB cable with chipscope
87712: 05/07/29: Jeremy Stringer: 2-bit RAM16X In a V2PRo
87724: 05/07/29: Michael: VHDL 200x? when?
    87728: 05/07/29: Andy Peters: Re: VHDL 200x? when?
        87731: 05/07/29: Joel Kolstad: Re: VHDL 200x? when?
87730: 05/07/29: Brad Smallridge: Spartan3 Done is not going high
    87732: 05/07/29: skherich: Re: Spartan3 Done is not going high
        87735: 05/07/29: Brad Smallridge: Re: Spartan3 Done is not going high
        87738: 05/07/29: Brad Smallridge: Re: Spartan3 Done is not going high
87740: 05/07/29: fpga: question about use SRAM on annapolis wildstarII board
    87767: 05/08/01: <ALuPin@web.de>: Re: question about use SRAM on annapolis wildstarII board
    87772: 05/08/01: Karl: Re: question about use SRAM on annapolis wildstarII board
    87773: 05/08/01: <ALuPin@web.de>: Re: question about use SRAM on annapolis wildstarII board
87741: 05/07/29: Chet Stemen: Xilinx ISE WebPACK-7.1i on NetBSD
    87743: 05/07/30: Chet Stemen: Re: Xilinx ISE WebPACK-7.1i on NetBSD
87742: 05/07/29: Andrew Lohbihler: Farrow filter VHDL implementation?
87744: 05/07/30: Chet Stemen: Xilinx ISE WebPACK-7.1i on NetBSD
    89758: 05/09/25: Darius: re:Xilinx ISE WebPACK-7.1i on NetBSD
    90122: 05/10/05: Darius: re:Xilinx ISE WebPACK-7.1i on NetBSD
87745: 05/07/30: vssumesh: About post synthesize
    87764: 05/07/31: vssumesh: Re: About post synthesize
        87786: 05/08/01: Vladislav Muravin: Re: About post synthesize
            87969: 05/08/04: Vladislav Muravin: Re: About post synthesize
                88153: 05/08/10: Vladislav Muravin: Re: About post synthesize
    87781: 05/08/01: vssumesh: Re: About post synthesize
    87869: 05/08/02: vssumesh: Re: About post synthesize
    87996: 05/08/04: vssumesh: Re: About post synthesize
87747: 05/07/30: <googlinggoogler@hotmail.com>: ISE webpack doesnt support Spartan xcs10, solution??
    87749: 05/07/30: John Adair: Re: ISE webpack doesnt support Spartan xcs10, solution??
    87750: 05/07/30: Guenter: Re: ISE webpack doesnt support Spartan xcs10, solution??
    87751: 05/07/30: <googlinggoogler@hotmail.com>: Re: ISE webpack doesnt support Spartan xcs10, solution??
        87760: 05/07/31: David Tweed: Re: ISE webpack doesnt support Spartan xcs10, solution??
    87753: 05/07/30: <googlinggoogler@hotmail.com>: Re: ISE webpack doesnt support Spartan xcs10, solution??
    87815: 05/08/01: Pedro: Re: ISE webpack doesnt support Spartan xcs10, solution??
87752: 05/07/30: <pinod01@sympatico.ca>: Altera Avalon Address format between Master & SDRAM controller?
    87788: 05/08/01: <kempaj@yahoo.com>: Re: Altera Avalon Address format between Master & SDRAM controller?
87754: 05/07/30: Telenochek: struggling with general digital design
    87763: 05/07/31: MM: Re: struggling with general digital design
        87801: 05/08/01: Mike Treseler: Re: struggling with general digital design
        87816: 05/08/02: MM: Re: struggling with general digital design
    87765: 05/07/31: vssumesh: Re: struggling with general digital design
    87769: 05/08/01: Jon Beniston: Re: struggling with general digital design
    87774: 05/08/01: <ALuPin@web.de>: Re: struggling with general digital design
    87780: 05/08/01: vssumesh: Re: struggling with general digital design
    87791: 05/08/01: Andy Peters: Re: struggling with general digital design
    87792: 05/08/01: Andy Peters: Re: struggling with general digital design
    87795: 05/08/01: Telenochek: Re: struggling with general digital design
87759: 05/07/31: ravindra kalla: FPGA
    87778: 05/08/01: <ALuPin@web.de>: Re: FPGA
87761: 05/07/31: lik: some virtexII clock pads are useless??
    87762: 05/07/31: Philip Freidin: Re: some virtexII clock pads are useless??
    87779: 05/08/01: Vladislav Muravin: Re: some virtexII clock pads are useless??
        87825: 05/08/02: Symon: Re: some virtexII clock pads are useless??
            87838: 05/08/02: Vladislav Muravin: Re: some virtexII clock pads are useless??
    88531: 05/08/22: Victor: Re: some virtexII clock pads are useless??


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