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I'm using the ISE WebPack version and have just got a Platform USB cable. Could anyone give me a clue as to how I install the drivers for the cable please? Documentation seems to say I need the ISE installation CDs but of course with WebPack I don't have any. TIA. Rog.Article: 89026
Using a LED with a forward voltage similar to that available is likely to give problems. The series resistor normally fitted gives a determination of currrent but does need some voltage itself. The smaller the notional voltage used across the resistor the wider the span of currents that may result due to tolerances. In short using small resistor voltage gives relatively un-predicatable currents. No resistor at all is asking for a LED meltdown assuming it actually lights at all. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk <denizdikmen@gmail.com> wrote in message news:1125575027.735673.124800@g44g2000cwa.googlegroups.com... > Hello, > > I want to connect a LED with Uf=1.8V and If=20mA to a CPLD (XC2C512). > But from the datasheet I get that the current is limited to I_OH and > I_OL = 8mA. Is this right? Means this that I couldn't use this LED with > 1.8V? Have I to operate the LED with 8mA and the corresponding voltage > (using a resistor in series)? > > Regards > Deniz >Article: 89027
We should have something for you in Raggedstone1 when it launches if you want to play with this. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Mike Harrison" <mike@whitewing.co.uk> wrote in message news:6evbh15t3h637dafnv0qobaplj710kg9uj@4ax.com... > Does anyone know how feasible it is to drive a TFT panel LVDS interface > (sometimes called Panel-link > I think) direct from the S3 I/Os ? If so, what sort of frequency can you > get up to - I saw a mention > recently about using the DDR registers to reduce the data rate but > couldn't immediately see any > Xilinx appnotes when I had a quick look. > > Also, as the IO banks on the lower-end dev boards tend to be tied to > +3.3v, but LVDS needs 2.5v, > what happens if you lie to the software about the supply - will it work to > any useful degree > (interested in lvds output only)?Article: 89028
I agree with everyone else and you are unlikely to get much for these. Spartan-3 that we use a lot of are broadly similar in performance to the 1M gate mentioned. The equivalent S3 is about 1/50, or less, of the figure you mentioned. Your only hope is to find a very long life design, still in manufacture, and still using them. Not easy to do and then you get a whole load of questions on where they came from etc etc. At best you will sell them at a significant discount at worst there is a good chance you won't find a buyer at all. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Ray Andraka" <ray@andraka.com> wrote in message news:QrMRe.7895$dm.4556@lakeread03... > Ram wrote: > >>Vladislav: >> >>Vladislav Muravin wrote: >> >> >>>First, I understand your situation and solidate with you. >>> >> >>Thank you. >> >> >>>Second, despite that DigiKey list those FPGAs for such high price, which >>>may be a bit old (?), the same devices from Virtex-II family are much >>>cheaper than the ones you have been screwed up with, if you check with >>>the >>>distributor. Check out also the prices for similar devices, so that you >>>would not be screwed up with the offer... >>> >> >>I understand. >> >>Two or three other people also wrote me and told me that these parts are >>out >>of date and that there are newer parts which are cheaper, therefore I >>would >>probably not get very much per device. >> >>As I said, I simply wish to recover what I can. Therefore, as long as the >>offer isn't insulting (such as 50 cents per chip), I would still entertain >>it. >> >>Thank you all for your kindness. >> >>Ram. >> > Your best bet may be to ebay the lot. The XCV1000-4's are the oldest of > the virtex line. The price you quoted is close to the price Xilinx asked > when these were the latest and greatest (btw, the 1000's were the biggest > in that family). That family has been superceded several times over > (virtexE, then virtex2 then virtex2pro and now virtex4), and even the low > cost Spartan3 line now reaches this 1M gate density, and will > significantly outperform it at a greatly reduced cost. BTW,, Digi-key's > chip prices for Xilinx have historically been way higher than you can get > the chips from just about any place else. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com http://www.andraka.com > "They that give up essential liberty to obtain a little temporary safety > deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 89029
My apologies - the case number was primarily for Austin's use if he wanted to see the traffic in the AE group about what has transpired so far. I don't know that the case can be accessed through mysupport by those who didn't submit the case. "huangjie" <huangjielg@gmail.com> wrote in message news:1125684166.632535.180980@o13g2000cwo.googlegroups.com... > John_h Wrote "My case # is 597160 if you'd like to track down the > active case to see > what's going on". > Where to find more information about case # 597160 ?Article: 89030
denizdikmen@gmail.com wrote: > Hello, > > I want to connect a LED with Uf=1.8V and If=20mA to a CPLD (XC2C512). > But from the datasheet I get that the current is limited to I_OH and > I_OL = 8mA. Is this right? Means this that I couldn't use this LED with > 1.8V? Have I to operate the LED with 8mA and the corresponding voltage > (using a resistor in series)? Look at the MAX DC voltage specifications, and the Typical I/O curves. Vol is < 0.4V @ 8mA, or 50 ohms (Max) RdsON. Typical is just over 2x beter than the worst case, and Typical current is ~30mA, so a worst-case port might deliver only 15mA (and still be in-spec) - thus 20mA is pushing it, from a single pin, for volume production. You can draw a load-line on the I/O curves, to see the LED current. eg assume a 3.3Vcc, and 1.8V Vf on LED, your load line will start at X=1.5V, and will hit the Y axis at 1.5V/Rseries A Y intercept of 30mA is appx 50 Ohms, and the Vol curve intercepts the 1.5V<=>30mA load line, at appx 22mA A 100 Ohms load line, gives ~12.5mA etc. -jgArticle: 89031
John_H wrote: > Isn't there a limited warranty printed on the CD jacket pushing > responsibility of a bad CD back onto the publisher? The book distributor > doesn't have that responsibility. > > And you *have* tried reading the CD on another machine, right? > > > > "Gra" <spamless-news@wildpossum.com> wrote in message > news:df8t6b$4ui$1@nnrp.waia.asn.au... >> Hi All. >> >> First off - Apologies if anyone considers this not the place to post such >> information - but I am getting desperate. >> >> I am self-studying the book "Advance Digital Design with the Verilog HDL" > by >> Michael D. Ciletti. Unfortunately the original CD supplied with the book >> was blank. So I went back to the local book distributor and after waiting >> some weeks got a replacement. The replacement CD has several sector >> errors and refuses to load at about half way through installation. The >> local distributor now doesn't want to know me or about my problem, Even >> after I paid ~15% of my weekly wage on his product. >> >> I would like to ask anyone who has the same CD, if they would kindly > supply Hi John. I have tried it on several other machines, both Windoze & Linux. Same results. Anyone person I know who purchased the book locally has the same issue - blank CD. So it looks like not a local problem, rather a problem with the original manufacture of the CD for Prentice-Hall. -- Cheers Grahame (grahame at location of wildpossum dot com) Spam Deflector ;-)Article: 89032
Indeed - for US$150 it's a good deal. It's a USB2.0 High Speed cable that can handle 25Mbps through the JTAG port. I just got one two weeks ago and, after struggling a bit to understand how to get ChipScope Pro running properly, promptly debugged and verified a Spartan 3 VHDL design written by someone else. Not bad for an old Altera AHDL weenie, if I say so myself. Thanks for a fine toolset, Xilinx! Jim Horn, Sonoma County CaliforniaArticle: 89033
Hello, Roger - Same installation here on my Toshiba A35 laptop with WinXPHome. I just plugged in the cable and let it find the drivers. Works fine. Jim Horn, Sonoma County CaliforniaArticle: 89034
>>> I am self-studying the book "Advance Digital Design with the Verilog >>> HDL" >> by >>> Michael D. Ciletti. Unfortunately the original CD supplied with the >>> book I also have that book. I didn't find the CD of much use. Install the free Xilinx webpack edition, and you're ok. You can also dowload errata, examples, etc. from author's site: http://eceweb.uccs.edu/ciletti/ I did also like a lot Palnitkar, "Verilog HDL", 2nd ed., Prentice Hall. Clear, concise, up to date.Article: 89035
<amir.intisar@gmail.com> schrieb im Newsbeitrag news:1125693351.090847.157570@g14g2000cwa.googlegroups.com... > Hey Folks, > i have a question about the RAM instantiations for the > Spartan 3(XC3S200) in the Xilinx verilog templates. You can instantiate > different types of SRAM sizes and bit widths, like 16K x 1, 2K x 8, > 512K x 32, but what if a user wants use the SRAM in a 256K x 16 format, > or something else not displayed in the templates?. Can this be done ?? The templates are just the basic primitives that represent 1 BRAM in different configurations. If you need larger RAM arrays, you have to combine multiple BRAMs by hand. Or use Core generator. > Also, the clock parameter (clk) in the instantiations, does this neeed > to be 100 Mhz, same as the SRAM clock frequency?. Do i need to use the ?? Dunno about this. I guess it's just for simulation. Regards FalkArticle: 89036
Hallo, which is the best way to sum 8 datas stored into a block ram? Many Thanks Marco ToschiArticle: 89037
"Marco" <marcotoschi@nospam.it> wrote in message news:dfbq24$64r$1@news.ngi.it... > Hallo, > which is the best way to sum 8 datas stored into a block ram? > > Many Thanks > Marco Toschi > Accumulator. Adder with output register connected back to one adder input, block RA< connected to other input. 1. Clear register 2. Step through block RAM addresses and clock accumulator register at end of each address cycle. 3. After n cycles (8?) result is in output of accumulator. SlurpArticle: 89038
<zoinks@mytrashmail.com> wrote in message news:1125675810.601949.45830@o13g2000cwo.googlegroups.com... >I just installed and updated both the EDK and ISE 7.1 > I'm using the XUP Virtex-II Pro, and downloaded the accompanying BSB > package. > > When I generate a design using BSB (selecting the XUP as a design > platform of course) I notice two things: > > A second DDR memory is added to the peripheral list, altough I have no > idea where it comes from and what it does (it's called > DDR-DRAM<something>). However, the biggest problem is that I cannot > start the bitstream generation, it quits immediatly with: > > ERROR:MDT - Invalid target architecture 'xc2vp30ff896-7' > ERROR:MDT - Invalid target architecture '' > ERROR:MDT - platgen failed with errors! > make: *** [implementation/system.bmm] Error 2 > Done. > > How can I fix this? Any help would be appreciated. > Installed any service packs yet ? 7.1 was unuseable for me without service packs for exactly the same setup. AlexArticle: 89039
Hi, I'm trying to reimplement the design at <http://themotionstore.com/leeedavison/6502/ide/index.html> in Verilog, targetting a Xilinx CPLD. Problem is, I've got all the GAL equations translated, but I can't work out how to handle the latches and buffers. Why am I doing this? Because I'm out of 74LS chips and all my suppliers are closed until Monday... Basically, when /LDW goes active, the top-right '574 latches in the data on D[0..7]. When /UDW goes active, the bottom-right '244 passes the data on D[0..7] straight onto ID[8..15] and the top-right '574's output is enabled. Reading is fairly simple too - /LDR goes active, the bottom-left '574 latches ID[8..15] and the top-left '245 passes the data on ID[0..7] onto D[0..7]. When /UDR goes active, the '244 is inactive and the '574's output gets enabled (ID[8..15] data gets popped onto the D[0..7] bus). Pretty simple on paper. How would you go about modelling this circuit in Verilog? Can anyone offer me some hints or suggestions? Thanks, -- Phil. | Acorn RiscPC600 SA220 64MB+6GB 100baseT philpem@despammed.com (valid address)| Athlon64 3200+ A8VDeluxe R2 512MB+100GB http://www.philpem.me.uk/ | Panasonic CF-25 Mk.2 Toughbook No software patents! <http://www.eff.org/> / <http://www.ffii.org/>Article: 89040
The individual BlockRAMs can go to 512x32, not 512kx32 (512x36, actually, thanks to the available undedicated parity bits). To get 256k x 32, you'd need about 256 BlockRAMs which wouln''t come close to fitting in an XC3S200. If you mean 256x32, you just need to instantiate one 512x36 and tie the MSbit of the address to 0. Both ports are read and/or write. Each port requires a clock for the operation to occur. There is no "SRAM clock frequency" but a frequency for the access at each port. This can be 100 MHz, 200 MHz, 50 MHz.... what are your needs? This determines which clocks you feed to the BlockRAMs. If you need 512kBytes, you need an external memory, no ways around it. <amir.intisar@gmail.com> wrote in message news:1125693351.090847.157570@g14g2000cwa.googlegroups.com... > Hey Folks, > i have a question about the RAM instantiations for the > Spartan 3(XC3S200) in the Xilinx verilog templates. You can instantiate > different types of SRAM sizes and bit widths, like 16K x 1, 2K x 8, > 512K x 32, but what if a user wants use the SRAM in a 256K x 16 format, > or something else not displayed in the templates?. Can this be done ?? > > Also, the clock parameter (clk) in the instantiations, does this neeed > to be 100 Mhz, same as the SRAM clock frequency?. Do i need to use the > DCM to double the FPGA clock frequency?. > > Thanks !!!Article: 89041
Dealers' choice. (designers' choice, actually) Your simulations will show you what looks "good" but if QDR II has the same on-die terminations for SSTL style signals like DDR II does, the point-to-point can be happy with one end terminated as long as the traces are short. Some FPGAs don't have convenient source resistors available, either as series resistors or as source-parallel terminations to Vcco/2. You just need valid logic levels (sometimes requiring a load) and rise times that are several times the round trip delay of your circuit path. If you have those, terminations aren't needed for SI reasons as your SI tools will show. "Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote in message news:11hh9e53hkofdd6@corp.supernews.com... > Hello, > > I'm designing a board with DDR and QDR II memories. When I look at the > memory design reference of the FPGA manufacturers, all the signals are > terminated by resistors. But when I look at the memory manufacturers app > notes they say that in the case of single memory chip (point to point) > configuration only a source resistor is needed. As modern FPGAs have builtin > controlled source impedance there should be not resistor at all. (QDRII > memories have controlled drivers too) > > So who is right here? > (And yes, I will have the design simulated before producing the boards > anyway ;-) > > MarcArticle: 89042
Hello all, I am interested in designing a custom board with serial interface and I am searching for RS232 port driver ICs which can support baud rates higher than 230kbps. There are many PCI or USB to serial interface options available which support bauds of upto 920kbps. I have designed a UART interface in FPGA but need higher baud rate driver ics to actaully get the performance I require. Any recommendations? Thanks MakArticle: 89043
Hi : I am just completing a control system implemented on a Cyclone using Quartus, entirely in schematic with loads of Mega Functions. The chip is getting full. When I look at a the resource usage, it is noticeable how much the many 12x12 signed multipliers are using. I played with the pipelining option in Mega Wizard, but after adding a pipe of 1, no further reduction in LE count is obtained by additional pipelining (I guess it's the same implementation with post latching). So what I plan to do is implement a signed 12x12 long multiply (probably as an unsigned block with absoluting, saturating and re-signing functions around it) I can picture the schematic for doing this in my mind (4x4 multiply(maybe as a LUT), 24 bit accumulator and a state-counter controlled muxing scheme to allocate "x16^n" shifting to the 9 multiplicands as they are accumulated) Whilst I do enjoy re-inventing the wheel, it occurs to me that someone must have a VHDL implementation of this somewhere. Can anybody point me at VHDL code for this ? Thanks GaryArticle: 89044
"Mak" <mansoor.naseer@gmail.com> schrieb im Newsbeitrag news:1125778063.960873.207120@g43g2000cwa.googlegroups.com... > There are many PCI or USB to serial interface options available which > support bauds of upto 920kbps. I have designed a UART interface in FPGA > but need higher baud rate driver ics to actaully get the performance I > require. Use RS422 or RS485. This tranceivers support up to 10 Mbit/s. Much more recommended than RS232 (differential, lower voltage swing, EMC etc.) Regards FalkArticle: 89045
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3nugdcF3d1k8U1@individual.net... > "Mak" <mansoor.naseer@gmail.com> schrieb im Newsbeitrag > news:1125778063.960873.207120@g43g2000cwa.googlegroups.com... > >> There are many PCI or USB to serial interface options available which >> support bauds of upto 920kbps. I have designed a UART interface in FPGA >> but need higher baud rate driver ics to actaully get the performance I >> require. > > Use RS422 or RS485. This tranceivers support up to 10 Mbit/s. Much more > recommended than RS232 (differential, lower voltage swing, EMC etc.) > > Regards > Falk > > > Or if you want to go even faster use LVDS. SlurpArticle: 89046
Mak wrote: > Hello all, > > I am interested in designing a custom board with serial interface and I > am searching for RS232 port driver ICs which can support baud rates > higher than 230kbps. > > There are many PCI or USB to serial interface options available which > support bauds of upto 920kbps. I have designed a UART interface in FPGA > but need higher baud rate driver ics to actaully get the performance I > require. > > Any recommendations? I think you are asking about the level translators ? You have tried the usual suspects at Maxim and Linear ? You might also want a 3.3V supply interface device. http://www.maxim-ic.com/Interface.cfm shows 150 devices under "RS-232 Line Driver/Receivers" -jgArticle: 89047
On Sat, 03 Sep 2005 19:58:18 +0100, Philip Pemberton <philpem@despammed.com> wrote: >Hi, > I'm trying to reimplement the design at ><http://themotionstore.com/leeedavison/6502/ide/index.html> in Verilog, >targetting a Xilinx CPLD. Problem is, I've got all the GAL equations >translated, but I can't work out how to handle the latches and buffers. Why am >I doing this? Because I'm out of 74LS chips and all my suppliers are closed >until Monday... > > Basically, when /LDW goes active, the top-right '574 latches in the data on >D[0..7]. When /UDW goes active, the bottom-right '244 passes the data on >D[0..7] straight onto ID[8..15] and the top-right '574's output is enabled. > Reading is fairly simple too - /LDR goes active, the bottom-left '574 >latches ID[8..15] and the top-left '245 passes the data on ID[0..7] onto >D[0..7]. When /UDR goes active, the '244 is inactive and the '574's output >gets enabled (ID[8..15] data gets popped onto the D[0..7] bus). Pretty simple >on paper. > > How would you go about modelling this circuit in Verilog? Can anyone offer >me some hints or suggestions? > >Thanks, actually 574 is not a latch but a posedge DFF with tri-state outputs so you can model it as : module t74574(CK, OEB, D, Q); input CK, OEB; input [7:0] D; output [7:0] Q; reg [7:0] Qi; always @(posedge CK) Qi[7:0] <= D[7:0]; assign Q = OEB ? 8'hz : Qi; endmodule of course you have make sure that the pins of the CPLD are tristated and not internal signals so the OEB should control pins of the CPLD.Article: 89048
I can't fault that explanation, really! Just to say that the Xilinx apps note on the use of the hard embedded multipliers in Spartan 3 (http://direct.xilinx.com/bvdocs/appnotes/xapp467.pdf) has a great diagram on p.5 that perfectly illustrates this decomposition of a wide signed multiplication into narrower signed and unsigned products. Richard.Article: 89049
Hi Gary, Google for "distributed arithmetic". I'm sure plenty of people are ready and willing to sell you some VHDL! Cheers, Syms.
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