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Messages from 89075

Article: 89075
Subject: Re: I2C "SCL" line problem
From: Jim Granville <no.spam@designtools.co.nz>
Date: Mon, 05 Sep 2005 20:23:54 +1200
Links: << >>  << T >>  << A >>
praveen.kantharajapura@gmail.com wrote:
> Hi Falk,
> 
> We cannot go for the Scmitt trigger option , because the PCB's are
> already out.Could any thing be done to avoid flase triggering in FPGA's
> only.

  Falk mentioned using a higher frequency clock ( if you have one in the
FPGA already) and running a state engine.

  Other solutions are to lower the SCL pullup resistor, and so raise the 
dV/dT.

  You can also create delay line elements in the FPGA, and create a
SET-RESET latch: effectively a low pass system, so that rapid clocking
is not legal.

-jg

> 
> Regards,
> Prav
> 
> Falk Brunner wrote:
> 
>><alan@nishioka.com> schrieb im Newsbeitrag
>>news:1125649231.259165.250930@g43g2000cwa.googlegroups.com...
>>
>>
>>>I2C is an open-collector bus with a resistor pullup.
>>>So the falling edge is sharp and the rising edge is exponential.
>>>
>>>I would guess that the rising edge is too slow and is causing problems
>>>for your input buffer at the input threshold.
>>
>>Yes, you should use the schmitt trigger option for the input (if it is a
>>coolrunner-II)
>>I2C is terribly slow for nowadays CPLDs, so a rising edge can (and WILL)
>>have enough noise on it to make the CPLD see double edges.
>>I also suggest to NOT use SCL directly as a clock (for the given reason).
>>Use a "high speed" (lets say 10 MHz) clock to sample SDA/SCL and make your
>>state machine rung on this 10 MHz clock using the samples SDA/SCL.
>>
>>Regards
>>Falk
> 
> 


Article: 89076
Subject: Re: High baud rate chips for RS232 protocol
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Mon, 5 Sep 2005 20:37:55 +1200
Links: << >>  << T >>  << A >>
You will find 1M baud devices in the sipex web site.  Just don't expect more
than a few meters.
I think the suggestion of using a differential driver is best.

Simon

<langwadt@ieee.org> wrote in message
news:1125872100.874546.264110@g44g2000cwa.googlegroups.com...
>
> Jim Granville skrev:
>
> > Mak wrote:
> > > Hello all,
> > >
> > > I am interested in designing a custom board with serial interface and
I
> > > am searching for RS232 port driver ICs which can support baud rates
> > > higher than 230kbps.
> > >
> > > There are many PCI or USB to serial interface options available which
> > > support bauds of upto 920kbps. I have designed a UART interface in
FPGA
> > > but need higher baud rate driver ics to actaully get the performance I
> > > require.
> > >
> > > Any recommendations?
> >
> > I think you are asking about the level translators ?
> > You have tried the usual suspects at Maxim and Linear ?
> > You might also want a 3.3V supply interface device.
> >
> > http://www.maxim-ic.com/Interface.cfm
> > shows 150 devices under "RS-232 Line Driver/Receivers"
> >
> > -jg
>
> If you follow the rs-232 spec you can't go above ~115.2Kbit, to go
> above that you need a level translator that supports higher speeds,
> usually
> with an extra pin that enables a higher slew rate
>
> -Lasse
>



Article: 89077
Subject: Reprogramming one MAXII EPM1270 vs security bit set
From: "abeaujean@gillam-fei.be" <abeaujean@gillam-fei.be>
Date: 5 Sep 2005 02:08:44 -0700
Links: << >>  << T >>  << A >>
Hi group,

I would like to share an impression I have.

Trying to erase and/or reprogram one Altera MAXII EPM1270 device using
the Quartus 5.0 Sp1 Web free edition software and the ByteBlasterII
programming adapter kept on failing (same thing with ByteBlasterMV and
previous revision of the soft).

After considering lots of possibilities (missing pullups, pulldowns,
JTAG clock with glitches, although none observed), I finally decided to
have the component de-soldered and a new one resoldered.

IT NOW WORKS.

Re-thinking the whole thing from the start, I now wonder if this
behaviour is not due to the previous use of the security bit. I
remember I set the security bit once on that device (on two different
prototypes, both of which were exhibiting the same problem).

The security bit, once set, should I believe not prevent the component
from being erased and re-programmed (am I right or wrong ?). If you
read the MAXII specification, it seems so.

The symptoms were :

Error: Can't recognize silicon ID for device 1
Error: Operation failed

on both prototypes.

Both prototypes are now working with the new soldered components.

Has anyone experienced such a behaviour before ?

So, I do believe that the problem could be once the security bit is
set.

It could also be due to an incorrect definition of the length of two
non Altera devices part of this JTAG chain (4 instead of 16), but
anyway it is so strange that one could set a condition in the component
that prevents it from being re-programmed.

Software bug ?

Any idea ?


Article: 89078
Subject: Re: Reading internal signals through a testbench.
From: ALuPin@web.de
Date: 5 Sep 2005 02:12:55 -0700
Links: << >>  << T >>  << A >>
One possibility could be to route the internal signal
to an output pin.=20

Rgds
Andr=E9


Article: 89079
Subject: Re: Platform Cable USB
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Mon, 05 Sep 2005 09:34:22 GMT
Links: << >>  << T >>  << A >>
Jim,

Thanks. That's interesting as when I let Windows do its thing, it didn't 
work. I'll play around with it some more.

Rog.


"James Horn" <jimhorn@svn.net> wrote in message 
news:11hidadis35d0c9@corp.supernews.com...
> Hello, Roger -
>
> Same installation here on my Toshiba A35 laptop with WinXPHome.  I just 
> plugged in the cable and let it find the drivers.  Works fine.
>
> Jim Horn, Sonoma County California 



Article: 89080
Subject: Defining Environment variables inside EDK
From: Sylvain Munaut <com.246tNt@tnt>
Date: Mon, 05 Sep 2005 12:06:10 +0200
Links: << >>  << T >>  << A >>
Hi,

I need to define some environment variable to
change the behavior of the synthesis tool in order
for my design to compile (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING).

I'd like to define that inside the EDK project, without having to modify
my system or user wide environment. I've tried adding that to the
system_incl.make but that file is overwritten at each build ...

What's the proper way to do that ? The search I've done so far didn't
get many relevant results ...


	Sylvain

Article: 89081
Subject: Fastest input IOB on a Spartan-3?
From: Paul Boven <p.boven@chello.nl>
Date: Mon, 05 Sep 2005 13:01:31 +0200
Links: << >>  << T >>  << A >>
Hi everyone,

I'd like to know which input pin/IOB of the Spartan-3 would be able to 
toggle (divide by 2) the highest frequency input signal. From earlier 
postings by Peter Alfke I understand that not all IOBs are created equal 
in this respect, although I don't know how big the differences between 
individual IOBs would be. I'm building a frequency counter, and the 
higher the input it can handle, the better. What would be the highest 
frequency input signal? And which IO-standard to use for highest 
performance? Ultimately I will need to design an input 
amplifier/discriminator, so input IO-standard is not fixed yet.

Regards, Paul Boven.

Article: 89082
Subject: Re: Logic??
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Mon, 05 Sep 2005 12:11:31 +0100
Links: << >>  << T >>  << A >>
The OP question is "what logic ?" and the quick answer is ..."good logic"
Aurash

Kumar wrote:

>What logic is needed for the
>
>4 bit add pipe
>
>to write the VHDL program????
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Article: 89083
Subject: Re: XUP Virtex-II Pro "invalid target architecture"
From: "zoinks@mytrashmail.com" <zoinks@mytrashmail.com>
Date: 5 Sep 2005 04:37:13 -0700
Links: << >>  << T >>  << A >>
I installed the EDK and ISE service packs. I still get the same error,
even after re-creating the system from scratch

to use the XUP board I simply d/l-ed and copied the XUPv2P pack to a
dir and specified that during the BSB. Did I forget to do something?

With the peripheral list I mean the list that is shown at the end of
the BSB. In particular the drop-down list you see when you are to
select in which memory peripheral the test-software should be loaded.

All the weird behaviour only occurs when I choose to use external DDR
memory.

I'll post the project when I have access to it.


Article: 89084
Subject: Re: XUP Virtex-II Pro "invalid target architecture"
From: "zoinks@mytrashmail.com" <zoinks@mytrashmail.com>
Date: 5 Sep 2005 05:22:49 -0700
Links: << >>  << T >>  << A >>
ok I think I know what is wrong:

Something went wrong during the installation of the ISE or the SDK. In
my list of available devices, only some spartans and the Virtex2 and
Virtex4 are listed. When I select one of the virtex, the program gives
an error message that it cannot find the specified device size.

Is there a way to add those devices to the system?


Article: 89085
Subject: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
From: xvhdl <>
Date: Mon, 5 Sep 2005 05:30:53 -0700
Links: << >>  << T >>  << A >>
there is error in you vhdl code, in this line : out std_logic_vector(4 downto 0)); delete the samecoln(;).

Article: 89086
Subject: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
From: xvhdl <>
Date: Mon, 5 Sep 2005 05:32:30 -0700
Links: << >>  << T >>  << A >>
sorry iwas wrong

Article: 89087
Subject: Re: bare die (non packaged) FPGA, CPLD, controllers ?
From: "Jon Beniston" <jon@beniston.com>
Date: 5 Sep 2005 06:19:42 -0700
Links: << >>  << T >>  << A >>
Atmel do a lot of bare die products (They do ARM's too).

Cheers,
Jon


Article: 89088
Subject: Nand Flash Emulator
From: "Gromer" <osIndgy@gmail.com>
Date: 5 Sep 2005 07:41:14 -0700
Links: << >>  << T >>  << A >>
Hi,

Ive been trying to find some Nand Flash Emulator for my nand Flash
driver to be tested....i cud'nt find one...
Is anyone aware of Nand Flash Emulator like Bochs Emulator.

Thanks,
Gromer


Article: 89089
Subject: False values in Quartus In-System Memory Editor
From: "Sebastian Schmidt" <fpga@gmx.de>
Date: Mon, 05 Sep 2005 16:54:06 +0200
Links: << >>  << T >>  << A >>
Hi.

I have a problem with the In-System Memory Editor in Quarts II 4.1.
I can read the memory contents and get the correct values when I do
not write the memory before.
But when I write any values (including the old memory contents) to
the memory and read thereafter, I get false values.
This only happens when using ram, when using the memory editor on
LPM_CONSTANT, I always read the correct values.
I verified that no logic of my design is responsible for that, by
creating a memory from the MegaWizard Plugin Manager and setting the
memory as the top level module, thus no other logic is there besides
the memory.

Can anybody help?

Sebastian Schmidt.

Article: 89090
Subject: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
From: "Narayan" <narayan.subramanian@gmail.com>
Date: 5 Sep 2005 07:55:03 -0700
Links: << >>  << T >>  << A >>
verilog code below gives the same error:

module test5 (a, b, c);

input [4:0] a, b;
output [4:0] c;

assign c = a & b;

endmodule

Error:  Net #10 (c[0]) has no driver and will cause
memory corruption.


Article: 89091
Subject: Re: False values in Quartus In-System Memory Editor
From: ALuPin@web.de
Date: 5 Sep 2005 08:30:32 -0700
Links: << >>  << T >>  << A >>
How do you read and write the memory?In simulation ?
Or in real hardware (How did you debug that) ?

Rgds
Andr=E9


Sebastian Schmidt schrieb:

> Hi.
>
> I have a problem with the In-System Memory Editor in Quarts II 4.1.
> I can read the memory contents and get the correct values when I do
> not write the memory before.
> But when I write any values (including the old memory contents) to
> the memory and read thereafter, I get false values.
> This only happens when using ram, when using the memory editor on
> LPM_CONSTANT, I always read the correct values.
> I verified that no logic of my design is responsible for that, by
> creating a memory from the MegaWizard Plugin Manager and setting the
> memory as the top level module, thus no other logic is there besides
> the memory.
>=20
> Can anybody help?
>=20
> Sebastian Schmidt.


Article: 89092
Subject: PPC405 32 bit aligned accesses
From: "I. Ulises Hernandez" <delete@e-vhdl.com>
Date: Mon, 5 Sep 2005 15:30:52 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hello everybody,

Hopefully someone can give me a hand with a PPC405 issue...

How do you configure the PPC so that it only performs 32-bit aligned 
accesses to DDR? The DDR2 module I am interfacing is byte wide and I do NOT 
have access to the Data Mask pins, a DDR Word becomes 8 (bits/byte) x 4 
(Burst Length) = 32 bits wide...

Thanks in advance,

--
Ulises Hernandez
" I'm not normally a praying man, but if you're up there, please save me, 
Superman!" - Homer Simpson ;O) 



Article: 89093
Subject: Re: False values in Quartus In-System Memory Editor
From: "Sebastian Schmidt" <fpga@gmx.de>
Date: Mon, 05 Sep 2005 18:09:37 +0200
Links: << >>  << T >>  << A >>
Hi.

I read the memory over the JTAG interface with the In-System Memory  
Content Editor.

Sebastian.

Am 05.09.2005, 17:30 Uhr, schrieb <ALuPin@web.de>:

> How do you read and write the memory?In simulation ?
> Or in real hardware (How did you debug that) ?
>
> Rgds
> André
>
>
> Sebastian Schmidt schrieb:
>
>> Hi.
>>
>> I have a problem with the In-System Memory Editor in Quarts II 4.1.
>> I can read the memory contents and get the correct values when I do
>> not write the memory before.
>> But when I write any values (including the old memory contents) to
>> the memory and read thereafter, I get false values.
>> This only happens when using ram, when using the memory editor on
>> LPM_CONSTANT, I always read the correct values.
>> I verified that no logic of my design is responsible for that, by
>> creating a memory from the MegaWizard Plugin Manager and setting the
>> memory as the top level module, thus no other logic is there besides
>> the memory.
>>
>> Can anybody help?
>>
>> Sebastian Schmidt.
>



-- 
Erstellt mit Operas revolutionärem E-Mail-Modul: http://www.opera.com/mail/

Article: 89094
Subject: Re: PPC405 32 bit aligned accesses
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 5 Sep 2005 09:27:14 -0700
Links: << >>  << T >>  << A >>
Hi Ulises,
I looked at this briefly a while ago. My initial impression of reading the 
datasheet is that if the cache is turned on, the accesses are in 8-word 
chunks, i.e. 32 bytes at a time. In this case the mask pins aren't needed.
Quote "The PPC405x3 implements separate instruction-cache and data-cache 
arrays. Each is 16 KB in size, is two-way set-associative, and operates 
using 8 word (32 byte) cache lines. The caches are non-blocking, allowing 
the PPC405x3 to overlap instruction execution with reads over the PLB (when 
cache misses occur)."
I haven't tried this yet, so, like you Ulises, I'd appreciate it if someone 
else can confirm this mode of operation is valid.
Thanks, Syms
"I. Ulises Hernandez" <delete@e-vhdl.com> wrote in message 
news:dfhobc$6in$1@nwrdmz02.dmz.ncs.ea.ibs-infra.bt.com...
> Hello everybody,
>
> Hopefully someone can give me a hand with a PPC405 issue...
>
> How do you configure the PPC so that it only performs 32-bit aligned 
> accesses to DDR? The DDR2 module I am interfacing is byte wide and I do 
> NOT have access to the Data Mask pins, a DDR Word becomes 8 (bits/byte) x 
> 4 (Burst Length) = 32 bits wide...
>
> Thanks in advance,
>
> --
> Ulises Hernandez
> " I'm not normally a praying man, but if you're up there, please save me, 
> Superman!" - Homer Simpson ;O)
> 



Article: 89095
Subject: Re: PPC405 32 bit aligned accesses
From: "I. Ulises Hernandez" <delete@e-vhdl.com>
Date: Mon, 5 Sep 2005 16:37:02 +0000 (UTC)
Links: << >>  << T >>  << A >>
Thanks Symon,

I had actually enabled the caches and still seems to be performing byte 
accesses every now and then... if variables have been defined as 'bytes' 
then the compiler seems to be generating Load Byte assembler instructions, 
also for strings (I can see in simulation - PPC swift model than 'printf' 
for instance is generating PLB byte accesses)...

Regards,

-- 
I.U. Hernandez
" I'm not normally a praying man, but if you're up there, please save me, 
Superman!" - Homer Simpson ;O)

"Symon" <symon_brewer@hotmail.com> wrote in message 
news:431c70e2$0$18650$14726298@news.sunsite.dk...
> Hi Ulises,
> I looked at this briefly a while ago. My initial impression of reading the 
> datasheet is that if the cache is turned on, the accesses are in 8-word 
> chunks, i.e. 32 bytes at a time. In this case the mask pins aren't needed.
> Quote "The PPC405x3 implements separate instruction-cache and data-cache 
> arrays. Each is 16 KB in size, is two-way set-associative, and operates 
> using 8 word (32 byte) cache lines. The caches are non-blocking, allowing 
> the PPC405x3 to overlap instruction execution with reads over the PLB 
> (when cache misses occur)."
> I haven't tried this yet, so, like you Ulises, I'd appreciate it if 
> someone else can confirm this mode of operation is valid.
> Thanks, Syms
> "I. Ulises Hernandez" <delete@e-vhdl.com> wrote in message 
> news:dfhobc$6in$1@nwrdmz02.dmz.ncs.ea.ibs-infra.bt.com...
>> Hello everybody,
>>
>> Hopefully someone can give me a hand with a PPC405 issue...
>>
>> How do you configure the PPC so that it only performs 32-bit aligned 
>> accesses to DDR? The DDR2 module I am interfacing is byte wide and I do 
>> NOT have access to the Data Mask pins, a DDR Word becomes 8 (bits/byte) x 
>> 4 (Burst Length) = 32 bits wide...
>>
>> Thanks in advance,
>>
>> --
>> Ulises Hernandez
>> " I'm not normally a praying man, but if you're up there, please save me, 
>> Superman!" - Homer Simpson ;O)
>>
>
> 



Article: 89096
Subject: Re: Spartan 3 Ram Instantiation
From: John_H <johnhandwork@mail.com>
Date: Mon, 05 Sep 2005 16:46:36 GMT
Links: << >>  << T >>  << A >>
amir.intisar@gmail.com wrote:
> Hi John,
>             basically, every 1ms (very slow) a 16 bit value is coming
> in from an ADC. I need to take this value and put it in memory. The
> Spartan 3 has 262,144(18 bit)  16 bit wide memory slots (two of). I
> just want to insert the ADC data in memory location one, increment the
> address, wait for the next ADC value and put it in memory address
> two...so on. I have written code for this in verilog but i was looking
> at maybe instantiating it using one of the xilinx templates, because my
> code is messy. Is there any better strategy for what i am doing?.
> ....Thanks !!!!!!!!!

You should be able to store up to 12k samples in the XC3S200 as Philip 
Freidin pointed out.

As for the clock, the clock you use to manipulate the ADC information 
should be sufficient.  If you're using a 100 MHz system clock to control 
the interface to the ADC, use that for the RAM, too.  Simply provide the 
EN (for read or rd/wr) and WE (combined with EN for write) to strobe the 
data in.

You can use dual-port memories to access the ADC data separate from the 
writing of that data so the addressing doesn't ahve to be muxed between 
the sequential write and a random read.

Note that many synthesizers will do a fine job of inferring a 2kx16 
memory with separate read and write addresses though some synthesizers 
want to see only one clock even though the dual-port BlockRAMs can have 
independent read and write clocks.

Your code should end up looking messier with instantiations but you 
would have significantly better control if you want to do anything 
slightly unusual.

Try something like:
reg [15:0] ADCvals [12287:0];
reg [15:0] ADCvalRd;
always @(posedge SysClk)
begin
   if( ADCrdValid )  ADCvals[inAddr] <= ADCinVal;
   ADCvalRd <= ADCvals[rdAddr];
end

The output should be registered to fit the BlockRAM structure - there 
are no async reads.  You supply the inAddr (you wanted that sequential?) 
and the strobe for when the data is valid.  When you read the value, you 
need the read address the clock before the data becomes present.

Inferrence is *great* when the synthesizer works well and you're not 
doing anything fancy.
If there's a problem with 12288-wide memories and the synth preferes 2^n 
sized arrays, consider implementing 3 4096-wide memories instead and 
coordinating between them.  See what you get!

Article: 89097
Subject: Re: I2C "SCL" line problem
From: John_H <johnhandwork@mail.com>
Date: Mon, 05 Sep 2005 16:50:27 GMT
Links: << >>  << T >>  << A >>
Jim Granville wrote:

> praveen.kantharajapura@gmail.com wrote:
> 
>> Hi Falk,
>>
>> We cannot go for the Scmitt trigger option , because the PCB's are
>> already out.Could any thing be done to avoid flase triggering in FPGA's
>> only.
> 
> 
>  Falk mentioned using a higher frequency clock ( if you have one in the
> FPGA already) and running a state engine.

<snip>

specifically, a separate "glitch filter" may be what the state engine 
needs.  The I2C calls for glitch handling of specific sizes in different 
modes.  It's pretty easy to delay the edge long enough to make sure the 
transition isn't a glitch at or below the specified size and still 
capture the data well within the setup/hold time.

The glitch handling is really a must for I2C.

Article: 89098
Subject: Area Estimation Issues
From: skatoulas@hotmail.com
Date: 5 Sep 2005 10:40:16 -0700
Links: << >>  << T >>  << A >>
Hello all,

I'd like to ask the following. My design has 3 different generic inputs
according to which it multiply instantiates some entities and generates
the appropriate bus widths, arithmetic modules etc. I'd like to do a
bottom up area estimation and come up with functions of area for the
three generics. Although I could simply write down the percentages of
chip area taken by each entity as the generics change etc, it is a bit
inconsistent as Xilinx gives me different percentages for LUTs, IOBs
etc.

What I'd like to ask is if there is an established metric for area
estimation, e.g thousands of gates and if there is direct translation
between number of IOBs, LUTs etc and that metric. I'm dealng with a
Virtex II FPGA. Thanks

Regards


Article: 89099
Subject: Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed."
From: "VSP" <vijayandra.poojari@gmail.com>
Date: 5 Sep 2005 11:04:14 -0700
Links: << >>  << T >>  << A >>
Hello All,

I am facing a very bugging problem while using XILINX ISE 7.1i with SP4
installed.

Some of my top level ports has been removed by the MAP utility of
ISE.The synthesis is successfully completing without any errors or
warnings. The post synthesis simulation model shows all the ports and
its related logic.

However after the MAP process has been completed, its throws up a
warning saying that some top level ports has been
removed.(WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level
port P_GPIO_3 has been removed.")

Please respond if any one has encountered such problems before.


Regards,
VSP




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2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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