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Threads Starting Dec 2006

112924: 06/12/01: Vangelis: PowerPC_bus
    112925: 06/12/01: Symon: Re: PowerPC_bus
112926: 06/12/01: S.T.: EDK 8.2 Busmaster Example
    113161: 06/12/07: S.T.: Re: EDK 8.2 Busmaster Example
112927: 06/12/01: rob.dimond@gmail.com: Firmware for Xilinx USB cable
    112961: 06/12/02: <mark.jarvin@gmail.com>: Re: Firmware for Xilinx USB cable
    112994: 06/12/04: rob.dimond@gmail.com: Re: Firmware for Xilinx USB cable
    112997: 06/12/04: <mark.jarvin@gmail.com>: Re: Firmware for Xilinx USB cable
    113115: 06/12/06: Eric Smith: Re: Firmware for Xilinx USB cable
    113215: 06/12/08: <mark.jarvin@gmail.com>: Re: Firmware for Xilinx USB cable
112928: 06/12/01: Rune Dahl Jorgensen: Caching of external memory
    113278: 06/12/10: Rune D. Jřrgensen: Re: Caching of external memory
112941: 06/12/01: MM: Aurora simplex channel problems
112947: 06/12/01: ram: Hi
    112957: 06/12/02: Subroto Datta: Re: Hi
    113014: 06/12/05: ram: Re: Hi
112951: 06/12/02: lubot77: Video Mux using FPGA
    112952: 06/12/02: PeteS: Re: Video Mux using FPGA
        112955: 06/12/02: lubot77: Re: Video Mux using FPGA
    112974: 06/12/03: fpgabuilder: Re: Video Mux using FPGA
        112988: 06/12/04: Symon: Re: Video Mux using FPGA
    113312: 06/12/11: Christian Kirschenlohr: Re: Video Mux using FPGA
112954: 06/12/02: JSalk: Digitally Controlled Impedance with Lattice ECP2M FPGA's
    112995: 06/12/04: Gabor: Re: Digitally Controlled Impedance with Lattice ECP2M FPGA's
    113140: 06/12/06: Kevin: Re: Digitally Controlled Impedance with Lattice ECP2M FPGA's
112959: 06/12/02: <bharadwaj.sr@gmail.com>: LUT input order
    112962: 06/12/02: Peter Alfke: Re: LUT input order
    112964: 06/12/02: Ray Andraka: Re: LUT input order
    112965: 06/12/02: Jim Wu: Re: LUT input order
        112966: 06/12/03: John_H: Re: LUT input order
            112989: 06/12/04: Symon: Re: LUT input order
                113006: 06/12/04: Mr.B: Re: LUT input order
    112967: 06/12/02: Jim Wu: Re: LUT input order
    113007: 06/12/04: Peter Alfke: Re: LUT input order
    113008: 06/12/04: <bharadwaj.sr@gmail.com>: Re: LUT input order
    113010: 06/12/04: Peter Alfke: Re: LUT input order
112970: 06/12/03: Wojciech Zabolotny: Buggy behaviour in Modelsim, when reading from pipe?
    112972: 06/12/03: Jon Beniston: Re: Buggy behaviour in Modelsim, when reading from pipe?
    112978: 06/12/04: Wojciech Zabolotny: Re: Buggy behaviour in Modelsim, when reading from pipe?
112973: 06/12/03: Quesito: Picoblaze C compiler 1.8.4
    112981: 06/12/04: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Picoblaze C compiler 1.8.4
    113000: 06/12/04: Nico Coesel: Re: Picoblaze C compiler 1.8.4
    113015: 06/12/05: Quesito: Re: Picoblaze C compiler 1.8.4
112975: 06/12/03: u_stadler@yahoo.de: EDk and DCM
    112976: 06/12/03: Alan Nishioka: Re: EDk and DCM
    112977: 06/12/03: Andrew Holme: Re: EDk and DCM
    112984: 06/12/04: u_stadler@yahoo.de: Re: EDk and DCM
    112985: 06/12/04: Antti: Re: EDk and DCM
    112986: 06/12/04: u_stadler@yahoo.de: Re: EDk and DCM
    112987: 06/12/04: Antti: Re: EDk and DCM
    112990: 06/12/04: u_stadler@yahoo.de: Re: EDk and DCM
    112991: 06/12/04: Antti: Re: EDk and DCM
    112993: 06/12/04: u_stadler@yahoo.de: Re: EDk and DCM
112992: 06/12/04: wangw8021: how can I use DCM in paritial reconfiguration design?
112996: 06/12/04: bioradio: coherent logic
112998: 06/12/04: john: XEM3010
    113011: 06/12/04: Andrew FPGA: Re: XEM3010
    113018: 06/12/05: Guru: Re: XEM3010
113001: 06/12/04: radarman: Can you configure an Altera Stratix without the nStatus line?
    113003: 06/12/04: Antti: Re: Can you configure an Altera Stratix without the nStatus line?
    113005: 06/12/04: radarman: Re: Can you configure an Altera Stratix without the nStatus line?
    113042: 06/12/05: radarman: Re: Can you configure an Altera Stratix without the nStatus line?
113004: 06/12/04: mpthompson@gmail.com: Xilinx EDK/XPS 8.2 freezes XP desktop when launching XMD
113013: 06/12/05: ee_ether: Spartan3 IBIS / Simulation questions
113016: 06/12/05: phoenix: Readback Jtag Problem
    113093: 06/12/06: Gabor: Re: Readback Jtag Problem
    113098: 06/12/06: phoenix: Re: Readback Jtag Problem
113017: 06/12/05: Steven Derrien: Using quartus "In system memory editor" from command line
    113045: 06/12/05: Subroto Datta: Re: Using quartus "In system memory editor" from command line
113019: 06/12/05: Antti: Spartan-3A launched
    113020: 06/12/05: Antti: Re: Spartan-3A launched
        113021: 06/12/05: Uwe Bonnes: Re: Spartan-3A launched
        113025: 06/12/05: Uwe Bonnes: Re: Spartan-3A launched
        113040: 06/12/05: Antti Lukats: Re: Spartan-3A launched
            113047: 06/12/05: Antti Lukats: Re: Spartan-3A launched
                113076: 06/12/06: Göran Bilski: Re: Spartan-3A launched
                    113081: 06/12/06: Göran Bilski: Re: Spartan-3A launched
                        113122: 06/12/07: Jim Granville: Re: Spartan-3A launched
                            113125: 06/12/06: Antti Lukats: Re: Spartan-3A launched
        113044: 06/12/05: Antti Lukats: Re: Spartan-3A launched
            113049: 06/12/05: Antti Lukats: Re: Spartan-3A launched
                113050: 06/12/05: Antti Lukats: Re: Spartan-3A launched
            113061: 06/12/05: Antti Lukats: Re: Spartan-3A launched
            113077: 06/12/06: <lb.edc@telenet.be>: Re: Spartan-3A launched
                113164: 06/12/07: Tim: Re: Spartan-3A launched
                    113175: 06/12/07: Austin Lesea: Re: Spartan-3A launched
    113022: 06/12/05: Antti: Re: Spartan-3A launched
    113023: 06/12/05: Jon Beniston: Re: Spartan-3A launched
    113024: 06/12/05: Antti: Re: Spartan-3A launched
    113043: 06/12/05: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan-3A launched
    113046: 06/12/05: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan-3A launched
    113048: 06/12/05: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan-3A launched
    113055: 06/12/05: Peter Alfke: Re: Spartan-3A launched
    113078: 06/12/06: Antti: Re: Spartan-3A launched
    113083: 06/12/06: Antti: Re: Spartan-3A launched
    113152: 06/12/06: Peter Alfke: Re: Spartan-3A launched
    113336: 06/12/11: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan-3A launched [Device DNA, Right Page, Corrected URL]
    113521: 06/12/15: Netoko Young: Re: Spartan-3A launched
    113522: 06/12/15: Antti: Re: Spartan-3A launched
    113537: 06/12/15: oen_br: Re: Spartan-3A launched
    113556: 06/12/16: Netoko Young: Re: Spartan-3A launched
    113557: 06/12/16: Antti: Re: Spartan-3A launched
113026: 06/12/05: <topweaver@hotmail.com>: Free Anydivider, Divide clock by any number
    113066: 06/12/05: Peter Alfke: Re: Free Anydivider, Divide clock by any number
        113112: 06/12/06: Georg Acher: Re: Free Anydivider, Divide clock by any number
            113136: 06/12/07: Jim Granville: Re: Free Anydivider, Divide clock by any number
    113106: 06/12/06: <topweaver@hotmail.com>: Re: Free Anydivider, Divide clock by any number
    113108: 06/12/06: Gabor: Re: Free Anydivider, Divide clock by any number
    113111: 06/12/06: Peter Alfke: Re: Free Anydivider, Divide clock by any number
    113142: 06/12/06: Peter Alfke: Re: Free Anydivider, Divide clock by any number
    113177: 06/12/07: <topweaver@hotmail.com>: Re: Free Anydivider, Divide clock by any number
    113178: 06/12/07: <topweaver@hotmail.com>: Re: Free Anydivider, Divide clock by any number
    113180: 06/12/07: Peter Alfke: Re: Free Anydivider, Divide clock by any number
    113331: 06/12/11: <topweaver@hotmail.com>: Re: Free Anydivider, Divide clock by any number
    113358: 06/12/11: Gabor: Re: Free Anydivider, Divide clock by any number
    113618: 06/12/18: <topweaver@hotmail.com>: Re: Free Anydivider, Divide clock by any number
113027: 06/12/05: ALuPin@web.de: Question concerning XAPP224
    113028: 06/12/05: Alan Nishioka: Re: Question concerning XAPP224
113029: 06/12/05: Robin Bruce: Creating a single logical netlist...
    113031: 06/12/05: David Dye: Re: Creating a single logical netlist...
113030: 06/12/05: <zhongqiang.cheng@gmail.com>: How to check high impedance of a RAM with Logic Analyzer
    113032: 06/12/05: rickman: Re: How to check high impedance of a RAM with Logic Analyzer
    113033: 06/12/05: Alan Nishioka: Re: How to check high impedance of a RAM with Logic Analyzer
    113036: 06/12/05: Symon: Re: How to check high impedance of a RAM with Logic Analyzer
    113039: 06/12/05: PeteS: Re: How to check high impedance of a RAM with Logic Analyzer
    113069: 06/12/05: Peter Alfke: Re: How to check high impedance of a RAM with Logic Analyzer
    113079: 06/12/06: <zhongqiang.cheng@gmail.com>: Re: How to check high impedance of a RAM with Logic Analyzer
113034: 06/12/05: Andreas Ehliar: RLOC weirdness
    113035: 06/12/05: John_H: Re: RLOC weirdness
    113038: 06/12/05: Ray Andraka: Re: RLOC weirdness
    113085: 06/12/06: Brian Drummond: Re: RLOC weirdness
        113090: 06/12/06: Ray Andraka: Re: RLOC weirdness
            113406: 06/12/13: Andreas Ehliar: Re: RLOC weirdness
113037: 06/12/05: Shela: Virtex-4 ML403 16x2 LCD
    113088: 06/12/06: Sean Durkin: Re: Virtex-4 ML403 16x2 LCD
113051: 06/12/05: ed_h: Xilinx MPMC2 "External Ports" question
    113052: 06/12/05: Antti Lukats: Re: Xilinx MPMC2 "External Ports" question
        113062: 06/12/06: Antti Lukats: Re: Xilinx MPMC2 "External Ports" question
    113057: 06/12/05: ed_h: Re: Xilinx MPMC2 "External Ports" question
    113067: 06/12/05: MM: Re: Xilinx MPMC2 "External Ports" question
    113084: 06/12/06: Guru: Re: Xilinx MPMC2 "External Ports" question
    113102: 06/12/06: ed_h: Re: Xilinx MPMC2 "External Ports" question
    113103: 06/12/06: ed_h: Re: Xilinx MPMC2 "External Ports" question
    113104: 06/12/06: ed_h: Re: Xilinx MPMC2 "External Ports" question
    113186: 06/12/07: Guru: Re: Xilinx MPMC2 "External Ports" question
    113248: 06/12/08: ed_h: Re: Xilinx MPMC2 "External Ports" question
        113265: 06/12/09: MM: Re: Xilinx MPMC2 "External Ports" question
            113335: 06/12/11: MM: Re: Xilinx MPMC2 "External Ports" question
    113296: 06/12/10: ed_h: Re: Xilinx MPMC2 "External Ports" question
113053: 06/12/05: Brandon Jasionowski: Usage of BUFIO in Virtex 4?
    113058: 06/12/05: John McCaskill: Re: Usage of BUFIO in Virtex 4?
    113059: 06/12/05: Joseph Samson: Re: Usage of BUFIO in Virtex 4?
    113070: 06/12/05: markus: Re: Usage of BUFIO in Virtex 4?
    113107: 06/12/06: Brandon Jasionowski: Re: Usage of BUFIO in Virtex 4?
    113119: 06/12/06: markus: Re: Usage of BUFIO in Virtex 4?
    113132: 06/12/06: Jim Wu: Re: Usage of BUFIO in Virtex 4?
    113133: 06/12/06: Jim Wu: Re: Usage of BUFIO in Virtex 4?
    113182: 06/12/07: Brandon Jasionowski: Re: Usage of BUFIO in Virtex 4?
113054: 06/12/05: Derek Simmons: First Look at QuartusII 6.1
    113056: 06/12/05: Thomas Entner: Re: First Look at QuartusII 6.1
    113060: 06/12/05: PeteS: Re: First Look at QuartusII 6.1
    113065: 06/12/05: Derek Simmons: Re: First Look at QuartusII 6.1
113063: 06/12/05: John: Timing constraings: min delay?
    113064: 06/12/05: John: Re: Timing constraings: min delay?
    113563: 06/12/16: glen herrmannsfeldt: Re: Timing constraings: min delay?
113068: 06/12/05: Peter Alfke: Re: Timing constraings: min delay?
113071: 06/12/05: ram: query in gate level simulationin quartus s/w 6.0
    113073: 06/12/06: Subroto Datta: Re: query in gate level simulationin quartus s/w 6.0
113072: 06/12/05: wanwan: Altera starter kits
    113074: 06/12/05: Tommy Thorn: Re: Altera starter kits
    113075: 06/12/06: Ben Twijnstra: Re: Altera starter kits
        113080: 06/12/06: Jim Granville: Re: Altera starter kits
            113089: 06/12/06: <lb.edc@telenet.be>: Re: Altera starter kits
            113120: 06/12/07: Jim Granville: Re: Altera starter kits
    113082: 06/12/06: alterauser: Re: Altera starter kits
    113086: 06/12/06: wanwan: Re: Altera starter kits
    113087: 06/12/06: Antti: Re: Altera starter kits
    113091: 06/12/06: Derek Simmons: Re: Altera starter kits
113092: 06/12/06: Philip Herzog: Timing constraint on DCM input ignored after update ISE 8.1 -> 8.2?
113094: 06/12/06: motty: EDK 8.2, MDM, and ChipScope....
    113096: 06/12/06: Antti: Re: EDK 8.2, MDM, and ChipScope....
        113117: 06/12/06: Antti Lukats: Re: EDK 8.2, MDM, and ChipScope....
            113118: 06/12/06: Antti Lukats: Re: EDK 8.2, MDM, and ChipScope....
    113110: 06/12/06: motty: Re: EDK 8.2, MDM, and ChipScope....
    113114: 06/12/06: motty: Re: EDK 8.2, MDM, and ChipScope....
113095: 06/12/06: Ashish: Xilinx PLB IPIF
113097: 06/12/06: Ashish: Clock phase shift
    113099: 06/12/06: Alan Myler: Re: Clock phase shift
        113101: 06/12/06: Frank Buss: Re: Clock phase shift
            113116: 06/12/06: Duane Clark: Re: Clock phase shift
            113151: 06/12/07: John_H: Re: Clock phase shift
            113220: 06/12/08: Daniel S.: Re: Clock phase shift
    113100: 06/12/06: Jim Wu: Re: Clock phase shift
    113105: 06/12/06: Ashish: Re: Clock phase shift
    113121: 06/12/06: Peter Alfke: Re: Clock phase shift
    113124: 06/12/06: markus: Re: Clock phase shift
    113148: 06/12/06: Ashish: Re: Clock phase shift
113109: 06/12/06: Morgan: help with Xilinx LVDS syntax
    113113: 06/12/06: davide: Re: help with Xilinx LVDS syntax
113123: 06/12/06: John: How do I delay signal to pad?
    113135: 06/12/06: Peter Alfke: Re: How do I delay signal to pad?
113126: 06/12/06: Bill Burris: How to find an FPGA board
    113134: 06/12/06: Andreas Ehliar: Re: How to find an FPGA board
        113166: 06/12/07: Ian Muncaster: Re: How to find an FPGA board
        113360: 06/12/11: Bill Burris: Re: How to find an FPGA board
    113147: 06/12/06: <jonas@mit.edu>: Re: How to find an FPGA board
113127: 06/12/06: David: Remove DCM wrappers from EDK designs
    113155: 06/12/06: Siva Velusamy: Re: Remove DCM wrappers from EDK designs
113128: 06/12/06: Am: How to reduce jitter of 30-bit accumulator
113129: 06/12/06: ted.franklin3@gmail.com: VHDL Variable Length Input file.
113130: 06/12/06: ted: VHDL Variable Length Input file.
    113131: 06/12/06: Nicolas Matringe: Re: VHDL Variable Length Input file.
113137: 06/12/06: john: XSA3S1000 board and SDRAM
113138: 06/12/06: avishay: FPGA to Camera (Channel) link
    113145: 06/12/07: Rob: Re: FPGA to Camera (Channel) link
    113157: 06/12/06: avishay: Re: FPGA to Camera (Channel) link
    113174: 06/12/07: wallge: Re: FPGA to Camera (Channel) link
113139: 06/12/06: John_H: Re: How to reduce jitter of 30-bit accumulator
113141: 06/12/06: Francois Choquette: Registers initial values with Altera Stratix II
    113146: 06/12/06: Subroto Datta: Re: Registers initial values with Altera Stratix II
113143: 06/12/06: johnp: Xilinx PAR crashing with 'make'
    113159: 06/12/07: Andreas Ehliar: Re: Xilinx PAR crashing with 'make'
    113187: 06/12/07: Jim Wu: Re: Xilinx PAR crashing with 'make'
    113196: 06/12/08: Petter Gustad: Re: Xilinx PAR crashing with 'make'
        113202: 06/12/08: Markus: Re: Xilinx PAR crashing with 'make'
113144: 06/12/06: Peter Alfke: Re: How to reduce jitter of 30-bit accumulator
113149: 06/12/06: <Jesper.Kristensen@tellabs.com>: Quartus II: Back-annotating bidir's gives two entries per pin...
    113158: 06/12/07: avishay: Re: Quartus II: Back-annotating bidir's gives two entries per pin...
113150: 06/12/07: Murali: Microblaze LMB bus
    113156: 06/12/06: Siva Velusamy: Re: Microblaze LMB bus
        113168: 06/12/07: Murali: Re: Microblaze LMB bus
            113189: 06/12/07: Siva Velusamy: Re: Microblaze LMB bus
                113195: 06/12/07: Muralidaran Vijayaraghavan: Re: Microblaze LMB bus
            113199: 06/12/07: Muralidaran Vijayaraghavan: Re: Microblaze LMB bus
                113204: 06/12/08: Göran Bilski: Re: Microblaze LMB bus
113153: 06/12/06: ekavirsrikanth@gmail.com: regarding -ve slack while doing post PAR timing analysis
    113162: 06/12/07: Ben Jones: Re: regarding -ve slack while doing post PAR timing analysis
113160: 06/12/07: wojtek_himself: PlanAhead : problems
113163: 06/12/07: <rponsard@gmail.com>: differential I/O with ISE 8.2 / spartan3E
    113181: 06/12/07: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: differential I/O with ISE 8.2 / spartan3E
    113190: 06/12/07: <rponsard@gmail.com>: Re: differential I/O with ISE 8.2 / spartan3E
113165: 06/12/07: Steve: FPGA+Ethernet
    113169: 06/12/07: Quesito: Re: FPGA+Ethernet
    113170: 06/12/07: Uwe Bonnes: Re: FPGA+Ethernet
    113185: 06/12/07: dexue: Re: FPGA+Ethernet
        113198: 06/12/08: Steve: Re: FPGA+Ethernet
    113259: 06/12/09: Jean Nicolle: Re: FPGA+Ethernet
        113341: 06/12/11: Antti Lukats: Re: FPGA+Ethernet
    113295: 06/12/10: kunil: Re: FPGA+Ethernet
    113301: 06/12/10: JJ: Re: FPGA+Ethernet
113167: 06/12/07: <davidc@ad-holdings.co.uk>: RTL Hardware design issue: Count Leading Zeros CLZ
    113171: 06/12/07: Jon Beniston: Re: RTL Hardware design issue: Count Leading Zeros CLZ
    113172: 06/12/07: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: RTL Hardware design issue: Count Leading Zeros CLZ
    113176: 06/12/07: Andy Ray: Re: RTL Hardware design issue: Count Leading Zeros CLZ
    113184: 06/12/07: Ray Andraka: Re: RTL Hardware design issue: Count Leading Zeros CLZ
        113218: 06/12/08: Ray Andraka: Re: RTL Hardware design issue: Count Leading Zeros CLZ
            113227: 06/12/08: Ray Andraka: Re: RTL Hardware design issue: Count Leading Zeros CLZ
    113192: 06/12/07: <davidc@ad-holdings.co.uk>: Re: RTL Hardware design issue: Count Leading Zeros CLZ
    113221: 06/12/08: <davidc@ad-holdings.co.uk>: Re: RTL Hardware design issue: Count Leading Zeros CLZ
    113254: 06/12/09: Nico Coesel: Re: RTL Hardware design issue: Count Leading Zeros CLZ
113173: 06/12/07: jim: testbench help
    113260: 06/12/09: Mike Treseler: Re: testbench help
113179: 06/12/07: Patrik Eriksson: Recursive component instantiation
    113183: 06/12/07: Ray Andraka: Re: Recursive component instantiation
    113213: 06/12/08: acd: Re: Recursive component instantiation
113188: 06/12/07: <googlinggoogler@hotmail.com>: Re: Recursive component instantiation
    113194: 06/12/07: Ray Andraka: Re: Recursive component instantiation
        113207: 06/12/08: Patrik Eriksson: Re: Recursive component instantiation
        113307: 06/12/11: Patrik Eriksson: Re: Recursive component instantiation
113193: 06/12/07: Andy: Re: Recursive component instantiation
113197: 06/12/07: Perry: About partial reconfiguration in Virtex 4
    113217: 06/12/08: Austin Lesea: Re: About partial reconfiguration in Virtex 4
        113238: 06/12/08: Vic Vadi: Re: About partial reconfiguration in Virtex 4
113200: 06/12/07: ram: query regarding capacitance of pins of cyclone device
113201: 06/12/07: bijoy: FPGA : LIFO
    113203: 06/12/07: Thomas Stanka: Re: FPGA : LIFO
    113518: 06/12/15: RCIngham: Re: FPGA : LIFO
113205: 06/12/08: Amirtham: Problem with connecting higher order address lines of SDRAM to FPGA
    113216: 06/12/08: Gabor: Re: Problem with connecting higher order address lines of SDRAM to FPGA
    113308: 06/12/10: Amirtham: Re: Problem with connecting higher order address lines of SDRAM to FPGA
    113373: 06/12/12: Amirtham: Re: Problem with connecting higher order address lines of SDRAM to FPGA
    113404: 06/12/12: Amirtham: Re: Problem with connecting higher order address lines of SDRAM to FPGA
    113405: 06/12/13: Ben Jackson: Re: Problem with connecting higher order address lines of SDRAM to FPGA
    113417: 06/12/13: Amirtham: Re: Problem with connecting higher order address lines of SDRAM to FPGA
    113462: 06/12/14: Amirtham: Re: Problem with connecting higher order address lines of SDRAM to FPGA
113206: 06/12/08: kypilop: About Unstable Operation of ACTEL(A3P1000)....
    113210: 06/12/08: Alan Myler: Re: About Unstable Operation of ACTEL(A3P1000)....
        113316: 06/12/11: Alan Myler: Re: About Unstable Operation of ACTEL(A3P1000)....
        113387: 06/12/12: Andreas Ehliar: Re: About Unstable Operation of ACTEL(A3P1000)....
    113214: 06/12/08: kypilop: Re: About Unstable Operation of ACTEL(A3P1000)....
    113244: 06/12/08: <burn.sir@gmail.com>: Re: About Unstable Operation of ACTEL(A3P1000)....
    113261: 06/12/09: Thomas Entner: Re: About Unstable Operation of ACTEL(A3P1000)....
    113315: 06/12/11: Thomas Stanka: Re: About Unstable Operation of ACTEL(A3P1000)....
113208: 06/12/08: Dolphin: source synchronous timing (Xilinx)
    113223: 06/12/08: Jim Wu: Re: source synchronous timing (Xilinx)
113209: 06/12/08: ALuPin@web.de: Organization of character bit maps
    113212: 06/12/08: ALuPin@web.de: Re: Organization of character bit maps
113211: 06/12/08: Mike Harrison: Looking for simple Cycone 2 example design
    113245: 06/12/08: <burn.sir@gmail.com>: Re: Looking for simple Cycone 2 example design
113222: 06/12/08: jjlindula@hotmail.com: Implementing DVI EDID on Stratix II GX?
    113224: 06/12/08: yttrium: Re: Implementing DVI EDID on Stratix II GX?
113225: 06/12/08: kartheic anantha: Query :Regarding Synthesis Report
    113234: 06/12/08: Eric Crabill: Re: Query :Regarding Synthesis Report
113226: 06/12/08: Vitaliy: FFT on Virtex II Pro (how to download .dat file?)
113228: 06/12/08: <fpga_toys@yahoo.com>: Xilinx platform flash data sheet confusion (ds123) for clocking
    113231: 06/12/08: Gabor: Re: Xilinx platform flash data sheet confusion (ds123) for clocking
    113239: 06/12/08: <fpga_toys@yahoo.com>: Re: Xilinx platform flash data sheet confusion (ds123) for clocking
113229: 06/12/08: Vitaliy: FFT on Virtex-II Pro (how to download .dat file?)
    113233: 06/12/08: Gabor: Re: FFT on Virtex-II Pro (how to download .dat file?)
        113237: 06/12/08: Matthew Hicks: Re: FFT on Virtex-II Pro (how to download .dat file?)
113230: 06/12/08: kartheic anantha: Query :Regarding Synthesis Report
113232: 06/12/08: <jetmarc@hotmail.com>: Barrel shifter in Virtex4?
    113236: 06/12/08: Ray Andraka: Re: Barrel shifter in Virtex4?
113235: 06/12/08: <sp_mclaugh@yahoo.com>: 50 MSPS ADC with Spartan 3 FPGA - clock issues
    113241: 06/12/08: Gabor: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
        113266: 06/12/09: Nico Coesel: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
            113289: 06/12/10: John_H: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
    113242: 06/12/08: John_H: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
        113262: 06/12/09: John_H: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
        113264: 06/12/09: John_H: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
            113288: 06/12/10: John_H: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
            113290: 06/12/10: John_H: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
    113246: 06/12/08: <sp_mclaugh@yahoo.com>: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
    113249: 06/12/08: <sp_mclaugh@yahoo.com>: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
    113252: 06/12/08: <sp_mclaugh@yahoo.com>: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
    113268: 06/12/09: <sp_mclaugh@yahoo.com>: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
113240: 06/12/08: ekavirsrikanth@gmail.com: regarding -ve slack while doing post PAR timing analysis
113243: 06/12/08: wallge: computer vision projects for open cores
113247: 06/12/08: <beagle197@hotmail.com>: How to develop custom opb devices for Microblaze?
    113270: 06/12/09: Ben Jackson: Re: How to develop custom opb devices for Microblaze?
    113303: 06/12/11: Zara: Re: How to develop custom opb devices for Microblaze?
    113311: 06/12/11: Göran Bilski: Re: How to develop custom opb devices for Microblaze?
        113371: 06/12/12: Göran Bilski: Re: How to develop custom opb devices for Microblaze?
    113356: 06/12/11: <beagle197@hotmail.com>: Re: How to develop custom opb devices for Microblaze?
113256: 06/12/09: <googlinggoogler@hotmail.com>: Using Jtag for general Communications
113257: 06/12/09: Nevo: JTAG programming of Altera Cyclone and CONF_DONE
    113267: 06/12/09: Marc Guardiani: Re: JTAG programming of Altera Cyclone and CONF_DONE
    113272: 06/12/10: Rob: Re: JTAG programming of Altera Cyclone and CONF_DONE
    113304: 06/12/11: Mark McDougall: Re: JTAG programming of Altera Cyclone and CONF_DONE
        113345: 06/12/11: Nevo: Re: JTAG programming of Altera Cyclone and CONF_DONE
            113552: 06/12/16: Marc Guardiani: Re: JTAG programming of Altera Cyclone and CONF_DONE
                113593: 06/12/18: Mark McDougall: Re: JTAG programming of Altera Cyclone and CONF_DONE
        113368: 06/12/12: Rob: Re: JTAG programming of Altera Cyclone and CONF_DONE
            113370: 06/12/12: Mark McDougall: Re: JTAG programming of Altera Cyclone and CONF_DONE
                113402: 06/12/13: Rob: Re: JTAG programming of Altera Cyclone and CONF_DONE
113258: 06/12/09: Nevo: Current programming hardware does not support Active Serial programming mode
113269: 06/12/10: Anonymous: impossible opb_emc hack?
    113271: 06/12/09: Ben Jackson: Re: impossible opb_emc hack?
    113281: 06/12/10: Anonymous: Re: impossible opb_emc hack?
        113283: 06/12/10: Antti Lukats: Re: impossible opb_emc hack?
            113330: 06/12/11: Anonymous: Re: impossible opb_emc hack?
113273: 06/12/09: Vitaliy: Some questions about FFT implementation
    113279: 06/12/10: Robert Scott: Re: Some questions about FFT implementation
        113287: 06/12/10: Robert Scott: Re: Some questions about FFT implementation
    113280: 06/12/10: Rune Allnor: Re: Some questions about FFT implementation
    113297: 06/12/10: Vitaliy: Re: Some questions about FFT implementation
    113298: 06/12/10: Ray Andraka: Re: Some questions about FFT implementation
        113319: 06/12/11: Robert Scott: Re: Some questions about FFT implementation
            113325: 06/12/11: Ray Andraka: Re: Some questions about FFT implementation
    113299: 06/12/10: Rune Allnor: Re: Some questions about FFT implementation
    113324: 06/12/11: Rune Allnor: Re: Some questions about FFT implementation
113274: 06/12/09: Vitaliy: Writing output signals to text file (VHDL)?
    113282: 06/12/10: Vitaliy: Re: Writing output signals to text file (VHDL)?
        113284: 06/12/10: KJ: Re: Writing output signals to text file (VHDL)?
            113300: 06/12/10: Ray Andraka: Re: Writing output signals to text file (VHDL)?
            113317: 06/12/11: KJ: Re: Writing output signals to text file (VHDL)?
                113519: 06/12/15: RCIngham: Re: Writing output signals to text file (VHDL)?
    113285: 06/12/10: Vitaliy: Re: Writing output signals to text file (VHDL)?
    113286: 06/12/10: Vitaliy: Re: Writing output signals to text file (VHDL)?
    113327: 06/12/11: Vitaliy: Re: Writing output signals to text file (VHDL)?
    113334: 06/12/11: KJ: Re: Writing output signals to text file (VHDL)?
113276: 06/12/10: alterauser: Re: JTAG programming of Altera Cyclone and CONF_DONE
113277: 06/12/10: alterauser: linking two fpga boards
    113344: 06/12/11: MM: Re: linking two fpga boards
        113379: 06/12/12: Will Dean: Re: linking two fpga boards
    113377: 06/12/12: alterauser: Re: linking two fpga boards
    113378: 06/12/12: Antti: Re: linking two fpga boards
113291: 06/12/10: <burn.sir@gmail.com>: approximation of an exponential ramp?
    113292: 06/12/11: Jim Granville: Re: approximation of an exponential ramp?
    113313: 06/12/11: Kolja Sulimma: Re: approximation of an exponential ramp?
    113342: 06/12/11: wallge: Re: approximation of an exponential ramp?
    113353: 06/12/11: Andy Peters: Re: approximation of an exponential ramp?
    113455: 06/12/13: John Larkin: Re: approximation of an exponential ramp?
113293: 06/12/10: <florent.peyrard@gmail.com>: How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?
    113310: 06/12/10: sutejok: Re: How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?
        115051: 07/01/29: BODDU Lokesh: Re: How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?
            115076: 07/01/30: davide: Re: How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?
113294: 06/12/10: Roger: Aurora v2.5
    113343: 06/12/11: MM: Re: Aurora v2.5
113302: 06/12/10: vittal: @(posedge clk)
    113305: 06/12/11: Ben Jackson: Re: @(posedge clk)
    113306: 06/12/10: Neo: Re: @(posedge clk)
        113375: 06/12/12: Andreas Ehliar: Re: @(posedge clk)
    113314: 06/12/11: vits: Re: @(posedge clk)
    113337: 06/12/11: mjl296@hotmail.com: Re: @(posedge clk)
113309: 06/12/10: sutejok: System ACE PROG_B and INIT pins
113318: 06/12/11: Guy_FPGA: How to read data from intel strata flash using microblaze?
    113320: 06/12/11: PeteS: Re: How to read data from intel strata flash using microblaze?
    113322: 06/12/11: Guy_FPGA: Re: How to read data from intel strata flash using microblaze?
    113323: 06/12/11: PeteS: Re: How to read data from intel strata flash using microblaze?
    113372: 06/12/12: Guy_FPGA: Re: How to read data from intel strata flash using microblaze?
113321: 06/12/11: Pablo: Integrate VHDL Cores in Microblaze (Spartan 3E Starter Kit)
113328: 06/12/11: Alfmyk: ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)
    113329: 06/12/11: Anonymous: Re: ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)
    113374: 06/12/12: Alfmyk: Re: ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)
        113380: 06/12/12: Anonymous: Re: ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)
113332: 06/12/11: <rponsard@gmail.com>: spartan3E : which differential inputs level fits CAN2B bus level ?
    113333: 06/12/11: PeteS: Re: spartan3E : which differential inputs level fits CAN2B bus level ?
    113346: 06/12/11: Peter Alfke: Re: spartan3E : which differential inputs level fits CAN2B bus level ?
        113347: 06/12/11: PeteS: Re: spartan3E : which differential inputs level fits CAN2B bus level
113338: 06/12/11: tenteric: Give me job :)
    113364: 06/12/11: Peter Alfke: Re: Give me job :)
113339: 06/12/11: Chao: DDR2 DIMM memory termination resistors?
    113352: 06/12/11: Ben Jackson: Re: DDR2 DIMM memory termination resistors?
    113365: 06/12/12: Joseph Samson: Re: DDR2 DIMM memory termination resistors?
        113391: 06/12/12: Chao: Re: DDR2 DIMM memory termination resistors?
113340: 06/12/11: A.D.: Partial reconfiguration
    113366: 06/12/11: David: Re: Partial reconfiguration
        113390: 06/12/12: A.D.: Re: Partial reconfiguration
    113513: 06/12/15: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: Partial reconfiguration
113348: 06/12/11: John Adair: Tarfessock1
    113350: 06/12/11: Antti Lukats: Re: Tarfessock1
    113351: 06/12/11: Tommy Thorn: Re: Tarfessock1
    113354: 06/12/11: Andy Peters: Re: Tarfessock1
        113355: 06/12/11: Antti Lukats: Re: Tarfessock1
            113397: 06/12/13: Jim Granville: Re: Tarfessock1
                113446: 06/12/13: Rube Bumpkin: Re: Tarfessock1
    113399: 06/12/12: John Adair: Re: Tarfessock1
    113423: 06/12/13: Nicolas Matringe: Re: Tarfessock1
113357: 06/12/11: colin: config prom power
113363: 06/12/11: John: Virtex4 : cleaner signals?
    113367: 06/12/11: Austin: Re: Virtex4 : cleaner signals?
    113389: 06/12/12: Dave Pollum: Re: Virtex4 : cleaner signals?
    113393: 06/12/12: JuanC: Re: Virtex4 : cleaner signals?
    113398: 06/12/12: Peter Alfke: Re: Virtex4 : cleaner signals?
    113409: 06/12/13: Symon: Re: Virtex4 : cleaner signals?
        113426: 06/12/13: Tim: Re: Virtex4 : cleaner signals?
    113443: 06/12/13: John: Re: Virtex4 : cleaner signals?
        113447: 06/12/13: John_H: Re: Virtex4 : cleaner signals?
        113468: 06/12/14: Symon: Re: Virtex4 : cleaner signals?
    113485: 06/12/14: John: Re: Virtex4 : cleaner signals?
113369: 06/12/11: <eascheiber@yahoo.com>: booting from isocm
113376: 06/12/12: cpmetz@googlemail.com: Question about Verilog Semantics / Xilinx Synthesis of embedded EMAC
    113382: 06/12/12: Gabor: Re: Question about Verilog Semantics / Xilinx Synthesis of embedded EMAC
    113410: 06/12/13: cpmetz@googlemail.com: Re: Question about Verilog Semantics / Xilinx Synthesis of embedded EMAC
113381: 06/12/12: <paulcullen@purewebsites.co.uk>: . What is the sign-and-magnitude of the following 4's complement number? (Leave answer in base 4).
    113383: 06/12/12: Ray Andraka: Re: . What is the sign-and-magnitude of the following 4's complement
    113384: 06/12/12: PeteS: Re: . What is the sign-and-magnitude of the following 4's complement number? (Leave answer in base 4).
    113432: 06/12/13: Brian Drummond: Re: . What is the sign-and-magnitude of the following 4's complement number? (Leave answer in base 4).
        113457: 06/12/13: glen herrmannsfeldt: Re: . What is the sign-and-magnitude of the following 4's complement
113385: 06/12/12: MJ Pearson: Camera Link to XUP V2Pro Board
    113388: 06/12/12: wallge: Re: Camera Link to XUP V2Pro Board
113386: 06/12/12: David: ISP interface
    113392: 06/12/12: Antti: Re: ISP interface
        113394: 06/12/12: PeteS: Re: ISP interface
            113396: 06/12/12: PeteS: Re: ISP interface
    113395: 06/12/12: Antti: Re: ISP interface
113401: 06/12/12: mike: Next Xilinx starter Kit
113403: 06/12/12: bijoy: FPGA : Async FIFO, Programmable full
    113408: 06/12/13: Symon: Re: FPGA : Async FIFO, Programmable full
        113424: 06/12/13: Kim Enkovaara: Re: FPGA : Async FIFO, Programmable full
            113429: 06/12/13: Ben Jones: Re: FPGA : Async FIFO, Programmable full
                113480: 06/12/14: RCIngham: Re: FPGA : Async FIFO, Programmable full
                    113535: 06/12/15: Ray Andraka: Re: FPGA : Async FIFO, Programmable full
                        113542: 06/12/15: Ray Andraka: Re: FPGA : Async FIFO, Programmable full
                    113572: 06/12/17: Daniel S.: Re: FPGA : Async FIFO, Programmable full
                        113585: 06/12/17: Daniel S.: Re: FPGA : Async FIFO, Programmable full
                            113592: 06/12/17: Daniel S.: Re: FPGA : Async FIFO, Programmable full
                                113610: 06/12/18: Daniel S.: Re: FPGA : Async FIFO, Programmable full
                                    113665: 06/12/19: Daniel S.: Re: FPGA : Async FIFO, Programmable full
    113451: 06/12/14: KJ: Re: FPGA : Async FIFO, Programmable full
        113471: 06/12/14: Kim Enkovaara: Re: FPGA : Async FIFO, Programmable full
    113486: 06/12/14: KJ: Re: FPGA : Async FIFO, Programmable full
    113487: 06/12/14: Tommy Thorn: Re: FPGA : Async FIFO, Programmable full
    113509: 06/12/14: Peter Alfke: Re: FPGA : Async FIFO, Programmable full
    113538: 06/12/15: Tommy Thorn: Re: FPGA : Async FIFO, Programmable full
    113546: 06/12/15: Tommy Thorn: Re: FPGA : Async FIFO, Programmable full
    113576: 06/12/17: Peter Alfke: Re: FPGA : Async FIFO, Programmable full
    113591: 06/12/17: Peter Alfke: Re: FPGA : Async FIFO, Programmable full
    113596: 06/12/17: Peter Alfke: Re: FPGA : Async FIFO, Programmable full
    113621: 06/12/18: Peter Alfke: Re: FPGA : Async FIFO, Programmable full
    113697: 06/12/19: Peter Alfke: Re: FPGA : Async FIFO, Programmable full
113407: 06/12/13: Metin: BLVDS_25 @ SPARTAN3
    113428: 06/12/13: John_H: Re: BLVDS_25 @ SPARTAN3
    113433: 06/12/13: Austin Lesea: Re: BLVDS_25 @ SPARTAN3
113411: 06/12/13: <shareef.jalloq@lightblueoptics.com>: NOR Flash Controller
    113436: 06/12/13: PeteS: Re: NOR Flash Controller
        113492: 06/12/14: PeteS: Re: NOR Flash Controller
    113463: 06/12/14: lbo_user: Re: NOR Flash Controller
    113464: 06/12/14: PeteS: Re: NOR Flash Controller
    113465: 06/12/14: PeteS: Re: NOR Flash Controller
    113469: 06/12/14: lbo_user: Re: NOR Flash Controller
113412: 06/12/13: Kurt Kaiser: electrical interface problem LVPECL - LVDS multi-inputs
    113441: 06/12/13: Andy: Re: electrical interface problem LVPECL - LVDS multi-inputs
        113456: 06/12/14: Kurt Kaiser: Re: electrical interface problem LVPECL - LVDS multi-inputs
    113491: 06/12/14: Andy: Re: electrical interface problem LVPECL - LVDS multi-inputs
    113526: 06/12/15: Gabor: Re: electrical interface problem LVPECL - LVDS multi-inputs
113413: 06/12/13: ma: IQ multiplier
    113427: 06/12/13: Jerry Avins: Re: IQ multiplier
        113437: 06/12/13: ma: Re: IQ multiplier
            113511: 06/12/15: Howard Long: Re: IQ multiplier
                113527: 06/12/15: Jerry Avins: Re: IQ multiplier
    113503: 06/12/14: Clay: Re: IQ multiplier
        113504: 06/12/14: Jerry Avins: Re: IQ multiplier
        113551: 06/12/16: Rick Lyons: Re: IQ multiplier
113414: 06/12/13: Alfmyk: MicroBlaze : -mcpu=4.00.b option for mb-gcc compiler...
    113445: 06/12/13: Vasanth Asokan: Re: MicroBlaze : -mcpu=4.00.b option for mb-gcc compiler...
    113479: 06/12/14: Alfmyk: Re: MicroBlaze : -mcpu=4.00.b option for mb-gcc compiler...
113415: 06/12/13: =?utf-8?B?R2FMYUt0SWtVc+KEog==?=: Energy consumption estimation of Virtex-4
    113416: 06/12/13: Symon: Re: Energy consumption estimation of Virtex-4
    113422: 06/12/13: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: Energy consumption estimation of Virtex-4
113418: 06/12/13: <rponsard@gmail.com>: what are your current SoC design for ?
    113420: 06/12/13: Jon Beniston: Re: what are your current SoC design for ?
    113430: 06/12/13: <rponsard@gmail.com>: Re: what are your current SoC design for ?
    113431: 06/12/13: Kolja Sulimma: Re: what are your current SoC design for ?
    113454: 06/12/14: Marco T.: Re: what are your current SoC design for ?
    113460: 06/12/14: Jim Granville: Re: what are your current SoC design for ?
    113476: 06/12/14: radarman: Re: what are your current SoC design for ?
    113478: 06/12/14: Antti: Re: what are your current SoC design for ?
    113595: 06/12/17: Daniel S.: Re: what are your current SoC design for ?
    114234: 07/01/08: Peter Y: Re: what are your current SoC design for ?
113419: 06/12/13: Jiten: Maplib Error 661.
    113421: 06/12/13: Jon Beniston: Re: Maplib Error 661.
    113483: 06/12/14: beeraka@gmail.com: Re: Maplib Error 661.
113425: 06/12/13: Koen Van Renterghem: Ones' complement addition
    113458: 06/12/13: glen herrmannsfeldt: Re: Ones' complement addition
        113473: 06/12/14: Koen Van Renterghem: Re: Ones' complement addition
            114227: 07/01/08: glen herrmannsfeldt: Re: Ones' complement addition
                114343: 07/01/12: glen herrmannsfeldt: Re: Ones' complement addition
                114388: 07/01/13: Eric Smith: Re: Ones' complement addition
                    114498: 07/01/17: Eric Smith: Re: Ones' complement addition
                        114684: 07/01/22: Eric Smith: Re: Ones' complement addition
                        114701: 07/01/23: Koen Van Renterghem: Re: Ones' complement addition
                    114559: 07/01/19: Koen Van Renterghem: Re: Ones' complement addition
113434: 06/12/13: JuanC: Re: FPGA : Async FIFO, Programmable full
113435: 06/12/13: chriskoh: more of ERROR:MapLib:661
    113442: 06/12/13: VC: Re: more of ERROR:MapLib:661
    113450: 06/12/13: chriskoh: Re: more of ERROR:MapLib:661
113438: 06/12/13: Martin: GUI Based vs. Manual Instantiation of Components
    113439: 06/12/13: John_H: Re: GUI Based vs. Manual Instantiation of Components
113440: 06/12/13: ma: Complex mixer
    113448: 06/12/13: Tim Wescott: Re: Complex mixer
113444: 06/12/13: Peter Alfke: Re: FPGA : Async FIFO, Programmable full
113449: 06/12/13: <ashish.dobhal@gmail.com>: How does FPGA tools infer FIFO
    113452: 06/12/14: John_H: Re: How does FPGA tools infer FIFO
        113470: 06/12/14: KJ: Re: How does FPGA tools infer FIFO
            113472: 06/12/14: Kim Enkovaara: Re: How does FPGA tools infer FIFO
                113481: 06/12/14: RCIngham: Re: How does FPGA tools infer FIFO
                    113489: 06/12/14: Mike Treseler: Re: How does FPGA tools infer FIFO
            113525: 06/12/15: Kolja Sulimma: Re: How does FPGA tools infer FIFO
                113528: 06/12/15: Hans: Re: How does FPGA tools infer FIFO
    113488: 06/12/14: Andy: Re: How does FPGA tools infer FIFO
113453: 06/12/14: Volker: CMI Coder/ Decoder
    113475: 06/12/14: John_H: Re: CMI Coder/ Decoder
113466: 06/12/14: ram: query
113467: 06/12/14: Pablo: SDRAM in SPARTAN 3E
113477: 06/12/14: Steve: How to get ISE to create a _bd.bmm file for BRAM initialization
    113490: 06/12/14: MM: Re: How to get ISE to create a _bd.bmm file for BRAM initialization
        113524: 06/12/15: Brian Drummond: Re: How to get ISE to create a _bd.bmm file for BRAM initialization
    113514: 06/12/15: Arnaud: Re: How to get ISE to create a _bd.bmm file for BRAM initialization
    115109: 07/01/31: Steve: Re: How to get ISE to create a _bd.bmm file for BRAM initialization
    116474: 07/03/09: MM: Re: How to get ISE to create a _bd.bmm file for BRAM initialization
113484: 06/12/14: Peter Alfke: Re: FPGA : Async FIFO, Programmable full
113494: 06/12/14: Thang Nguyen: Port OS: Error when generate the Libraryies and BSPs
113496: 06/12/14: Kolja Sulimma: Virtex-V MGT SONET alignment
    113515: 06/12/15: Kolja Sulimma: Re: Virtex-V MGT SONET alignment
113497: 06/12/14: abright52: Virtex-II Pro: Reading/Writing data with Compact Flash
    113508: 06/12/14: Lasse: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
    113533: 06/12/15: David: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
    113649: 06/12/18: abright52: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
    113650: 06/12/18: abright52: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
    113796: 06/12/21: abright52: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
    113801: 06/12/22: Jon Beniston: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
    114265: 07/01/09: abright52: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
113499: 06/12/14: sonetguest: Adding Jitter
    113501: 06/12/14: John_H: Re: Adding Jitter
113500: 06/12/14: sonetguest: Using SYSTEM_JITTER and INPUT_JITTER for timing analysis.
113502: 06/12/14: sonetguest: Xilinx SYSTEM_JITTER, INPUT_JITTER Questions - Part II
113505: 06/12/15: mk: gtkwave 3.0.18 for win32
    113510: 06/12/15: AMONTEC: Re: gtkwave 3.0.18 for win32
    114956: 07/01/28: mk: gtkwave 3.0.20 for win32
        122171: 07/07/21: mk: GTKWave 3.0.29 for win32
113506: 06/12/14: ram: Query
    113507: 06/12/14: ram: Re: Query
113516: 06/12/15: Thomas Reinemann: Resource estimation
    113517: 06/12/15: Symon: Re: Resource estimation
    113520: 06/12/15: RCIngham: Re: Resource estimation
113523: 06/12/15: meshoshow: Lcd Block Diagram - Vhdl - On Fpga.. help!
113529: 06/12/15: Richard Henry: Re: electrical level conversion
    113530: 06/12/15: Austin Lesea: Re: electrical level conversion
        113534: 06/12/15: Symon: Re: electrical level conversion
            113536: 06/12/15: Austin Lesea: Re: electrical level conversion
        113543: 06/12/15: John Larkin: Re: electrical level conversion
113531: 06/12/15: marc_ely: Xilinx ISE 8.2.3 - Re-Creating Projects
113532: 06/12/15: marc_ely: Xilins ISE Re-Creating Projects
    113565: 06/12/17: jtw: Re: Xilins ISE Re-Creating Projects
    113566: 06/12/16: David M. Palmer: Re: Xilins ISE Re-Creating Projects
        113599: 06/12/18: Antti Lukats: Re: Xilins ISE Re-Creating Projects
    113582: 06/12/17: marc_ely: Re: Xilins ISE Re-Creating Projects
    113594: 06/12/17: johnp: Re: Xilins ISE Re-Creating Projects
113539: 06/12/15: jerzy.zielinski: uClinux bootloader on Spartan-3e Starter Kit
    113562: 06/12/16: Ben Jackson: Re: uClinux bootloader on Spartan-3e Starter Kit
    113714: 06/12/20: John Williams: Re: uClinux bootloader on Spartan-3e Starter Kit
113540: 06/12/15: Dale: 3.3V LVPECL into a LVPECL_25, VCCO-2.5V on a Virtex-4
    113544: 06/12/15: Austin Lesea: Re: 3.3V LVPECL into a LVPECL_25, VCCO-2.5V on a Virtex-4
113541: 06/12/15: tersono: Xilinx WebPack 8.2.03i: can't make .bit file when memories used in design
113545: 06/12/15: johnp: Xilinx PMCD+DCM reset question...
    113547: 06/12/15: Austin Lesea: Re: Xilinx PMCD+DCM reset question...
    113549: 06/12/15: johnp: Re: Xilinx PMCD+DCM reset question...
    113555: 06/12/16: Ricky Su: Re: Xilinx PMCD+DCM reset question...
113548: 06/12/15: Gabor: Re: Xilins ISE Re-Creating Projects
113550: 06/12/15: johnp: Re: Xilins ISE Re-Creating Projects
113553: 06/12/15: Brian Davis: Re: electrical level conversion
    113579: 06/12/17: Austin: Re: electrical level conversion
        113587: 06/12/17: Austin: Re: electrical level conversion
            113590: 06/12/17: Austin: Re: electrical level conversion
                113629: 06/12/18: Austin Lesea: Re: electrical level conversion
                    113659: 06/12/19: Symon: Re: electrical level conversion
        113606: 06/12/18: Symon: Re: electrical level conversion
            113611: 06/12/18: Tim: Re: electrical level conversion
            113671: 06/12/19: Symon: Re: electrical level conversion
113554: 06/12/15: personel: Netlist Simulation for PPC (Virtex-4 FPGA)
113558: 06/12/16: Vangelis: PowerPC_EDK to ISE
    113561: 06/12/16: Antti: Re: PowerPC_EDK to ISE
    113577: 06/12/17: Moti Cohen: Re: PowerPC_EDK to ISE
    113583: 06/12/17: Vangelis: Re: PowerPC_EDK to ISE
113564: 06/12/16: alterauser: Re: Xilinx ISE 8.2.3 - Re-Creating Projects
113567: 06/12/16: kyori: DSP or FPGA for high-speed image processing?
    113584: 06/12/17: Tim Wescott: Re: DSP or FPGA for high-speed image processing?
    113604: 06/12/18: Martin Thompson: Re: DSP or FPGA for high-speed image processing?
    113817: 06/12/22: kyori: Re: DSP or FPGA for high-speed image processing?
    113819: 06/12/22: kyori: Re: DSP or FPGA for high-speed image processing?
113568: 06/12/17: <222>: Frequency divider?
    113569: 06/12/17: <222>: Re: Frequency divider?
        113573: 06/12/17: Daniel S.: Re: Frequency divider?
            113574: 06/12/17: <222>: Re: Frequency divider?
                113597: 06/12/17: Daniel S.: Re: Frequency divider?
                    113622: 06/12/18: Matthew Hicks: Re: Frequency divider?
                    113623: 06/12/18: Matthew Hicks: Re: Frequency divider?
                        113632: 06/12/18: <222>: Re: Frequency divider?
                            113636: 06/12/18: glen herrmannsfeldt: Re: Frequency divider?
                        113639: 06/12/18: PeteS: Re: Frequency divider?
    113570: 06/12/17: PeteS: Re: Frequency divider?
        113571: 06/12/17: PeteS: Re: Frequency divider?
            113578: 06/12/17: <222>: Re: Frequency divider?
                113580: 06/12/17: tersono: Re: Frequency divider?
                    113586: 06/12/17: <222>: Re: Frequency divider?
    113625: 06/12/18: Peter Alfke: Re: Frequency divider?
113575: 06/12/17: Pasacco: EDK, header file modified and problem
113581: 06/12/17: Brian Davis: Re: electrical level conversion
113588: 06/12/17: Brian Davis: Re: electrical level conversion
113589: 06/12/17: Michael A. Terrell: Re: electrical level conversion
113598: 06/12/17: Thang Nguyen: ERROR:MDT - ERROR FROM TCL:- linux_mvl31 ()
113600: 06/12/17: <eascheiber@yahoo.com>: ppc elf data and vectors sections
    113614: 06/12/18: cpope: Re: ppc elf data and vectors sections
113601: 06/12/18: Al: solder mask for fpga dissipation
    113602: 06/12/18: AMONTEC: Re: solder mask for fpga dissipation
        113603: 06/12/18: Al: Re: solder mask for fpga dissipation
            113605: 06/12/18: Al: Re: solder mask for fpga dissipation
                113607: 06/12/18: Symon: Re: solder mask for fpga dissipation
                113644: 06/12/19: Jim Granville: Re: solder mask for fpga dissipation
            113638: 06/12/18: PeteS: Re: solder mask for fpga dissipation
                113640: 06/12/18: John_H: Re: solder mask for fpga dissipation
                    113641: 06/12/19: glen herrmannsfeldt: Re: solder mask for fpga dissipation
                        113655: 06/12/19: Al: Re: solder mask for fpga dissipation
    113829: 06/12/23: John Larkin: Re: solder mask for fpga dissipation
113608: 06/12/18: Pablo: VHDL CODE FOR SDRAM IN SPARTAN 3E
    113609: 06/12/18: Antti: Re: VHDL CODE FOR SDRAM IN SPARTAN 3E
    113612: 06/12/18: Ricky Su: Re: VHDL CODE FOR SDRAM IN SPARTAN 3E
    113619: 06/12/18: Pablo: Re: VHDL CODE FOR SDRAM IN SPARTAN 3E
113613: 06/12/18: Johannes Hausensteiner: unpredictable FPGA behaviour
    113615: 06/12/18: Gabor: Re: unpredictable FPGA behaviour
    113620: 06/12/18: Dave Pollum: Re: unpredictable FPGA behaviour
    113719: 06/12/20: Miro: Re: unpredictable FPGA behaviour
113616: 06/12/18: <thomas.neitzel@gmail.com>: unexplainable Problem on Spartan 3
    113667: 06/12/19: rickman: Re: unexplainable Problem on Spartan 3
    113675: 06/12/19: Randy Robinson: Re: unexplainable Problem on Spartan 3
    113683: 06/12/19: <thomas.neitzel@gmail.com>: Re: unexplainable Problem on Spartan 3
113617: 06/12/18: Christian Wiesner: OFFSET Constraining a Signal behind a DCM?
113624: 06/12/18: Andreas Ehliar: Announce: XDLAnalyze v1.1 and colorized_signals (for ModelSim) v1.1
    113660: 06/12/19: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Announce: XDLAnalyze v1.1 and colorized_signals (for ModelSim) v1.1
        113677: 06/12/19: Martin Thompson: Re: Announce: XDLAnalyze v1.1 and colorized_signals (for ModelSim) v1.1
            113720: 06/12/20: Andreas Ehliar: Re: Announce: XDLAnalyze v1.1 and colorized_signals (for ModelSim) v1.1
113626: 06/12/18: <jetmarc@hotmail.com>: FX12 ethernet resource usage
    113628: 06/12/18: Sean Durkin: Re: FX12 ethernet resource usage
        113642: 06/12/18: davide: Re: FX12 ethernet resource usage
    113634: 06/12/18: Ben Jackson: Re: FX12 ethernet resource usage
113627: 06/12/18: David B. Thomas: incremental compiles in quartus
    113631: 06/12/18: jbnote: Re: incremental compiles in quartus
    113648: 06/12/18: Subroto Datta: Re: incremental compiles in quartus
113643: 06/12/19: <222>: Frequency divider ?
    113645: 06/12/19: KJ: Re: Frequency divider ?
        113646: 06/12/19: <222>: Re: Frequency divider ?
            113647: 06/12/19: KJ: Re: Frequency divider ?
                113663: 06/12/19: <222>: Re: Frequency divider ?
                    113668: 06/12/19: Andreas Ehliar: Re: Frequency divider ?
                        113670: 06/12/19: <222>: Re: Frequency divider ?
                            113678: 06/12/19: Mike Lewis: Re: Frequency divider ?
                                113680: 06/12/19: Will Dean: Re: Frequency divider ?
                                113685: 06/12/19: <222>: Re: Frequency divider ?
    113681: 06/12/19: motty: Re: Frequency divider ?
    113686: 06/12/19: motty: Re: Frequency divider ?
    113688: 06/12/19: Peter Alfke: Re: Frequency divider ?
113651: 06/12/18: Brian Davis: Re: electrical level conversion
113652: 06/12/18: gomsi: jtag reset seq
    113653: 06/12/18: Jim Wu: Re: jtag reset seq
        113662: 06/12/19: Dominic: Re: jtag reset seq
    113654: 06/12/19: gomsi: Re: jtag reset seq
    113656: 06/12/19: Antti: Re: jtag reset seq
    113666: 06/12/19: gomsi: Re: jtag reset seq
    113669: 06/12/19: Antti: Re: jtag reset seq
    113715: 06/12/19: gomsi: Re: jtag reset seq
    113716: 06/12/19: Antti: Re: jtag reset seq
    113721: 06/12/20: gomsi: Re: jtag reset seq
113657: 06/12/19: <zhongqiang.cheng@gmail.com>: Operate on RAM through FPGA
    113664: 06/12/19: Pablo: Re: Operate on RAM through FPGA
    113687: 06/12/19: Vangelis: Re: Operate on RAM through FPGA
113658: 06/12/19: Andreas F.: C2H problems
    113672: 06/12/19: Subroto Datta: Re: C2H problems
    113674: 06/12/19: Karl: Re: C2H problems
    113718: 06/12/19: Andreas F.: Re: C2H problems
113661: 06/12/19: Friedrich Kiesel: Integrating Atera =?UTF-8?B?4oCcRkZUIE1lZ2FDb3JlIEZ1bmN0aW9u4oCd?=
113673: 06/12/19: Antti: Xilinx Quiz: 150/3 = ?
    113684: 06/12/19: Sylvain Munaut: Re: Xilinx Quiz: 150/3 = ?
        113731: 06/12/20: Brian Drummond: Re: Xilinx Quiz: 150/3 = ?
            113745: 06/12/20: Sylvain Munaut: Re: Xilinx Quiz: 150/3 = ?
113676: 06/12/19: <rpd_computer06@yahoo.com>: dcf file format
113679: 06/12/19: Ndf: PLL minimum input clock frequency
    113689: 06/12/19: Gabor: Re: PLL minimum input clock frequency
        113724: 06/12/20: Symon: Re: PLL minimum input clock frequency
            113733: 06/12/20: Ndf: Re: PLL minimum input clock frequency
    113791: 06/12/21: <kayrock66@yahoo.com>: Re: PLL minimum input clock frequency
113682: 06/12/19: chriskoh: interrupt handling using microblaze with XPS
    113692: 06/12/19: CBFalconer: Re: interrupt handling using microblaze with XPS
        113699: 06/12/19: Grant Edwards: Re: interrupt handling using microblaze with XPS
            113707: 06/12/19: CBFalconer: Re: interrupt handling using microblaze with XPS
    113701: 06/12/19: FreeRTOS.org: Re: interrupt handling using microblaze with XPS
113690: 06/12/19: Vangelis: PowerPC_simulation
    113732: 06/12/20: Brian Drummond: Re: PowerPC_simulation
113691: 06/12/19: Antti Lukats: ANN: PicoBlaze C: compile to bitstream!
    113693: 06/12/20: Jim Granville: Re: ANN: PicoBlaze C: compile to bitstream!
        113704: 06/12/19: Antti Lukats: Re: ANN: PicoBlaze C: compile to bitstream!
    113753: 06/12/20: Nico Coesel: Re: ANN: PicoBlaze C: compile to bitstream!
    113783: 06/12/21: spartan3wiz: Re: ANN: PicoBlaze C: compile to bitstream!
        113788: 06/12/21: Antti Lukats: Re: ANN: PicoBlaze C: compile to bitstream!
    113825: 06/12/23: spartan3wiz: Re: ANN: PicoBlaze C: compile to bitstream!
    113911: 06/12/29: Alex Gibson: Re: PicoBlaze C: compile to bitstream!
        113941: 06/12/29: Antti Lukats: Re: PicoBlaze C: compile to bitstream!
113694: 06/12/19: cutemonster: Dynamic DCM Controller help
113695: 06/12/19: MM: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
    113703: 06/12/19: glen herrmannsfeldt: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
        113705: 06/12/19: MM: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
            113945: 06/12/29: Eric Smith: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
    113706: 06/12/19: Antti: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
        113708: 06/12/19: glen herrmannsfeldt: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
        113709: 06/12/19: Uwe Bonnes: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
    113711: 06/12/19: Joseph Samson: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV
    113712: 06/12/19: cpope: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
        113734: 06/12/20: MM: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
    113717: 06/12/20: AMONTEC: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV
    113728: 06/12/20: Symon: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
    113996: 07/01/02: Guenter: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
113696: 06/12/19: <212>: Need book for verilog on xc9536?
    113700: 06/12/19: Gabor: Re: Need book for verilog on xc9536?
    113702: 06/12/19: Dave Pollum: Re: Need book for verilog on xc9536?
    113710: 06/12/19: PeteS: Re: Need book for verilog on xc9536?
113698: 06/12/19: cutemonster: Dynamic DCM Controller help
113713: 06/12/19: karrelsj: Board for sale
113722: 06/12/20: Yaseen Zaidi: Tracing UNKNOWN drivers
    113727: 06/12/20: KJ: Re: Tracing UNKNOWN drivers
113723: 06/12/20: Yaseen Zaidi: Tracing UNKNOWN drivers
113725: 06/12/20: Manfred Balik: CPLD speed/temperature equivalent
    113730: 06/12/20: Gabor: Re: CPLD speed/temperature equivalent
113726: 06/12/20: Guru: Re: Spartan 3E Starter Kit Woes
    113749: 06/12/20: Ben Jackson: Re: Spartan 3E Starter Kit Woes
        113752: 06/12/20: Antti Lukats: Re: Spartan 3E Starter Kit Woes
            113758: 06/12/20: Ray Andraka: Re: Spartan 3E Starter Kit Woes
                113760: 06/12/20: Ray Andraka: Re: Spartan 3E Starter Kit Woes
                    113764: 06/12/20: Ray Andraka: Re: Spartan 3E Starter Kit Woes
                    113774: 06/12/21: John Williams: Re: Spartan 3E Starter Kit Woes
113729: 06/12/20: Antti: Re: Spartan 3E Starter Kit Woes
113735: 06/12/20: Pablo: MICROBLAZE AND OPB: TOO SLOW FOR VGA
    113741: 06/12/20: Antti: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
        113776: 06/12/21: Marco T.: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
            113785: 06/12/21: Marco T.: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
    113742: 06/12/20: Pablo: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
    113746: 06/12/20: Erik Widding: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
    113747: 06/12/20: Erik Widding: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
    113775: 06/12/21: Marco T.: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
    113777: 06/12/20: Antti: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
113736: 06/12/20: Symon: CCLK Virtex4 IBIS model.
    113737: 06/12/20: Symon: Re: CCLK Virtex4 IBIS model.
    113743: 06/12/20: Austin Lesea: Re: CCLK Virtex4 IBIS model.
        113748: 06/12/20: Symon: Re: CCLK Virtex4 IBIS model.
            113750: 06/12/20: Austin Lesea: Re: CCLK Virtex4 IBIS model.
                113751: 06/12/20: Symon: Re: CCLK Virtex4 IBIS model.
113738: 06/12/20: bg: A nice CIC-Filter, but I can't find the result in the bitsequence!?
    113767: 06/12/20: Ray Andraka: Re: A nice CIC-Filter, but I can't find the result in the bitsequence!?
    113779: 06/12/21: bg: Re: A nice CIC-Filter, but I can't find the result in the bitsequence!?
113739: 06/12/20: David: Manually creating a LUT in VHDL
    113740: 06/12/20: Andreas Ehliar: Re: Manually creating a LUT in VHDL
    113744: 06/12/20: Tim: Re: Manually creating a LUT in VHDL
    113765: 06/12/20: Ray Andraka: Re: Manually creating a LUT in VHDL
    113802: 06/12/22: David: Re: Manually creating a LUT in VHDL
113754: 06/12/20: Antti: Re: ANN: PicoBlaze C: compile to bitstream!
    113768: 06/12/20: Nico Coesel: Re: ANN: PicoBlaze C: compile to bitstream!
113755: 06/12/20: Karen Halgren: New user help required
    113757: 06/12/20: Jon Beniston: Re: New user help required
        113762: 06/12/20: Karen Halgren: Re: New user help required
            113780: 06/12/21: Symon: Re: New user help required
    113770: 06/12/20: chris: Re: New user help required
113756: 06/12/20: Venu: nets not recognised
113759: 06/12/20: Antti: Re: Spartan 3E Starter Kit Woes
113761: 06/12/20: Antti: Re: Spartan 3E Starter Kit Woes
113763: 06/12/20: <hattangady@gmail.com>: Soft processor Microblaze vs embedded core PowerPC
    113766: 06/12/20: Jon Beniston: Re: Soft processor Microblaze vs embedded core PowerPC
        113769: 06/12/20: Austin Lesea: Re: Soft processor Microblaze vs embedded core PowerPC
        113773: 06/12/21: John Williams: Re: Soft processor Microblaze vs embedded core PowerPC
    113792: 06/12/21: <kayrock66@yahoo.com>: Re: Soft processor Microblaze vs embedded core PowerPC
113771: 06/12/21: <223>: timing?
    113772: 06/12/21: Rob: Re: timing?
    113789: 06/12/21: Mike Treseler: Re: timing?
    113814: 06/12/22: motty: Re: timing?
113778: 06/12/21: Andy: Embedded Development Tools
113781: 06/12/21: Pablo: XILKERNEL and MICROBLAZE (how to probe this)
    113782: 06/12/21: Jon Beniston: Re: XILKERNEL and MICROBLAZE (how to probe this)
113784: 06/12/21: <phooey>: How to simulate from the xilinx ISE
    113786: 06/12/21: Pablo: Re: How to simulate from the xilinx ISE
    113787: 06/12/21: <helmut.leonhardt@gmail.com>: Re: How to simulate from the xilinx ISE
113790: 06/12/21: jjlindula@hotmail.com: What next next big thing coming for HDL?
    113820: 06/12/23: Bob Smith: Re: What next next big thing coming for HDL?
    113824: 06/12/23: Norbert Stuhrmann: Re: What next next big thing coming for HDL?
        113886: 06/12/28: Hans: Re: What next next big thing coming for HDL?
    113868: 06/12/26: jjlindula@hotmail.com: Re: What next next big thing coming for HDL?
    113882: 06/12/27: ChampDog: Re: What next next big thing coming for HDL?
    113883: 06/12/27: ChampDog: Re: What next next big thing coming for HDL?
    113889: 06/12/28: Guenter: Re: What next next big thing coming for HDL?
    113892: 06/12/28: jjlindula@hotmail.com: Re: What next next big thing coming for HDL?
    113895: 06/12/28: Guenter: Re: What next next big thing coming for HDL?
113793: 06/12/21: Roger: DCM start up
    113795: 06/12/21: Austin: Re: DCM start up
    113798: 06/12/22: Brian Drummond: Re: DCM start up
    113800: 06/12/22: Brian Davis: Re: DCM start up
    113804: 06/12/22: Roger: Re: DCM start up
113794: 06/12/21: <hattangady@gmail.com>: FSL feasibiliity
    113797: 06/12/22: Lorne Mower: Re: FSL feasibiliity
113811: 06/12/22: <xx>: Help with xilinx simulation?
    113812: 06/12/22: davide: Re: Help with xilinx simulation?
        113813: 06/12/22: <xx>: Re: Help with xilinx simulation?
            113816: 06/12/23: <xx>: Re: Help with xilinx simulation?
                113827: 06/12/23: Mike Treseler: Re: Help with xilinx simulation?
                    113847: 06/12/25: <xx>: Re: Help with xilinx simulation?
            113830: 06/12/23: KJ: Re: Help with xilinx simulation?
                113848: 06/12/25: <xx>: Re: Help with xilinx simulation?
                    113870: 06/12/26: KJ: Re: Help with xilinx simulation?
    113834: 06/12/23: Brad Smallridge: Re: Help with xilinx simulation?
        113846: 06/12/25: <xx>: Re: Help with xilinx simulation?
            113869: 06/12/26: Brad Smallridge: Re: Help with xilinx simulation?
        113849: 06/12/25: <xx>: Re: Help with xilinx simulation?
    113859: 06/12/26: Josep Duran: Re: Help with xilinx simulation?
113818: 06/12/22: Andy: Embedded Development Tools
113822: 06/12/23: Manny: IEEE fixed-point package FATAL_ERROR
113832: 06/12/23: Antti Lukats: PicoChristmas - 112 Free PicoBlaze KCPSM based MicroFpga's released
113833: 06/12/23: jacko: max II dev kit pin grid
113836: 06/12/23: Vitaliy: Matlab (.m) to VHDL
    113876: 06/12/27: David Bishop: Re: Matlab (.m) to VHDL
        113986: 07/01/01: Jim Lewis: Re: Matlab (.m) to VHDL
    113878: 06/12/27: Hemang Parekh: Re: Matlab (.m) to VHDL
113837: 06/12/24: <mwiesbock@gmail.com>: Signal <foo> is assigned but never used. XST Warning help
    113843: 06/12/24: KJ: Re: Signal <foo> is assigned but never used. XST Warning help
    113844: 06/12/24: Joseph Samson: Re: Signal <foo> is assigned but never used. XST Warning help
113838: 06/12/24: chat: mobius, from codetronix, anyone has been tested
    113845: 06/12/24: Mike Treseler: Re: mobius, from codetronix, anyone has been tested
113839: 06/12/24: Guy_FPGA: Need Recommandation for DDR2 controller virtex4
    113841: 06/12/24: tbrown: Re: Need Recommandation for DDR2 controller virtex4
    113842: 06/12/24: Guy_FPGA: Re: Need Recommandation for DDR2 controller virtex4
113840: 06/12/24: Venu: OPB master implementation
    113855: 06/12/26: Zara: Re: OPB master implementation
        113875: 06/12/27: Zara: Re: OPB master implementation
    113874: 06/12/27: <jetmarc@hotmail.com>: Re: OPB master implementation
    113921: 06/12/29: Venu: Re: OPB master implementation
113850: 06/12/25: <topweaver@hotmail.com>: Judge complex degree by state numbers?
    113864: 06/12/26: KJ: Re: Judge complex degree by state numbers?
        114397: 07/01/14: KJ: Re: Judge complex degree by state numbers?
    114390: 07/01/14: <topweaver@hotmail.com>: Re: Judge complex degree by state numbers?
    114421: 07/01/15: <topweaver@hotmail.com>: Re: Judge complex degree by state numbers?
113851: 06/12/25: CMOS: better ways for debugging?
    113852: 06/12/25: Rob: Re: better ways for debugging?
    113858: 06/12/26: Nico Coesel: Re: better ways for debugging?
        113861: 06/12/26: Rube Bumpkin: Re: better ways for debugging?
    113860: 06/12/26: Brian Drummond: Re: better ways for debugging?
    113866: 06/12/26: KJ: Re: better ways for debugging?
    113897: 06/12/28: Marlboro: Re: better ways for debugging?
    114103: 07/01/04: CMOS: Re: better ways for debugging?
113853: 06/12/25: fpgauser: moving from xlinx 8.1 to 8.2 or better wait ?
    113854: 06/12/25: Antti Lukats: Re: moving from xlinx 8.1 to 8.2 or better wait ?
    113857: 06/12/26: tersono: Re: moving from xlinx 8.1 to 8.2 or better wait ?
        113908: 06/12/29: Zara: Re: moving from xlinx 8.1 to 8.2 or better wait ?
        113926: 06/12/29: tersono: Re: moving from xlinx 8.1 to 8.2 or better wait ?
    113902: 06/12/28: radarman: Re: moving from xlinx 8.1 to 8.2 or better wait ?
    113944: 06/12/29: radarman: Re: moving from xlinx 8.1 to 8.2 or better wait ?
113856: 06/12/26: Antti Lukats: Impact with non-standard LPT base addresses
    113863: 06/12/26: Dave Pollum: Re: Impact with non-standard LPT base addresses
        113865: 06/12/26: Antti Lukats: Re: Impact with non-standard LPT base addresses
    113867: 06/12/26: Dave Pollum: Re: Impact with non-standard LPT base addresses
113862: 06/12/26: Pablo: Problem in Xilkernel
    113873: 06/12/27: Pablo: Re: Problem in Xilkernel
    154116: 12/08/10: Jone_yang: RE: Problem in Xilkernel
113871: 06/12/26: Shenli: SystemVerilog Sequence Coverage Problem?
113872: 06/12/27: axalay: assigned a special pins in ISE
    113877: 06/12/27: Jim Wu: Re: assigned a special pins in ISE
        113930: 06/12/29: Austin: Re: assigned a special pins in ISE
    113914: 06/12/28: axalay: Re: assigned a special pins in ISE
113879: 06/12/27: jjlindula@hotmail.com: Why AHDL didn't catch on like Verilog or VHDL?
    113881: 06/12/28: KJ: Re: Why AHDL didn't catch on like Verilog or VHDL?
    113885: 06/12/28: John_H: Re: Why AHDL didn't catch on like Verilog or VHDL?
113880: 06/12/27: <axr0284@yahoo.com>: ethernet checksum nightmare
    113884: 06/12/28: Kim Enkovaara: Re: ethernet checksum nightmare
        113890: 06/12/28: Kim Enkovaara: Re: ethernet checksum nightmare
        114346: 07/01/12: glen herrmannsfeldt: Re: ethernet checksum nightmare
            114347: 07/01/12: Kim Enkovaara: Re: ethernet checksum nightmare
                114565: 07/01/19: glen herrmannsfeldt: Re: ethernet checksum nightmare
    113887: 06/12/28: axr0284: Re: ethernet checksum nightmare
    113888: 06/12/28: axr0284: Re: ethernet checksum nightmare
    113896: 06/12/28: Colin Hankins: Re: ethernet checksum nightmare
        114345: 07/01/12: glen herrmannsfeldt: Re: ethernet checksum nightmare
            114376: 07/01/13: Mike Treseler: Re: ethernet checksum nightmare
    113907: 06/12/29: Philip Freidin: Re: ethernet checksum nightmare
        114344: 07/01/12: glen herrmannsfeldt: Re: ethernet checksum nightmare
            114378: 07/01/13: Mike Treseler: Re: ethernet checksum nightmare
    113938: 06/12/29: axr0284: Re: ethernet checksum nightmare
113891: 06/12/28: hsfranck@gmail.com: remove logic redundancy
    113898: 06/12/28: Marlboro: Re: remove logic redundancy
        113931: 06/12/29: Austin: Re: remove logic redundancy
            113933: 06/12/29: Symon: Re: remove logic redundancy
                113936: 06/12/29: Austin: Re: remove logic redundancy
    113912: 06/12/28: Nicolas Matringe: Re: remove logic redundancy
    113929: 06/12/29: Marlboro: Re: remove logic redundancy
    113932: 06/12/29: Nicolas Matringe: Re: remove logic redundancy
113893: 06/12/28: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: ChipScope - impact on design or not?
    113894: 06/12/28: Symon: Re: ChipScope - impact on design or not?
        113923: 06/12/29: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: ChipScope - impact on design or not?
            113924: 06/12/29: Symon: Re: ChipScope - impact on design or not?
                113927: 06/12/29: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: ChipScope - impact on design or not?
            113925: 06/12/29: Nico Coesel: Re: ChipScope - impact on design or not?
    113899: 06/12/28: radarman: Re: ChipScope - impact on design or not?
        113918: 06/12/29: Nico Coesel: Re: ChipScope - impact on design or not?
            113928: 06/12/29: John Retta: Re: ChipScope - impact on design or not?
                113989: 07/01/02: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: ChipScope - impact on design or not?
            113939: 06/12/29: Nico Coesel: Re: ChipScope - impact on design or not?
        113922: 06/12/29: Symon: Re: ChipScope - impact on design or not?
            113940: 06/12/29: Symon: Re: ChipScope - impact on design or not?
    113937: 06/12/29: radarman: Re: ChipScope - impact on design or not?
    113942: 06/12/29: radarman: Re: ChipScope - impact on design or not?
    113943: 06/12/29: <zwsdotcom@gmail.com>: Re: ChipScope - impact on design or not?
113900: 06/12/28: vdauthor: Visual IP Designer
113901: 06/12/28: vdauthor: Visual IP Designer
113903: 06/12/28: sutejok: system ace - ERROR: IMPACT:477 - what is this?
    113904: 06/12/28: googlinggoogler@hotmail.com: Re: system ace - ERROR: IMPACT:477 - what is this?
113905: 06/12/28: <mankin18@gmail.com>: SPI slave problem
    113906: 06/12/28: Ben Jackson: Re: SPI slave problem
        113915: 06/12/29: Ben Twijnstra: Re: SPI slave problem
        113920: 06/12/29: Ralf Hildebrandt: Re: SPI slave problem
            113951: 06/12/30: Thomas Reinemann: Re: SPI slave problem
                113956: 06/12/30: KJ: Re: SPI slave problem
    113909: 06/12/28: <mankin18@gmail.com>: Re: SPI slave problem
    113916: 06/12/29: <mankin18@gmail.com>: Re: SPI slave problem
    113917: 06/12/29: <mankin18@gmail.com>: Re: SPI slave problem
    113935: 06/12/29: <langwadt@ieee.org>: Re: SPI slave problem
    113946: 06/12/29: tullio: Re: SPI slave problem
    113973: 06/12/31: tersono: Re: SPI slave problem
    114020: 07/01/02: <mankin18@gmail.com>: Re: SPI slave problem
    114025: 07/01/02: <mankin18@gmail.com>: Re: SPI slave problem
113910: 06/12/28: makhan: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 2
113919: 06/12/29: Pablo: SUNDANCE FPGA CONFIGURATION
    114101: 07/01/04: Martin Thompson: Re: SUNDANCE FPGA CONFIGURATION
        114133: 07/01/05: Martin Thompson: Re: SUNDANCE FPGA CONFIGURATION
    114128: 07/01/05: Pablo: Re: SUNDANCE FPGA CONFIGURATION
113950: 06/12/29: subint: Tools available to split the design into multiple FPGAs.
    113954: 06/12/30: Hans: Re: Tools available to split the design into multiple FPGAs.
    114068: 07/01/03: subint: Re: Tools available to split the design into multiple FPGAs.
113952: 06/12/29: Shenli: (Improve Verilog skill) Recommend CPU core with good document and coding?
    113955: 06/12/30: Jon Beniston: Re: (Improve Verilog skill) Recommend CPU core with good document and coding?
        113972: 06/12/31: joseph2k: Re: (Improve Verilog skill) Recommend CPU core with good document and coding?
    113960: 06/12/30: Shenli: Re: (Improve Verilog skill) Recommend CPU core with good document and coding?
113953: 06/12/30: Venu: ERROR:NgdBuild:604
    114035: 07/01/03: Guru: Re: ERROR:NgdBuild:604
    114107: 07/01/04: Venu: Re: ERROR:NgdBuild:604
    114129: 07/01/05: Guru: Re: ERROR:NgdBuild:604
113957: 06/12/30: ZHI: How to deal with the negative value
    113958: 06/12/30: ZHI: Re: How to deal with the negative value
    114122: 07/01/04: Tom J: Re: How to deal with the negative value
    114141: 07/01/05: Tom J: Re: How to deal with the negative value
113959: 06/12/30: Piotr Wyderski: Memory controller design
    113962: 06/12/31: Jerzy Gbur: Re: Memory controller design
        113963: 06/12/31: Piotr Wyderski: Re: Memory controller design
    113967: 06/12/31: KJ: Re: Memory controller design
        113970: 06/12/31: Piotr Wyderski: Re: Memory controller design
            114003: 07/01/02: KJ: Re: Memory controller design
        113971: 06/12/31: Nico Coesel: Re: Memory controller design
113961: 06/12/30: salu: hi......
    113964: 06/12/31: Austin: Re: hi......
113965: 06/12/31: <highZ>: xilinx xc9536?
    113974: 06/12/31: Ben Jackson: Re: xilinx xc9536?
    113976: 06/12/31: Peter Alfke: Re: xilinx xc9536?
        113979: 07/01/01: <highZ>: Re: xilinx xc9536?
            113983: 07/01/01: Austin: Re: xilinx xc9536?
                113984: 07/01/02: <highZ>: Re: xilinx xc9536?
                    113987: 07/01/02: Ben Jackson: Re: xilinx xc9536?
                    113999: 07/01/02: <smount>: Re: xilinx xc9536?
                        114006: 07/01/02: PeteS: Re: xilinx xc9536?
    113980: 07/01/01: Peter Alfke: Re: xilinx xc9536?
    113991: 07/01/02: PeteS: Re: xilinx xc9536?
    114022: 07/01/02: <Jim.Granville@gmail.com>: Re: xilinx xc9536?
    114023: 07/01/02: Peter Alfke: Re: xilinx xc9536?
113966: 06/12/31: idp2: Help with ISE (multi-source in unit error)
    113968: 06/12/31: mk: Re: Help with ISE (multi-source in unit error)
        113975: 06/12/31: Sean Durkin: Re: Help with ISE (multi-source in unit error)
            113977: 07/01/01: mk: Re: Help with ISE (multi-source in unit error)
    113969: 06/12/31: idp2: Re: Help with ISE (multi-source in unit error)
    114015: 07/01/02: idp2: Re: Help with ISE (multi-source in unit error)


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