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Hi, I did an objdump on my elf file and I got an text section of approx 4KB, vectors section approx 8KB and data section approx 16KB. I would like to know why the vectors and data sections are so much bigger and if there is a way to make them smaller. I noticed there is a huge MfDcrTable in the data section, I am using the xilinx interrupt drivers, but does this need to be that big? Regards, eArticle: 113601
Hi guys, I have to produce a PCB with a couple of FPGA on it and I was wondering if the solder mask right under the FPGA would prevent a good heat dissipation (provided that we will put the thermal paste underneath). Some of our designers suggested that the gain you have in heat dissipation you will loose it in short-circuit problems on the mounting, through the via underneath which are much more of a pain. Could you give me any suggestion? Thanks a lot Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 113602
Al wrote: > Hi guys, > I have to produce a PCB with a couple of FPGA on it and I was wondering > if the solder mask right under the FPGA would prevent a good heat > dissipation (provided that we will put the thermal paste underneath). > Some of our designers suggested that the gain you have in heat > dissipation you will loose it in short-circuit problems on the mounting, > through the via underneath which are much more of a pain. > Could you give me any suggestion? > > Thanks a lot > > Al > For BGA or TQFP ? I think CERN is working on big BGA ;-) Laurent www.amontec.comArticle: 113603
AMONTEC wrote: > Al wrote: > >> Hi guys, >> I have to produce a PCB with a couple of FPGA on it and I was >> wondering if the solder mask right under the FPGA would prevent a good >> heat dissipation (provided that we will put the thermal paste >> underneath). Some of our designers suggested that the gain you have in >> heat dissipation you will loose it in short-circuit problems on the >> mounting, through the via underneath which are much more of a pain. >> Could you give me any suggestion? >> >> Thanks a lot >> >> Al >> > > For BGA or TQFP ? > I think CERN is working on big BGA ;-) > Well, it's a Cern official experiment, but it's not going on any beams. It's for space application (AMS-02). Anyway I'm talking about PQFP 208 (Actel A54SX072A). Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 113604
"kyori" <ggkyori@gmail.com> writes: > Hi, > Hi, > I am going to start a project of onboard high-speed CMOS image > processing. > I am goint to perform certain *block matching algorithm* or *Fourier > Transform* between successive frames and the fps would be 1000 or > more.. > What size of frame? That's a lot of memory-bandwidth! > > The interface between the CMOS camera and the board is standord > CamLink. Do you mean Camera Link? There's VGA resolution cameras that'll do 1000fps that way. What's the end application? > I've learned that both DSP and FPGA based circuits can do certain > onboard image processing tasks, and I'd like to know whick is better? > DSP or FPGA? > It depends. Sorry! However, I think a single DSP is going to struggle to do a 2D FT of even a VGA image at 1000 fps. And once you go beyond a single DSP, my opinion is you might as well go to FPGA as you have a lot more flexibility in how you parallelise things then. > > I know some corporations use FPGA based boards as development boards > for their cameras. And my cooperators have some DSP development > experiences. So, the question arises, and I want your suggestions. I'd > like to know the advantages of each choise and maybe the direction of > onboard realtime high-speed image processing. > If you want to do *really* high speed processing, FPGAs are a sensible choice. Assuming your algorithms are a) parallelisable and b) actually compute limited, not memory latency or bandwidth limited. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 113605
Al wrote: > AMONTEC wrote: > >> Al wrote: >> >>> Hi guys, >>> I have to produce a PCB with a couple of FPGA on it and I was >>> wondering if the solder mask right under the FPGA would prevent a >>> good heat dissipation (provided that we will put the thermal paste >>> underneath). Some of our designers suggested that the gain you have >>> in heat dissipation you will loose it in short-circuit problems on >>> the mounting, through the via underneath which are much more of a pain. >>> Could you give me any suggestion? >>> >>> Thanks a lot >>> >>> Al >>> >> >> For BGA or TQFP ? >> I think CERN is working on big BGA ;-) >> > > Well, it's a Cern official experiment, but it's not going on any beams. > It's for space application (AMS-02). > Anyway I'm talking about PQFP 208 (Actel A54SX072A). > > Al > ...and TQFP 100 (Actel A54SX08A). Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 113606
"Brian Davis" <brimdavis@aol.com> wrote in message news:1166385670.603702.192040@73g2000cwn.googlegroups.com... > Austin wrote: >> >> The specification is min 3pF; max 10 pF for 3E. >> > Try looking at the IBIS files, which show a total max Cin > ( C_pkg plus C_comp ) of a mere 2.4 pF for a VQ100. > > Measured reflections off a fast LVDS driver in the lab > also agree with a Cin value in that range. > >> >> Which makes no distinction between input only pins, I/O pins, >>global clock input pins, left/right side clock pins, dual mode >>config pins, Vref pins, dedicated config pins, etc >> > > Brian > Hi Brian, Always good to read your posts, I hope all's well with you and yours. So, it was particularly interesting to read about your measurements on S3e. Also, Austin, your comments re. the pin capacitance is affected a lot by the presense of the high power drivers, gives me hope that the S3e 'dedicated inputs', i.e. input only, IOBs may have especially low Cpin. Brian, I don't suppose that was part of your measuring exercise when you looked at the LVDS? I looked at the IBIS files (ver2.1) and didn't find the input only pins. Thanks, Syms. Finally, it was interesting glancing through the IBIS files. For anyone who still believes the various myths surrounding bypass caps (see CAF passim), the lead inductance of the various packages makes enlightening reading. I guess the power leads have comparable inductance to the signal pin leads, so don't forget to include these data in your 'resonant bypass array' calculations! :-) Oh, and if anyone is planning on using a PQ208, make sure that any cost savings you make in assembly is spent on an SI simulator...Article: 113607
Al, You need to do the sums. Find out the:- thickness of the solder mask. the thermal conductivity of the solder mask. the power per unit area going through the solder mask. Are there any physicists where you work? They might be able to help with this calculation. :-) Let us know your answer. I reckon you'll find that the solder mask makes bugger all difference. I certainly wouldn't use a <1 thou thick sheet of solder mask to insulate my house. HTH, Syms. http://en.wikipedia.org/wiki/Thou_%28unit_of_length%29Article: 113608
Does anyone try to read values from sdram without the use of Microblaze?. It is simple to read/write values in ddr sdram with the use of pointer in MIcroblaze but how can you read values in vhdl code for displaying an image (store in sdram) with the use of a vga core.Article: 113609
Pablo schrieb: > Does anyone try to read values from sdram without the use of > Microblaze?. It is simple to read/write values in ddr sdram with the > use of pointer in MIcroblaze but how can you read values in vhdl code > for displaying an image (store in sdram) with the use of a vga core. connect VGA core to the OPB bus. done, works - simple :) AnttiArticle: 113610
Peter Alfke wrote: > Let's leave it at that. We won't agree, but then: we do not have to... To agree, there would need to be an argument to agree on in the first place. Since I was only proposing an alternative way of going about pointer data domain crossing, the only thing possibly worth arguing over is whether or not the approach is valid... and since I have used this approach in an ASIC project, I have reasonable proof that it is. Is it the best implementation? That answer is application-specific. > BTW, Google lists over 1000 patents on FIFOs. > A few of them are mine, but I could not believe the total number... The wheel has been patented a few times as well, there are way too many duplicate, obvious and useless patents out there, it makes finding truly relevant stuff an extremely tedious task. From what I have seen in FIFO patents, they suffer from the same redundancy and irrelevance as other patents: they reinvent multi-bits signal domain crossing, not FIFOs themselves. All claims beyond that are frivolous at best - once the cross-over is done, everything beyond that is easily 20+ years old common knowledge. I am very much surprised to see that some async FIFO patents are under 10 years old... the gray code and DP-SRAM or register file FIFO combo is much older than that AFAIK. > On Dec 17, 6:02 pm, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> > wrote: >> Yes, one can do "ptrA == ptrB" directly in gray... but if I want to do >> "ptrA - ptrB" to know how much headroom I have, it does not work quite >> as nicely, this does require G2B conversion. >> >> For a gray implementation, it is probably preferable to generate a >> straight gray counter and convert that to linear binary for local use to >> avoid combinational paths and routing between the counter's registers >> and the other domain's resync registers since it increases the risk >> transcoding glitches (path delays + non-existing phase relation + ...) >> getting through. With a binary counter, the gray conversion must be >> registered on the local clock before resyncing to the other clock. >> >> In any case, the most important point of any design always is: it has to >> work.Article: 113611
Symon wrote: > Finally, it was interesting glancing through the IBIS files. For anyone who > still believes the various myths surrounding bypass caps (see CAF passim), > the lead inductance of the various packages makes enlightening reading. I > guess the power leads have comparable inductance to the signal pin leads, so > don't forget to include these data in your 'resonant bypass array' > calculations! :-) Oh, and if anyone is planning on using a PQ208, make sure > that any cost savings you make in assembly is spent on an SI simulator... The capacitors manufacturers have impressive figures for the parasitic inductance improvement (i.e. reduction) you can get by moving to reverse geometry capacitors and to multi-pad interdigitated capacitors. The numbers seem to be approx 600pH for 0805, 300pH for 0508, 100pH for eight pad 0508. We use reverse geometry caps and we were thinking of trying the interdigitated parts. Does anyone have any warnings? And if I could go back to the ever-popular discussion of optimal board layout... Presumably the best strategy for for the power planes is to have one of them reachable via an in-pad microvia from the component layer. Should we also put voids in this power plane so that a second microvia can punch down to a second power plane? Or even interdigitate the power plane to get power and ground microvia-reachable from the component? TimArticle: 113612
Have you tried MIG? http://www.xilinx.com/products/design_resources/mem_corner/index.htm "Pablo " > Does anyone try to read values from sdram without the use of > Microblaze?. It is simple to read/write values in ddr sdram with the > use of pointer in MIcroblaze but how can you read values in vhdl code > for displaying an image (store in sdram) with the use of a vga core.Article: 113613
Hi there,
I apologize for the unspecific subject, but for me it is like that.
I am working on an FPGA project which consists of a CPU (8bit), a
UART, a sensor keypad controller, LCD module controller, and SPI
flash controller. Since all these modules need a clock to run, but
with different clock speeds I decided to do a dedicated "clock
generator" module which divides the various frequencies from the
master clock. The "unpredictable behaviour" manifests itself most
prominently in this clock generator module; although I assume that
there might be other effects as well. The sequence is this:
- I edit a VHDL source file (currently I am working on the keypad
controller module)
- I compile the project
- I load the bitstream into the FPGA
- the CPU would not run, or maybe the LCD, or maybe the SPI or the UART
The point I quite do not understand is that the area I made the last
changes definitely does have nothing to do with the affected design
area (e.g. keypad - LCD). (ha, I am sounding like a SW developer...)
Anyway, to give a bit more information here is like I implemented the
clock dividers:
****************************** code ******************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clock_generator is
port (
rst : in std_logic;
clk_in : in std_logic; -- input clock (25MHz)
sel : in std_logic;
nWR : in std_logic;
ddrive : in std_logic;
d_in : in std_logic_vector (7 downto 0);
d_out : out std_logic_vector (7 downto 0);
cpu_clk : out std_logic; -- CPU clock (3Hz .. 12.5MHz)
uart_clk : out std_logic; -- UART clock (115.2kHz:38400b/sec)
lcd_clk : out std_logic; -- LCD controller clock (1MHz)
key_clk : out std_logic; -- keypad controller clock (333kHz)
spi_clk : out std_logic -- SPI controller clock (6.25MHz)
);
end clock_generator;
architecture divider of clock_generator is
constant SYS_FREQ : integer := 25000000; -- 25MHz
constant UART_FREQ : integer := 115200; -- 3*38.4kHz
constant LCD_FREQ : integer := 1000000; -- 1MHz
constant KEY_FREQ : integer := 333333; -- 333kHz
constant SPI_FREQ : integer := 6250000; -- 6.25MHz
signal uart_cnt : integer;
signal lcd_cnt : integer;
signal key_cnt : integer;
signal spi_cnt : integer;
signal cpu_cnt, cpu_end : std_logic_vector (23 downto 0);
signal cpu_div : std_logic_vector (7 downto 0);
signal wr_cpu_div : std_logic;
begin
-- write the clock divider
wr_cpu_div <= not nWR and sel;
cpu_div_latch : process (rst, wr_cpu_div)
begin
if rst = '1' then
cpu_div <= x"01";
elsif falling_edge (wr_cpu_div) then
if d_in = x"00" then
cpu_div <= x"01";
else
cpu_div <= d_in;
end if;
end if;
end process;
-- read the clock divider
d_out(0) <= sel and not ddrive and cpu_div(0);
d_out(1) <= sel and not ddrive and cpu_div(1);
d_out(2) <= sel and not ddrive and cpu_div(2);
d_out(3) <= sel and not ddrive and cpu_div(3);
d_out(4) <= sel and not ddrive and cpu_div(4);
d_out(5) <= sel and not ddrive and cpu_div(5);
d_out(6) <= sel and not ddrive and cpu_div(6);
d_out(7) <= sel and not ddrive and cpu_div(7);
-- the counter
cpu_divider : process (rst, clk_in)
variable segment : std_logic_vector (15 downto 0);
begin
if rst = '1' then
cpu_cnt <= x"000000";
cpu_clk <= '0';
elsif rising_edge (clk_in) then
if unsigned(cpu_cnt) < unsigned('0' & cpu_end(23 downto 1)) then
cpu_clk <= '0';
else
cpu_clk <= '1';
end if;
if unsigned(cpu_cnt) >= unsigned(cpu_end) then
cpu_clk <= '0';
cpu_cnt <= x"000001";
else
cpu_cnt <= cpu_cnt + 1;
end if;
end if;
case cpu_div (7 downto 4) is
when x"0" => -- 0000 0000 0000 0000 000x xxx0
segment := x"0000";
cpu_end <= "000" & segment & cpu_div(3 downto 0) & '0';
when x"1" => -- 0000 0000 0000 0000 001x xxx0
segment := x"0001";
cpu_end <= "000" & segment & cpu_div(3 downto 0) & '0';
when x"2" => -- 0000 0000 0000 0000 010x xxx0
segment := x"0002";
cpu_end <= "000" & segment & cpu_div(3 downto 0) & '0';
when x"3" => -- 0000 0000 0000 0000 100x xxx0
segment := x"0004";
cpu_end <= "000" & segment & cpu_div(3 downto 0) & '0';
when x"4" => -- 0000 0000 0000 0010 000x xxx0
segment := x"0008";
cpu_end <= "00" & segment & '0' & cpu_div(3 downto 0) & '0';
when x"5" => -- 0000 0000 0000 0100 00xx xx00
segment := x"0010";
cpu_end <= "00" & segment & cpu_div(3 downto 0) & "00";
when x"6" => -- 0000 0000 0001 0000 00xx xx00
segment := x"0020";
cpu_end <= '0' & segment & '0' & cpu_div(3 downto 0) & "00";
when x"7" => -- 0000 0000 0010 0000 00xx xx00
segment := x"0040";
cpu_end <= '0' & segment & '0' & cpu_div(3 downto 0) & "00";
when x"8" => -- 0000 0000 0100 0000 0xxx x000
segment := x"0080";
cpu_end <= '0' & segment & cpu_div(3 downto 0) & "000";
when x"9" => -- 0000 0001 0000 0000 0xxx x000
segment := x"0100";
cpu_end <= segment & '0' & cpu_div(3 downto 0) & "000";
when x"A" => -- 0000 0010 0000 0000 0xxx x000
segment := x"0200";
cpu_end <= segment & '0' & cpu_div(3 downto 0) & "000";
when x"B" => -- 0000 0100 0000 0000 xxxx 0000
segment := x"0400";
cpu_end <= segment & cpu_div(3 downto 0) & "0000";
when x"C" => -- 0001 0000 0000 0000 xxxx 0000
segment := x"0800";
cpu_end <= segment(14 downto 0) & '0' & cpu_div(3 downto 0) &
"0000";
when x"D" => -- 0010 0000 0000 0000 xxxx 0000
segment := x"1000";
cpu_end <= segment(14 downto 0) & '0' & cpu_div(3 downto 0) &
"0000";
when x"E" => -- 0100 0000 0000 000x xxx0 0000
segment := x"2000";
cpu_end <= segment(14 downto 0) & cpu_div(3 downto 0) & "00000";
when x"F" => -- 1000 0000 0000 000x xxx0 0000
segment := x"4000";
cpu_end <= segment(14 downto 0) & cpu_div(3 downto 0) & "00000";
when others => null;
end case;
end process;
uart_divider : process (rst, clk_in)
begin
if rst = '1' then
uart_cnt <= 0;
uart_clk <= '0';
elsif rising_edge (clk_in) then
uart_cnt <= uart_cnt + 1;
if uart_cnt >= ((SYS_FREQ/2) / UART_FREQ) then
uart_clk <= '0';
else
uart_clk <= '1';
end if;
if uart_cnt >= ((SYS_FREQ / UART_FREQ) - 1) then
uart_cnt <= 0;
end if;
end if;
end process;
lcd_divider : process (rst, clk_in)
begin
if rst = '1' then
lcd_cnt <= 0;
lcd_clk <= '0';
elsif rising_edge (clk_in) then
if lcd_cnt >= ((SYS_FREQ/2) / LCD_FREQ) then
lcd_clk <= '0';
else
lcd_clk <= '1';
end if;
if lcd_cnt >= ((SYS_FREQ / LCD_FREQ) - 1) then
lcd_cnt <= 0;
else
lcd_cnt <= lcd_cnt + 1;
end if;
end if;
end process;
key_divider : process (rst, clk_in)
begin
if rst = '1' then
key_cnt <= 0;
key_clk <= '0';
elsif rising_edge (clk_in) then
if key_cnt >= ((SYS_FREQ/2) / KEY_FREQ) then
key_clk <= '0';
else
key_clk <= '1';
end if;
if key_cnt >= ((SYS_FREQ / KEY_FREQ) - 1) then
key_cnt <= 0;
else
key_cnt <= key_cnt + 1;
end if;
end if;
end process;
spi_divider : process (rst, clk_in)
begin
if rst = '1' then
spi_cnt <= 0;
spi_clk <= '0';
elsif rising_edge (clk_in) then
if spi_cnt >= ((SYS_FREQ/2) / SPI_FREQ) then
spi_clk <= '0';
else
spi_clk <= '1';
end if;
if spi_cnt >= ((SYS_FREQ / SPI_FREQ) - 1) then
spi_cnt <= 0;
else
spi_cnt <= spi_cnt + 1;
end if;
end if;
end process;
end divider;
*************************** end of code **************************
The CPU clock divider is under software control - it allows for really
slow speeds (downto 3Hz).
I already tried slightly different divider desgins but that did not
change the behaviour.
Everytime I encounter a "mysterious" disfunction anywhere in the system
I tweak the individual frequencies a little - and voila: it works again.
I am using a Lattice ECP33 chip on a Gleichmann HPEmini development
board, ispLEVER version 6.0.01.46.29.06SP2006.01 (Windows), using the
Precision VHDL compiler.
As I said this is my first FPGA project, so I am really unsure about
setting timing constraints, routing constraints, etc.
Basically I set the parameters to an easy-for-the-compiler/fitter-
setting, since one run takes about 10 min on my machine.
The FPGA runs off a 25MHz crystal oscillator; my CPU is running at
12.5MHz at most.
I have been designing programmable logic for many years now, using
MAX7000 with AHDL and GALs with ABEL.
Additionally I am new to VHDL; I am learning with this project. I am
absolutely willing to improve my coding style and design process.
Any help or hint for reading about partitioning, etc. is highly
appreciated!
Thanks a lot! Also thanks to this list, from where I already got
valuable information several times.
Johannes
Article: 113614Just right click your software project in EDK and select "generate linker script". Then you can edit it for whatever sizes you like. -clark <eascheiber@yahoo.com> wrote in message news:1166426134.344362.80000@16g2000cwy.googlegroups.com... > Hi, > > I did an objdump on my elf file and I got an text section of approx > 4KB, > vectors section approx 8KB and data section approx 16KB. > > I would like to know why the vectors and data sections are so much > bigger > and if there is a way to make them smaller. > > I noticed there is a huge MfDcrTable in the data section, I am using > the > xilinx interrupt drivers, but does this need to be that big? > > Regards, > e >Article: 113615
Johannes Hausensteiner wrote: > Hi there, > > I apologize for the unspecific subject, but for me it is like that. > > I am working on an FPGA project which consists of a CPU (8bit), a > UART, a sensor keypad controller, LCD module controller, and SPI > flash controller. Since all these modules need a clock to run, but > with different clock speeds I decided to do a dedicated "clock > generator" module which divides the various frequencies from the > master clock. The "unpredictable behaviour" manifests itself most > prominently in this clock generator module; although I assume that > there might be other effects as well. The sequence is this: > - I edit a VHDL source file (currently I am working on the keypad > controller module) > - I compile the project > - I load the bitstream into the FPGA > - the CPU would not run, or maybe the LCD, or maybe the SPI or the UART > > The point I quite do not understand is that the area I made the last > changes definitely does have nothing to do with the affected design > area (e.g. keypad - LCD). (ha, I am sounding like a SW developer...) > Anyway, to give a bit more information here is like I implemented the > clock dividers: > [snip] > > The CPU clock divider is under software control - it allows for really > slow speeds (downto 3Hz). > I already tried slightly different divider desgins but that did not > change the behaviour. > Everytime I encounter a "mysterious" disfunction anywhere in the system > I tweak the individual frequencies a little - and voila: it works again. > > I am using a Lattice ECP33 chip on a Gleichmann HPEmini development > board, ispLEVER version 6.0.01.46.29.06SP2006.01 (Windows), using the > Precision VHDL compiler. > > As I said this is my first FPGA project, so I am really unsure about > setting timing constraints, routing constraints, etc. > Basically I set the parameters to an easy-for-the-compiler/fitter- > setting, since one run takes about 10 min on my machine. > The FPGA runs off a 25MHz crystal oscillator; my CPU is running at > 12.5MHz at most. > I have been designing programmable logic for many years now, using > MAX7000 with AHDL and GALs with ABEL. > Additionally I am new to VHDL; I am learning with this project. I am > absolutely willing to improve my coding style and design process. > > Any help or hint for reading about partitioning, etc. is highly > appreciated! > > Thanks a lot! Also thanks to this list, from where I already got > valuable information several times. > > Johannes The best advice you'll probably get here is to clock everything with your 25 MHz oscillator and use clock enables to slow down the various modules. This will avoid problems with clock domain crossings and simplify the clock distribution. If you're comfortable with the clock crossing issues, and you still want to run with multiple clocks, make sure your implemetation is using the global clock routing resources (use the design planner to force use of primary clock distribution for as many clocks as this supports, usually 4). Also realize that although the clocks are generated from the same input clock, the delay from the 25 MHz rising edge to the generated clock rising edge may have significant differences from clock to clock, especially due to routing delays. So you'll need to treat clocks as asynchronous unless you make sure your various counters don't create more than one output clock rising edge on the same rising edge of 25 MHz. Finally realize that the timing from clock to clock will not be computed by the TRACE program unless you specify cross-clock analysis. It's unlikely that you will have setup violations at 25 MHz, but unless you deal with clock to clock skew issues you can easily end up with hold violations. HTH, GaborArticle: 113616
Greetings to all !
I started programming with VHDL two months ago. Now I want to implement
a project on a Spartan 3 (XC3S50 VQ100). The software I=B4m using is the
ISE Webpack 8.2.03i (Application Version: I.34).
This project is later supposed to be a bit error testing instance in
combination with an Microcontroller that is used to read out an compare
the sended and received data from the block RAMs of the Spartan 3.
I tested the components I used as standalone-designs and they all seem
to function but when I try to make one pice of all designs the FPGA
doesn=B4t show any expected behaviour at all-even some simple LED I
integrated in the design to indicate if the clock is active don't start
flashing.
Although i know it's probably not the smartest way to ask for help but
as I need this project to function for my thesis i have no other ideas
than posting the whole code - any words are very appreciated (the
comments are in german and not so important)!!!
p=2Es.: It would also help if someone would just copy and paste this code
into a new projektfile to find out if it=B4s running(simplest
indication: the State LED_Z0 should be on and the LED_Z1 should be
flashing) on his hardware.
#UCF - File :
***************************************************************************=
*************************
NET "CLK_IN" LOC =3D "P36" | IOSTANDARD =3D LVTTL ; #Takt vom
Meltemi-Board (66 MHz)
NET "CLK_fromMC" LOC =3D "P39" | IOSTANDARD =3D LVTTL ;#Takt com MC
NET "DATA_toMC<0>" LOC =3D "P30" | IOSTANDARD =3D LVTTL
;#Datenleitungen
NET "DATA_toMC<1>" LOC =3D "P32" | IOSTANDARD =3D LVTTL ;
NET "DATA_toMC<2>" LOC =3D "P34" | IOSTANDARD =3D LVTTL ;
NET "DATA_toMC<3>" LOC =3D "P35" | IOSTANDARD =3D LVTTL ;
NET "MC_READY" LOC =3D "P43" | IOSTANDARD =3D LVTTL ;#MC ist fertig mit
Auslesen
NET "MC_READ" LOC =3D "P44" | IOSTANDARD =3D LVTTL ;#MC soll mit Auslesen
beginnen
NET "INDICATION_MUXtoMC<1>" LOC =3D "P47" | IOSTANDARD =3D LVTTL ;
NET "INDICATION_MUXtoMC<0>" LOC =3D "P59" | IOSTANDARD =3D LVTTL ;
NET "LED_Z0" LOC =3D "P72" | IOSTANDARD =3D LVTTL ;
NET "LED_Z1" LOC =3D "P50" | IOSTANDARD =3D LVTTL ;
NET "LED_Z2" LOC =3D "P55" | IOSTANDARD =3D LVTTL ;
###############LVDS-Kan=E4le###############################
NET "LVDS_Nr" LOC =3D "P88" | IOSTANDARD =3D LVDSEXT_25 ;#r: receive
NET "LVDS_Ns" LOC =3D "P90" | IOSTANDARD =3D LVDSEXT_25 ;#s: send
NET "LVDS_Pr" LOC =3D "P87" | IOSTANDARD =3D LVDSEXT_25 ;
NET "LVDS_Ps" LOC =3D "P89" | IOSTANDARD =3D LVDSEXT_25 ;
################TASTER####################################
NET "BUTTON" LOC =3D "P21" | IOSTANDARD =3D LVTTL ;#USERSTART
--Topmodule -File:
***************************************************************************=
*******************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity TOPMODULE is
generic(
WAIT_WIDTH_USERSTART : positive :=3D 28;
WAIT_WIDTH_MC_READY : positive :=3D 10;
CNT_WIDTH : positive :=3D 25
);
Port ( CLK_IN : in STD_LOGIC;
MC_READY : in STD_LOGIC;
BUTTON : in std_logic;
LVDS_Pr : in STD_LOGIC; --receive
LVDS_Nr : in STD_LOGIC;
LVDS_Ps : out STD_LOGIC;--send
LVDS_Ns : out STD_LOGIC;
LED_Z0 : out STD_LOGIC;
LED_Z1 : out STD_LOGIC;
LED_Z2 : out STD_LOGIC;
DATA_toMC : out STD_LOGIC_VECTOR (3 downto 0);
MC_READ : out STD_LOGIC;
CLK_fromMC : in std_logic;
INDICATION_MUXtoMC : out std_logic_vector(1 downto 0)
);
end TOPMODULE;
architecture Behavioral of TOPMODULE is
component STATE_MACHINE
port(CLKX1 : in std_logic;
USER_START : in std_logic;
ADDRESS_CONTROL_FINISH : in std_logic;
MC_READY : in std_logic;
BRAM1_EN_toMUX : out std_logic; --Ausgangssignale zu BRAM1
BRAM1_EN_SEND : out std_logic;
BRAM1_RESET_toMUX : out std_logic;
BRAM1_RESET_SEND : out std_logic;
BRAM2_EN_RECEIVE : out std_logic; --Ausgangssignale zu BRAM2
BRAM2_EN_toMUX : out std_logic;
BRAM2_RESET_toMUX : out std_logic;
BRAM2_WRITE_EN : out std_logic;
MUX_RESET : out std_logic;
DES_EN : out std_logic;
SER_NEN : out std_logic;
SER_RESET : out std_logic;
ADDR_CONTROL_RESET_NEN : out
std_logic;--ADDRESS_CONTROL_RESET_(and)NotENable
MC_READ : out std_logic;
LED_Z0 : out std_logic; --die LEDs signalisieren den aktuellen
Zustand
LED_Z2 : out std_logic--;
);
end component;
component ADDRESS_CONTROL
generic(
ADDRESS_WIDTH : positive :=3D 10
);
Port ( CLKX1 : in std_logic;
RESET_NEN : in STD_LOGIC;
ADDR_BRAM1 : out STD_LOGIC_VECTOR (9 downto 0);
ADDR_BRAM2 : out STD_LOGIC_VECTOR (9 downto 0);
FINISH : out std_logic
);
end component;
component SER16to1
Port ( CLKX8 : in std_logic; --8facher Takt (bezogen auf den Takt des
16 Bit breiten Datenbus)
CLKX8_180 : in std_logic; --8facher Takt invertiert
RESET : in std_logic; --Reseteingang
NotENABLE : in std_logic;
DATA_PARALLEL : in std_logic_vector(15 downto 0);
ODATA_LVDSP : out std_logic;
ODATA_LVDSN : out std_logic);
end component;
component DES1to16
Port ( ENABLE : in std_logic; --mit DCM_LOCKED verbinden
IDATA_LVDSP : in std_logic;
IDATA_LVDSN : in std_logic;
CLKX8 : in STD_LOGIC;
CLKX8_180 : in STD_LOGIC;
CLKX1 : in STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component MUX
generic(
DATA_WIDTH: positive :=3D 4;--Breite des Datenbusses
ADRESS_WIDTH_toMC: positive :=3D 12;
CONTROL_WIDTH: positive :=3D 2--Anzahl der Steuerleitungen
);
Port ( DATA1 : in STD_LOGIC_VECTOR (3 downto 0);--Daten von BRAM1
DATA2 : in STD_LOGIC_VECTOR (3 downto 0);--Daten von BRAM2
DATA_OUT : out STD_LOGIC_VECTOR (3 downto 0);--Datenbus zum
Mikrocontroller
ADRESS1 : out std_logic_vector(11 downto 0);--Adressbusse zu den
BRAMs
ADRESS2 : out std_logic_vector(11 downto 0);
RESET : in std_logic;--asynchrones Resetsignal von der
State-Machine
INDICATION : out STD_LOGIC_VECTOR(1 downto 0);--Kontrollbus
zum Mikrocontroller
CLK_extMC : in STD_LOGIC;--Auslesetakt f=FCr die BRAMs (vom
Mikrocontroller generiert)
CLK_fromMC :out STD_LOGIC
);
end component;
component BRAM_SEND
port(
DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
Data Output
DATA_toSER : out std_logic_vector(15 downto 0); -- Port B
16-bit Data Output
ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
Address Input
ADDRESS_SEND: in std_logic_vector(9 downto 0); -- Port B 10-bit
Address Input
CLK_MUX : in std_logic; -- Port A Clock
CLKX1 : in std_logic; -- Port B Clock
EN_toMUX : in std_logic; -- Port A RAM Enable Input
EN_SEND : in std_logic; -- PortB RAM Enable Input
RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
Input
RESET_SEND : in std_logic -- Port B Synchronous Set/Reset Input
);
end component;
component BRAM_RECEIVE
port(
DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
Data Output
DATA_fromDES : in std_logic_vector(15 downto 0); -- Port B
16-bit Data Intput
ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
Address Input
ADDRESS_RECEIVE: in std_logic_vector(9 downto 0); -- Port B
10-bit Address Input
CLK_MUX : in std_logic; -- Port A Clock
CLKX1_PS : in std_logic; -- Port B Clock (PS: phase-shifted)
Verz=F6gerung des DUTs
EN_toMUX : in std_logic; -- Port A RAM Enable Input
EN_RECEIVE : in std_logic; -- PortB RAM Enable Input
RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
Input
WRITE_ENABLE : in std_logic
);
end component;
component GENERATE_CLOCK
Port ( CLKIN_IN : in std_logic; --Oszillator mit 66 MHz
(meltemi: P36)
CLKDV_OUT : out std_logic; --33 Mhz Takt
CLKFX_OUT : out std_logic; --264 MHz Takt
CLKFX180_OUT : out std_logic
);
end component;
signal CLKX1, CLKX8, CLKX8_180 : std_logic;
signal ADDRESS_CONTROL_FINISH, BRAM1_EN_SEND, BRAM1_RESET_toMUX,
BRAM1_RESET_SEND : std_logic;
signal BRAM2_EN_RECEIVE, BRAM2_RESET_toMUX, BRAM2_WRITE_EN, MUX_RESET :
std_logic;
signal DES_EN, SER_NEN, SER_RESET, ADDR_CONTROL_RESET_NEN : std_logic;
signal ADDR_BRAM1, ADDR_BRAM2 : std_logic_vector(9 downto 0);
signal DATA_toSER16to1, DATA_fromDES1to16 : std_logic_vector(15 downto
0);
signal DATA_toMUX_BRAM_S, DATA_toMUX_BRAM_R : std_logic_vector(3 downto
0);
signal ADDRESS_BRAM_SEND, ADDRESS_BRAM_RECEIVE : std_logic_vector(11
downto 0);
signal BRAM1_EN_toMUX, BRAM2_EN_toMUX : std_logic;
signal USERSTART : std_logic :=3D '0';
signal CLK_fromMC_buffered : STD_LOGIC;
--Taster :
--Tatser1 :
signal SHIFT_PB1 : STD_LOGIC_VECTOR (3 downto 0) :=3D "0000";
signal BUTTON_DEBOUNCED1 : std_logic :=3D '0';
signal LEVEL1 : std_logic :=3D '0';
--CLK-Indication :
signal CNT : std_logic_vector(CNT_WIDTH-1 downto 0) :=3D (others =3D> '0');
constant MAX_CNT : std_logic_vector(CNT_WIDTH-1 downto 0) :=3D (others =3D>
'1');
signal LEVEL : std_logic :=3D '0';
begin
inst_GC : GENERATE_CLOCK
port map(
CLKIN_IN =3D> CLK_IN, --externer Takt
CLKDV_OUT =3D> CLKX1, --33 Mhz Takt
CLKFX_OUT =3D> CLKX8, --264 MHz Takt
CLKFX180_OUT =3D> CLKX8_180--CLKX8 um 180=B0 phasenverschoben
);
inst_SM : STATE_MACHINE
port map(
CLKX1 =3D> CLKX1,
USER_START =3D> USERSTART,
ADDRESS_CONTROL_FINISH =3D> ADDRESS_CONTROL_FINISH,
MC_READY =3D> MC_READY,--MC herausgenommen
BRAM1_EN_toMUX =3D> BRAM1_EN_toMUX, --Ausgangssignale zu BRAM1
BRAM1_EN_SEND =3D> BRAM1_EN_SEND,
BRAM1_RESET_toMUX =3D> BRAM1_RESET_toMUX,
BRAM1_RESET_SEND =3D> BRAM1_RESET_SEND,
BRAM2_EN_RECEIVE =3D> BRAM2_EN_RECEIVE, --Ausgangssignale zu BRAM2
BRAM2_EN_toMUX =3D> BRAM2_EN_toMUX,
BRAM2_RESET_toMUX =3D> BRAM2_RESET_toMUX,
BRAM2_WRITE_EN =3D> BRAM2_WRITE_EN,
MUX_RESET =3D> MUX_RESET,
DES_EN =3D> DES_EN,
SER_NEN =3D> SER_NEN,
SER_RESET =3D> SER_RESET,
ADDR_CONTROL_RESET_NEN =3D>
ADDR_CONTROL_RESET_NEN,--ADDRESS_CONTROL_RESET_(and)NotENable
MC_READ =3D> MC_READ,
LED_Z0 =3D> LED_Z0, --die LEDs signalisieren den aktuellen Zustand
LED_Z2 =3D> LED_Z2
);
inst_AC : ADDRESS_CONTROL
port map(
CLKX1 =3D> CLKX1,
RESET_NEN =3D> ADDR_CONTROL_RESET_NEN,
ADDR_BRAM1 =3D> ADDR_BRAM1, --BRAM_SEND
ADDR_BRAM2 =3D> ADDR_BRAM2, --BRAM_RECEIVE
FINISH =3D> ADDRESS_CONTROL_FINISH
);
inst_SER : SER16to1
port map(
CLKX8 =3D> CLKX8, --8facher Takt (bezogen auf den Takt des 16 Bit
breiten Datenbus)
CLKX8_180 =3D> CLKX8_180, --8facher Takt invertiert
RESET =3D> SER_RESET, --Reseteingang
NotENABLE =3D> SER_NEN,
DATA_PARALLEL =3D> DATA_toSER16to1,
ODATA_LVDSP =3D> LVDS_Ps,
ODATA_LVDSN =3D> LVDS_Ns
);
inst_DES : DES1to16
port map(
ENABLE =3D> DES_EN, --mit DCM_LOCKED verbinden
IDATA_LVDSP =3D> LVDS_Pr,
IDATA_LVDSN =3D> LVDS_Nr,
CLKX8 =3D> CLKX8,
CLKX8_180 =3D> CLKX8_180,
CLKX1 =3D> CLKX1,
DATA_OUT =3D> DATA_fromDES1to16
);
inst_MUX : MUX
port map(
DATA1 =3D> DATA_toMUX_BRAM_S,--Daten von BRAM1
DATA2 =3D> DATA_toMUX_BRAM_R,--Daten von BRAM2
DATA_OUT =3D> DATA_toMC,--Datenbus zum Mikrocontroller
ADRESS1 =3D> ADDRESS_BRAM_SEND,--Adressbusse zu den BRAMs
ADRESS2 =3D> ADDRESS_BRAM_RECEIVE,
RESET =3D> MUX_RESET,--asynchrones Resetsignal von der State-Machine
INDICATION =3D> INDICATION_MUXtoMC,--Kontrollbus zum
Mikrocontroller
CLK_extMC =3D> CLK_fromMC--Auslesetakt f=FCr die BRAMs (vom
Mikrocontroller generiert)
);
inst_BRAM_S : BRAM_SEND --BRAM1
port map(
DATA_toMUX =3D> DATA_toMUX_BRAM_S, -- Port A 4-bit Data Output
DATA_toSER =3D> DATA_toSER16to1, -- Port B 16-bit Data Output
ADDRESS_MUX =3D> ADDRESS_BRAM_SEND, -- Port A 12-bit Address Input
ADDRESS_SEND =3D> ADDR_BRAM1, -- Port B 10-bit Address Input
CLK_MUX =3D> CLK_fromMC_buffered, -- Port A Clock
CLKX1 =3D> CLKX1, -- Port B Clock
EN_toMUX =3D> BRAM1_EN_toMUX, -- Port A RAM Enable Input
EN_SEND =3D> BRAM1_EN_SEND, -- PortB RAM Enable Input
RESET_toMUX =3D> BRAM1_RESET_toMUX, -- Port A Synchronous
Set/Reset Input
RESET_SEND =3D> BRAM1_RESET_SEND -- Port B Synchronous Set/Reset
Input
);
inst_BRAM_R : BRAM_RECEIVE
port map(
DATA_toMUX =3D> DATA_toMUX_BRAM_R, -- Port A 4-bit Data Output
DATA_fromDES =3D> DATA_fromDES1to16, -- Port B 16-bit Data
Intput
ADDRESS_MUX =3D> ADDRESS_BRAM_RECEIVE, -- Port A 12-bit Address
Input
ADDRESS_RECEIVE =3D> ADDR_BRAM2, -- Port B 10-bit Address Input
CLK_MUX =3D> CLK_fromMC_buffered, -- Port A Clock
CLKX1_PS =3D> CLKX1, -- Port B Clock (PS: phase-shifted)
Verz=F6gerung des DUTs
EN_toMUX =3D> BRAM2_EN_toMUX, -- Port A RAM Enable Input
EN_RECEIVE =3D> BRAM2_EN_RECEIVE, -- PortB RAM Enable Input
RESET_toMUX =3D> BRAM2_RESET_toMUX, -- Port A Synchronous
Set/Reset Input
WRITE_ENABLE =3D> BRAM2_WRITE_EN
);
--CLK-Indication :
CLK_indication: process(CLKX1)
begin
if (CLKX1'event and CLKX1 =3D '1') then
if CNT =3D MAX_CNT then
LEVEL <=3D not LEVEL;
CNT <=3D (others =3D> '0');
else
CNT <=3D CNT +1;
end if;
end if;
end process;
LED_Z1 <=3D LEVEL;
--LED_Z1 <=3D '1';
----Taster1 :
DEBOUNCE1: process(CLKX1)
begin
if (CLKX1'event and CLKX1 =3D '1') then
-- Use a shIFt register to filter switch contact bounce
SHIFT_PB1(2 downto 0) <=3D SHIFT_PB1(3 downto 1);
SHIFT_PB1(3) <=3D BUTTON;
if SHIFT_PB1(3 downto 0) =3D "0000" then
BUTTON_DEBOUNCED1 <=3D '0';
else
BUTTON_DEBOUNCED1 <=3D '1';
end if;
end if;
end process;
SWITCH1: process(BUTTON_DEBOUNCED1)
begin
if (BUTTON_DEBOUNCED1'event and BUTTON_DEBOUNCED1 =3D '1') then
LEVEL1 <=3D not LEVEL1;
end if;
end process;
USERSTART <=3D LEVEL1;
end Behavioral;
--GENERATE_CLOCK-FILE :
***************************************************************************=
******
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
--konfiguriert f=FCr einen Eingangstakt der Frequenz 66 MHz
entity GENERATE_CLOCK is
port ( CLKIN_IN : in std_logic; --Oszillator mit 66 MHz
(meltemi: P36)
CLKDV_OUT : out std_logic; --33 Mhz Takt
CLKFX_OUT : out std_logic; --264 MHz Takt
CLKFX180_OUT : out std_logic
);-- =3D '1' -> DCM eingeschwungen
end GENERATE_CLOCK;
architecture BEHAVIORAL of GENERATE_CLOCK is
component BUFG
port ( I : in std_logic;
O : out std_logic);
end component;
component IBUFG
port ( I : in std_logic;
O : out std_logic);
end component;
-- Period Jitter (unit interval) for block DCM_INST =3D 0.17 UI
-- Period Jitter (Peak-to-Peak) for block DCM_INST =3D 0.63 ns
component DCM
generic( CLK_FEEDBACK : string :=3D "1X";
CLKDV_DIVIDE : real :=3D 2.0;
CLKFX_DIVIDE : integer :=3D 1;
CLKFX_MULTIPLY : integer :=3D 4; ---sonst 4 !!!
CLKIN_DIVIDE_BY_2 : boolean :=3D FALSE;
CLKIN_PERIOD : real :=3D 10.0;
CLKOUT_PHASE_SHIFT : string :=3D "NONE";
DESKEW_ADJUST : string :=3D "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string :=3D "LOW";
DLL_FREQUENCY_MODE : string :=3D "LOW";
DUTY_CYCLE_CORRECTION : boolean :=3D TRUE;
FACTORY_JF : bit_vector :=3D x"8080";
PHASE_SHIFT : integer :=3D 0;
STARTUP_WAIT : boolean :=3D FALSE;
DSS_MODE : string :=3D "NONE");
port ( CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
DSSEN : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
STATUS : out std_logic_vector (7 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic);
end component;
signal CLKDV_BUF : std_logic;
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKFX180_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND1 : std_logic;
begin
GND1 <=3D '0';
CLKDV_BUFG_INST : BUFG
port map (I=3D>CLKDV_BUF,
O=3D>CLKDV_OUT);
CLKFX_BUFG_INST : BUFG
port map (I=3D>CLKFX_BUF,
O=3D>CLKFX_OUT);
CLKFX180_BUFG_INST : BUFG
port map (I=3D>CLKFX180_BUF,
O=3D>CLKFX180_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=3D>CLKIN_IN,
O=3D>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=3D>CLK0_BUF,
O=3D>CLKFB_IN);
DCM_INST : DCM
generic map( CLK_FEEDBACK =3D> "1X",
CLKDV_DIVIDE =3D> 2.0,
CLKFX_DIVIDE =3D> 1,
CLKFX_MULTIPLY =3D> 4,
CLKIN_DIVIDE_BY_2 =3D> FALSE,
CLKIN_PERIOD =3D> 15.1515,
CLKOUT_PHASE_SHIFT =3D> "NONE",
DESKEW_ADJUST =3D> "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE =3D> "HIGH",
DLL_FREQUENCY_MODE =3D> "LOW",
DUTY_CYCLE_CORRECTION =3D> TRUE,
FACTORY_JF =3D> x"8080",
PHASE_SHIFT =3D> 0,
STARTUP_WAIT =3D> TRUE)
port map (CLKFB=3D>CLKFB_IN,
CLKIN=3D>CLKIN_IBUFG,
DSSEN=3D>GND1,
PSCLK=3D>GND1,
PSEN=3D>GND1,
PSINCDEC=3D>GND1,
RST=3D>'0',
CLKDV=3D>CLKDV_BUF,
CLKFX=3D>CLKFX_BUF,
CLKFX180=3D>CLKFX180_BUF,
CLK0=3D>CLK0_BUF,
CLK2X=3D>open,
CLK2X180=3D>open,
CLK90=3D>open,
CLK180=3D>open,
CLK270=3D>open,
LOCKED=3D>open,
PSDONE=3D>open,
STATUS=3D>open);
end BEHAVIORAL;
--STATE_MACHINE-FILE :
***************************************************************************=
*********
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity STATE_MACHINE is
port(CLKX1 : in std_logic;
USER_START : in std_logic;
ADDRESS_CONTROL_FINISH : in std_logic;
MC_READY : in std_logic;
BRAM1_EN_toMUX : out std_logic; --Ausgangssignale zu BRAM1
BRAM1_EN_SEND : out std_logic;
BRAM1_RESET_toMUX : out std_logic;
BRAM1_RESET_SEND : out std_logic;
BRAM2_EN_RECEIVE : out std_logic; --Ausgangssignale zu BRAM2
BRAM2_EN_toMUX : out std_logic;
BRAM2_RESET_toMUX : out std_logic;
BRAM2_WRITE_EN : out std_logic;
MUX_RESET : out std_logic;
DES_EN : out std_logic;
SER_NEN : out std_logic;
SER_RESET : out std_logic;
ADDR_CONTROL_RESET_NEN : out
std_logic;--ADDRESS_CONTROL_RESET_(and)NotENable
MC_READ : out std_logic;
LED_Z0 : out std_logic;
LED_Z2 : out std_logic--;
);
end STATE_MACHINE;--Moore-Automat
architecture Behavioral of STATE_MACHINE is
type STATES is (Z0, Z1, Z2);
signal STATE: STATES :=3D Z0;
signal NEXT_S: STATES :=3D Z0;
signal STATE_Z0, STATE_Z2 : std_logic;
begin
STATE_MEMORY: process(CLKX1)
begin
if CLKX1'event and CLKX1 =3D '1' then--eventuell Flanke =E4ndern?
STATE <=3D NEXT_S;
end if;
end process;
DEFINE_NEXT_STATE: process(USER_START, ADDRESS_CONTROL_FINISH, MC_READY
,STATE)
begin
case STATE is
when Z0 =3D> if USER_START =3D '1' then
NEXT_S <=3D Z1;
else
NEXT_S <=3DZ0;
end if;
when Z1 =3D> if ADDRESS_CONTROL_FINISH =3D '1' then
NEXT_S <=3D Z2;
else
NEXT_S <=3DZ1;
end if;
when Z2 =3D> if MC_READY =3D '1' then
NEXT_S <=3D Z0;
else
NEXT_S <=3DZ2;
end if;
end case;
end process;
SET_OUTPUTS: process(STATE)
begin
case STATE is
when Z0 =3D> BRAM1_EN_toMUX <=3D '0';
BRAM1_EN_SEND <=3D '0';
BRAM1_RESET_toMUX <=3D '1';
BRAM1_RESET_SEND <=3D '1';
BRAM2_EN_RECEIVE <=3D '0';
BRAM2_EN_toMUX <=3D '0';
BRAM2_RESET_toMUX <=3D '1';
BRAM2_WRITE_EN <=3D '0';
MUX_RESET <=3D '1';
DES_EN <=3D '0';
SER_NEN <=3D '1';
SER_RESET <=3D '1';
ADDR_CONTROL_RESET_NEN <=3D '1';
MC_READ <=3D '0';
when Z1 =3D> BRAM1_EN_toMUX <=3D '0';
BRAM1_EN_SEND <=3D '1';
BRAM1_RESET_toMUX <=3D '1';
BRAM1_RESET_SEND <=3D '0';
BRAM2_EN_RECEIVE <=3D '1';
BRAM2_EN_toMUX <=3D '0';
BRAM2_RESET_toMUX <=3D '1';
BRAM2_WRITE_EN <=3D '1';
MUX_RESET <=3D '1';
DES_EN <=3D '1';
SER_NEN <=3D '0';
SER_RESET <=3D '0';
ADDR_CONTROL_RESET_NEN <=3D '0';
MC_READ <=3D '0';
when Z2 =3D> BRAM1_EN_toMUX <=3D '1';
BRAM1_EN_SEND <=3D '0';
BRAM1_RESET_toMUX <=3D '0';
BRAM1_RESET_SEND <=3D '1';--eventuall =E4ndern !
BRAM2_EN_RECEIVE <=3D '0';
BRAM2_EN_toMUX <=3D '1';
BRAM2_RESET_toMUX <=3D '0';
BRAM2_WRITE_EN <=3D '0';
MUX_RESET <=3D '0';
DES_EN <=3D '0';
SER_NEN <=3D '1';
SER_RESET <=3D '1';
ADDR_CONTROL_RESET_NEN <=3D '1';
MC_READ <=3D '1';
end case;
end process;
INDICATE_STATE: process(STATE)
begin
case STATE is
when Z0 =3D> STATE_Z0 <=3D '1';
STATE_Z2 <=3D '0';
when Z1 =3D> STATE_Z0 <=3D '0';
STATE_Z2 <=3D '0';
when Z2 =3D> STATE_Z0 <=3D '0';
STATE_Z2 <=3D '1';
end case;
end process;
LED_Z0 <=3D STATE_Z0; --die LEDs signalisieren den aktuellen Zustand
LED_Z2 <=3D STATE_Z2;
end Behavioral;
ADDRESS_CONTROL-FILE :
***************************************************************************=
*****
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ADDRESS_CONTROL is
generic(
ADDRESS_WIDTH : positive :=3D 10
);
Port ( CLKX1 : in std_logic;
RESET_NEN : in STD_LOGIC;
ADDR_BRAM1 : out STD_LOGIC_VECTOR (ADDRESS_WIDTH-1 downto
0);
ADDR_BRAM2 : out STD_LOGIC_VECTOR (ADDRESS_WIDTH-1 downto
0);
FINISH : out std_logic
);
end ADDRESS_CONTROL;
architecture Behavioral of ADDRESS_CONTROL is
signal FINISH_FLAG : std_logic;
signal CNT : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
constant MAX_ADDRESS : std_logic_vector(ADDRESS_WIDTH-1 downto 0) :=3D
"1111111111";
begin
CHANGE_ADDRESS: process(CLKX1)
begin
if CLKX1'event and CLKX1 =3D '1' then
if RESET_NEN =3D '1' then
CNT <=3D (others =3D> '0');
FINISH_FLAG <=3D '0';
else
if CNT =3D MAX_ADDRESS then
FINISH_FLAG <=3D '1';
else
CNT <=3D CNT + 1;
FINISH_FLAG <=3D '0';
end if;
end if;
end if;
end process;
ADDR_BRAM1 <=3D CNT;
ADDR_BRAM2 <=3D CNT;
FINISH <=3D FINISH_FLAG;
end Behavioral;
--SER-FILE :
***************************************************************************=
*************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity SER16to1 is
Port ( CLKX8 : in std_logic; --8facher Takt (bezogen auf den Takt des
16 Bit breiten Datenbus)
CLKX8_180 : in std_logic; --8facher Takt invertiert
RESET : in std_logic; --Reseteingang
NotENABLE : in std_logic;
DATA_PARALLEL : in std_logic_vector(15 downto 0);
ODATA_LVDSP : out std_logic;
ODATA_LVDSN : out std_logic);
end SER16to1;
architecture Behavioral of SER16to1 is
signal DATA_POS_EDGE, DATA_NEG_EDGE, DOUBLE_R_DATA : std_logic;
signal CNT, CNT0: std_logic_vector(2 downto 0):=3D (others =3D> '0');
begin
OFDDRRSE_inst : FDDRRSE --double datarate
port map (
Q =3D> DOUBLE_R_DATA, -- Data output (connect directly to
top-level port)
C0 =3D> CLKX8, -- 0 degree clock input
C1 =3D> CLKX8_180, -- 180 degree clock input
--Commonly, the Digital Clock Manager
--(DCM) generates the two clock signals by mirroring an
--incoming signal, then shifting it 180 degrees. This approach
--ensures minimal skew between the two signals.
CE =3D> '1', -- Clock enable input
D0 =3D> DATA_POS_EDGE, -- Posedge data input
D1 =3D> DATA_NEG_EDGE, -- Negedge data input
R =3D> NotENABLE, -- Synchronous reset input
S =3D> '0' -- Synchronous preset input
);
OBUFDS_inst : OBUFDS --LVDS-Output
generic map(
IOSTANDARD =3D> "LVDSEXT_25")--Standard: siehe Datasheet S.62(Tabelle
36)
port map (
O =3D> ODATA_LVDSP, -- Diff_p output (connect directly to
top-level port)
OB =3D> ODATA_LVDSN, -- Diff_n output (connect directly to
top-level port)
I =3D> DOUBLE_R_DATA -- Buffer input
);
--***********************************************************************
-- Prozess: COUNT
--
--Der Prozess fungiert als taktsynchroner Z=E4hler von 0 bis 7 mit
--synchronem Reseteingang(highaktiv), der den Z=E4hlerstand auf Null
setzt.
--
-- Input (->): CLK8X, RESET
--***********************************************************************
COUNT: process(CLKX8_180)
begin
if(CLKX8_180'event and CLKX8_180=3D'1') then
if RESET =3D '1' then
CNT <=3D (others =3D> '0');
CNT0 <=3D (others =3D> '0');
else
CNT <=3D CNT + '1';
CNT0 <=3D CNT;
end if;
end if;
end process;
--***********************************************************************
-- Prozess: MULTIPLEX
--
--Der Prozess legt in Abh=E4ngigkeit des Z=E4hlerstandes in CNT zwei
--aufeinanderfolgende Bits des parallelen Datenbusses DATA_PARALLEL an
--DATA_POS_EDGE und DATA_NEG_EDGE an.
--
-- Input (->): CLK8X_180, DATA_PARALLEL, CNT
-- Output(<-): DATA_POS_EDGE, DATA_NEG_EDGE
--***********************************************************************
MULTIPLEX: process(CLKX8_180)
begin
if(CLKX8_180'event and CLKX8_180=3D'1') then
if(CNT0 =3D 0) then
DATA_POS_EDGE <=3D DATA_PARALLEL(0);--eventuell Reihenfolge aus
SERDES-File verwenden
DATA_NEG_EDGE <=3D DATA_PARALLEL(1);
elsif(CNT0 =3D 1) then
DATA_POS_EDGE <=3D DATA_PARALLEL(2);
DATA_NEG_EDGE <=3D DATA_PARALLEL(3);
elsif(CNT0 =3D 2) then
DATA_POS_EDGE <=3D DATA_PARALLEL(4);
DATA_NEG_EDGE <=3D DATA_PARALLEL(5);
elsif(CNT0 =3D 3) then
DATA_POS_EDGE <=3D DATA_PARALLEL(6);
DATA_NEG_EDGE <=3D DATA_PARALLEL(7);
elsif(CNT0 =3D 4) then
DATA_POS_EDGE <=3D DATA_PARALLEL(8);
DATA_NEG_EDGE <=3D DATA_PARALLEL(9);
elsif(CNT0 =3D 5) then
DATA_POS_EDGE <=3D DATA_PARALLEL(10);
DATA_NEG_EDGE <=3D DATA_PARALLEL(11);
elsif(CNT0 =3D 6) then
DATA_POS_EDGE <=3D DATA_PARALLEL(12);
DATA_NEG_EDGE <=3D DATA_PARALLEL(13);
else
DATA_POS_EDGE <=3D DATA_PARALLEL(14);
DATA_NEG_EDGE <=3D DATA_PARALLEL(15);
end if;
end if;
end process;--nach dem Reset wird die seriellen Daten mit CLK8X/2
verz=F6gert ausgegeben
end Behavioral;
--DES-FILE :
***************************************************************************=
*************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Die Daten werden nach 2 Perioden von CLKX1 an DATA_OUT ausgegeben
library UNISIM;
use UNISIM.VComponents.all;
entity DES1to16 is
Port ( ENABLE : in std_logic; --mit DCM_LOCKED verbinden
IDATA_LVDSP : in std_logic;
IDATA_LVDSN : in std_logic;
CLKX8 : in STD_LOGIC;
CLKX8_180 : in STD_LOGIC;
CLKX1 : in STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0));
end DES1to16;
architecture Behavioral of DES1to16 is
signal DOUBLE_RATE_DATA_DES, DATA_NEG_EDGE, DATA_POS_EDGE : std_logic;
signal DD2 : std_logic_vector(15 downto 0);
signal DD1 : std_logic_vector(13 downto 0);
begin
IBUFDS_inst : IBUFDS
generic map (
IOSTANDARD =3D> "LVDSEXT_25")
port map (
O =3D> DOUBLE_RATE_DATA_DES, -- Clock buffer output
I =3D> IDATA_LVDSP, -- Diff_p clock buffer input (connect directly
to top-level port)
IB =3D> IDATA_LVDSN -- Diff_n clock buffer input (connect directly
to top-level port)
);
double_data_rate1: process(CLKX8)
begin
if CLKX8'event and CLKX8 =3D '1' then
DATA_POS_EDGE <=3D DOUBLE_RATE_DATA_DES;
end if;
end process;
double_data_rate2: process(CLKX8_180)
begin
if CLKX8_180'event and CLKX8_180 =3D '1' then
DATA_NEG_EDGE <=3D DOUBLE_RATE_DATA_DES;
end if;
end process;
process(CLKX8_180) begin
if(CLKX8_180'event and CLKX8_180=3D'1') then
DD2(15) <=3D DATA_POS_EDGE;
DD2(14) <=3D DATA_NEG_EDGE;
DD2(13) <=3D DD2(15);
DD2(12) <=3D DD2(14);
DD2(11) <=3D DD2(13);
DD2(10) <=3D DD2(12);
DD2(9) <=3D DD2(11);
DD2(8) <=3D DD2(10);
DD2(7) <=3D DD2(9);
DD2(6) <=3D DD2(8);
DD2(5) <=3D DD2(7);
DD2(4) <=3D DD2(6);
DD2(3) <=3D DD2(5);
DD2(2) <=3D DD2(4);
DD2(1) <=3D DD2(3);
DD2(0) <=3D DD2(2);
end if;
end process;
process(CLKX1) begin
if(CLKX1'event and CLKX1 =3D '1') then
DD1 <=3D DD2(15 downto 2);
end if;
end process;
process(CLKX1) begin
if(CLKX1'event and CLKX1 =3D '1') then
if ENABLE =3D '1' then
DATA_OUT <=3D DD2(1 downto 0) & DD1;
else
DATA_OUT <=3D (others =3D> '0');
end if;
end if;
end process;
end Behavioral;
--MUX-FILE :
***************************************************************************=
*************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity MUX is
generic(
DATA_WIDTH: positive :=3D 4;--Breite des Datenbusses
ADRESS_WIDTH_toMC: positive :=3D 12;
CONTROL_WIDTH: positive :=3D 2--Anzahl der Steuerleitungen
);
Port ( DATA1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);--Daten
von BRAM1
DATA2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);--Daten
von BRAM2
DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto
0);--Datenbus zum Mikrocontroller
ADRESS1 : out std_logic_vector(ADRESS_WIDTH_toMC-1 downto
0);--Adressbusse zu den BRAMs
ADRESS2 : out std_logic_vector(ADRESS_WIDTH_toMC-1 downto 0);
RESET : in std_logic;--asynchrones Resetsignal von der
State-Machine
INDICATION : out STD_LOGIC_VECTOR(CONTROL_WIDTH-1 downto
0);--Kontrollbus zum Mikrocontroller
CLK_extMC : in STD_LOGIC;--Auslesetakt f=FCr die BRAMs (vom
Mikrocontroller generiert)
CLK_fromMC :out STD_LOGIC
);
end MUX;
architecture Behavioral of MUX is
signal CHOOSE: std_logic :=3D '0';
signal ADRESS : std_logic_vector(ADRESS_WIDTH_toMC-1 downto 0);
signal CLK_MC : std_logic;
signal DATA_OUTs : std_logic_vector(DATA_WIDTH-1 downto 0);
constant MAX_ADRESS : std_logic_vector(ADRESS_WIDTH_toMC-1 downto 0) :=3D
"111111111111";--:=3D (others =3D> '1');
begin
IBUFG_inst : IBUFG
generic map (
IOSTANDARD =3D> "LVTTL")--Vmax =3D 3,3 V
port map (
O =3D> CLK_MC, -- Clock buffer output
I =3D> CLK_extMC -- Clock buffer input (connect directly to
top-level port)
);
COUNT: process(RESET,CLK_MC)
begin
if RESET =3D '1' then
ADRESS <=3D (others =3D> '0'); --eventuell auf 2 oder 3 setzen
(Verz=F6gerung des DES)
INDICATION <=3D "00";
CHOOSE <=3D '0';
DATA_OUTs <=3D "0000";
elsif CLK_MC'event and CLK_MC =3D '1' then
if ADRESS =3D MAX_ADRESS and CHOOSE =3D '1' then
INDICATION <=3D "11";
elsif CHOOSE =3D '1' then
INDICATION <=3D "10";
ADRESS <=3D ADRESS + 1;
DATA_OUTs <=3D DATA2;
CHOOSE <=3D not CHOOSE;
elsif CHOOSE =3D '0' then
INDICATION <=3D "01";
DATA_OUTs <=3D DATA1;
CHOOSE <=3D not CHOOSE;
end if;
end if;
end process;
ADRESS1 <=3D ADRESS;
ADRESS2 <=3D ADRESS;
DATA_OUT <=3D DATA_OUTs;
CLK_fromMC <=3D CLK_MC;
end Behavioral;
--BRAM_SEND-FILE :
***************************************************************************=
**************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM_SEND is
port(
DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
Data Output
DATA_toSER : out std_logic_vector(15 downto 0); -- Port B
16-bit Data Output
ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
Address Input
ADDRESS_SEND: in std_logic_vector(9 downto 0); -- Port B 10-bit
Address Input
CLK_MUX : in std_logic; -- Port A Clock
CLKX1 : in std_logic; -- Port B Clock
EN_toMUX : in std_logic; -- Port A RAM Enable Input
EN_SEND : in std_logic; -- PortB RAM Enable Input
RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
Input
RESET_SEND : in std_logic -- Port B Synchronous Set/Reset Input
);
end BRAM_SEND;
architecture Behavioral of BRAM_SEND is
begin
RAMB16_S4_S18_instBRAM_S : RAMB16_S4_S18
generic map (
INIT_A =3D> X"0", -- Value of output RAM registers on Port A at
startup
INIT_B =3D> "000000000000000000", -- Value of output RAM registers
on Port B at startup
SRVAL_A =3D> X"0", -- Port A ouput value upon SSR assertion
SRVAL_B =3D> "000000000000000000", -- Port B ouput value upon SSR
assertion
WRITE_MODE_A =3D> "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
NO_CHANGE
WRITE_MODE_B =3D> "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
NO_CHANGE
SIM_COLLISION_CHECK =3D> "ALL", -- "NONE", "WARNING",
"GENERATE_X_ONLY", "ALL
-- The following INIT_xx declarations specify the initial
contents of the RAM
-- Port A Address 0 to 1023, Port B Address 0 to 255
INIT_00 =3D>
X"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa",
INIT_01 =3D>
X"31A24DB059A566389894651BBD99BD2D8C9B354390CB86B5E70923CC10B65204",
INIT_02 =3D>
X"B75A641ACB7C72335E48B321BA380BC5AE9283A6251BEA66393419843808728D",
INIT_03 =3D>
X"3D2602D4EB565E4BD3ED9E420A33DC4880330B8BE847CCD78EA28B0D1629203B",
INIT_04 =3D>
X"7B584C96B3261E267E525534B3690D7A2AD1CC72E9BEB9DC5AE412A0D3E34174",
INIT_05 =3D>
X"4764D5C1BA875991B1B88A0DC825861D6714624105DBEEC93E9559134288753B",
INIT_06 =3D>
X"2A24E99ECED52732D58D25C5872420D4D2B6DC080B272BEA253E5AA815B2AA5E",
INIT_07 =3D>
X"A9EAB4871BD31ED9E7ACA6A2A562D3997107CE0748D5273B21A54A715116623A",
INIT_08 =3D>
X"0E8D512E0DDDA220348A7EC887150339A019A1CADA6B6C67C646B272C65B3945",
INIT_09 =3D>
X"47658CE4977E28C8BA23A832911095B56EAD0D46DE2E6D6A23B0D6A022B798C8",
INIT_0A =3D>
X"6D5D528AC725EB0D5AC9AA396A985E2041340DCCE61726EA3E62AD8796790D74",
INIT_0B =3D>
X"A63A2C98BD68A190ECE31E3705A9378C9D1E8552B3E7E5EE00A8D013C727A363",
INIT_0C =3D>
X"825E50D3C337E391D285B3E810E3A0D7685653D94D3E71908B1A0B41E592532B",
INIT_0D =3D>
X"37BBD94017A3516B4967BD75065601C1A07433BCD239DE86D92D4DA53D55B981",
INIT_0E =3D>
X"3E764373E02864893E1301E208892D2569D1ED0979D06EC0000928245A49AA11",
INIT_0F =3D>
X"AEA8387C19D3BAD3DED01AE68780851E039D6569CD94656616126E516764E078",
INIT_10 =3D>
X"9107D66D37276715944658B74A886219E8245299D83648117887622ACD2C35C5",
INIT_11 =3D>
X"397370A02C1787D6B595D4A5AC755CBE31E689D3051A08405ECC1E99030855C1",
INIT_12 =3D>
X"7331991EA02E2DEA3D652D24661C90E9D16940AA1AAE91399003462DD631AC94",
INIT_13 =3D>
X"A2CB044E7A59C17279009084672932CC3533E4EBED516AC7721ECBD266883CD1",
INIT_14 =3D>
X"A1765046C93423316DD2B122D28AD0DCDD103BA92EE602D8422012220C91032D",
INIT_15 =3D>
X"4592C5C36758B8D5D1C023E6382A362A9D368B2D4A55B635A832D51AA42728CE",
INIT_16 =3D>
X"EE8C72A89284A695C3D69DB5902E5319A2EA837D7609ACA4AA6CA489B7D302B1",
INIT_17 =3D>
X"5C3E3E9E9C0878C8AC6ECBE615836CCB43C1A5E4603224A7B01C4D30BA613848",
INIT_18 =3D>
X"70CE6A81349A33784ED013CDB6E62C469B471315970CB17B7589025586833A6C",
INIT_19 =3D>
X"05540E35E27C1277A11C0E6D17D114926B534032D816C57B7B11B524306498ED",
INIT_1A =3D>
X"708D82706D0B19581D1A8E58BCE5D5296C61CA6022E55BDD1DD16162094D4EED",
INIT_1B =3D>
X"2A693B87804ABE0A13AA3AB724B2A791C18DA76921DC35228D5EC1D9763C6725",
INIT_1C =3D>
X"D990AB41C6BD350363DB64D013484D6A59A0065A6DE67C00A7A256C28001D80B",
INIT_1D =3D>
X"E820A2025B1818A1A471AC876C288829A0594A85445B1B7834C73D5434DEC9E5",
INIT_1E =3D>
X"5247B680E5856510890DEB25C1835930256A2CEE12857D397DDE185EB277186D",
INIT_1F =3D>
X"BA60A017C650389739C753904943A841538E0670A65E83AC4043790C30E6669A",
INIT_20 =3D>
X"246C9E9DCB5D2D4CC66AA13C65AC49401B640926975ED881D5BE04838EA68123",
INIT_21 =3D>
X"3B98B3398E27C17667801A7AB02CA95E8756A83B02A24CD777936336AB82B0B7",
INIT_22 =3D>
X"EAB1A46DD0A426D85C40E307D858ADC1608B8CCDECD0CDC508129ED37712EA08",
INIT_23 =3D>
X"906539C37E94749A9EE3587351CB4DD87E382834ACABCB5C1B805D840C3C22A0",
INIT_24 =3D>
X"23BBD272324592E18081970242A3BA026693A37DA93CD1AC2CB3A7A8186951B5",
INIT_25 =3D>
X"BA4CD0D6ABC1C9948551DAA39CDA85BE7D666853B026573D5A6149D83C83230B",
INIT_26 =3D>
X"E82DE897419589BE836419AC18918889C2D9A1EACDE94ABD93E92A845B9D6C00",
INIT_27 =3D>
X"6061B4CDA55B0B32779A270D19D8AA0531A0C89BA1E17A4016A002ADD2235777",
INIT_28 =3D>
X"9CB86AED9549A707235322D3C5463796DE311DC541AB2CD0912CDE44B8DDCE71",
INIT_29 =3D>
X"B43024155B29AC819D78944DA8574EED8A0E357072CEE0916AE57D686471EE3C",
INIT_2A =3D>
X"DD6C8048AE468CD92990C481D7C1EB6ED8681E022A608828D190B171463592C4",
INIT_2B =3D>
X"11ED653750DC76D8B653769DE776DCA4279A0DC428ABBE7934917B70EB280301",
INIT_2C =3D>
X"E679CCAB8C41DA9B3C68E037E62CCDA28AC3B962EAB29EB840A2A6648C910749",
INIT_2D =3D>
X"B3E18D758E9B71D12B73BB60DEB04C7951BC8D98BD468207AC1C06C1C04DB702",
INIT_2E =3D>
X"B2A81000A55C3B44BE30D942E9E6068DA8BE420998BE13EB6813059B03C71897",
INIT_2F =3D>
X"CD935A639274D03D83B1597E77BA72725D6543414079037792295D6D3ED02B6E",
INIT_30 =3D>
X"D3EB4528A277C02A53B405BAC8C291B90D86A83AAB0C0659A64D9A1722B2E7D6",
INIT_31 =3D>
X"A52B397960E0BB813D650DEDDE8934E6E7CC0CD738835C83BD0670310A89035E",
INIT_32 =3D>
X"3008A539DA3B2B0CC660AB7C3335BD7B4E7851EDBB1D82494D09EC22011E5C59",
INIT_33 =3D>
X"867370158A154636585837376EB91D7B5A3CA037846706665D94A89DC25E6590",
INIT_34 =3D>
X"52B23273DD410DD802E4D86211B4866A46D719B12187B7C9E21DC9D816CA43A9",
INIT_35 =3D>
X"494494A876798145C8D4C19D2C4828D2698C994356323A4A3444ED9D03D67DD9",
INIT_36 =3D>
X"3560BB813222D28614B06885C11BADB5481ADE0402EE672076DD96935A02EBAC",
INIT_37 =3D>
X"747673B5ACB7B60DC6B8BA3B99612D36B82D479503719C6C0BBE9E9BB0AB5C50",
INIT_38 =3D>
X"7E5B3037525C8044D085A4C294204C32786478A4D7D08D1C2E91486C5CCA00DA",
INIT_39 =3D>
X"72E9D33644047E9C975DC8EACD22A7C1BCA17E08AC475B5382D57712DD5B9495",
INIT_3A =3D>
X"E1ECEA16C38C7B91004A1DB9621DEBE7AAAA53319860BAB59736958915AE8110",
INIT_3B =3D>
X"06D6C17D9EA65C31707CE127460640BE179626E758C41A5D117E85748E79770D",
INIT_3C =3D>
X"46746B699DBE74D2582A669821825634984163E8C49B48494A71122A135CA2EC",
INIT_3D =3D>
X"E63E9317D9678103A976196BE59BB75816A6140C68E95221567E103CB184E5A1",
INIT_3E =3D>
X"55BADDCBB01705A7A516A9EE5261952711D56002138E300DC5A8068ACE48243E",
INIT_3F =3D>
X"DA2A16DDDC46264E61237022D97510AA6AC244EA0A66C6D62A0A934EDB27C9CB",
-- The next set of INITP_xx are for the parity bits
-- Port A Address 0 to 1023, Port B Address 0 to 255
INITP_00 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port A Address 1024 to 2047, Port B Address 256 to 511
INITP_02 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port A Address 2048 to 3071, Port B Address 512 to 767
INITP_04 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port A Address 3072 to 4095, Port B Address 768 to 1023
INITP_06 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DOA =3D> DATA_toMUX, -- Port A 4-bit Data Output
DOB =3D> DATA_toSER, -- Port B 16-bit Data Output
DOPB =3D> open, -- Port B 2-bit Parity Output
ADDRA =3D> ADDRESS_MUX, -- Port A 12-bit Address Input
ADDRB =3D> ADDRESS_SEND, -- Port B 10-bit Address Input
CLKA =3D> CLK_MUX, -- Port A Clock
CLKB =3D> CLKX1, -- Port B Clock
DIA =3D> "1111", -- Port A 4-bit Data Input
DIB =3D> "1111111111111111", -- Port B 16-bit Data Input
DIPB =3D> "11", -- Port-B 2-bit parity Input
ENA =3D> EN_toMUX, -- Port A RAM Enable Input
ENB =3D> EN_SEND, -- PortB RAM Enable Input
SSRA =3D> RESET_toMUX, -- Port A Synchronous Set/Reset Input
SSRB =3D> RESET_SEND, -- Port B Synchronous Set/Reset Input
WEA =3D> '0', -- Port A Write Enable Input
WEB =3D> '0' -- Port B Write Enable Input
);
end Behavioral;
--BRAM_RECEIVE-FILE :
***************************************************************************=
**********
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM_RECEIVE is
port(
DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
Data Output
DATA_fromDES : in std_logic_vector(15 downto 0); -- Port B
16-bit Data Intput
ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
Address Input
ADDRESS_RECEIVE: in std_logic_vector(9 downto 0); -- Port B
10-bit Address Input
CLK_MUX : in std_logic; -- Port A Clock
CLKX1_PS : in std_logic; -- Port B Clock (PS: phase-shifted)
Verz=F6gerung des DUTs
EN_toMUX : in std_logic; -- Port A RAM Enable Input
EN_RECEIVE : in std_logic; -- PortB RAM Enable Input
RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
Input
WRITE_ENABLE : in std_logic
);
end BRAM_RECEIVE;
architecture Behavioral of BRAM_RECEIVE is
begin
RAMB16_S4_S18_instBRAM_R : RAMB16_S4_S18
generic map (
INIT_A =3D> X"0", -- Value of output RAM registers on Port A at
startup
INIT_B =3D> "000000000000000000", -- Value of output RAM registers
on Port B at startup
SRVAL_A =3D> X"0", -- Port A ouput value upon SSR assertion
SRVAL_B =3D> "000000000000000000", -- Port B ouput value upon SSR
assertion
WRITE_MODE_A =3D> "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
NO_CHANGE
WRITE_MODE_B =3D> "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
NO_CHANGE
SIM_COLLISION_CHECK =3D> "ALL", -- "NONE", "WARNING",
"GENERATE_X_ONLY", "ALL
-- The following INIT_xx declarations specify the initial
contents of the RAM
-- Port A Address 0 to 1023, Port B Address 0 to 255
INIT_00 =3D>
X"0B3590A1A174768987DBEA2C0A79BC3074933CE64B47E2B94839CABE379ECC71",
INIT_01 =3D>
X"757BD429738DA3B5A0B9494ED34701908332C6C3E6E7B76EA71E874BD75ACC6D",
INIT_02 =3D>
X"EE5D23172975488DE0E4C2CBB8107AC1E5944BB3DA3C0EB51318D2EA77138A60",
INIT_03 =3D>
X"579DB42A34470D66B69964892EE560544E7403D0487D9CA8010837BDAD631005",
INIT_04 =3D>
X"2399A631B2036C2EB2AC8E53ABE27DEDBC5188D14B3A3392557ABE3738321422",
INIT_05 =3D>
X"C8090DEA9B8B3E883E6489635B31E416468ED9687A5B358874275327AE030008",
INIT_06 =3D>
X"731B6C3308B38B6C0D326BB6D3E06770238588261AA155D9C1C4A5A3D13429C7",
INIT_07 =3D>
X"C918863BBECA868E6B3C85928E1CBDB6C38E6CA474D1679D512EC630D4714340",
INIT_08 =3D>
X"10566A52029BCCB3908DEDE5BCD66D8A0B9A8EA8209E86E46846C0B2809843B9",
INIT_09 =3D>
X"859E4E4D966313D79E3D6468BE556E5D2E86E7DED1E6BCA47B8A969969AB0356",
INIT_0A =3D>
X"5C8D1CEBB5E6E922785C707BED2633EB00BD915C902A056B5D06ED024914310A",
INIT_0B =3D>
X"550D1E5B4D9A10859202097C13533CDD9A9760BDB0D15C5A8404AC334CE35E32",
INIT_0C =3D>
X"134CB61CC92880A2A3A07045E587DECE9B9211B70944E4A2521E0940AC9113E3",
INIT_0D =3D>
X"EC82D7253C621B02A01DB21467D4A940EAE7491CE779070CDD17C0180DA6E7D6",
INIT_0E =3D>
X"7515EB022A8849ACA9A5C75251862103763144ADDB5AD12D599A57A120E4223B",
INIT_0F =3D>
X"24A096D40000CCBC1AAB8A64746725837098DE73BDBDC5324B670B7E29240533",
INIT_10 =3D>
X"D53CE81960775D439C74ED1D2754229BD42D46DDB9950CE2859B7B8241166535",
INIT_11 =3D>
X"A7A790B1BED30631AB5EC5B9BDB59EAB0CAC4E3D88EDDD6A1D182AADA54B3D4A",
INIT_12 =3D>
X"251CBA57185B5D4668AB34A466D81970AD1CEBE3AC0A187E3EB74187A6AC2CDA",
INIT_13 =3D>
X"7EEDE77DD75437D53E9207A92BBC67914A41A408566072127EA3B2DEB9D53C06",
INIT_14 =3D>
X"E0D1C599386389B6B54BA14C2B789E3A979811CB416933A62937ADD04EB189AB",
INIT_15 =3D>
X"464662DA8020A74474A87C2A52A407C41CE69291558C3937C34C86DACA5D2775",
INIT_16 =3D>
X"16A4643C5E97803607E2864BE61C5BA3014B497CE6128D18A6E77C582681A4A8",
INIT_17 =3D>
X"C6A37A99254E0DD0462D39BEC8034DCECCDAE6BB732134CD59878443E675A089",
INIT_18 =3D>
X"739914A602CD098E674EE2A54AD370EC953A4ADCB8D35EA090394325DC72B3CC",
INIT_19 =3D>
X"63A805EACD00E597D70C8AB5A681BA8294272390BE1C33BC6D1725509C23EDAC",
INIT_1A =3D>
X"B144B8C3B9B62748CE689E60B1C5A36DCE9E268D484B9154976ADAE407567E18",
INIT_1B =3D>
X"D4077889214A840C1A88E3CADE1A880EC65E97784521D515C37D575B0ABEA0E1",
INIT_1C =3D>
X"41403DE8985618E4D9D71A8856371D92C76DBA6E890929A021DCBA19051A60C4",
INIT_1D =3D>
X"6DACB5AA04550902A834C0B4031A04A6BC0DB5149DCA4BB2B9C7EE058586885C",
INIT_1E =3D>
X"DD3DE0AB96E7EED41168A0EA91E9D0715A48DA1C947D0383DD73A5BBECE04E38",
INIT_1F =3D>
X"6864B20C2D189816EC938CB71656978122D7781DA562ADB21CAED81AC5E2A53A",
INIT_20 =3D>
X"B2236BB14A6770370DED633D27ECB88C50622A3D7D77EB87A7E0379662DBCA98",
INIT_21 =3D>
X"289EC1D363D15E3B38601D02A13523815674B6B59335BB8815309DA65EC8381B",
INIT_22 =3D>
X"3EBAE3DE211C45498C23112D6765593CE3B6CE3C436C2D16A8E84BD7D4968C8B",
INIT_23 =3D>
X"DC91077562070CDC3DB6CECE4776AD272663D3467C2C162C06041C9017714181",
INIT_24 =3D>
X"2E1715E9C1C88E9A1D23B47E7EB3CA8C1D71DB28E4A5AE90D3E6A8D4D22D34E3",
INIT_25 =3D>
X"62C6327D4A632400B881AC5C789708D4434B51E6A006C582B3201913B742A06C",
INIT_26 =3D>
X"34BB8C76C978EC4BB4092BD8645E5B7B7BA4465D0D7038ADE925D8C17133E249",
INIT_27 =3D>
X"02E14B2469EA143810931358BBE92B3917948E026B91B8207BBD18CCB41B0536",
INIT_28 =3D>
X"B15BDDB22ED3989D6A58D0A63D1D1CEBDB8340E917447B31950EC8C347BB0D17",
INIT_29 =3D>
X"66052893E55DC45710706D8E3CBBD618CA2D67162DE6E8EE0AD2049BA2B46777",
INIT_2A =3D>
X"977285925069B73AC154A8ECE130AD752A897E48AC719623504164B83C76E0C5",
INIT_2B =3D>
X"89B4BE42541A847B0223922554D451094A635DE9544205622B36D293799B11A1",
INIT_2C =3D>
X"79B9CD247A7973EA5B762E132C955D0901C3AE80C74CB38CC58C8EBDD4DBE0E3",
INIT_2D =3D>
X"2C92774BAA711678215E1A62B54395664089B050AC764D18463D6E025888103D",
INIT_2E =3D>
X"A94C2C9C964974C62ADC092CC62AA01B53814B569290A0DE47C61E084D49BEDC",
INIT_2F =3D>
X"7BCBA95019C7D167B6A6BC80584578582C9389EE1757C4D506249C2BBAD9BE9C",
INIT_30 =3D>
X"81211DC8374AD2D8AAAE52068C386219D13749970D68D60B97CE1ED587786C32",
INIT_31 =3D>
X"CE616EA9658D4B3724958B4DCB9C7C308929AC8BA7C7B048BE8DD12D31E09A57",
INIT_32 =3D>
X"CAE0555E5C4AED028CE36ECE5CAEA51E5C790CD086D69513970B538117ED91D4",
INIT_33 =3D>
X"79EE0487DC6BC15325DE54501B4E6A86C36291590CAAC1D2300BB75E382066E0",
INIT_34 =3D>
X"48CC0E891D2146B3A1524249B64321EA29EA7A0ECB60066E7AA0CE99035A2B53",
INIT_35 =3D>
X"ACA96E9CDDDEB7CBE385827B481BC8454A6D97117CBAA7E64421E5D9E6C24946",
INIT_36 =3D>
X"4CC35D2066B48B1545E9393DC665EDC8EA458C9753EC40910935507B6A3C8582",
INIT_37 =3D>
X"5C0279A105462789E9AC29566D527E65324A26ECC674D31A3E8A7CED5ACD525D",
INIT_38 =3D>
X"888551B655EC6E6930C940B71B755A7E3EEC888729349B981ECEE2C4A9437681",
INIT_39 =3D>
X"A13539E0D35A409D50E07EACE4D86067D219A133EEA04CBBB8533356EAD153AC",
INIT_3A =3D>
X"D7AE7AA282818050A618B3321458D9190A9C8274402C18C7ED2901487E7D36B0",
INIT_3B =3D>
X"05B4E9256519A36309D976C500ADE14590D51A175C3D6B68351424C15A8462C5",
INIT_3C =3D>
X"9BB38E3071EE97A40156A5AD5DBE49E757E16D1BD195DEC7C7A7D79D488AB5AA",
INIT_3D =3D>
X"13539E09B9339078A1151363907AA370AB6A49B1366A6889DCD2AD14741DA981",
INIT_3E =3D>
X"765B0AED38804B7D11A8CC166E97A3A3676AE7A1C656A80116A394203D03D4B8",
INIT_3F =3D>
X"35061DB65D374DB727B6AA34C3ADA0E8D6A4A00489978B220AD0214A73C5D8E9")
port map (
DOA =3D> DATA_toMUX, -- Port A 4-bit Data Output
DOB =3D> open, -- Port B 16-bit Data Output
DOPB =3D> open, -- Port B 2-bit Parity Output
ADDRA =3D> ADDRESS_MUX, -- Port A 12-bit Address Input
ADDRB =3D> ADDRESS_RECEIVE, -- Port B 10-bit Address Input
CLKA =3D> CLK_MUX, -- Port A Clock
CLKB =3D> CLKX1_PS, -- Port B Clock
DIA =3D> "1111", -- Port A 4-bit Data Input
DIB =3D> DATA_fromDES, -- Port B 16-bit Data Input
DIPB =3D> "11", -- Port-B 2-bit parity Input
ENA =3D> EN_toMUX, -- Port A RAM Enable Input
ENB =3D> EN_RECEIVE, -- PortB RAM Enable Input
SSRA =3D> RESET_toMUX, -- Port A Synchronous Set/Reset Input
SSRB =3D> '0', -- Port B Synchronous Set/Reset Input
WEA =3D> '0', -- Port A Write Enable Input
WEB =3D> WRITE_ENABLE -- Port B Write Enable Input
);
end Behavioral;
Article: 113617Hi, I have a design, where I want to interface an ADC (250 MHz) to a Spartan-3E. The clock from the ADC enters the FPGA via LVDS, gets IBUFGDSed and enters the DCM. It leaves the DCM as CLOCK_0 and half the inputclock, CLOCK_DV. CLOCK_0 then clocks a IP-Core FIFO. Meanwhile, the DATA from the ADC (LVDS as well) enter the FPGA and are routed into the 8-bit input of the FIFO. There I want to be sure, that the DATA are valid, 0.92ns (!) before the rising edge of CLOCK_0. How can I constraint this? OFFSET does not work, because it just constraints clocksignals from the pads. I noticed, that the translator creates "TS_dcm1_CLK0_BUF" and "TS_dcm1_CLKDV_BUF" with the appropriate periods (4ns and 8ns) for the signals behind the DCM. This is very nice, but I can't refer to these clocks before the compilation. Furthermore, how can I reach my goal? I will try to use a phase-shifted clock on the DCM, but how can I control if my constraints are met? Any help is greatly appreciated, since the Help-Section concerning Constraints on xilinx.com is down at the moment. I'm using ISE Webpack. regards, ChristianArticle: 113618
Hi, Topweaver Anydivider (TAD) 1.1 has been released. DLL/PLL resources provide a good way to frequency synthesis. But sometimes people write their own HDL code to fulfill the clock division function, for special multiply/divide values, adjustable duty cycle or other requirements that can hardly be achieved by using a DLL/PLL. For more information, please visit http://www.topweaver.com/doc/tad/tad.htm Download (free) http://www.topweaver.com/download.htm TADArticle: 113619
Antti ha escrito: > Pablo schrieb: > > > Does anyone try to read values from sdram without the use of > > Microblaze?. It is simple to read/write values in ddr sdram with the > > use of pointer in MIcroblaze but how can you read values in vhdl code > > for displaying an image (store in sdram) with the use of a vga core. > > connect VGA core to the OPB bus. > done, works - simple :) > > Antti Thanks, I have not considered this because I would create an independient core, but I suppose that it's a good idea.Article: 113620
Johannes Hausensteiner wrote:
> Hi there,
>
> I apologize for the unspecific subject, but for me it is like that.
>
> I am working on an FPGA project which consists of a CPU (8bit), a
> UART, a sensor keypad controller, LCD module controller, and SPI
> flash controller. Since all these modules need a clock to run, but
> with different clock speeds I decided to do a dedicated "clock
> generator" module which divides the various frequencies from the
> master clock. The "unpredictable behaviour" manifests itself most
> prominently in this clock generator module; although I assume that
> there might be other effects as well. The sequence is this:
> - I edit a VHDL source file (currently I am working on the keypad
> controller module)
> - I compile the project
> - I load the bitstream into the FPGA
> - the CPU would not run, or maybe the LCD, or maybe the SPI or the UART
>
> The point I quite do not understand is that the area I made the last
> changes definitely does have nothing to do with the affected design
> area (e.g. keypad - LCD). (ha, I am sounding like a SW developer...)
> Anyway, to give a bit more information here is like I implemented the
> clock dividers:
>
> ****************************** code ******************************
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> entity clock_generator is
> port (
> rst : in std_logic;
> clk_in : in std_logic; -- input clock (25MHz)
> sel : in std_logic;
> nWR : in std_logic;
> ddrive : in std_logic;
> d_in : in std_logic_vector (7 downto 0);
> d_out : out std_logic_vector (7 downto 0);
> cpu_clk : out std_logic; -- CPU clock (3Hz .. 12.5MHz)
> uart_clk : out std_logic; -- UART clock (115.2kHz:38400b/sec)
> lcd_clk : out std_logic; -- LCD controller clock (1MHz)
> key_clk : out std_logic; -- keypad controller clock (333kHz)
> spi_clk : out std_logic -- SPI controller clock (6.25MHz)
> );
> end clock_generator;
>
> architecture divider of clock_generator is
> constant SYS_FREQ : integer := 25000000; -- 25MHz
> constant UART_FREQ : integer := 115200; -- 3*38.4kHz
> constant LCD_FREQ : integer := 1000000; -- 1MHz
> constant KEY_FREQ : integer := 333333; -- 333kHz
> constant SPI_FREQ : integer := 6250000; -- 6.25MHz
> signal uart_cnt : integer;
> signal lcd_cnt : integer;
> signal key_cnt : integer;
> signal spi_cnt : integer;
> signal cpu_cnt, cpu_end : std_logic_vector (23 downto 0);
> signal cpu_div : std_logic_vector (7 downto 0);
> signal wr_cpu_div : std_logic;
> begin
> -- write the clock divider
> wr_cpu_div <= not nWR and sel;
> cpu_div_latch : process (rst, wr_cpu_div)
> begin
> if rst = '1' then
> cpu_div <= x"01";
> elsif falling_edge (wr_cpu_div) then
> if d_in = x"00" then
> cpu_div <= x"01";
> else
> cpu_div <= d_in;
> end if;
> end if;
> end process;
>
> -- read the clock divider
> d_out(0) <= sel and not ddrive and cpu_div(0);
> d_out(1) <= sel and not ddrive and cpu_div(1);
> d_out(2) <= sel and not ddrive and cpu_div(2);
> d_out(3) <= sel and not ddrive and cpu_div(3);
> d_out(4) <= sel and not ddrive and cpu_div(4);
> d_out(5) <= sel and not ddrive and cpu_div(5);
> d_out(6) <= sel and not ddrive and cpu_div(6);
> d_out(7) <= sel and not ddrive and cpu_div(7);
>
> -- the counter
> cpu_divider : process (rst, clk_in)
> variable segment : std_logic_vector (15 downto 0);
> begin
> if rst = '1' then
> cpu_cnt <= x"000000";
> cpu_clk <= '0';
> elsif rising_edge (clk_in) then
> if unsigned(cpu_cnt) < unsigned('0' & cpu_end(23 downto 1)) then
> cpu_clk <= '0';
> else
> cpu_clk <= '1';
> end if;
> if unsigned(cpu_cnt) >= unsigned(cpu_end) then
> cpu_clk <= '0';
> cpu_cnt <= x"000001";
> else
> cpu_cnt <= cpu_cnt + 1;
> end if;
> end if;
> case cpu_div (7 downto 4) is
> when x"0" => -- 0000 0000 0000 0000 000x xxx0
> segment := x"0000";
> cpu_end <= "000" & segment & cpu_div(3 downto 0) & '0';
>
> when x"1" => -- 0000 0000 0000 0000 001x xxx0
> segment := x"0001";
> cpu_end <= "000" & segment & cpu_div(3 downto 0) & '0';
>
> when x"2" => -- 0000 0000 0000 0000 010x xxx0
> segment := x"0002";
> cpu_end <= "000" & segment & cpu_div(3 downto 0) & '0';
>
> when x"3" => -- 0000 0000 0000 0000 100x xxx0
> segment := x"0004";
> cpu_end <= "000" & segment & cpu_div(3 downto 0) & '0';
>
> when x"4" => -- 0000 0000 0000 0010 000x xxx0
> segment := x"0008";
> cpu_end <= "00" & segment & '0' & cpu_div(3 downto 0) & '0';
>
> when x"5" => -- 0000 0000 0000 0100 00xx xx00
> segment := x"0010";
> cpu_end <= "00" & segment & cpu_div(3 downto 0) & "00";
>
> when x"6" => -- 0000 0000 0001 0000 00xx xx00
> segment := x"0020";
> cpu_end <= '0' & segment & '0' & cpu_div(3 downto 0) & "00";
>
> when x"7" => -- 0000 0000 0010 0000 00xx xx00
> segment := x"0040";
> cpu_end <= '0' & segment & '0' & cpu_div(3 downto 0) & "00";
>
> when x"8" => -- 0000 0000 0100 0000 0xxx x000
> segment := x"0080";
> cpu_end <= '0' & segment & cpu_div(3 downto 0) & "000";
>
> when x"9" => -- 0000 0001 0000 0000 0xxx x000
> segment := x"0100";
> cpu_end <= segment & '0' & cpu_div(3 downto 0) & "000";
>
> when x"A" => -- 0000 0010 0000 0000 0xxx x000
> segment := x"0200";
> cpu_end <= segment & '0' & cpu_div(3 downto 0) & "000";
>
> when x"B" => -- 0000 0100 0000 0000 xxxx 0000
> segment := x"0400";
> cpu_end <= segment & cpu_div(3 downto 0) & "0000";
>
> when x"C" => -- 0001 0000 0000 0000 xxxx 0000
> segment := x"0800";
> cpu_end <= segment(14 downto 0) & '0' & cpu_div(3 downto 0) &
> "0000";
>
> when x"D" => -- 0010 0000 0000 0000 xxxx 0000
> segment := x"1000";
> cpu_end <= segment(14 downto 0) & '0' & cpu_div(3 downto 0) &
> "0000";
>
> when x"E" => -- 0100 0000 0000 000x xxx0 0000
> segment := x"2000";
> cpu_end <= segment(14 downto 0) & cpu_div(3 downto 0) & "00000";
>
> when x"F" => -- 1000 0000 0000 000x xxx0 0000
> segment := x"4000";
> cpu_end <= segment(14 downto 0) & cpu_div(3 downto 0) & "00000";
> when others => null;
> end case;
> end process;
>
> uart_divider : process (rst, clk_in)
> begin
> if rst = '1' then
> uart_cnt <= 0;
> uart_clk <= '0';
> elsif rising_edge (clk_in) then
> uart_cnt <= uart_cnt + 1;
> if uart_cnt >= ((SYS_FREQ/2) / UART_FREQ) then
> uart_clk <= '0';
> else
> uart_clk <= '1';
> end if;
> if uart_cnt >= ((SYS_FREQ / UART_FREQ) - 1) then
> uart_cnt <= 0;
> end if;
> end if;
> end process;
>
> lcd_divider : process (rst, clk_in)
> begin
> if rst = '1' then
> lcd_cnt <= 0;
> lcd_clk <= '0';
> elsif rising_edge (clk_in) then
> if lcd_cnt >= ((SYS_FREQ/2) / LCD_FREQ) then
> lcd_clk <= '0';
> else
> lcd_clk <= '1';
> end if;
> if lcd_cnt >= ((SYS_FREQ / LCD_FREQ) - 1) then
> lcd_cnt <= 0;
> else
> lcd_cnt <= lcd_cnt + 1;
> end if;
> end if;
> end process;
>
> key_divider : process (rst, clk_in)
> begin
> if rst = '1' then
> key_cnt <= 0;
> key_clk <= '0';
> elsif rising_edge (clk_in) then
> if key_cnt >= ((SYS_FREQ/2) / KEY_FREQ) then
> key_clk <= '0';
> else
> key_clk <= '1';
> end if;
> if key_cnt >= ((SYS_FREQ / KEY_FREQ) - 1) then
> key_cnt <= 0;
> else
> key_cnt <= key_cnt + 1;
> end if;
> end if;
> end process;
>
> spi_divider : process (rst, clk_in)
> begin
> if rst = '1' then
> spi_cnt <= 0;
> spi_clk <= '0';
> elsif rising_edge (clk_in) then
> if spi_cnt >= ((SYS_FREQ/2) / SPI_FREQ) then
> spi_clk <= '0';
> else
> spi_clk <= '1';
> end if;
> if spi_cnt >= ((SYS_FREQ / SPI_FREQ) - 1) then
> spi_cnt <= 0;
> else
> spi_cnt <= spi_cnt + 1;
> end if;
> end if;
> end process;
> end divider;
> *************************** end of code **************************
>
> The CPU clock divider is under software control - it allows for really
> slow speeds (downto 3Hz).
> I already tried slightly different divider desgins but that did not
> change the behaviour.
> Everytime I encounter a "mysterious" disfunction anywhere in the system
> I tweak the individual frequencies a little - and voila: it works again.
>
> I am using a Lattice ECP33 chip on a Gleichmann HPEmini development
> board, ispLEVER version 6.0.01.46.29.06SP2006.01 (Windows), using the
> Precision VHDL compiler.
>
> As I said this is my first FPGA project, so I am really unsure about
> setting timing constraints, routing constraints, etc.
> Basically I set the parameters to an easy-for-the-compiler/fitter-
> setting, since one run takes about 10 min on my machine.
> The FPGA runs off a 25MHz crystal oscillator; my CPU is running at
> 12.5MHz at most.
> I have been designing programmable logic for many years now, using
> MAX7000 with AHDL and GALs with ABEL.
> Additionally I am new to VHDL; I am learning with this project. I am
> absolutely willing to improve my coding style and design process.
>
> Any help or hint for reading about partitioning, etc. is highly
> appreciated!
>
> Thanks a lot! Also thanks to this list, from where I already got
> valuable information several times.
>
> Johannes
Johannes
I made a simple test bench using Xilinx ISE 8.2i. I made Reset briefly
active. I loaded x"00" into "cpu_div". I simulated using ModelSim XE
III (Xilinx Edition), vers 6.0d. Clock output results:
cpu_clk = 12.5 MHz
lcd_clk = 1.0 MHz
spi_clk = 6.22 MHz
uart_clk = 76.7 Mhz
I suggest you similate your code to see if you are getting the rusults
you expect. The case statement in the "cpu_divider" process makes the
process quite compilcated, and I'm not sure what the code is supposed
to do.
BTW, your "cpu_divider" process is missing "cpu_dev" in the process
sensitivity list.
HTH
-Dave Pollum
Article: 113621For what it is worth: I designed the very first FIFO integrated circuit, the Fairchild 3341 in 1969/70. It was very popular for a while. But Fairchild did not patent it. Peter Alfke On Dec 18, 5:13 am, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> wrote: > Peter Alfke wrote: > > Let's leave it at that. We won't agree, but then: we do not have to...To agree, there would need to be an argument to agree on in the first > place. Since I was only proposing an alternative way of going about > pointer data domain crossing, the only thing possibly worth arguing over > is whether or not the approach is valid... and since I have used this > approach in an ASIC project, I have reasonable proof that it is. > > Is it the best implementation? That answer is application-specific. > > > BTW, Google lists over 1000 patents on FIFOs. > > A few of them are mine, but I could not believe the total number...The wheel has been patented a few times as well, there are way too many > duplicate, obvious and useless patents out there, it makes finding truly > relevant stuff an extremely tedious task. > > From what I have seen in FIFO patents, they suffer from the same > redundancy and irrelevance as other patents: they reinvent multi-bits > signal domain crossing, not FIFOs themselves. All claims beyond that are > frivolous at best - once the cross-over is done, everything beyond that > is easily 20+ years old common knowledge. > > I am very much surprised to see that some async FIFO patents are under > 10 years old... the gray code and DP-SRAM or register file FIFO combo is > much older than that AFAIK. > > > On Dec 17, 6:02 pm, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> > > wrote: > >> Yes, one can do "ptrA == ptrB" directly in gray... but if I want to do > >> "ptrA - ptrB" to know how much headroom I have, it does not work quite > >> as nicely, this does require G2B conversion. > > >> For a gray implementation, it is probably preferable to generate a > >> straight gray counter and convert that to linear binary for local use to > >> avoid combinational paths and routing between the counter's registers > >> and the other domain's resync registers since it increases the risk > >> transcoding glitches (path delays + non-existing phase relation + ...) > >> getting through. With a binary counter, the gray conversion must be > >> registered on the local clock before resyncing to the other clock. > > >> In any case, the most important point of any design always is: it has to > >> work.Article: 113622
always @(*) will synthesize, at least in some situations, as I have done it before and had no problem. This was with ISE, I can't speak for other synthesis engines. ---Matthew Hicks "Daniel S." <digitalmastrmind_no_spam@hotmail.com> wrote in message news:0dphh.25718$qD1.247465@wagner.videotron.net... > 222 wrote: >>>> Correction, this is wrong >>>> out =out +1; >>>> Put this in instead >>>> out =!out >>>> >>>> >>> Since you toggle "out" every time your counter reaches 10, you are >>> actually creating a waveform with twice the period you intended. Also, >> >> Does "always @(x)" work on _any_ change, i.e. it should react twice >> on each clock, which would make it right, or does it default to positive >> edge, >> which would make it twice the period? > > As I said, I have only poked into verilog with a pole... I overlooked that > little detail and yes, this does appear to be equivalent to clk'event in > VHDL. > > In this case, try synthesizing your code with free tools from most FPGA > vendors and I think you will get an error saying that you have to pick an > edge - the FFs in all FPGAs I know of do not work with both edges, even > the DDR IOBs are implemented with two register banks clocked on opposite > edges. > > It might work the way you intended in simulation but I am almost 100% > certain that it will fail in synthesis. > >>> because counting starts at 0 and you compare with 10, there are actually >>> 11 counts between toggles instead of 10. >> >> Correct, I need to count to 9.Article: 113623
Sorry, ignore my last post, I looked back and saw that you refering to an
actual signal not a catch all, which will also work, if you test the value
in the always block, but will create a level sensitive instead of edge
triggered (combinatiorial vs sequential) circuit. Here are my corrections
to the OP's code and the reasons behind them.
//divide oscillator clock by 10 (xc9536)
module clk_div10 (in,out)
input in;
output out;
// Set initial value for cnt, 0 to 4 = 5 ticks, period of slow signal = 10
ticks(periods of fast signal
reg[0..3] cnt = 4;
// Changed to edge triggered
always @ (posedge in) begin
// Subtraction method synthesizes better than addition
cnt=cnt-1;
if (cnt == 0) begin
cnt = 4;
// Logic operations better than mathematical ones, although the
synthesizer would probably optomize it for you
out = ~out;
end
end
endmodule
"Daniel S." <digitalmastrmind_no_spam@hotmail.com> wrote in message
news:0dphh.25718$qD1.247465@wagner.videotron.net...
> 222 wrote:
>>>> Correction, this is wrong
>>>> out =out +1;
>>>> Put this in instead
>>>> out =!out
>>>>
>>>>
>>> Since you toggle "out" every time your counter reaches 10, you are
>>> actually creating a waveform with twice the period you intended. Also,
>>
>> Does "always @(x)" work on _any_ change, i.e. it should react twice
>> on each clock, which would make it right, or does it default to positive
>> edge,
>> which would make it twice the period?
>
> As I said, I have only poked into verilog with a pole... I overlooked that
> little detail and yes, this does appear to be equivalent to clk'event in
> VHDL.
>
> In this case, try synthesizing your code with free tools from most FPGA
> vendors and I think you will get an error saying that you have to pick an
> edge - the FFs in all FPGAs I know of do not work with both edges, even
> the DDR IOBs are implemented with two register banks clocked on opposite
> edges.
>
> It might work the way you intended in simulation but I am almost 100%
> certain that it will fail in synthesis.
>
>>> because counting starts at 0 and you compare with 10, there are actually
>>> 11 counts between toggles instead of 10.
>>
>> Correct, I need to count to 9.
Article: 113624
I thought that some people on this newsgroup might be interested
in two small hacks I've written recently:
---------------------------------------------------------------------------
xdlanalyze.pl:
Shows statistics about an XDL file (or NCD file) as in the following
example: (I'm not aware of any Xilinx command that will print this kind
of (hierarchical) information about a place and routed design, please
enlighten me if I've missed something.)
$ perl xdlanalyze.pl dafk.xdl
XDLAnalyze V1.1 by Andreas Ehliar <ehliar@isy.liu.se>
Analyzing the file dafk.xdl...................................................
+-------------+--------+--------+--------+-----------+--------+--------+
| Module | LUTS | FF | RAMB16 | MULT18x18 | IOB | DCM |
+-------------+--------+--------+--------+-----------+--------+--------+
| / | 64 | | | | 216 | |
| cpu | 5065 | 1345 | 12 | 4 | | |
| dma0 | 654 | 254 | 1 | | | |
| dvga | 816 | 755 | 4 | | | |
| eth3 | 2995 | 2337 | 4 | | | |
| jpg0 | 1682 | 681 | 2 | 13 | | |
| leela | 684 | 552 | 4 | 2 | | |
| pia | 9 | | | | | |
| pkmc_mc | 219 | 122 | | | | |
| rom0 | 111 | 3 | 12 | | | |
| sys_sig_gen | | 6 | | | | 2 |
| uart2 | 824 | 346 | | | | |
| wb_conbus | 618 | 10 | | | | |
+-------------+--------+--------+--------+-----------+--------+--------+
| Total | 13741 | 6411 | 39 | 19 | 216 | 2 |
+-------------+--------+--------+--------+-----------+--------+--------+
This allows you to see the resources used by different modules in your
design without having to resynthesize just that part of the design. This
also means that we can get resource usage of individual modules after the
module has been optimized for a certain design. Some fuzziness will remain
because logic from more than one module might have been placed in the
same LUT, there is nothing I can do about this. You can also show the
hierarchy in more detail as in the following example:
$ perl xdlanalyze.pl dafk.xdl 1
XDLAnalyze V1.1 by Andreas Ehliar <ehliar@isy.liu.se>
Analyzing the file dafk.xdl...................................................
+-----------------------------+--------+--------+--------+-----------+--------+--------+
| Module | LUTS | FF | RAMB16 | MULT18x18 | IOB | DCM |
+-----------------------------+--------+--------+--------+-----------+--------+--------+
| / | 64 | | | | 216 | |
| cpu | 1 | | | | | |
| cpu/dwb_biu | 10 | 72 | | | | |
| cpu/iwb_biu | 64 | 73 | | | | |
| cpu/or1200_cpu | 4441 | 987 | 2 | 4 | | |
| cpu/or1200_dc_top | 208 | 40 | 5 | | | |
| cpu/or1200_ic_top | 182 | 38 | 5 | | | |
| cpu/or1200_immu_top | 11 | 33 | | | | |
| cpu/or1200_pic | 32 | 38 | | | | |
| cpu/or1200_tt | 116 | 64 | | | | |
| dma0 | 617 | 235 | | | | |
...
many lines removed
...
| uart2/wb_interface | 65 | 80 | | | | |
| wb_conbus | 618 | | | | | |
| wb_conbus/arb | | 10 | | | | |
+-----------------------------+--------+--------+--------+-----------+--------+--------+
| Total | 13741 | 6411 | 39 | 19 | 216 | 2 |
+-----------------------------+--------+--------+--------+-----------+--------+--------+
If run against a .NCD file it will use xdl -ncd2xdl to automatically
convert a design to .XDL before analyzing it.
You can download it at http://www.da.isy.liu.se/~ehliar/stuff/xdlanalyze.pl
Only tested in Linux.
---------------------------------------------------------------------------
colorized_signals.tcl:
A modelsim hack which allows you to add all signals in a certain module to
the wave window and change the color of inputs, outputs and inouts so that
they are different than internal signals. Screenshots are available at
http://www.da.isy.liu.se/~ehliar/stuff/colorized_menu.png and
http://www.da.isy.liu.se/~ehliar/stuff/colorized_signal.png .
You can download it at
http://www.da.isy.liu.se/~ehliar/stuff/colorized_signals.tcl .
Tested with Modelsim 6.2b in Linux.
---------------------------------------------------------------------------
I hope someone will find this useful :)
/Andreas
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