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Messages from 113650

Article: 113650
Subject: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
From: "abright52" <abright52@gmail.com>
Date: 18 Dec 2006 18:33:29 -0800
Links: << >>  << T >>  << A >>
We have created a circuit to using the clocks to read and write to the
card.  The original file is created with a Hex Editor in Windows XP.

David wrote:
> Are you using any type of operating system to do the reading and
> writing?


Article: 113651
Subject: Re: electrical level conversion
From: "Brian Davis" <brimdavis@aol.com>
Date: 18 Dec 2006 20:26:17 -0800
Links: << >>  << T >>  << A >>
Michael A. Terrell wrote:
>
>Are you the Brian Davis that workled for Microdyne?
>
Not me, sorry!

Austin wrote:
>
>OK, now I see it.  Spartan 3/3E/3A dropped HSTL IV
>
 If you look at the available S3E TTL/LVCMOS drive strengths,
they are mostly around half of the S3 max strengths.

Symon wrote:
>
> gives me hope that the S3e 'dedicated  inputs', i.e. input only,
> IOBs may have especially low Cpin. Brian, I don't suppose
> that was part of your measuring exercise when you looked
> at the LVDS?
>
 Not yet, only took some initial measurements on an eval board of
an I/O capable global clock pair in a FT256 package, which seemed
in line with a ~3 pF Cin.

 Note that many of those input only pins don't travel in pairs, and
they also lack the internal termination feature.

>
> I looked at the IBIS files (ver2.1) and didn't find the input only pins.
>
 I also haven't spotted any detail on those, or any limits for the
S3E diff_term range.

 BTW, if you check the S3A datasheet, they provide better numbers
for the DIFF_TERM range and spec them for usage at 3.3V VCCIO;
they've also gone to a top/bottom left/right split between the
"goes to eleven" drivers and the lightweight S3E versions.

Brian


Article: 113652
Subject: jtag reset seq
From: "gomsi" <gautamsharma24@gmail.com>
Date: 18 Dec 2006 23:13:20 -0800
Links: << >>  << T >>  << A >>
I have a simple doubt about resetting sequence of Tap state machine
One way of resetting TAP FSM is through trst signal. Making trst
1(along with TMS=1 for the time trst transitions from 0 to 1) resets
the state machine and it enter run-test-idle mode.

A other way is by asserting TMS=1 for five TCK.. But am not able to do
it this way.. Any clues where i may be going wrong? What should be the
value on other test signals at this time? Since in my case the TAP
remains in test-logic-reset state


Article: 113653
Subject: Re: jtag reset seq
From: "Jim Wu" <jimwu88NOOOSPAM@yahoo.com>
Date: 18 Dec 2006 23:30:02 -0800
Links: << >>  << T >>  << A >>
Not sure why you think the tap controller should be in run-test-idle
after reset. It should go to the reset state (well, ie
test-logic-reset).

HTH,
Jim
http://home.comcast.net/~jimwu88/tools/


gomsi wrote:
> I have a simple doubt about resetting sequence of Tap state machine
> One way of resetting TAP FSM is through trst signal. Making trst
> 1(along with TMS=1 for the time trst transitions from 0 to 1) resets
> the state machine and it enter run-test-idle mode.
>
> A other way is by asserting TMS=1 for five TCK.. But am not able to do
> it this way.. Any clues where i may be going wrong? What should be the
> value on other test signals at this time? Since in my case the TAP
> remains in test-logic-reset state


Article: 113654
Subject: Re: jtag reset seq
From: "gomsi" <gautamsharma24@gmail.com>
Date: 19 Dec 2006 00:59:30 -0800
Links: << >>  << T >>  << A >>
Actually following the normal logic of resetting the TAP using trst, if
after assetion of trst if TMS is low, it will come to run-test-idle
state.It is clearly visible from TAP state machine. It can remain in
test-logic-reset after reset from trst only if TMS is held high..


Jim Wu wrote:
> Not sure why you think the tap controller should be in run-test-idle
> after reset. It should go to the reset state (well, ie
> test-logic-reset).
>
> HTH,
> Jim
> http://home.comcast.net/~jimwu88/tools/
>
>
> gomsi wrote:
> > I have a simple doubt about resetting sequence of Tap state machine
> > One way of resetting TAP FSM is through trst signal. Making trst
> > 1(along with TMS=1 for the time trst transitions from 0 to 1) resets
> > the state machine and it enter run-test-idle mode.
> >
> > A other way is by asserting TMS=1 for five TCK.. But am not able to do
> > it this way.. Any clues where i may be going wrong? What should be the
> > value on other test signals at this time? Since in my case the TAP
> > remains in test-logic-reset state


Article: 113655
Subject: Re: solder mask for fpga dissipation
From: Al <alessandro.basili@cern.ch>
Date: Tue, 19 Dec 2006 09:59:33 +0100
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:
> John_H <newsgroup@johnhandwork.com> wrote:
> (snip on thermal conductivity of solder mask for PQFP packaging)
>  
> 
>>Isn't the thermal resistance of air (or vacuum, perhaps, for the CERN 
>>folks) that would be between the package and the board be greater than 
>>when filling the gap with solder mask?  There is a specific, designed 
>>gap between the PQFP package and the pins' mounting plane.  Any solder 
>>mask would help to fill that gap but there will still be a thermal gap.
> 
>  
> 
>>Only if there's a desire to fill the gap with a thermally conductive 
>>material should there be a concern about reduced thermal conductivity 
>>from solder mask.  Perhaps black soldermask would work well for radiated 
>>heat transfer?
> 
> 
> PC boards don't have that much conductivity, either.  Maybe a big
> metal pad would help, but that doesn't help get it out.  
> 
> How about a BeO solder mask?
> 
> -- glen

Hi everyone, I would like to thank you all for your suggestions and a 
need a bit of time to check them all carefully because I'm not an expert 
at all in this field. Anyway I think we have to fill the gap with some 
paste anyway because of the big temperature range of our system (working 
-25 + 55 C and -45 +85 for surviving!). If not I think we will have 
problems with dissipation (moreover we should check carefully at the 
paste, so that it will not have a big dilatation coefficient, otherwise 
it will be a problem as well!)
Luckily there's a pressurized container which will keep the electronics 
in a non-vacuum condition, so that we can still rely on conductivity.
They've told me that short-circuit may occour easily without solder 
mask, but I think the best way is to have it on the pads (of course) and 
then leave a margin to the "heat sink", which will be unmasked, like 2 
mm. In this case I will not have problems with short-circuits and I will 
maximize the heat dissipation.
I will go through your technical comments in some time. Thanks guys

Al


-- 
Alessandro Basili
CERN, PH/UGC
Hardware Designer

Article: 113656
Subject: Re: jtag reset seq
From: "Antti" <Antti.Lukats@xilant.com>
Date: 19 Dec 2006 01:49:41 -0800
Links: << >>  << T >>  << A >>
gomsi schrieb:

> Actually following the normal logic of resetting the TAP using trst, if
> after assetion of trst if TMS is low, it will come to run-test-idle
> state.It is clearly visible from TAP state machine. It can remain in
> test-logic-reset after reset from trst only if TMS is held high..
>
>

TAP will not transit to any state except on rising edge of TCK

1) if TRST is implemented then when asserted will go to TLR
2) if TRST is not implemented power up default should be TLR
3) if TRST not asserted or not implemented and TMS=1 during 5 TCK
rising edges then state will be TLR
4) transition to RTI will happen on first rising of TCK when TMS=0 and
TRST not asserted when state was TLR

if your TAP controller does something else it is not IEEE 1149.1
confirm.
.

Antti


Article: 113657
Subject: Operate on RAM through FPGA
From: zhongqiang.cheng@gmail.com
Date: 19 Dec 2006 02:05:01 -0800
Links: << >>  << T >>  << A >>
hi,

I've formulate my problem in this page. Perhaps can someone tell me,
what kind of typical error can made, when operating on RAM through
FPGA.

http://homepage.ruhr-uni-bochum.de/Qian.Tang-2/cheng/fpga_ram.htm

Someone can help me out!!!


Article: 113658
Subject: C2H problems
From: "Andreas F." <hse02009@fh-hagenberg.at>
Date: 19 Dec 2006 02:09:11 -0800
Links: << >>  << T >>  << A >>
Hi!

i've tried to implement an very simple example to evaluate C2H. i've
accelerated a function
named testalg. c2h compiles it, in the sopc builder everything is fine,
the quartus flow doesn't report any errors, nor the C2H Register build
log at Nios II IDE says anything. it looks everything fine, but
the result is always -1

here's the whole code


#include <stdio.h>

int testalg(int a, int b )
{
return a*a + b*b;
}


int main()
{
int sum = 0;
printf("sum before = %d\n",sum);
sum = testalg(5,5);
printf("sum after = %d\n",sum);
printf("should be 50\n");
return 0;
}

P.S. can i avoid the c2h compiler to restart the whole quartus flow,
when i just
change something in the software project, and not in the accelerated
function?


Thanks 4 reading
and it would be good, if someone can help me out

greetz Andreas


Article: 113659
Subject: Re: electrical level conversion
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 19 Dec 2006 10:53:20 -0000
Links: << >>  << T >>  << A >>
"Austin Lesea" <austin@xilinx.com> wrote in message 
news:em6o57$gg73@cnn.xsj.xilinx.com...
> Brian,
>
> OK, now I see it.  Spartan 3/3E/3A dropped HSTL IV, which is a 48 mA
> drive strength standard.  III is 24 mA.  That means the area required is
> cut in half, so the C could be half that of the Virtex series IOB's
> (that have HSTL IV).
>
> I wonder how many people need IV?
>
I would guess fewer than the number who would like the I/O performance 
doubled? :-) Congrats to the Spartan group!

There should be some way to disconnect unwanted output standards before 
assembly. Some system with fuses integrated on the FPGA in series with the 
FETs , a test fixture, a car battery and a big red button marked "Cpin 
enhance".

Cheers, Syms.

p.s. Like this (Fixed font!):-

   Fusable FET         Regular FET
      \
          |              |
        |-             |-
    ----|           ---|
        |-             |-
          |              |
          |              |
          -------fuse-----
            |            |
            |            |
Vfuse--|>|---            -----I/O Pad
          \
         Diode

Vfuse is an external pin grounded during normal operation. 



Article: 113660
Subject: Re: Announce: XDLAnalyze v1.1 and colorized_signals (for ModelSim) v1.1
From: "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com>
Date: 19 Dec 2006 03:39:29 -0800
Links: << >>  << T >>  << A >>

> ---------------------------------------------------------------------------
> xdlanalyze.pl:
>
>
> Shows statistics about an XDL file (or NCD file) as in the following
> example: (I'm not aware of any Xilinx command that will print this kind
> of (hierarchical) information about a place and routed design, please
> enlighten me if I've missed something.)

Interesting, I didn't find it either and write my own tool that does
exactly
the same thing, just a few weeks ago ;)


    Sylvain


Article: 113661
Subject: Integrating Atera =?UTF-8?B?4oCcRkZUIE1lZ2FDb3JlIEZ1bmN0aW9u4oCd?=
From: Friedrich Kiesel <friedrich_kiesel@web.de>
Date: Tue, 19 Dec 2006 13:26:30 +0100
Links: << >>  << T >>  << A >>
Hi,

I want to use the Atera “FFT MegaCore Function” in a Design created with 
Mentor FPGA Advantage 7.2.
Importing the created Files in HDL Designer is no Problem, but when I 
try to run Synthesis with the integrated Plugin “Quartus II Synthesis 
Flow” Quartus shows this Error:
Error (10481): VHDL Use Clause error at fft.vhd(35): design library 
"fft_lib" does not contain primary unit "fft_pack" File:
Z:/hds_scratch/FFT/hdl/fft.vhd Line: 35

I think the problem is that Quartus can’t find the library-files which 
belong to this MegaCore.
A direct in Quartus generated Design worked well. I found out, in 
difference to the direct generatet Project, the Quarts Project Files 
created by the HDL Designer Pulgin don’t contain “fft_pack.vhd” at 
“Device Design Files”.

Is it possible to add this per-compiled File to the HDL Designer that it 
is included by the Synthesis Plugin?

Article: 113662
Subject: Re: jtag reset seq
From: Dominic <Dominic.at.usenet@gmx.com>
Date: Tue, 19 Dec 2006 13:30:41 +0100
Links: << >>  << T >>  << A >>
Antti wrote:
> TAP will not transit to any state except on rising edge of TCK
I guess you meant "any state other than T-L-R, except...", as TRST is an
asynchronous reset. All other state transitions are of course synchronous
to the rising edge of TCK.

> if your TAP controller does something else it is not IEEE 1149.1 
> confirm. 
Unfortunately, most implementations are not really 1149.1 confirm, in one
way or another. Usually you can work around those problems though.

Regards,

Dominic

Article: 113663
Subject: Re: Frequency divider ?
From: <222>
Date: Tue, 19 Dec 2006 12:41:35 -0000
Links: << >>  << T >>  << A >>

"KJ" <kkjennings@sbcglobal.net> wrote in message
news:XRHhh.38396$qO4.9412@newssvr13.news.prodigy.net...
>
> <222> wrote in message news:45874059$1_1@mk-nntp-2.news.uk.tiscali.com...
> >
> > "KJ" <kkjennings@sbcglobal.net> wrote in message
> > news:s6Hhh.4519$yC5.3050@newssvr27.news.prodigy.net...
> >>
> >> <222> wrote in message
news:45873ba6$1_3@mk-nntp-2.news.uk.tiscali.com...
> >> >I feel it is better to start a new thread, I have compiled my
> >> > divide oscillator clock by ten module, what do I do now?
> >>
> >> Get out a simulator and see if it works.  Once you've done some of your
> > own
> >> work, perhaps ask for some help.
> >
> >
> > No, no need to simulate, I am ready for the real thing
> > Please contine (as opposed to 'break')
> >
>
> You have EVERY reason to simulate.. By trivial inspection I can tell that
> your design doesn't do anything at all.  You could start by pondering on
the
> warning messages out of the HDL Synthesis that 'warn' you that input 'in'
is
> never used and output 'out' is never assigned and try to figure out why
that

Why do you say that my input is never used, what about

always @ (in)  ?


> would be (Hint:  Input 'in' is never used BECAUSE output 'out' is never
> assigned and since 'out' is the only output this would imply that there is
> no need for any inputs).  Since no inputs or resources of any kind are
> needed to implement your code, eventually this leads to the fitting
> error....once again, perhaps read the error message that says that your
> module has no outputs.


What about

out = !out   is that not an assignment ?


>
> In any case, I'll repeat the suggestion to start to use a simulator and
> simulate your code.  There is not much point in running through the
> synthesis process until you have functioning code....and you can't say you
> have functioning code until it works at least in a simulation environment.


Please explain how to simulate, my device is xc9536 and the software is
Xilinx ISE 8.2i

Tia.


>
> KJ
>
>



Article: 113664
Subject: Re: Operate on RAM through FPGA
From: "Pablo" <pbantunez@gmail.com>
Date: 19 Dec 2006 05:01:24 -0800
Links: << >>  << T >>  << A >>

zhongqiang.cheng@gmail.com wrote:
> hi,
>
> I've formulate my problem in this page. Perhaps can someone tell me,
> what kind of typical error can made, when operating on RAM through
> FPGA.
>
> http://homepage.ruhr-uni-bochum.de/Qian.Tang-2/cheng/fpga_ram.htm
>
> Someone can help me out!!!

I am not a FPGA expert, but Why don't you use MIcroblaze?? I have a
design with a SDRAM, and I only need to define a pointer (in C), and
with it I can read/write on the memory.

I hope this can help you.


Article: 113665
Subject: Re: FPGA : Async FIFO, Programmable full
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Tue, 19 Dec 2006 08:04:03 -0500
Links: << >>  << T >>  << A >>
I wonder if I should be jealous... on one hand, you got to do one-man IC 
designs while on the other hand, the function alone is useless. All I 
will ever see on the ASIC side is my functions representing only a 
fraction of some 10M+ gates design.

Well, I suppose you probably envy younger designers for having access to 
programmable logic from the very start... but that's probably offset by 
the pride of having a hand in making FPGAs a reality for the rest of us :)

Peter Alfke wrote:
> For what it is worth:
> I designed the very first FIFO integrated circuit, the Fairchild 3341
> in 1969/70. It was very popular for a while. But Fairchild did not
> patent it.
> Peter Alfke
> 
> On Dec 18, 5:13 am, "Daniel S." <digitalmastrmind_no_s...@hotmail.com>
> wrote:
>> Peter Alfke wrote:
>>> Let's leave it at that. We won't agree, but then: we do not have to...To agree, there would need to be an argument to agree on in the first
>> place. Since I was only proposing an alternative way of going about
>> pointer data domain crossing, the only thing possibly worth arguing over
>> is whether or not the approach is valid... and since I have used this
>> approach in an ASIC project, I have reasonable proof that it is.
>>
>> Is it the best implementation? That answer is application-specific.

Article: 113666
Subject: Re: jtag reset seq
From: "gomsi" <gautamsharma24@gmail.com>
Date: 19 Dec 2006 05:06:04 -0800
Links: << >>  << T >>  << A >>
thanks for the replies..
But As stated by you TAP is working fine.. Since i just wanted to
bypass any effect of TRST on TAP. I followed two ways to bypass trst:
1. Ties TRST to 1 from zero simulation time and then after the power on
of the design i made TMS = 1 for 5 positive edges of TCK. The TAP
does'nt enter RTI.
2. I tried with TRST to 0 from zero simulation, the same logic as
stated earlier, but with the same results..
In both the cases the state machine remains in TLR state throughout the
simulations, irrespective of any stimulus on TMS or TCK

Anyways if the following sequence if followed
(a)  TRST remains low.
(b) TMS is made one and TCK is applied.
(c) TMS remains 1 for 3 TCK
(d) After 3 TCK, TRST is made 1 and TMS made 0.
(e) This sets the TAP in RTI mode and then it works fine..

I was only thinking the other way round i.e. to bypass TRST to get into
RTI from TLR.. And if suggestions are there for that... please guide


Dominic wrote:
> Antti wrote:
> > TAP will not transit to any state except on rising edge of TCK
> I guess you meant "any state other than T-L-R, except...", as TRST is an
> asynchronous reset. All other state transitions are of course synchronous
> to the rising edge of TCK.
>
> > if your TAP controller does something else it is not IEEE 1149.1
> > confirm.
> Unfortunately, most implementations are not really 1149.1 confirm, in one
> way or another. Usually you can work around those problems though.
> 
> Regards,
> 
> Dominic


Article: 113667
Subject: Re: unexplainable Problem on Spartan 3
From: "rickman" <gnuarm@gmail.com>
Date: 19 Dec 2006 05:11:23 -0800
Links: << >>  << T >>  << A >>
You might try a different approach.  You say you have verified all the
pieces separately.  If so, you know the code segments are written
correctly.  This means the problem is in how you have them connected or
how you combined them.  So try it in small steps.  Simplify to your LED
flasher alone.  Make sure that works on the chip.  Then combine the LED
flasher with one other module that you can test.  Make sure the LED
flasher works and then verify the other module.  Next add another
module and test.  You can do this serially or you can do a binary
search by splitting the group of modules in half and testing the two
halves separately.  If one works and the other does not, you can
procede to split the non-working group in two.  But if your problem has
to do with how you are combining the modules it is likely that none of
the groups will work.

I seriously doubt that you will get anyone to test your code for you.
It will go much faster if you learn debugging techniques yourself.  You
might be surprised at how simple it can be to find problems.  A lot of
times the hard part is realizing that it is realy very simple even if
it is a lot of work.


thomas.neitzel@gmail.com wrote:
> Greetings to all !
>
> I started programming with VHDL two months ago. Now I want to implement
> a project on a Spartan 3 (XC3S50 VQ100). The software I=B4m using is the
> ISE Webpack 8.2.03i (Application Version: I.34).


Article: 113668
Subject: Re: Frequency divider ?
From: Andreas Ehliar <ehliar@isy.liu.se>
Date: Tue, 19 Dec 2006 13:11:30 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2006-12-19, <222> <222> wrote:
> Why do you say that my input is never used, what about
>
> always @ (in)  ?

If I run your design through leda (a linter for VHDL and
Verilog) I get the following two warnings:

* Signal cnt is missing in the sensitivity list
* An asynchronous feedback loop was detected on cnt.

What it boils down to is that if you have an @() statement
with only signals in it (no posedge or negedge) the synthesizer
will infer combinatorial logic from it. And the synthesizer will
not care about the sensitivity list at all basically. (It will
handle it like you wrote always @* in Verilog 2001 more or
less.)

If you want something to synthesize, restrict yourself to
always @(*) and always @(posedge clocksignal).

If you want an asynchronous reset you can also use something like
always @(posedge clocksignal or posedge resetsignal).

(Or negedge as appropriate.)

Otherwise you will most likely get a design that will not
work in the same way as your simulation.


/Andreas

Article: 113669
Subject: Re: jtag reset seq
From: "Antti" <Antti.Lukats@xilant.com>
Date: 19 Dec 2006 05:30:30 -0800
Links: << >>  << T >>  << A >>
gomsi schrieb:

> thanks for the replies..
> But As stated by you TAP is working fine.. Since i just wanted to
> bypass any effect of TRST on TAP. I followed two ways to bypass trst:
> 1. Ties TRST to 1 from zero simulation time and then after the power on
> of the design i made TMS = 1 for 5 positive edges of TCK. The TAP
> does'nt enter RTI.

OF COURSE it does not enter RTI when shift in TMS=1

when you clock 5 times TMS=1 then the TAP enter TLR not RTI !!

Antti


Article: 113670
Subject: Re: Frequency divider ?
From: <222>
Date: Tue, 19 Dec 2006 13:46:11 -0000
Links: << >>  << T >>  << A >>

"Andreas Ehliar" <ehliar@isy.liu.se> wrote in message
news:em8oe2$2j0$1@news.lysator.liu.se...
> On 2006-12-19, <222> <222> wrote:
> > Why do you say that my input is never used, what about
> >
> > always @ (in)  ?
>
> If I run your design through leda (a linter for VHDL and
> Verilog) I get the following two warnings:
>
> * Signal cnt is missing in the sensitivity list

What is a sensitivity list, please add it as appropriate so that
I can recompile the program.


> * An asynchronous feedback loop was detected on cnt.

Please, can you correct the feedback, I have no idea where
this feedback is coming from, thanks.


>
> What it boils down to is that if you have an @() statement
> with only signals in it (no posedge or negedge) the synthesizer
> will infer combinatorial logic from it. And the synthesizer will
> not care about the sensitivity list at all basically. (It will

There currently is no sensitivity list, hence I assume combinational
logic is what we want.


> handle it like you wrote always @* in Verilog 2001 more or
> less.)
>
> If you want something to synthesize, restrict yourself to
> always @(*) and always @(posedge clocksignal).
>
> If you want an asynchronous reset you can also use something like
> always @(posedge clocksignal or posedge resetsignal).
>
> (Or negedge as appropriate.)
>
> Otherwise you will most likely get a design that will not
> work in the same way as your simulation.
>
>
> /Andreas



Article: 113671
Subject: Re: electrical level conversion
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 19 Dec 2006 14:12:17 -0000
Links: << >>  << T >>  << A >>
"Brian Davis" <brimdavis@aol.com> wrote in message 
news:1166502377.044055.250990@a3g2000cwd.googlegroups.com...
>
> I also haven't spotted any detail on those, or any limits for the
> S3E diff_term range.
>
> BTW, if you check the S3A datasheet, they provide better numbers
> for the DIFF_TERM range and spec them for usage at 3.3V VCCIO;
> they've also gone to a top/bottom left/right split between the
> "goes to eleven" drivers and the lightweight S3E versions.
>
> Brian
>
That's a bit more like it for documentation.
Thanks for the pointer! Syms. 



Article: 113672
Subject: Re: C2H problems
From: "Subroto Datta" <sdatta@altera.com>
Date: Tue, 19 Dec 2006 06:29:03 -0800
Links: << >>  << T >>  << A >>
Hi Andreas,

  While I will forward this to the relevant engineer, your chances of 
obtaining help for Nios related problems will be better if you post at 
www.niosforum.org. The niosforum board is monitored by a power users and 
Altera engineers who work with Nios/C2H and SOPC Builder. Please post which 
version of the Nios II IDE is being used.

Hope this helps,
Subroto Datta
Altera Corp.

"Andreas F." <hse02009@fh-hagenberg.at> wrote in message 
news:1166522951.888604.290600@80g2000cwy.googlegroups.com...
> Hi!
>
> i've tried to implement an very simple example to evaluate C2H. i've
> accelerated a function
> named testalg. c2h compiles it, in the sopc builder everything is fine,
> the quartus flow doesn't report any errors, nor the C2H Register build
> log at Nios II IDE says anything. it looks everything fine, but
> the result is always -1
>
> here's the whole code
>
>
> #include <stdio.h>
>
> int testalg(int a, int b )
> {
> return a*a + b*b;
> }
>
>
> int main()
> {
> int sum = 0;
> printf("sum before = %d\n",sum);
> sum = testalg(5,5);
> printf("sum after = %d\n",sum);
> printf("should be 50\n");
> return 0;
> }
>
> P.S. can i avoid the c2h compiler to restart the whole quartus flow,
> when i just
> change something in the software project, and not in the accelerated
> function?
>
>
> Thanks 4 reading
> and it would be good, if someone can help me out
>
> greetz Andreas
> 



Article: 113673
Subject: Xilinx Quiz: 150/3 = ?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 19 Dec 2006 06:38:31 -0800
Links: << >>  << T >>  << A >>
Quiz:

what is DCM CLKFX output frequncy if the CLKFX Divisor is set to 3 in
MHS file and input clock is 150MHz?

snippet from MHS file
--------------------
BEGIN dcm_module
 PARAMETER C_CLKFX_DIVIDE = 3
...
END
--------------------


Answer:

DCM FX output will be 200MHz because the CLKFX multiply default value
is 4 ! When the FX multiply is set to default then the multiply
parameter is not present in the MHS file, and without knowing the
default or using the GUI to view the parameters its really hard to
guess.
unless you just know.

Antti


Article: 113674
Subject: Re: C2H problems
From: "Karl" <karl@chello.nl>
Date: 19 Dec 2006 06:52:53 -0800
Links: << >>  << T >>  << A >>

> > P.S. can i avoid the c2h compiler to restart the whole quartus flow,
> > when i just
> > change something in the software project, and not in the accelerated
> > function?

Hi Andreas,

In the C2H window you can select "Analyse all accelerators" to just get
the report on the C2H acceleration, without generating all the HDL,
SOPC Builder output and sof file.

With the "Use existing accelerators" you keep the current HW build and
just compile the SW.

Greats, Karl.




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