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Threads Starting Dec 2002

50090: 02/12/01: zhengyu: CAM tutorial
    50124: 02/12/02: Assaf Sarfati: Re: CAM tutorial
50091: 02/12/01: zhengyu: string to int conversion
    50095: 02/12/02: glen herrmannsfeldt: Re: string to int conversion
    50106: 02/12/02: Mike Treseler: Re: string to int conversion
    50108: 02/12/02: Steve Casselman: Re: string to int conversion
    50121: 02/12/02: Jay: Re: string to int conversion
50094: 02/12/02: Kim Noer: WARNING:Xst:646 - Signal <vcc> is assigned but never used ? (ISE 4.2wp2)
    50096: 02/12/02: Bill Turnip: Re: WARNING:Xst:646 - Signal <vcc> is assigned but never used ? (ISE 4.2wp2)
        50098: 02/12/02: Kim Noer: Re: WARNING:Xst:646 - Signal <vcc> is assigned but never used ? (ISE 4.2wp2)
50097: 02/12/02: walala: anybody used synopsys pathmill give me a hand please
50100: 02/12/02: Muthu: MetaStability Issue on BRAMs
    50111: 02/12/02: Peter Alfke: Re: MetaStability Issue on BRAMs
    50115: 02/12/02: andyman: Re: MetaStability Issue on BRAMs
50107: 02/12/02: Jon Elson: ESD problems
    50112: 02/12/03: Jim Granville: Re: ESD problems
        50158: 02/12/03: Jon Elson: Re: ESD problems
            50166: 02/12/04: Jim Granville: Re: ESD problems
    50156: 02/12/04: Gregory C. Read: Re: ESD problems
        50196: 02/12/05: Jim Granville: Re: ESD problems
            50198: 02/12/04: Jon Elson: Re: ESD problems
        50197: 02/12/04: Jon Elson: Re: ESD problems
50109: 02/12/02: Anand: question about series termination resistors and VIAS
    50110: 02/12/02: John_H: Re: question about series termination resistors and VIAS
    50122: 02/12/03: Thomas Rudloff: Re: question about series termination resistors and VIAS
50114: 02/12/02: siriuswmx: register OR latch ?
    50125: 02/12/03: Markus Sponsel: Re: register OR latch ?
        50161: 02/12/03: siriuswmx: Re: register OR latch ?
    50136: 02/12/03: Muthu: Re: register OR latch ?
        50160: 02/12/03: siriuswmx: Re: register OR latch ?
        50163: 02/12/03: siriuswmx: Re: register OR latch ?
50116: 02/12/02: siriuswmx: register OR latch ? (source code)
    50129: 02/12/03: Matjaz Finc: Re: register OR latch ? (source code)
    50164: 02/12/03: Jim Lewis: Re: register OR latch ? (source code)
    50120: 02/12/03: Bill Turnip: Re: Modelsim:Too few port connections
50123: 02/12/02: longjin: block and distributed RAM
    50126: 02/12/03: Peng Cong: Re: block and distributed RAM
    50149: 02/12/03: John_H: Re: block and distributed RAM
        50150: 02/12/03: Peter Alfke: Re: block and distributed RAM
            50159: 02/12/03: longjin: Re: block and distributed RAM
50131: 02/12/03: Thomas Buerner: ISA bus VGA
    50134: 02/12/03: Laurent Gauch: Re: ISA bus VGA
    50141: 02/12/03: rickman: Re: ISA bus VGA
        50173: 02/12/04: Symon: Re: ISA bus VGA
            50179: 02/12/04: Thomas Buerner: Re: ISA bus VGA
                50182: 02/12/04: Pat Ford: Re: ISA bus VGA
                50189: 02/12/04: emanuel stiebler: Re: ISA bus VGA
                50190: 02/12/04: Iwo Mergler: Re: ISA bus VGA
    50148: 02/12/04: Jim Granville: Re: ISA bus VGA
    50191: 02/12/04: Jay: Re: ISA bus VGA
    50195: 02/12/04: eric - Mtl: Re: ISA bus VGA
        50207: 02/12/05: Ralph Mason: Re: ISA bus VGA
            50227: 02/12/05: eric - Mtl: Re: ISA bus VGA
                50393: 02/12/10: Thomas Buerner: Re: ISA bus VGA
                    50396: 02/12/10: Uwe Bonnes: Re: ISA bus VGA
                    50423: 02/12/10: rickman: Re: ISA bus VGA
                        50438: 02/12/10: Ray Andraka: Re: ISA bus VGA
                            50446: 02/12/10: Eric Smith: Re: ISA bus VGA
                    50619: 02/12/14: Rob Finch: Re: ISA bus VGA
50132: 02/12/03: Rosaria: Leonardo and Clock Buffer
    50169: 02/12/04: Nachiket Kapre: Re: Leonardo and Clock Buffer
50133: 02/12/03: Kim Noer: ISE Impact 4.2 and Windows XP parallel port - works then it doesn't?
    50171: 02/12/04: Nachiket Kapre: Re: ISE Impact 4.2 and Windows XP parallel port - works then it doesn't?
50135: 02/12/03: Muthu: Parameterising the Core-gen Macro.....!!!
50139: 02/12/03: Cristian: PROM for XC2S300
    50146: 02/12/03: MM: Re: PROM for XC2S300
        50170: 02/12/04: Nachiket Kapre: Re: PROM for XC2S300
            50175: 02/12/04: Mark McMahon: Re: PROM for XC2S300
50142: 02/12/03: <bwickman@QUACKQUACKSPAMumich.edu>: Clock fan-out and other issues
    50193: 02/12/04: Jay: Re: Clock fan-out and other issues
        50223: 02/12/05: <bwickman@quackspamumich.edu>: Re: Clock fan-out and other issues
50147: 02/12/03: E. Napoli: free software for XC4000
    50153: 02/12/03: Kevin Brace: Re: free software for XC4000
        50154: 02/12/03: Larry Doolittle: Re: free software for XC4000
            50162: 02/12/03: Kevin Brace: Re: free software for XC4000
                50270: 02/12/07: Stephen Williams: Re: free software for XC4000
50151: 02/12/03: Christof Paar: CHES 2003 - 1st CFP
50152: 02/12/03: Francisco Rodriguez: Weird problem with RPM
    50185: 02/12/04: Chen Wei Tseng: Re: Weird problem with RPM
        50259: 02/12/06: Francisco Rodriguez: Re: Weird problem with RPM
    50165: 02/12/03: TC: Re: Low Speed Serial Bus Suggestions
    50177: 02/12/04: M. Randelzhofer: Re: Low Speed Serial Bus Suggestions
50167: 02/12/04: fizz: Where can i find a Harddisk behavior module, and a ATAPI CD-ROM behavior behavior module in Verilog?
50174: 02/12/04: Talal: Full-Page in SDRAM
    50186: 02/12/04: Andreas Schweizer: Re: Full-Page in SDRAM
    50192: 02/12/04: Jay: Re: Full-Page in SDRAM
        50255: 02/12/06: Jay: Re: Full-Page in SDRAM
50176: 02/12/04: Uwe Bonnes: [POLL] What JTAG/Configuration connector to use
50178: 02/12/04: Wolfgang Brandt: Modelsim
50180: 02/12/04: Markus Meng: HowTo 'freeze' a placement
    50184: 02/12/04: Chen Wei Tseng: Re: HowTo 'freeze' a placement
        50217: 02/12/05: Muthu: Re: HowTo 'freeze' a placement
            50221: 02/12/05: Chen Wei Tseng: Re: HowTo 'freeze' a placement
                50242: 02/12/06: Muthu: Re: HowTo 'freeze' a placement
                    50246: 02/12/06: Chen Wei Tseng: Re: HowTo 'freeze' a placement
                        50254: 02/12/06: Ryan Laity: Re: HowTo 'freeze' a placement
                        50277: 02/12/07: Muthu: Re: HowTo 'freeze' a placement
                            50344: 02/12/09: Chen Wei Tseng: Re: HowTo 'freeze' a placement
    50249: 02/12/06: Pierre-Olivier Laprise: Re: HowTo 'freeze' a placement
    50263: 02/12/06: Chen Wei Tseng: Re: HowTo 'freeze' a placement
50181: 02/12/04: Tom: Digital filter
    50340: 02/12/09: Ken Chapman: Re: Digital filter
50183: 02/12/04: Matjaz Finc: Altera Nios pipeline
50194: 02/12/04: Kolin Paul: FPGA Actual Power Measurement
    50199: 02/12/04: Jon Elson: Re: FPGA Actual Power Measurement
        50211: 02/12/04: Muthu: Re: FPGA Actual Power Measurement
            50213: 02/12/05: Hal Murray: Re: FPGA Actual Power Measurement
        50233: 02/12/05: Kolin Paul: Re: FPGA Actual Power Measurement
            50234: 02/12/06: Hal Murray: Re: FPGA Actual Power Measurement
                50236: 02/12/05: Kolin Paul: Re: FPGA Actual Power Measurement
                    50237: 02/12/06: Hal Murray: Re: FPGA Actual Power Measurement
    50314: 02/12/08: Pete Dudley: Re: FPGA Actual Power Measurement
50205: 02/12/04: Chip: 285MHz multipliers
    50252: 02/12/06: David Hawke: Re: 285MHz multipliers
50208: 02/12/04: siriuswmx: Can QUARTUS open *.vec file?
    50240: 02/12/06: Subroto Datta: Re: Can QUARTUS open *.vec file?
50215: 02/12/05: Stephan Eichler: Communication between DSP and FPGA
50216: 02/12/05: Pinco Pallino: external ACEX DMA controller interfacing to a StrongArm prob.
50219: 02/12/05: Anand: series termination question
    50230: 02/12/05: Mike Treseler: Re: series termination question
        50232: 02/12/05: Peter Alfke: Re: series termination question
    50231: 02/12/05: Hal Murray: Re: series termination question
        50258: 02/12/06: Anand: Re: series termination question
            50261: 02/12/06: John_H: Re: series termination question
            50267: 02/12/07: Hal Murray: Re: series termination question
50225: 02/12/05: Aroen (nospam): Looking for older version Xilinx Foundation
50226: 02/12/05: Dimitris Theodoropoulos: memory in VHDL
    50280: 02/12/07: Uncle Noah: Re: memory in VHDL
    50291: 02/12/07: John Retta: Re: memory in VHDL
        50295: 02/12/08: Ray Andraka: Re: memory in VHDL
    50229: 02/12/05: Steve Casselman: Re: meaning of system gates vs. logic gates?
        50241: 02/12/06: glen herrmannsfeldt: Re: meaning of system gates vs. logic gates?
            50244: 02/12/06: Uwe Bonnes: Re: meaning of system gates vs. logic gates?
                50260: 02/12/06: glen herrmannsfeldt: Re: meaning of system gates vs. logic gates?
        50256: 02/12/06: Jay: Re: meaning of system gates vs. logic gates?
        51058: 02/12/29: Steve: Re: meaning of system gates vs. logic gates?
    50235: 02/12/06: Ray Andraka: Re: meaning of system gates vs. logic gates?
        50238: 02/12/06: Tim: Re: meaning of system gates vs. logic gates?
            50250: 02/12/06: Peter Alfke: Re: meaning of system gates vs. logic gates?
            50279: 02/12/07: Rick Filipkiewicz: Re: meaning of system gates vs. logic gates?
    50245: 02/12/06: Uwe Bonnes: Re: map error:FATAL_ERROR:MapLib:basmmngm.c
50243: 02/12/06: Magnus Jacobsson: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
    50248: 02/12/06: Austin Lesea: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
        50253: 02/12/06: Magnus Jacobsson: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
            50552: 02/12/12: Kate Kelley: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
                50635: 02/12/15: <hamish@cloud.net.au>: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
                    51141: 03/01/03: Kate Kelley: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
50247: 02/12/06: Aroen (nospam): Looking for older version Xilinx Foundation
50257: 02/12/06: Prashant: Hold time violation
    50307: 02/12/08: Pete Dudley: Re: Hold time violation
50264: 02/12/06: Jamie Morken: Clocking in a Spartan IIE
    50265: 02/12/07: Hal Murray: Re: Clocking in a Spartan IIE
        50276: 02/12/07: Igor Orlovich: Re: Clocking in a Spartan IIE
            50318: 02/12/08: Clyde R. Shappee: Re: Clocking in a Spartan IIE
    50266: 02/12/07: Sylvain Yon: Re: Clocking in a Spartan IIE
        50268: 02/12/07: Jamie Morken: Re: Clocking in a Spartan IIE
            50273: 02/12/07: Sylvain Yon: Re: Clocking in a Spartan IIE
                50312: 02/12/08: Jamie Morken: Re: Clocking in a Spartan IIE
                    50347: 02/12/09: Sylvain Yon: Re: Clocking in a Spartan IIE
                        50361: 02/12/09: Jamie Morken: Re: Clocking in a Spartan IIE
                            50365: 02/12/10: Hal Murray: Re: Clocking in a Spartan IIE
                                50380: 02/12/10: rickman: Re: Clocking in a Spartan IIE
                                    50406: 02/12/10: Ray Andraka: Re: Clocking in a Spartan IIE
                                        50424: 02/12/10: rickman: Re: Clocking in a Spartan IIE
                                            50428: 02/12/10: Larry Doolittle: Re: Clocking in a Spartan IIE
                                            50433: 02/12/10: Ray Andraka: Re: Clocking in a Spartan IIE
                                    50445: 02/12/11: Sylvain Yon: Re: Clocking in a Spartan IIE
    50269: 02/12/07: Ray Andraka: Re: Clocking in a Spartan IIE
        50271: 02/12/07: Ray Andraka: Re: Clocking in a Spartan IIE
        50275: 02/12/07: Hal Murray: Re: Clocking in a Spartan IIE
        50289: 02/12/07: Jamie Morken: Re: Clocking in a Spartan IIE
            50297: 02/12/08: Falk Brunner: Re: Clocking in a Spartan IIE
50272: 02/12/06: John: CPLD current measurement
    50274: 02/12/07: Thomas Rudloff: Re: CPLD current measurement
        50284: 02/12/07: Klaus Vestergaard Kragelund: Re: CPLD current measurement
    50412: 02/12/10: John Hubbard: Re: CPLD current measurement
50278: 02/12/07: Kevin Yeoh: Warnings in FPGA express
    50283: 02/12/07: Spam Hater: Re: Warnings in FPGA express
        50330: 02/12/09: Martin Thompson: Re: Warnings in FPGA express
            50373: 02/12/10: Spam Hater: Re: Warnings in FPGA express
                50386: 02/12/10: Martin Thompson: Re: Warnings in FPGA express
    50286: 02/12/07: Jim Lewis: Re: Warnings in FPGA express
        50292: 02/12/08: Spam Hater: Re: Warnings in FPGA express
    50302: 02/12/08: Steve Casselman: Re: FPGA Downloader
50285: 02/12/07: valentin tihomirov: and vs. nand
    50287: 02/12/07: Mike Treseler: Re: and vs. nand
    50294: 02/12/08: valentin tihomirov: Re: and vs. nand
        50296: 02/12/08: Falk Brunner: Re: and vs. nand
50288: 02/12/07: Jingjing (Amy) Hu: Virtex archtecture question
    50290: 02/12/07: Nicholas C. Weaver: Re: Virtex archtecture question
        50300: 02/12/08: Kuan Zhou: Re: Virtex archtecture question
            50301: 02/12/08: Nicholas C. Weaver: Re: Virtex archtecture question
                50304: 02/12/08: Kuan Zhou: Re: Virtex archtecture question
                    50308: 02/12/08: Ray Andraka: Re: Virtex archtecture question
                        50309: 02/12/08: Kuan Zhou: Re: Virtex archtecture question
                            50313: 02/12/08: Nicholas C. Weaver: Re: Virtex archtecture question
    50303: 02/12/08: John_H: Re: Virtex archtecture question
50293: 02/12/07: siriuswmx: How to assign pins in VHDL?
    50298: 02/12/08: Falk Brunner: Re: How to assign pins in VHDL?
    50310: 02/12/08: Laurent Gauch, Amontec: Re: How to assign pins in VHDL?
        50351: 02/12/09: Mike Treseler: Re: How to assign pins in VHDL?
            50366: 02/12/10: Hal Murray: Re: How to assign pins in VHDL?
                50367: 02/12/10: Ray Andraka: Re: How to assign pins in VHDL?
                    50369: 02/12/10: Hal Murray: Re: How to assign pins in VHDL?
                        50374: 02/12/10: Ray Andraka: Re: How to assign pins in VHDL?
                        50376: 02/12/10: Spam Hater: Re: How to assign pins in VHDL?
                        50387: 02/12/10: Martin Thompson: Re: How to assign pins in VHDL?
                50400: 02/12/10: Phil Hays: Re: How to assign pins in VHDL?
                    50408: 02/12/10: Ray Andraka: Re: How to assign pins in VHDL?
            50385: 02/12/10: Holger Veit: Re: How to assign pins in VHDL?
    50333: 02/12/09: Frederic Bastenaire: Re: How to assign pins in VHDL?
        50372: 02/12/09: siriuswmx: Re: How to assign pins in VHDL?
            50375: 02/12/10: Ray Andraka: Re: How to assign pins in VHDL?
50299: 02/12/08: Nahum Barnea: XIL_PAR_SKIPAUTOCLOCKPLACEMENT question
50305: 02/12/08: transformer: vlsi implementation of multipliers
    50321: 02/12/09: Sanjay Patil: Re: vlsi implementation of multipliers
        50322: 02/12/09: Kevin Yeoh: Re: vlsi implementation of multipliers
            50338: 02/12/09: transformer: Re: vlsi implementation of multipliers
                50364: 02/12/09: del cecchi: Re: vlsi implementation of multipliers
                    50382: 02/12/09: john jakson: Re: vlsi implementation of multipliers
                        50452: 02/12/10: del cecchi: Re: vlsi implementation of multipliers
    50416: 02/12/10: Prashant: Re: vlsi implementation of multipliers
        50531: 02/12/12: transformer: Re: vlsi implementation of multipliers
            50548: 02/12/12: Prashant: Re: vlsi implementation of multipliers
50306: 02/12/08: Pete Dudley: virtex 2 temperture sensing with max1617a on DXN and DXP
    50325: 02/12/09: Allan Herriman: Re: virtex 2 temperture sensing with max1617a on DXN and DXP
50311: 02/12/08: Jamie Morken: Using DLL's
50315: 02/12/09: Hal Murray: FPGA/PCI on low budget
    50327: 02/12/09: Rene Tschaggelar: Re: FPGA/PCI on low budget
        50331: 02/12/09: Hal Murray: Re: FPGA/PCI on low budget
    50329: 02/12/09: Laurent Gauch, Amontec: Re: FPGA/PCI on low budget
    50337: 02/12/09: Uwe Bonnes: Re: FPGA/PCI on low budget
        50360: 02/12/09: Stephen Williams: Re: FPGA/PCI on low budget
            50496: 02/12/11: Austin Franklin: Re: FPGA/PCI on low budget
    50339: 02/12/09: Paul Taylor: Re: FPGA/PCI on low budget
    50345: 02/12/09: Austin Franklin: Re: FPGA/PCI on low budget
        50357: 02/12/09: Eric Smith: Re: FPGA/PCI on low budget
    50363: 02/12/09: Steen Larsen: Re: FPGA/PCI on low budget
    50368: 02/12/10: Hal Murray: Re: FPGA/PCI on low budget
        50377: 02/12/10: Ray Andraka: Re: FPGA/PCI on low budget
            50459: 02/12/11: Hal Murray: Re: FPGA/PCI on low budget
            50472: 02/12/11: Austin Franklin: Re: FPGA/PCI on low budget
                50504: 02/12/11: Ray Andraka: Re: FPGA/PCI on low budget
                    50525: 02/12/11: Austin Franklin: Re: FPGA/PCI on low budget
        50390: 02/12/10: Kevin Brace: Re: FPGA/PCI on low budget
        50494: 02/12/11: Austin Franklin: Re: FPGA/PCI on low budget
            50534: 02/12/12: Hal Murray: Re: FPGA/PCI on low budget
            50593: 02/12/13: Wayne Fisher: Re: FPGA/PCI on low budget
    50388: 02/12/10: Kevin Brace: Re: FPGA/PCI on low budget
        50409: 02/12/10: Ray Andraka: Re: FPGA/PCI on low budget
            50437: 02/12/10: Kevin Brace: Re: FPGA/PCI on low budget
                50440: 02/12/10: Ray Andraka: Re: FPGA/PCI on low budget
                50453: 02/12/11: Pete Ormsby: Re: FPGA/PCI on low budget
        50426: 02/12/10: Kolja Sulimma: Re: FPGA/PCI on low budget
    50526: 02/12/11: Brian Davis: Re: FPGA/PCI on low budget
    50528: 02/12/11: Brian Davis: Re: FPGA/PCI on low budget
50316: 02/12/09: Steve: LFSR question
    50320: 02/12/08: Mike Treseler: Re: LFSR question
        50324: 02/12/09: Allan Herriman: Re: LFSR question
50317: 02/12/08: Clyde R. Shappee: Pierce Crystal Oscillator in Cypress 37128 CPLD
    50323: 02/12/09: Ray Andraka: Re: Pierce Crystal Oscillator in Cypress 37128 CPLD
    50326: 02/12/09: Jim Granville: Re: Pierce Crystal Oscillator in Cypress 37128 CPLD
        50451: 02/12/10: Clyde R. Shappee: Re: Pierce Crystal Oscillator in Cypress 37128 CPLD
50319: 02/12/08: Tom Hawkins: Synthesis and Design Hierarchy
    50350: 02/12/09: Mike Treseler: Re: Synthesis and Design Hierarchy
    50415: 02/12/10: Ken McElvain: Re: Synthesis and Design Hierarchy
50328: 02/12/09: Steve T Shannon: clock recovery suggestions
    50332: 02/12/09: Hal Murray: Re: clock recovery suggestions
        50341: 02/12/09: Steve T Shannon: Re: clock recovery suggestions
            50349: 02/12/09: Ray Andraka: Re: clock recovery suggestions
            50355: 02/12/09: Mike Mitchener: Re: clock recovery suggestions
            50371: 02/12/10: Hal Murray: Re: clock recovery suggestions
50334: 02/12/09: Saurabh Pal: problem in Handel-C
    50342: 02/12/09: Richard Crewe: Re: problem in Handel-C
        50389: 02/12/10: Saurabh Pal: Re: problem in Handel-C
            50413: 02/12/10: Richard Crewe: Re: problem in Handel-C
50335: 02/12/09: Martin Schoeberl: Ann.: Ethernet, IO expansion for protoyping board
50336: 02/12/09: Matthias Dyer: virtex output pin voltage
    50343: 02/12/09: Austin Lesea: Re: virtex output pin voltage
        50353: 02/12/09: Marc Randolph: Re: virtex output pin voltage
            50354: 02/12/09: Austin Lesea: Re: virtex output pin voltage
50346: 02/12/09: Markus Meng: [Spartan-IIE] Additional DLL input pins
    50419: 02/12/10: Marc Baker: Re: [Spartan-IIE] Additional DLL input pins
50348: 02/12/09: Nahum Barnea: Xilinx DCM status bits
    50379: 02/12/09: Vikram: Re: Xilinx DCM status bits
50356: 02/12/09: Theron Hicks: question about fft vs. cross corelation in fpga
    50359: 02/12/09: Paul Baxter: Re: question about fft vs. cross corelation in fpga
        50449: 02/12/10: Jay: Re: question about fft vs. cross corelation in fpga
            50479: 02/12/11: Pete Fraser: Re: question about fft vs. cross corelation in fpga
                50523: 02/12/11: Keith: Re: question about fft vs. cross corelation in fpga
                50524: 02/12/12: John_H: Re: question about fft vs. cross corelation in fpga
50358: 02/12/09: Rene Tschaggelar: ByteblasterMV on Quartus2
    50362: 02/12/09: Rene Tschaggelar: Re: ByteblasterMV on Quartus2
50370: 02/12/10: Ralph Mason: Tiny Forth Processors
    50378: 02/12/09: Jan Gray: Re: Tiny Forth Processors
    50381: 02/12/10: rickman: Re: Tiny Forth Processors
        50394: 02/12/10: Roelf Toxopeus: Re: Tiny Forth Processors
            50398: 02/12/10: Bernd Paysan: Re: Tiny Forth Processors
                50399: 02/12/10: Uwe Bonnes: Re: Tiny Forth Processors
                    50403: 02/12/10: Martin Schoeberl: Re: Tiny Forth Processors
                        50422: 02/12/10: rickman: Re: Tiny Forth Processors
                            50429: 02/12/10: Uwe Bonnes: Re: Tiny Forth Processors
                50401: 02/12/10: Thomas Womack: Re: Tiny Forth Processors
                    50404: 02/12/10: Martin Schoeberl: Re: Tiny Forth Processors
                50432: 02/12/10: Mark Sandford: Re: Tiny Forth Processors
    50384: 02/12/10: Martin Schoeberl: Re: Tiny Forth Processors
        50414: 02/12/10: William Tanksley Google: Re: Tiny Forth Processors
            50421: 02/12/11: Ralph Mason: Re: Tiny Forth Processors
                50434: 02/12/10: Kip Ingram: Re: Tiny Forth Processors
                    50436: 02/12/10: Martin Schoeberl: Re: Tiny Forth Processors
                50460: 02/12/11: Hal Murray: Re: Tiny Forth Processors
                    50461: 02/12/11: Tim: Re: Tiny Forth Processors
                        50500: 02/12/11: rickman: Re: Tiny Forth Processors
                            50519: 02/12/12: Tim: Re: Tiny Forth Processors
                                50675: 02/12/16: Garry Allen: Re: Tiny Forth Processors
                                    50679: 02/12/17: rickman: Re: Tiny Forth Processors
                                        50701: 02/12/17: Garry Allen: Re: Tiny Forth Processors
                    50484: 02/12/11: William Tanksley Google: Re: Tiny Forth Processors
                50482: 02/12/11: William Tanksley Google: Re: Tiny Forth Processors
            50435: 02/12/10: Martin Schoeberl: Re: Tiny Forth Processors
                50443: 02/12/11: tim simpson: Re: Tiny Forth Processors
                    50462: 02/12/11: Martin Schoeberl: Re: Tiny Forth Processors
                        50481: 02/12/12: Jim Granville: Re: Tiny Forth Processors
                            50510: 02/12/11: Martin Schoeberl: Re: Tiny Forth Processors
                                50585: 02/12/13: Jim Granville: Re: JVM/.NET on FPGA (was Tiny Forth Processors)
                        50486: 02/12/11: dwight elvey: Re: Tiny Forth Processors
                            50511: 02/12/11: Martin Schoeberl: Re: Tiny Forth Processors
                        50493: 02/12/12: tim simpson: Re: Tiny Forth Processors
                        50616: 02/12/14: Tim Tyler: Re: Tiny Forth Processors
                50448: 02/12/11: Ralph Mason: Re: Tiny Forth Processors
                    50450: 02/12/11: Jim Granville: Re: Tiny Forth Processors
                    50463: 02/12/11: Martin Schoeberl: Re: Tiny Forth Processors
                        50503: 02/12/11: rickman: Re: Tiny Forth Processors
                    50488: 02/12/11: William Tanksley Google: Re: Tiny Forth Processors
                50483: 02/12/11: dwight elvey: Re: Tiny Forth Processors
                50497: 02/12/11: William Tanksley Google: Re: Tiny Forth Processors
                50617: 02/12/14: Tim Tyler: Re: Tiny Forth Processors
    50391: 02/12/10: Ken Chapman: Re: Tiny Forth Processors
    50431: 02/12/10: Kip Ingram: Re: Tiny Forth Processors
    50444: 02/12/10: Alex Kouznetsov: Re: Tiny Forth Processors
50392: 02/12/10: javid: Xilinx ISE 5.1 Wait for statement unsupported??
    50407: 02/12/10: Spam Hater: Re: Xilinx ISE 5.1 Wait for statement unsupported??
    50410: 02/12/10: Ray Andraka: Re: Xilinx ISE 5.1 Wait for statement unsupported??
        50430: 02/12/10: javid: Re: Xilinx ISE 5.1 Wait for statement unsupported??
            50439: 02/12/10: Ray Andraka: Re: Xilinx ISE 5.1 Wait for statement unsupported??
                50465: 02/12/11: javid: Re: Xilinx ISE 5.1 Wait for statement unsupported??
            50441: 02/12/11: David R Brooks: Re: Xilinx ISE 5.1 Wait for statement unsupported??
50395: 02/12/10: Dimitris Theodoropoulos: Synopsys MemPro
50397: 02/12/10: Muthu: Area contrain for a Module
    50425: 02/12/10: Chen Wei Tseng: Re: Area contrain for a Module
50402: 02/12/10: Thomas Womack: State of the PCB world
    50405: 02/12/10: Martin Schoeberl: Re: State of the PCB world
    50457: 02/12/10: Kevin Brace: Re: State of the PCB world
    50790: 02/12/19: Theo Markettos: Re: State of the PCB world
        50866: 02/12/20: Theron Hicks (Terry): Re: State of the PCB world
            50894: 02/12/22: Theo Markettos: Re: State of the PCB world
        50867: 02/12/20: Theron Hicks (Terry): Re: State of the PCB world
    50874: 02/12/21: Rudolf Usselmann: Re: State of the PCB world
    50907: 02/12/22: Marc Van Riet: Re: State of the PCB world
    50946: 02/12/23: Steen Larsen: Re: State of the PCB world
        51009: 02/12/26: Hal Murray: Re: State of the PCB world
        53329: 03/03/10: Stan Lackey: Re: State of the PCB world
            53352: 03/03/11: Bob Perlman: Re: State of the PCB world
                53356: 03/03/11: Theron Hicks: Re: State of the PCB world
50411: 02/12/10: Hristo Stevic: on FPGA startup what is going on?
50417: 02/12/10: hristo: FPGA startup events
    50420: 02/12/10: Falk Brunner: Re: FPGA startup events
        50442: 02/12/10: hristo: Re: FPGA startup events
            50468: 02/12/11: hristo: Re: FPGA startup events
                50514: 02/12/12: Falk Brunner: Re: FPGA startup events
                    50527: 02/12/12: Ray Andraka: Re: FPGA startup events
            50512: 02/12/12: Falk Brunner: Re: FPGA startup events
50427: 02/12/10: Martin Euredjian: VirtexII pin assignments/signal flow
    50509: 02/12/11: Martin Euredjian: Re: VirtexII pin assignments/signal flow
        50551: 02/12/12: Marc Randolph: Re: VirtexII pin assignments/signal flow
            50559: 02/12/12: Martin Euredjian: Re: VirtexII pin assignments/signal flow
                50565: 02/12/12: Marc Randolph: Re: VirtexII pin assignments/signal flow
50447: 02/12/11: Seiran: Some boards for designers...
    50454: 02/12/11: CBFalconer: Re: Some boards for designers...
        50455: 02/12/11: Seiran: Re: Some boards for designers...
            50458: 02/12/11: Steven: Re: Some boards for designers...
    50469: 02/12/11: Laurent Gauch: Re: Some boards for designers...
        50505: 02/12/11: Seiran: Re: Some boards for designers...
    50470: 02/12/11: Lewin A.R.W. Edwards: Re: Some boards for designers...
50464: 02/12/11: J R: Urgent : Need help with VHDL modeling on Cypress's Warp 5.2
50467: 02/12/11: Mathew Orman: ispDesignEXPERT installation
50471: 02/12/11: Heiko Kalte: partial Bitstream Size in Virtex-II
    50476: 02/12/11: Peter Alfke: Re: partial Bitstream Size in Virtex-II
        50480: 02/12/11: Heiko Kalte: Re: partial Bitstream Size in Virtex-II
    50489: 02/12/11: Austin Lesea: Re: partial Bitstream Size in Virtex-II
50475: 02/12/11: Prashant: Hold violation in synthesis but not fitting
    50477: 02/12/11: Muzaffer Kal: Re: Hold violation in synthesis but not fitting
        50521: 02/12/11: Prashant: Re: Hold violation in synthesis but not fitting
            50567: 02/12/12: Mike Treseler: Re: Hold violation in synthesis but not fitting
                50598: 02/12/13: Prashant: Re: Hold violation in synthesis but not fitting
    50604: 02/12/13: Jay: Re: Hold violation in synthesis but not fitting
50478: 02/12/11: Brad Eckert: Power consumption question
    50485: 02/12/11: Mathew Orman: Re: Power consumption question
        50498: 02/12/11: Peter Alfke: Re: Power consumption question
            50501: 02/12/11: Uwe Bonnes: Re: Power consumption question
                50502: 02/12/11: Austin Lesea: Re: Power consumption question
                    50506: 02/12/11: Uwe Bonnes: Re: Power consumption question
                        50529: 02/12/12: rickman: Re: Power consumption question
                    50507: 02/12/12: Jim Granville: Re: Power consumption question
                        50515: 02/12/11: Peter Alfke: Re: Power consumption question
                            50517: 02/12/12: Kip Ingram: Re: Power consumption question
    50492: 02/12/11: Kip Ingram: Re: Power consumption question
        50499: 02/12/12: Jim Granville: Re: Power consumption question
50487: 02/12/11: cheema: HDL for Hough tranform
50495: 02/12/11: Jason Hannula: Any experience with Altera Apex PCI Development Kit?
50520: 02/12/11: Skept: When to use CLKDLL vs. DCM in Virtex devices
    50522: 02/12/12: John_H: Re: When to use CLKDLL vs. DCM in Virtex devices
50530: 02/12/12: Ryan: Problem with Symbol generation in Quartus2
    50538: 02/12/12: Thomas Pollischansky: Re: Problem with Symbol generation in Quartus2
    50569: 02/12/13: Subroto Datta: Re: Problem with Symbol generation in Quartus2
50532: 02/12/12: Saurabh Pal: Suggestions required for Handel-C code
    50558: 02/12/12: qlyus: Re: Suggestions required for Handel-C code
    50574: 02/12/13: Phil Hays: Re: Suggestions required for Handel-C code
    50582: 02/12/13: Alan Fitch: Re: Suggestions required for Handel-C code
    50615: 02/12/13: John: Re: Suggestions required for Handel-C code
50533: 02/12/12: Nagaraj: MTBF Calculation
    50537: 02/12/12: Alan Fitch: Re: MTBF Calculation
    50555: 02/12/12: Peter Alfke: Re: MTBF Calculation
        50579: 02/12/12: Nagaraj: Re: MTBF Calculation
            50600: 02/12/13: rickman: Re: MTBF Calculation
            50603: 02/12/13: Peter Alfke: Re: MTBF Calculation
                50611: 02/12/14: Hal Murray: Re: MTBF Calculation
                50620: 02/12/14: Rick Filipkiewicz: Re: MTBF Calculation
50535: 02/12/12: Lorenzo Lutti: Two clocks for the same module
    50544: 02/12/12: Muthu: Re: Two clocks for the same module
        50547: 02/12/12: Lorenzo Lutti: Re: Two clocks for the same module
            50570: 02/12/12: Jay: Re: Two clocks for the same module
            50591: 02/12/13: Lorenzo Lutti: Re: Two clocks for the same module
                50594: 02/12/13: Lorenzo Lutti: Re: Two clocks for the same module
                    50605: 02/12/13: Jay: Re: Two clocks for the same module
                        50633: 02/12/14: Mike Treseler: Re: Two clocks for the same module
                            50792: 02/12/19: Loan Nguyen: Re: Two clocks for the same module
50536: 02/12/12: FPGA Wonderkid: Distributed RAM in cyclone
    50571: 02/12/12: Jay: Re: Distributed RAM in cyclone
        50588: 02/12/13: FPGA Wonderkid: Re: Distributed RAM in cyclone
            50606: 02/12/13: Jay: Re: Distributed RAM in cyclone
50539: 02/12/12: Thomas Pollischansky: NIOS C Programming: Accesing the Status Register?
    50540: 02/12/12: Matjaz Finc: Re: NIOS C Programming: Accesing the Status Register?
50541: 02/12/12: Muthu: RPM Using ISE5.1i FloorPlanner
    50545: 02/12/12: Chen Wei Tseng: Re: RPM Using ISE5.1i FloorPlanner
        50573: 02/12/12: Muthu: Re: RPM Using ISE5.1i FloorPlanner
            50583: 02/12/13: Alan Fitch: Re: RPM Using ISE5.1i FloorPlanner
                50584: 02/12/13: Uwe Bonnes: Re: RPM Using ISE5.1i FloorPlanner
            50596: 02/12/13: Chen Wei Tseng: Re: RPM Using ISE5.1i FloorPlanner
        50638: 02/12/15: <hamish@cloud.net.au>: Re: RPM Using ISE5.1i FloorPlanner
50542: 02/12/12: Ryan: Textio in Quartus2
50543: 02/12/12: AE: READBACK black box...
    50563: 02/12/13: John Williams: Re: READBACK black box...
    50564: 02/12/13: John Williams: Re: READBACK black box...
50546: 02/12/12: Uwe Bonnes: Using smaller configuration device possible with Xilinx
    50554: 02/12/12: Steve Casselman: Re: Using smaller configuration device possible with Xilinx
        50572: 02/12/12: Rudolf Usselmann: Re: Using smaller configuration device possible with Xilinx
            50581: 02/12/13: Uwe Bonnes: Re: Using smaller configuration device possible with Xilinx
            50586: 02/12/13: Steve Casselman: Re: Using smaller configuration device possible with Xilinx
50549: 02/12/12: millim: Help:encode FSM into Block RAM
50550: 02/12/12: hristo: what makes an implementation a patent?
    50553: 02/12/12: Uwe Bonnes: Re: what makes an implementation a patent?
        50643: 02/12/15: Austin Franklin: Re: what makes an implementation a patent?
    50556: 02/12/12: Ray Andraka: Re: what makes an implementation a patent?
        50557: 02/12/12: Nicholas C. Weaver: Re: what makes an implementation a patent?
    50561: 02/12/12: Steve Casselman: Re: what makes an implementation a patent?
    50562: 02/12/12: glen herrmannsfeldt: Re: what makes an implementation a patent?
        50644: 02/12/15: Austin Franklin: Re: what makes an implementation a patent?
            50711: 02/12/18: glen herrmannsfeldt: Re: what makes an implementation a patent?
        50646: 02/12/15: Austin Franklin: Re: what makes an implementation a patent?
            50657: 02/12/16: rickman: Re: what makes an implementation a patent?
                50659: 02/12/16: Jim Granville: Re: what makes an implementation a patent?
                50664: 02/12/16: Austin Franklin: Re: what makes an implementation a patent?
            50669: 02/12/16: Steve Casselman: Re: what makes an implementation a patent?
                50670: 02/12/16: Austin Franklin: Re: what makes an implementation a patent?
                    50673: 02/12/16: Steve Casselman: Re: what makes an implementation a patent?
                        50695: 02/12/17: Austin Franklin: Re: what makes an implementation a patent?
50566: 02/12/12: Jeff: Want to buy an board with Xilinx FPGA Virtex II
    51027: 02/12/27: Philip Freidin: Re: Want to buy an board with Xilinx FPGA Virtex II
        51030: 02/12/26: john jakson: Re: Want to buy an board with Xilinx FPGA Virtex II
50575: 02/12/12: sthiruppathirajan: Single Event Upset in One Time PROM configuring FPGA
    50576: 02/12/13: John Williams: Re: Single Event Upset in One Time PROM configuring FPGA
    50590: 02/12/13: sthiruppathirajan: Re: Single Event Upset in One Time PROM configuring FPGA
50577: 02/12/12: wosiqiu: Can I use bus keeper like this?
    50580: 02/12/13: Falser Klaus: Re: Can I use bus keeper like this?
50578: 02/12/12: wosiqiu: Can I use bus keeper like this?
    50609: 02/12/13: Jay: Re: Can I use bus keeper like this?
        50614: 02/12/13: wosiqiu: Re: Can I use bus keeper like this?
50587: 02/12/13: sthiruppathirajan: Single event Upset effect in One Time PROM used for configuration in Xilix FPGA
    50592: 02/12/13: Josh Model: Re: Single event Upset effect in One Time PROM used for configuration in Xilix FPGA
            50656: 02/12/15: sthiruppathirajan: Re: Single event Upset effect in One Time PROM used for configuration in Xilix FPGA
            50681: 02/12/17: sthiruppathirajan: Re: Single event Upset effect in One Time PROM used for configuration in Xilix FPGA
                    50820: 02/12/20: sthiruppathirajan: Re: Single event Upset effect in One Time PROM used for configuration in Xilix FPGA
50595: 02/12/13: Dirk_Doerr: Xilinx Startup Symbol / Global reset net
50597: 02/12/13: Tim: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50599: 02/12/13: Stephen Williams: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
        50626: 02/12/14: Tim: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50601: 02/12/13: Eric Smith: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
        50602: 02/12/13: rickman: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
            50628: 02/12/14: Tim: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
                50634: 02/12/14: rickman: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
                    50639: 02/12/15: <hamish@cloud.net.au>: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
                    50650: 02/12/16: Tim: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
                        50658: 02/12/16: rickman: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
        50624: 02/12/14: Steven: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
        50627: 02/12/14: Tim: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50607: 02/12/13: Jay: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
        50629: 02/12/14: Tim: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50613: 02/12/14: Nicholas C. Weaver: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
        50630: 02/12/14: Tim: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
50610: 02/12/13: Duane Clark: Packing clock enable flipflops into IOB
    50612: 02/12/13: Roger Green: Re: Packing clock enable flipflops into IOB
        50645: 02/12/15: Duane Clark: Re: Packing clock enable flipflops into IOB
    50653: 02/12/15: Kevin Brace: Re: Packing clock enable flipflops into IOB
50618: 02/12/14: Rob Finch: SpartanII Internal Clock ?
    50625: 02/12/14: Ray Andraka: Re: SpartanII Internal Clock ?
50623: 02/12/14: strut911: Strange error on Xilinx Bitgen/Netcheck DRC check
    50717: 02/12/18: Shareef Jalloq: Re: Strange error on Xilinx Bitgen/Netcheck DRC check
50632: 02/12/14: Martin Schoeberl: Quartus does not start on Windows ME
    50636: 02/12/15: Leon Heller: Re: Quartus does not start on Windows ME
50637: 02/12/15: Jeff: Could you explain compact PCI, PCI and PCI bridge to me?
    50641: 02/12/15: Roger Green: Re: Could you explain compact PCI, PCI and PCI bridge to me?
        50652: 02/12/15: Kevin Brace: Re: Could you explain compact PCI, PCI and PCI bridge to me?
50640: 02/12/15: Nahum Barnea: virtex PRO migration cost
50642: 02/12/15: Tom Hawkins: EDIF LPM Support in Synthesis
    50648: 02/12/15: Mike Treseler: Re: EDIF LPM Support in Synthesis
    50649: 02/12/15: Uncle Noah: Re: EDIF LPM Support in Synthesis
        50662: 02/12/16: Tom Hawkins: Re: EDIF LPM Support in Synthesis
            50672: 02/12/16: Mike Treseler: Re: EDIF LPM Support in Synthesis
50647: 02/12/15: alison: Matrics Memory controller
    50655: 02/12/16: Rob Finch: Re: Matrics Memory controller
        50666: 02/12/16: alison: Re: Matrics Memory controller
            50667: 02/12/16: Peter Alfke: Re: Matrics Memory controller
                50671: 02/12/16: alison: Re: Matrics Memory controller
                    50674: 02/12/16: Peter Alfke: Re: Matrics Memory controller
                    50677: 02/12/17: Hal Murray: Re: Matrics Memory controller
                    50678: 02/12/17: Rob Finch: Re: Matrics Memory controller
                    50756: 02/12/18: Ray Andraka: Re: Matrics Memory controller
                        50872: 02/12/21: Rob Finch: Re: Matrics Memory controller
                            51103: 03/01/01: alison: Re: Matrics Memory controller
50651: 02/12/16: Brad Parker: OT: know anyone who worked on NCD Explora 451 FPGA?
50654: 02/12/16: Hua Ai: Internal_Error of ISE 5.1.02i xst F.25.
    50682: 02/12/17: Alan Fitch: Re: Internal_Error of ISE 5.1.02i xst F.25.
        50699: 02/12/17: Hua Ai: Re: Internal_Error of ISE 5.1.02i xst F.25.
            50713: 02/12/18: Alan Fitch: Re: Internal_Error of ISE 5.1.02i xst F.25.
50660: 02/12/16: Terrence Mak: VirtexII Pro question
50661: 02/12/16: Terrence Mak: Virtex2Pro question
    50663: 02/12/16: Austin Lesea: Re: Virtex2Pro question
        50665: 02/12/16: Austin Franklin: Re: Virtex2Pro question
            50668: 02/12/16: Austin Lesea: Re: Virtex2Pro question
                50676: 02/12/16: Ed: Re: Virtex2Pro question
    50854: 02/12/20: Kuan Zhou: Re: Virtex2Pro question
        50857: 02/12/20: Peter Alfke: Re: Virtex2Pro question
50680: 02/12/16: strut911: Xilinx PAR looks as if it is adding X_BUF instances in my clock tree
    50696: 02/12/17: Mike Mitchener: Re: Xilinx PAR looks as if it is adding X_BUF instances in my clock tree
50683: 02/12/17: Rob Finch: neural networks
    50686: 02/12/17: Leon Heller: Re: neural networks
    50687: 02/12/17: Will Dwinnell: Re: neural networks
50684: 02/12/17: strut911: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
    50690: 02/12/17: Spam Hater: Re: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
    50697: 02/12/17: Jay: Re: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
    50700: 02/12/17: Mike Mitchener: Re: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
            50736: 02/12/18: john jakson: Re: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
50685: 02/12/17: Erwan: MPEG FPGA
    50693: 02/12/17: Nicholas C. Weaver: Re: MPEG FPGA
        50728: 02/12/18: andyman: Re: MPEG FPGA
        50817: 02/12/20: Erwan: Re: MPEG FPGA
    50735: 02/12/18: john jakson: Re: MPEG FPGA
    50974: 02/12/24: Rudolf Usselmann: Re: MPEG FPGA
50688: 02/12/17: Dirk_Doerr: Xilinx FPGA PAR warning
    50698: 02/12/17: Jay: Re: Xilinx FPGA PAR warning
        50719: 02/12/18: Dirk_Doerr: Re: Xilinx FPGA PAR warning
50691: 02/12/17: Khim Bittle: ACEX 1K Configuration Time
    50692: 02/12/17: Rene Tschaggelar: Re: ACEX 1K Configuration Time
        50694: 02/12/17: Khim Bittle: Re: ACEX 1K Configuration Time
            50706: 02/12/17: Greg Steinke: Re: ACEX 1K Configuration Time
                50707: 02/12/18: Khim Bittle: Re: ACEX 1K Configuration Time
50702: 02/12/17: Roger: Video timing generator on a Flex 20K / Acex 1K.
    50704: 02/12/18: Ray Andraka: Re: Video timing generator on a Flex 20K / Acex 1K.
    50710: 02/12/17: Jay: Re: Video timing generator on a Flex 20K / Acex 1K.
    50716: 02/12/18: Jonathan Bromley: Re: Video timing generator on a Flex 20K / Acex 1K.
50703: 02/12/18: Ray Andraka: Re: How to asynchronously reset a flip-flop?
    50744: 02/12/18: Christopher R. Carlen: Re: How to asynchronously reset a flip-flop?
50705: 02/12/17: Christopher R. Carlen: How to asynchronously reset a flip-flop?
    50740: 02/12/18: Peter Alfke: Re: How to asynchronously reset a flip-flop?
        50742: 02/12/18: Jonathan Bromley: Re: How to asynchronously reset a flip-flop?
            50747: 02/12/18: Peter Alfke: Re: How to asynchronously reset a flip-flop?
            50748: 02/12/19: Jim Granville: Re: How to asynchronously reset a flip-flop?
                50750: 02/12/18: Peter Alfke: Re: How to asynchronously reset a flip-flop?
        50754: 02/12/18: Ray Andraka: Re: How to asynchronously reset a flip-flop?
    50784: 02/12/19: Jim Lewis: Re: How to asynchronously reset a flip-flop?
        50821: 02/12/20: Alan Fitch: Re: How to asynchronously reset a flip-flop?
50708: 02/12/17: Al Williams: PLD Project of the Month
50709: 02/12/18: Kload: Different Versions of Coregen
    51272: 03/01/09: Jeff Weintraub: Re: Different Versions of Coregen
50712: 02/12/18: Masoud Naderi: FPGA instead of HDMP-1022/24
    50726: 02/12/18: Ray Andraka: Re: FPGA instead of HDMP-1022/24
50715: 02/12/18: John Daae: Avoiding SRL16 in Synplify
    50721: 02/12/18: Steven Derrien: Re: Avoiding SRL16 in Synplify
50718: 02/12/18: Xefteris Stefanos: Power Estimation
    50729: 02/12/18: Alan Raphael: Re: Power Estimation
        51219: 03/01/07: Brendan Cullen: Re: Power Estimation - supported simulators
50720: 02/12/18: Bill Sloman: A/D converter in FPGA
    50722: 02/12/18: Lorenzo Lutti: Re: A/D converter in FPGA
        50724: 02/12/18: Allan Herriman: Re: A/D converter in FPGA
            50727: 02/12/18: Jonathan Bromley: Re: A/D converter in FPGA
            50749: 02/12/18: Lorenzo Lutti: Re: A/D converter in FPGA
                50793: 02/12/19: rickman: Re: A/D converter in FPGA
                    50819: 02/12/20: Bill Sloman: Re: A/D converter in FPGA
    50723: 02/12/18: Martin Schoeberl: Re: A/D converter in FPGA
        50840: 02/12/20: Kolja Sulimma: Re: A/D converter in FPGA
    50741: 02/12/18: Peter Alfke: Re: A/D converter in FPGA
        50746: 02/12/19: Jim Granville: Re: A/D converter in FPGA
            50757: 02/12/18: Bill Sloman: Re: A/D converter in FPGA
                50758: 02/12/19: Jim Granville: Re: A/D converter in FPGA
                    50773: 02/12/19: Rob Finch: Re: A/D converter in FPGA
                    50774: 02/12/19: Bill Sloman: Re: A/D converter in FPGA
                        50795: 02/12/19: rickman: Re: A/D converter in FPGA
                            50798: 02/12/20: Jim Granville: Re: A/D converter in FPGA
50725: 02/12/18: Leon Heller: Errors in Xilinx pinout spreadsheet
    50760: 02/12/18: Marc Baker: Re: Errors in Xilinx pinout spreadsheet
50730: 02/12/18: dasari: Is there any generic BIST architectures for Xilinx FPGAs for functional test?
        50769: 02/12/19: dasari: Re: Is there any generic BIST architectures for Xilinx FPGAs for functional test?
            50781: 02/12/19: Ray Andraka: Re: Is there any generic BIST architectures for Xilinx FPGAs for
50731: 02/12/18: dasari: LUT architecture!!
50732: 02/12/18: Kevin Becker: Display "real" waves in simulation?
    50733: 02/12/18: Jonathan Bromley: Re: Display "real" waves in simulation?
    50745: 02/12/18: Ray Andraka: Re: Display "real" waves in simulation?
        50763: 02/12/19: Allan Herriman: Re: Display "real" waves in simulation?
            50764: 02/12/19: Ray Andraka: Re: Display "real" waves in simulation?
50734: 02/12/18: Rene Tschaggelar: embedded programming of an ACEX1k30
    50777: 02/12/19: Rene Tschaggelar: Re: embedded programming of an ACEX1k30
    50789: 02/12/19: Chris: Re: embedded programming of an ACEX1k30
        50887: 02/12/21: Rene Tschaggelar: Re: embedded programming of an ACEX1k30
    50943: 02/12/23: ikauranen: Re: embedded programming of an ACEX1k30
        50975: 02/12/24: Rene Tschaggelar: Re: embedded programming of an ACEX1k30
50737: 02/12/18: Prashant: Async RAM on an FPGA board
    50738: 02/12/18: Jonathan Bromley: Re: Async RAM on an FPGA board
        50771: 02/12/19: Rob Finch: Re: Async RAM on an FPGA board
            50783: 02/12/19: Prashant: Re: Async RAM on an FPGA board
                50786: 02/12/19: Jonathan Bromley: Re: Async RAM on an FPGA board
                    50797: 02/12/19: eric - Mtl: Re: Async RAM on an FPGA board
                        50799: 02/12/19: Peter Alfke: Re: Async RAM on an FPGA board
                    50800: 02/12/19: Prashant: Re: Async RAM on an FPGA board
                        50801: 02/12/20: Jim Granville: Re: Async RAM on an FPGA board
                        50824: 02/12/20: Jonathan Bromley: Re: Async RAM on an FPGA board
                            50842: 02/12/20: Hal Murray: Re: Async RAM on an FPGA board
                            50844: 02/12/20: Prashant: Re: Async RAM on an FPGA board
                                50846: 02/12/20: Falk Brunner: Re: Async RAM on an FPGA board
                                    50850: 02/12/20: Ray Andraka: Re: Async RAM on an FPGA board
                                        50884: 02/12/21: rickman: Re: Async RAM on an FPGA board
                                            50886: 02/12/21: Ray Andraka: Re: Async RAM on an FPGA board
                                50868: 02/12/21: Hal Murray: Re: Async RAM on an FPGA board
                                50870: 02/12/21: Rob Finch: Re: Async RAM on an FPGA board
                                    50931: 02/12/23: Prashant: Re: Async RAM on an FPGA board
50739: 02/12/18: Jee: What's the easy way to port an ISE project
    50743: 02/12/18: Uwe Bonnes: Re: What's the easy way to port an ISE project
    50755: 02/12/18: Hua Ai: Re: What's the easy way to port an ISE project
50752: 02/12/18: Stephen Henry: Embedded Linux for V2Pro
    50770: 02/12/19: Peter Vandenabeele: Re: Embedded Linux for V2Pro
50759: 02/12/18: John: What voltage level is considered as "floating"?
    50762: 02/12/19: Hal Murray: Re: What voltage level is considered as "floating"?
    50802: 02/12/19: rickman: Re: What voltage level is considered as "floating"?
        50804: 02/12/19: Peter Alfke: Re: What voltage level is considered as "floating"?
50761: 02/12/18: mike gibson: parameterized priority encoder in AHDL
50766: 02/12/18: Loganathan Lingappan: Xilinx 4000 FPGA : ERROR XNFO-11
    50772: 02/12/19: Alan Fitch: Re: Xilinx 4000 FPGA : ERROR XNFO-11
50767: 02/12/18: dasari: 16-bit LFSR
    50775: 02/12/19: Rene Tschaggelar: Re: 16-bit LFSR
        50778: 02/12/19: Allan Herriman: Re: 16-bit LFSR
            50782: 02/12/19: Ray Andraka: Re: 16-bit LFSR
                50807: 02/12/19: Stan Lackey: Re: 16-bit LFSR
                    50834: 02/12/20: Peter Alfke: Re: 16-bit LFSR
                50822: 02/12/20: Alan Fitch: Re: 16-bit LFSR
        50823: 02/12/20: Jacky Renaux: Re: 16-bit LFSR
50768: 02/12/18: TI: vlsi training in austria, greece, romania or hungary?
    50776: 02/12/19: john jakson: Re: vlsi training in austria, greece, romania or hungary?
50779: 02/12/19: H.Azmi: FPGA-based FSK Caller ID
50780: 02/12/19: Muthu: Multi cycle Paths..
    50785: 02/12/19: Ken McElvain: Re: Multi cycle Paths..
        50787: 02/12/19: Austin Lesea: Re: Multi cycle Paths..
            50794: 02/12/19: Ray Andraka: Re: Multi cycle Paths..
                50796: 02/12/19: Austin Lesea: Re: Multi cycle Paths..
                    50813: 02/12/19: Muthu: Re: Multi cycle Paths..
                        50814: 02/12/20: Muzaffer Kal: Re: Multi cycle Paths..
                            50815: 02/12/20: Hal Murray: Re: Multi cycle Paths..
                            50825: 02/12/20: Muthu: Re: Multi cycle Paths..
                                50827: 02/12/20: rickman: Re: Multi cycle Paths..
                50809: 02/12/19: Stan Lackey: Re: Multi cycle Paths..
                    50826: 02/12/20: Rick Filipkiewicz: Re: Multi cycle Paths..
            50836: 02/12/20: Ken McElvain: Re: Multi cycle Paths..
    50828: 02/12/20: Jon Schneider: Re: Multi cycle Paths..
50788: 02/12/19: Bert Cuzeau: looking for 100-Base-x Interface board w/wo FPGA
50791: 02/12/19: Giaccaglini Giorgio: Programming ACEX1K from FlashEprom
    50860: 02/12/20: Greg Steinke: Re: Programming ACEX1K from FlashEprom
        50897: 02/12/22: Martin Schoeberl: Re: Programming ACEX1K from FlashEprom
50803: 02/12/20: Russell: Hi xilinx
    50805: 02/12/19: Peter Alfke: Re: Hi xilinx
        50808: 02/12/20: Ray Andraka: Re: Hi xilinx
            50837: 02/12/20: Ken McElvain: Re: Hi xilinx
                50849: 02/12/20: Ray Andraka: Re: Hi xilinx
                    50851: 02/12/20: Nicholas C. Weaver: Re: Hi xilinx
        50864: 02/12/21: Russell: Re: Hi xilinx
    50818: 02/12/20: Uwe Bonnes: Re: Hi xilinx
        50865: 02/12/21: Russell: Re: Hi xilinx
            50873: 02/12/21: Uwe Bonnes: Re: Hi xilinx
    50881: 02/12/21: Petter Gustad: Re: Hi xilinx
        50905: 02/12/22: Igor Orlovich: Re: Hi xilinx
    51256: 03/01/08: david: Re: Hi xilinx
50806: 02/12/20: Hua Ai: Problem of ISE 5.1i installation.
50810: 02/12/19: ed: stupid rookie timing question
    50811: 02/12/20: Kevin Neilson: Re: stupid rookie timing question
    50812: 02/12/20: Phil Hays: Re: stupid rookie timing question
        50832: 02/12/20: Ray Andraka: Re: stupid rookie timing question
        50835: 02/12/20: ed: Re: stupid rookie timing question
        50838: 02/12/20: Ken McElvain: Re: stupid rookie timing question
            50877: 02/12/21: Phil Hays: Re: stupid rookie timing question
                50885: 02/12/21: Ray Andraka: Re: stupid rookie timing question
                50888: 02/12/21: Ray Andraka: Re: stupid rookie timing question
                    50890: 02/12/22: Jim Granville: Re: Xmas Wish Lists ( was stupid rookie timing question )
    50880: 02/12/21: rickman: Re: stupid rookie timing question
50816: 02/12/20: Sanjay Patil: Xilinx 1024 Pt FFT
50830: 02/12/20: AE: XC400XL, Xchecker, and Hardware Debugger
50831: 02/12/20: Paul Butler: Re: Gray code comparisons
50833: 02/12/20: John Jakson: FPGA Supercomputing opportunity
    50847: 02/12/20: Ray Andraka: Re: FPGA Supercomputing opportunity
        50853: 02/12/20: John Jakson: Re: FPGA Supercomputing opportunity
            50855: 02/12/20: Ray Andraka: Re: FPGA Supercomputing opportunity
                50858: 02/12/20: Jim Lewis: Re: FPGA Supercomputing opportunity
                    50861: 02/12/20: Nicholas C. Weaver: Re: FPGA Supercomputing opportunity
                        50863: 02/12/21: Nicholas C. Weaver: Re: FPGA Supercomputing opportunity
                    50862: 02/12/21: John Jakson: Re: FPGA Supercomputing opportunity
                50871: 02/12/21: glen herrmannsfeldt: Re: FPGA Supercomputing opportunity
                    50876: 02/12/21: Ray Andraka: Re: FPGA Supercomputing opportunity
            50879: 02/12/21: rickman: Re: FPGA Supercomputing opportunity
                50882: 02/12/21: Hal Murray: Re: FPGA Supercomputing opportunity
                    50924: 02/12/23: rickman: Re: FPGA Supercomputing opportunity
                        50933: 02/12/23: Hal Murray: Re: FPGA Supercomputing opportunity
                            50957: 02/12/23: rickman: Re: FPGA Supercomputing opportunity
        50875: 02/12/21: Austin Franklin: Re: FPGA Supercomputing opportunity
            50904: 02/12/22: Jay: Re: FPGA Supercomputing opportunity
                50918: 02/12/23: Falk Brunner: Re: FPGA Supercomputing opportunity
                50925: 02/12/23: rickman: Re: FPGA Supercomputing opportunity
                    50951: 02/12/23: john jakson: Re: FPGA Supercomputing opportunity
                        50958: 02/12/23: rickman: Re: FPGA Supercomputing opportunity
                            50962: 02/12/24: glen herrmannsfeldt: Re: FPGA Supercomputing opportunity
                                50978: 02/12/24: john jakson: Re: FPGA Supercomputing opportunity
50839: 02/12/20: Hal Murray: Re: Gray code comparisons
50841: 02/12/20: Weifeng Xu: How to handle Fautly Interconnection in Virtex ?
    50845: 02/12/20: Peter Alfke: Re: How to handle Fautly Interconnection in Virtex ?
        50878: 02/12/21: Phil Hays: Re: How to handle Fautly Interconnection in Virtex ?
    50848: 02/12/20: Ray Andraka: Re: How to handle Fautly Interconnection in Virtex ?
50843: 02/12/20: Marlboro: Vitex DLL and external PLL
50852: 02/12/20: Theron Hicks: thermal issues on FPGA
    50856: 02/12/20: Peter Alfke: Re: thermal issues on FPGA
        50859: 02/12/20: Nicholas C. Weaver: Re: thermal issues on FPGA
    50869: 02/12/21: glen herrmannsfeldt: Re: thermal issues on FPGA
        50898: 02/12/22: Theron Hicks (Terry): Re: thermal issues on FPGA
            50899: 02/12/22: Theron Hicks (Terry): Re: thermal issues on FPGA (oops.. wrong patent no.)
            50902: 02/12/23: Jim Granville: Re: thermal issues on FPGA
                50945: 02/12/23: Theron Hicks: Re: thermal issues on FPGA
                    51066: 02/12/30: Jim Granville: Re: thermal issues on FPGA
                        51081: 02/12/30: Theron Hicks: Re: thermal issues on FPGA
    50883: 02/12/21: rickman: Re: thermal issues on FPGA
        50944: 02/12/23: Theron Hicks: Re: thermal issues on FPGA
            50947: 02/12/23: nospam: Re: thermal issues on FPGA
            50948: 02/12/24: Hal Murray: Re: thermal issues on FPGA
                50949: 02/12/23: Peter Alfke: Re: thermal issues on FPGA
            50971: 02/12/24: Brian Drummond: Re: thermal issues on FPGA
                50990: 02/12/24: Theron Hicks (Terry): Re: thermal issues on FPGA
                    50992: 02/12/25: Hal Murray: Re: thermal issues on FPGA
                    51005: 02/12/26: Brian Drummond: Re: thermal issues on FPGA
    50973: 02/12/24: Aurash Lazarut: Re: thermal issues on FPGA
50889: 02/12/21: TigerMole: CPLD ISP cables (newbie question)
    50892: 02/12/22: Leon Heller: Re: CPLD ISP cables (newbie question)
    50895: 02/12/22: Rene Tschaggelar: Re: CPLD ISP cables (newbie question)
50891: 02/12/22: Toshihiro: I didn't understand altera's max+plus2 software to setting up.
    50903: 02/12/22: Jay: Re: I didn't understand altera's max+plus2 software to setting up.
        50927: 02/12/24: Toshihiro: Re: I didn't understand altera's max+plus2 software to setting up.
            50929: 02/12/24: Toshihiro: Re: I didn't understand altera's max+plus2 software to setting up.
    50942: 02/12/23: Helmut Sennewald: Re: I didn't understand altera's max+plus2 software to setting up.
50893: 02/12/22: Jamil: Compiling Altera LPM on leonardo
    50906: 02/12/22: Brian Guralnick: Re: Compiling Altera LPM on leonardo
    50909: 02/12/23: Subroto Datta: Re: Compiling Altera LPM on leonardo
50896: 02/12/22: Nachiket Kapre: distributed computing with Modesim
    50915: 02/12/23: Steve Casselman: Re: distributed computing with Modesim
        50936: 02/12/23: Nachiket Kapre: Re: distributed computing with Modesim
            50952: 02/12/23: john jakson: Re: distributed computing with Modesim
                50981: 02/12/24: Nachiket Kapre: Re: distributed computing with Modesim
                51018: 02/12/26: Petter Gustad: Re: distributed computing with Modesim
                    51026: 02/12/26: john jakson: Re: distributed computing with Modesim
                    51028: 02/12/26: Nachiket Kapre: Re: distributed computing with Modesim
                        51088: 02/12/31: Petter Gustad: Re: distributed computing with Modesim
    51020: 02/12/26: Petter Gustad: Re: distributed computing with Modesim
50900: 02/12/22: Anonymous4: incomplete MNM specification???? timing not working
50901: 02/12/22: Anonymous4: following to my previous email
50908: 02/12/22: Jeff: Where can I download ISE 4.x?
    50913: 02/12/22: Jeff: Re: Where can I download ISE 4.x?
    50964: 02/12/24: Russell: Re: Where can I download ISE 4.x?
50912: 02/12/23: FPGA: serdes
    50920: 02/12/23: Ray Andraka: Re: serdes
        50926: 02/12/23: Austin Franklin: Re: serdes
    50923: 02/12/23: Rene Tschaggelar: Re: serdes
    50928: 02/12/23: Aurash Lazarut: Re: serdes
        50932: 02/12/23: Austin Lesea: Re: serdes
            50967: 02/12/24: Rob Finch: Re: serdes
        50935: 02/12/23: Austin Franklin: Re: serdes
    50930: 02/12/23: Spam Hater 7: Re: serdes
        50934: 02/12/23: Austin Franklin: Re: serdes
50914: 02/12/22: Nagaraj: Digital Resampling
    51023: 02/12/26: MM: Re: Digital Resampling
50916: 02/12/23: valentin tihomirov: How to generate a clock signal for CPLD?
    50922: 02/12/23: Rene Tschaggelar: Re: How to generate a clock signal for CPLD?
        50938: 02/12/23: valentin tihomirov: Re: How to generate a clock signal for CPLD?
            50939: 02/12/23: Peter Alfke: Re: How to generate a clock signal for CPLD?
            50941: 02/12/23: Rene Tschaggelar: Re: How to generate a clock signal for CPLD?
50921: 02/12/23: Martin Schoeberl: Pin definition in Quartus
    50937: 02/12/23: Subroto Datta: Re: Pin definition in Quartus
    51021: 02/12/26: Petter Gustad: Re: Pin definition in Quartus
50940: 02/12/23: Antonio Pasini: ChipScope Pro not importing Inserter project
    51216: 03/01/07: Sasa Bremec: Re: ChipScope Pro not importing Inserter project
50950: 02/12/23: Tim: Combinatorial clock source question
    50953: 02/12/24: Uwe Bonnes: Re: Combinatorial clock source question
    50960: 02/12/24: Ralph Mason: Re: Combinatorial clock source question
        50961: 02/12/24: Muzaffer Kal: Re: Combinatorial clock source question
            50984: 02/12/24: Tim: Re: Combinatorial clock source question
    50988: 02/12/24: Hal Murray: Re: Combinatorial clock source question
50954: 02/12/24: cfk: Prom Splitting
    50968: 02/12/24: Aurash Lazarut: Re: Prom Splitting
        50969: 02/12/24: Aurash Lazarut: Re: Prom Splitting
50955: 02/12/23: john jakson: FPGA accelerated FPGA/ASIC tools
    50963: 02/12/23: James Bonanno: Re: FPGA accelerated FPGA/ASIC tools
        50965: 02/12/24: Aurash Lazarut: Re: FPGA accelerated FPGA/ASIC tools
    50976: 02/12/24: Rene Tschaggelar: Re: FPGA accelerated FPGA/ASIC tools
        50979: 02/12/24: Steve Casselman: Re: FPGA accelerated FPGA/ASIC tools
            50980: 02/12/24: Austin Lesea: Re: FPGA accelerated FPGA/ASIC tools
                50983: 02/12/24: Steve Casselman: Re: FPGA accelerated FPGA/ASIC tools
                50989: 02/12/25: Nicholas C. Weaver: Re: FPGA accelerated FPGA/ASIC tools
                51293: 03/01/09: Eric Smith: Re: FPGA accelerated FPGA/ASIC tools
                    51295: 03/01/09: Austin Franklin: Re: FPGA accelerated FPGA/ASIC tools
            51040: 02/12/27: Mike Butts: Re: FPGA accelerated FPGA/ASIC tools
                51051: 02/12/28: Nicholas C. Weaver: Re: FPGA accelerated FPGA/ASIC tools
            51050: 02/12/28: Austin Franklin: Re: FPGA accelerated FPGA/ASIC tools
        50982: 02/12/24: James Bonanno: Re: FPGA accelerated FPGA/ASIC tools
            50998: 02/12/25: john jakson: Re: FPGA accelerated FPGA/ASIC tools
50956: 02/12/23: Peter Wtorek: Altera SOPC Builder 2.61 problems ...
    51185: 03/01/06: Matjaz Finc: Re: Altera SOPC Builder 2.61 problems ...
        51209: 03/01/06: Kerri Golden: Re: Altera SOPC Builder 2.61 problems ...
            51225: 03/01/07: Kerri Golden: Re: Altera SOPC Builder 2.61 problems ...
50959: 02/12/23: Nagaraj: DLL wave shape
50966: 02/12/24: Muthu: Floor Planning DCM
    50970: 02/12/24: Aurash Lazarut: Re: Floor Planning DCM
        50994: 02/12/25: Muthu: Re: Floor Planning DCM
            51035: 02/12/27: Vikram: Re: Floor Planning DCM
                51145: 03/01/03: Kate Kelley: Re: Floor Planning DCM
                    52074: 03/01/30: M Schreiber: Re: Floor Planning DCM
                        52113: 03/01/31: Kate Kelley: Re: Floor Planning DCM
50972: 02/12/24: John McMiller: HSTL standards
    50977: 02/12/24: Austin Lesea: Re: HSTL standards
        50991: 02/12/25: Bob: Re: HSTL standards
        50995: 02/12/25: John McMiller: Re: HSTL standards
50985: 02/12/24: Aki Niimura: Xilinx Makefile for ISE 5.1i
    51149: 03/01/03: Kate Kelley: Re: Xilinx Makefile for ISE 5.1i
        51155: 03/01/03: Aki Niimura: Re: Xilinx Makefile for ISE 5.1i
50986: 02/12/24: Matthew Campbell: Newbie Question
    51007: 02/12/25: Kevin Brace: Re: Newbie Question
        51039: 02/12/27: Matthew Campbell: Re: Newbie Question
            51047: 02/12/28: Kevin Brace: Re: Newbie Question
50987: 02/12/24: Lyndon Amsdon: Altera Quartus or MAX Plus?
    50996: 02/12/25: Rene Tschaggelar: Re: Altera Quartus or MAX Plus?
        50999: 02/12/25: Lyndon Amsdon: Re: Altera Quartus or MAX Plus?
            51002: 02/12/26: Rene Tschaggelar: Re: Altera Quartus or MAX Plus?
    51004: 02/12/26: luigi funes: Re: Altera Quartus or MAX Plus?
        51012: 02/12/26: siriuswmx: Re: Altera Quartus or MAX Plus?
        51013: 02/12/26: Lyndon Amsdon: Re: Altera Quartus or MAX Plus?
            51017: 02/12/26: luigi funes: Re: Altera Quartus or MAX Plus?
                51024: 02/12/26: Lyndon Amsdon: Re: Altera Quartus or MAX Plus?
                    51025: 02/12/26: Rene Tschaggelar: Re: Altera Quartus or MAX Plus?
50993: 02/12/25: Masoud Naderi: Parallel Automatic Synchronization System in HDMP-1034
50997: 02/12/25: Allan Herriman: syn_evaleffort attribute
    51022: 02/12/26: Allan Herriman: Re: syn_evaleffort attribute
51000: 02/12/25: Jeff: Question from newbie of WebPACK
    51008: 02/12/25: Nachiket Kapre: Re: Question from newbie of WebPACK
51001: 02/12/25: Jamil: Free Opne hardware designs and tools on CDROMs
51003: 02/12/26: MM: Has anyone implemented IEEE1394 LLC in a FPGA?
51006: 02/12/25: dasari: free fpga soft core
    51011: 02/12/26: Rudolf Usselmann: Re: free fpga soft core
        51029: 02/12/26: dasari: Re: free fpga soft core
            51095: 02/12/31: Rudolf Usselmann: Re: free fpga soft core
    51068: 02/12/30: Tony Burch: Re: free fpga soft core
        51113: 03/01/02: dasari: Re: free fpga soft core
51010: 02/12/26: Nachiket Kapre: probing modesim simulator state
    51056: 02/12/28: Mike Treseler: Re: probing modesim simulator state
        51063: 02/12/29: Nachiket Kapre: Re: probing modesim simulator state - elaborated question
            51065: 02/12/29: Mike Treseler: Re: probing modesim simulator state - elaborated question
51014: 02/12/26: Muthu: RPM Portability?
51015: 02/12/26: R.Sriram: Interested in FPGA design
    51016: 02/12/26: Andrew McMeikan: Re: Interested in FPGA design
51019: 02/12/26: Muthu: FIFO FULL
51031: 02/12/27: RANGA REDDY: RAMDAC implementation in FPGA
    51071: 02/12/30: RANGA REDDY: Re: RAMDAC implementation in FPGA
51032: 02/12/27: Tom Deblauwe: sram cells
    51037: 02/12/27: Peter Alfke: Re: sram cells
51033: 02/12/27: Charles Krinke: optimization
    51038: 02/12/27: Hal Murray: Re: optimization
51034: 02/12/27: bob: Actel 32300 power-up behavoiur
    51111: 03/01/02: Kate Atkins: Re: Actel 32300 power-up behavoiur
51043: 02/12/28: Dave: BP programmer questions, prices, alternatives
    51045: 02/12/28: William Meyer: Re: BP programmer questions, prices, alternatives
    51072: 02/12/30: Mathew Orman: Re: BP programmer questions, prices, alternatives
        51074: 02/12/30: Austin Franklin: Re: BP programmer questions, prices, alternatives
            51077: 02/12/30: Mathew Orman: Re: BP programmer questions, prices, alternatives
                51082: 02/12/30: Austin Franklin: Re: BP programmer questions, prices, alternatives
                    51091: 02/12/31: Mathew Orman: Re: BP programmer questions, prices, alternatives
    51075: 02/12/30: Austin Franklin: Re: BP programmer questions, prices, alternatives
    51089: 02/12/31: Aurash Lazarut: Re: BP programmer questions, prices, alternatives
    51097: 03/01/01: John Eaton: Re: BP programmer questions, prices, alternatives
    51101: 03/01/01: chris: Re: BP programmer questions, prices, alternatives
    51126: 03/01/02: Jay: Re: BP programmer questions, prices, alternatives
    51152: 03/01/03: Daniel Lang: Re: BP programmer questions, prices, alternatives
    51176: 03/01/05: David: Re: BP programmer questions, prices, alternatives
        51180: 03/01/05: Dave: Re: BP programmer questions, prices, alternatives
            51193: 03/01/06: Austin Franklin: Re: BP programmer questions, prices, alternatives
                51196: 03/01/06: Austin Franklin: Re: BP programmer questions, prices, alternatives
51044: 02/12/28: Carl De Far: How suppress Xilinx XCT complier warnings: WARNING:HDLCompilers?
    51046: 02/12/28: Carl De Far: Re: How suppress Xilinx XCT complier warnings: WARNING:HDLCompilers?
    51146: 03/01/03: Paulo Dutra: Re: How suppress Xilinx XCT complier warnings: WARNING:HDLCompilers?
51049: 02/12/28: Anonymous4: VCC,GND with the new version of tool
51053: 02/12/28: Kuan Zhou: Virtex architecture newbie question
    51054: 02/12/28: Nicholas C. Weaver: Re: Virtex architecture newbie question
    51055: 02/12/28: Peter Alfke: Re: Virtex architecture newbie question
51059: 02/12/28: sean da: dualport ram instantiation in Spartan IIE
    51086: 02/12/31: Igor Orlovich: Re: dualport ram instantiation in Spartan IIE
        51228: 03/01/07: name: Re: dualport ram instantiation in Spartan IIE
            51233: 03/01/07: John_H: Re: dualport ram instantiation in Spartan IIE
                51857: 03/01/23: Michael: Re: dualport ram instantiation in Spartan IIE
                    51863: 03/01/23: John_H: Re: dualport ram instantiation in Spartan IIE
                        51882: 03/01/24: Rick Filipkiewicz: Re: dualport ram instantiation in Spartan IIE
51060: 02/12/29: Rob Finch: interface DRAM to FPGA
    51073: 02/12/30: rickman: Re: interface DRAM to FPGA
        51079: 02/12/30: Eric Pearson: Re: interface DRAM to FPGA
            51117: 03/01/02: jakab tanko: Re: interface DRAM to FPGA
                51118: 03/01/02: Andreas Schweizer: Re: interface DRAM to FPGA
                    51120: 03/01/02: jakab tanko: Re: interface DRAM to FPGA
                        51123: 03/01/02: Eric Pearson: Re: interface DRAM to FPGA
                        51128: 03/01/02: Peter Alfke: Re: interface DRAM to FPGA
                            51135: 03/01/03: jakab tanko: Re: interface DRAM to FPGA
                                51139: 03/01/03: rickman: Re: interface DRAM to FPGA
                                    51144: 03/01/03: Peter Alfke: Re: interface DRAM to FPGA
                                        51160: 03/01/04: rickman: Re: interface DRAM to FPGA
                                            51169: 03/01/04: Peter Alfke: Re: interface DRAM to FPGA
                                                51184: 03/01/05: rickman: Re: interface DRAM to FPGA
                                51142: 03/01/03: Peter Alfke: Re: interface DRAM to FPGA
                            51151: 03/01/04: Thomas Rudloff: Re: interface DRAM to FPGA
                                51201: 03/01/06: Mike Butts: Re: interface DRAM to FPGA
51061: 02/12/29: TI: Future of VLSI in developing countries
    51062: 02/12/29: Rene Tschaggelar: Re: Future of VLSI in developing countries
    51064: 02/12/29: john jakson: Re: Future of VLSI in developing countries
51067: 02/12/29: Ganesan: Xilinx Answer Record # 15857: input to an IBUF cannot be tied to ground!
51069: 02/12/29: Valli: what is bus keeper / bus gate.
    51076: 02/12/30: Allan Herriman: Re: what is bus keeper / bus gate.
        51094: 02/12/31: ben cohen: Re: what is bus keeper / bus gate.
            51112: 03/01/02: Valli: Re: what is bus keeper / bus gate.
        51116: 03/01/02: Rick Filipkiewicz: Re: what is bus keeper / bus gate.
51080: 02/12/30: Adam Elbirt: Xilinx Gate Counts
    51109: 03/01/01: FPGA Wonderkid: Re: Xilinx Gate Counts
        51114: 03/01/02: dasari: Re: Xilinx Gate Counts
            51115: 03/01/02: Tim: Re: Xilinx Gate Counts
51083: 02/12/30: Naveen Gupta: xilinx virtex "done" pin problem with jtag
    51085: 02/12/31: Bob: Re: xilinx virtex "done" pin problem with jtag
51084: 02/12/30: TI: VLSI training and prospects?
    51329: 03/01/10: Phil Tomson: Re: VLSI training and prospects?
        51344: 03/01/10: john jakson: Re: VLSI training and prospects?
            51354: 03/01/11: Phil Tomson: Re: VLSI training and prospects?
51087: 02/12/30: TI: VLSI training in Germany, the Balcans or Russia?
51090: 02/12/31: Andreas Schweizer: Unused FPGA I/O Pins?
    51092: 02/12/31: Kumaran Selvaratnam: Re: Unused FPGA I/O Pins?
    51093: 02/12/31: Peter Alfke: Re: Unused FPGA I/O Pins?
        51104: 03/01/01: Spam Hater: Re: Unused FPGA I/O Pins?
            51105: 03/01/01: Peter Alfke: Re: Unused FPGA I/O Pins?
        51110: 03/01/02: Andreas Schweizer: Re: Unused FPGA I/O Pins?
    51132: 03/01/03: Thomas Kurth: Re: Unused FPGA I/O Pins?
        51189: 03/01/06: svhb: Re: Unused FPGA I/O Pins?
51096: 02/12/31: Lana: shift register implementation
    51100: 03/01/01: Jim Granville: Re: shift register implementation
    51325: 03/01/10: jetmarc: Re: shift register implementation
        51330: 03/01/10: Peter Alfke: Re: shift register implementation


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