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Authors (G)

2G:
    142814: 09/09/02: Virtex-5 clock input is excessively loading SERDES recovered clock
    142817: 09/09/02: Re: Virtex-5 clock input is excessively loading SERDES recovered
    142841: 09/09/03: Re: Virtex-5 clock input is excessively loading SERDES recovered
    142842: 09/09/03: Re: Virtex-5 clock input is excessively loading SERDES recovered
    142856: 09/09/03: Re: Virtex-5 clock input is excessively loading SERDES recovered
G:
    36595: 01/11/12: Timing constraints for multiple clock logic paths
    39641: 02/02/15: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
    77253: 05/01/01: Verilog /DIP Switch Question....
    77261: 05/01/02: Re: Verilog /DIP Switch Question....
    77272: 05/01/02: Re: Verilog /DIP Switch Question....
    89017: 05/09/02: Re: Problem with ModelSim XE
G E Geiger:
    34598: 01/08/30: Re: WinMe installation
G Henry Yogendran:
    12929: 98/11/05: Free I2C model
    14099: 99/01/13: 1-wire
    15658: 99/04/06: LCD Ip Core
G Iveco:
    125756: 07/11/04: How do I meet this memory IO with least resources on FPGA?
    125759: 07/11/04: Re: How do I meet this memory IO with least resources on FPGA?
    125766: 07/11/04: Re: How do I meet this memory IO with least resources on FPGA?
G Swindell:
    74398: 04/10/10: VHDL help needed ($)
G. Brandenburg:
    18368: 99/10/20: load VIRTEX via JTAG
G. Carvajal:
    134654: 08/08/24: Writing data on CF card using EDK 10.1 and xilfatfs
    134726: 08/08/28: Mass storage device on ML403 board
g. Field:
    49186: 02/11/04: Re: Incremental design question
    49918: 02/11/25: Re: An Virtex FPGA architecture question
g. giachella:
    31441: 01/05/24: Altera APEX internal signal coupling ?
    35019: 01/09/18: Re: Altera Quartus II: Ouput skew ;-(
    40373: 02/03/06: QPRO Virtex
    56660: 03/06/11: Re: Acex1k100 & Quartus
    56713: 03/06/11: Re: Acex1k100 & Quartus
    56980: 03/06/20: Re: FPGA device + CPU
    59773: 03/08/28: Re: Please help me!!!!! ModelSim question...
    65087: 04/01/20: Non deterministic routing in Quartus 3.0 ?
    65141: 04/01/20: Re: Non deterministic routing in Quartus 3.0 ?
    65205: 04/01/21: Re: Non deterministic routing in Quartus 3.0 ?
    65274: 04/01/23: Re: Non deterministic routing in Quartus 3.0 ?
    74298: 04/10/07: PLL lock usage into Altera Stratix devices
    78541: 05/02/03: Altera PLL and Timing Analysis
    78607: 05/02/03: Re: Altera PLL and Timing Analysis
    82182: 05/04/07: Difference between BUFGDS and IBUFDS on clocks
    82405: 05/04/12: Global buffer feeding non clock pins in VIRTEX II
    82455: 05/04/12: Re: Global buffer feeding non clock pins in VIRTEX II
G. Herrmannsfeldt:
    2642: 96/01/17: Re: [q][Reverse Engineering Protection]
    2695: 96/01/24: Re: XILINX XACT 6.0.0 Tools flaky
    2884: 96/02/23: Re: Floating Point and Reconfigurable Architectures
    4123: 96/09/13: Re: Gate Count - Notion of Gate
    5281: 97/02/03: Re: DES Challenge
    5485: 97/02/19: Re: Duplicate PLD?
    6197: 97/04/24: Re: prep benchmarks for FPGAs
    7712: 97/10/06: Re: High Speed FPGAs
    7713: 97/10/06: How fast can fully pipelined XC4000 logic go?
    8122: 97/11/19: Re: XC: bitfile to ASCII file
    8241: 97/12/03: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
    8368: 97/12/10: Re: what is metastability time of a flip_flop
    8408: 97/12/12: dynamic power in Xilinx designs
    8455: 97/12/16: Re: metastability: full citation of Hohl, extracting TAU and T0
    9480: 98/03/17: Re: Strange Xilinx question?
    9509: 98/03/20: Re: Strange Xilinx question?
    9643: 98/03/27: Re: Q: Random number generator
    9949: 98/04/16: Re: XactStep6 - The cure for a dongle
    9996: 98/04/21: Re: Could you help me save CLB's?
    10642: 98/06/08: Re: XC4000: post routing "customization"
    11017: 98/07/10: Re: high-speed place and route
G. Hobson Frater:
    9055: 98/02/17: Re: Fun with Orcad Express and M1!
    23573: 00/06/30: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
    23809: 00/07/10: Re: JTAG headers
G. R. Jeffrey:
    11500: 98/08/19: Example Code
    11536: 98/08/21: inter fpga communication
G. Scott Bright:
    12088: 98/09/28: Re: DataIO + EPC1 problem
G.Bartelt:
    63728: 03/12/02: Re: Functional Simulation QuartusII
<g.bernocchi@gmail.com>:
    107349: 06/08/27: Re: Problem with netlister in System Generator
    115028: 07/01/29: Re: USB 2.0 Streaming using FPGAs
<g.drozdzowski@gmail.com>:
    130843: 08/04/03: Beginner's silly question about ICAP
    130878: 08/04/04: Re: Beginner's silly question about ICAP
<g.eckersley@ieee.org>:
    118002: 07/04/16: Xilinx ISE 9.1
    118009: 07/04/16: Re: Running Xilinx 9.1 GUIs on FC6
    118047: 07/04/16: Re: Xilinx ISE 9.1
    118048: 07/04/16: Re: Running Xilinx 9.1 GUIs on FC6
G.H. Hardy:
    89882: 05/09/29: Using LogicCORE on development board with Web ISE
    90064: 05/10/04: Re: Using LogicCORE on development board with Web ISE
G.Harrison:
    17592: 99/08/12: A problem with ORCAD/VHDL
g.k.:
    65557: 04/02/02: nios c++ and ethernet [may by ot?]
    65866: 04/02/09: Is nobody using c++ and/or plugs-lib? was Re: nios c++ and ethernet [may by ot?]
    65918: 04/02/10: Re: Is nobody using c++ and/or plugs-lib? was Re: nios c++ and ethernet [may by ot?]
G.LOCHON:
    312: 94/10/18: Re: ALTERA EPLDs
G.S. Vigneault:
    18387: 99/10/21: Re: New to FPGA
    18428: 99/10/23: Re: Announcing Free VHDL Simulator for Windows
    18557: 99/10/31: VPR for FPGAs
    18725: 99/11/10: Re: where can I find fitter algorithms
g.wall:
    91642: 05/11/10: fpga speed logic/density MIPS/FLOPS as compared to general purpose
    91643: 05/11/10: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working
    91653: 05/11/10: Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose
    92296: 05/11/25: virtex 4 extreme DSP linux PCI driver
    92409: 05/11/29: grabbing PCI signals, rev-eng dev board
    92429: 05/11/29: nallatech benone fpga board
<g00dminkey@yahoo.com>:
    138219: 09/02/09: Newbie queston: How to remove user core from EDK
    138220: 09/02/09: Strange EDK 10.1.i error message
G?nter Wolpert:
    67331: 04/03/10: Keeping unused ports of an entity
G_Abg:
    126396: 07/11/21: partial dynamic reconfiguration on Virtex-4 SX35
    126415: 07/11/21: Re: partial dynamic reconfiguration on Virtex-4 SX35
    126416: 07/11/21: Re: partial dynamic reconfiguration on Virtex-4 SX35
G_Abgrall:
    131682: 08/04/29: Problem with PlanAhead on Partial Reconfiguration on ML403 (Virtex 4)
    131691: 08/04/29: Re: Problem with PlanAhead on Partial Reconfiguration on ML403
    132093: 08/05/13: Re: Problem with PlanAhead on Partial Reconfiguration on ML403
g_ping:
    45047: 02/07/10: Re: Xilinx adder RLOCs
Gabby Shpirer:
    4983: 97/01/08: Altera clique
    5798: 97/03/16: PEEL16V8 with PALASM
    6311: 97/05/14: HELP!!! can't work with ByteBlaster
    8662: 98/01/18: ByteBlaster
GABBY SHPIRER:
    3673: 96/07/11: WANTED:: Altera second source
gabor:
    93078: 05/12/13: Re: Mean value filter
    119164: 07/05/14: Re: Xilinx Webpack 9.1i.03 Verilog synthesis bug?
    137111: 08/12/23: Re: DFFR using DFF (only, may be extra gates)
    137307: 09/01/08: Re: DFFR using DFF (only, may be extra gates)
    138423: 09/02/21: Re: Very fast counter in VirtexII
    138438: 09/02/23: Re: Spartan 3E Slave Serial problems
    138454: 09/02/23: Re: Spartan 3E Slave Serial problems
    138516: 09/02/25: Re: virtex 5 columns
    138537: 09/02/26: Re: MIG 2.0 for DDR - Spartan3E
    138640: 09/03/02: Re: Lattice announces ECP3
    138701: 09/03/05: Re: Spartan 3AN wake up problem
    138733: 09/03/06: Re: make ise take ngc as source
    138832: 09/03/12: Re: I2C EEPROM
    138952: 09/03/16: Re: I2C EEPROM
    139056: 09/03/19: Re: Xilinx XAPP052 LFSR and its understanding
    139094: 09/03/20: Re: FPGA users, Please take a few seconds to report SPAM
    139197: 09/03/23: Re: Xilinx XAPP052 LFSR and its understanding
    139198: 09/03/23: Re: Xilinx XAPP052 LFSR and its understanding
    139257: 09/03/24: Re: flash controller
    139287: 09/03/25: Re: Which ISE Webpack version for S3A..?
    139346: 09/03/27: Re: Best way to export Xilinx EDK project in ISE and how to
    139348: 09/03/27: Re: PLL in Actel Igloo part
    139357: 09/03/27: Re: Using LVDS in Lattice ECP3
    139359: 09/03/27: Re: Using LVDS in Lattice ECP3
    139480: 09/03/31: Re: XST removes duplicate logic no matter what
    139530: 09/04/02: Re: SSO
    139532: 09/04/02: Re: delays in XC95144XL CPLD
    139540: 09/04/02: Re: Switching an AC power socket from an FPGA
    139560: 09/04/03: Re: delays in XC95144XL CPLD
    139561: 09/04/03: Re: clock multipliers, dividers, and more clocks...
    139565: 09/04/03: Re: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
    139592: 09/04/06: Re: IO Type
    139610: 09/04/07: Re: Modulo-10 counter
    139724: 09/04/10: Re: Xilinx user constraints with respect to output clock from the
    139726: 09/04/10: Re: Strange order of BRAM data bus connections
    139773: 09/04/13: Re: microblaze and flash access
    139799: 09/04/14: Re: Mobile low power DDR SDRAM and MIG
    139801: 09/04/14: Re: Xilinx ISE bug, or?
    139802: 09/04/14: Re: Low-cost Altera FPGA roadmap
    139814: 09/04/14: Re: Low-cost Altera FPGA roadmap
    139834: 09/04/15: Re: sync timer register
    139848: 09/04/16: Re: OFFSET OUT
    139898: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
    139899: 09/04/18: Re: Why is XST optimizing away my registers and how do I stop it?
    139942: 09/04/20: re: FPGA Inernal reset
    139943: 09/04/20: Re: Why is XST optimizing away my registers and how do I stop it?
    139985: 09/04/22: Re: problem with high speed data transfer
    139986: 09/04/22: Re: source for Spartan 3E chips
    140016: 09/04/23: Re: MIG DDR2 controller functional model available
    140070: 09/04/27: Re: ERROR: NgdBuild:604 - logical block
    140082: 09/04/27: Re: ERROR: NgdBuild:604 - logical block
    140083: 09/04/27: Re: FPGA/DSP/Video Board
    140084: 09/04/27: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
    140157: 09/04/30: Re: ERROR: NgdBuild:604 - logical block
    140239: 09/05/05: Re: High-speed signals crossing a split-ground
    140245: 09/05/05: Re: Setting top level VHDL generics in XST
    140601: 09/05/19: Re: Prob with verilog memory
    140615: 09/05/20: Re: DCM Jitter
    140628: 09/05/20: Re: i2c Start and stop detection
    140700: 09/05/22: Re: DCM Jitter
    140880: 09/05/28: Re: writing to reset vectors - xilinx spartan 3an
    140881: 09/05/28: Re: Reading from and writing to a text file in verilog hdl
    140895: 09/05/28: Re: phase locking a slow (2Mhz) signal.
    140923: 09/05/29: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
    140966: 09/06/01: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
    140967: 09/06/01: Re: time constraining asynchronous fifo
    141082: 09/06/04: Re: Help with Remote debugging ideas.
    141086: 09/06/04: Re: I2C SDA LINE
    141110: 09/06/05: Re: digital RGB Video to Analog VGA triple DAC question
    141148: 09/06/08: Re: Xilinx Block RAM Sim
    141302: 09/06/16: Re: NTSC/PAL Encoder using FPGA and DAC
    141341: 09/06/19: Re: Spartan 3A vs 3E SSO guidelines
    141404: 09/06/23: Re: i2c Start and stop detection
    141405: 09/06/23: Re: i2c Start and stop detection
    141494: 09/06/25: Re: SRAM vs Flash based FPGA one more time
    141501: 09/06/25: Re: SRAM vs Flash based FPGA one more time
    141599: 09/06/29: Re: usefulness of Virtex-II devices
    141603: 09/06/29: Re: dual port inference problem
    141658: 09/07/02: Re: Cheapest FPGA with decent PCI- e interface ?
    141664: 09/07/02: Re: Active-HDL simulator recompile... or not recompiling
    141775: 09/07/08: Re: About configuring FPGAs
    141814: 09/07/10: Re: pullup
    141844: 09/07/13: Re: Why do both Xilinx and Altera DPS use 18*18?
    141846: 09/07/13: Re: Xilinx Spartan 3 DCM no output!
    141879: 09/07/14: Re: pullup
    141909: 09/07/16: Re: Generating a negated clock
    142034: 09/07/22: Re: gate capacity between old Virtex-II and newer Virtex-4
    142052: 09/07/23: Re: DONE pin does'nt go high in SPARTAN - 3AN
    142101: 09/07/24: Re: spartan-3 starter kit board JTAG-usb cable
    142138: 09/07/26: Re: How to start FPGA development
    142176: 09/07/28: Re: Lattice EC - some .bit files not loading from SPI flash
    142179: 09/07/28: Re: Daisychaining fpga with SPI flash?
    142191: 09/07/28: Re: Daisychaining fpga with SPI flash?
    142192: 09/07/28: Re: PAR runs successfully, simulation fails
    142193: 09/07/28: Re: Different behavior of FSM in same simulation
    142211: 09/07/29: Re: cool chart
    142212: 09/07/29: Re: Lattice EC - some .bit files not loading from SPI flash
    142304: 09/08/03: Re: Single ended LVDS into FPGA
    142309: 09/08/03: Re: ucf and clock pin placement on Spartan 3E?
    142319: 09/08/04: Re: File I/O read in verilog
    142327: 09/08/04: Re: AES encryption of bitstream - is my design secure?
    142336: 09/08/05: Re: AES encryption of bitstream - is my design secure?
    142337: 09/08/05: Re: Driving Multiple FPGAs and Fanout (Cyclone III)
    142352: 09/08/05: Re: how to sign extend or round?
    142356: 09/08/05: Re: how to sign extend or round?
    142379: 09/08/07: Re: can't write to a bram module (verilog)
    142518: 09/08/14: Re: Initializing BRAM & ISE 10.1
    142593: 09/08/19: Re: Help with crystal oscillator (MG-7010SA replacement)?
    142625: 09/08/22: Re: Ideas needed for implementing SerDes on low-cost fpga (like
    142748: 09/08/30: Re: Does ModelSim or any simulator software have a function similar
    142789: 09/09/01: Re: Wants an update on FPGA development IDE/toolchains
    142811: 09/09/02: Re: ERROR:Pack:1564
    142851: 09/09/03: Re: Wants an update on FPGA development IDE/toolchains
    142924: 09/09/08: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
    142942: 09/09/09: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
    142968: 09/09/10: Re: Bidirectional Bus
    143141: 09/09/23: Re: VHDL question
    143197: 09/09/25: Re: Weird DDR Addressing problem
    143203: 09/09/25: Re: Weird DDR Addressing problem
    143309: 09/10/01: Re: Why won't Xilinx use an FDR?
    143340: 09/10/03: Re: Implement ARM cores on a FPGA chip?
    143355: 09/10/05: Re: Post route simulation and real implementation
    143404: 09/10/09: Re: foundation 2.1 - 3.1 sharing...
    143462: 09/10/12: Re: FPGA ruined (?)
    143477: 09/10/12: Re: Win a Dev Kit--Join Us on Twitter & Facebook
    143501: 09/10/13: Re: FPGA ruined (?)
    144088: 09/11/10: Re: Jan on HDL Design
    145120: 10/01/28: Re: Thank you, SunMicrosystem
    147024: 10/04/09: Re: I'd rather switch than fight!
Gabor:
    66266: 04/02/16: Re: confused DCM clkin_period vs true input clock
    66291: 04/02/16: Re: Xilinx Chipscope Sample rate
    66292: 04/02/16: Re: IOB's
    76730: 04/12/09: Re: Verilog Book Recommendation
    77041: 04/12/20: Re: PCB construction for PCI
    77233: 04/12/31: Re: Xilinx ISE : How to make Modelsim reload when design changed ?
    77409: 05/01/06: Re: Refresh rate in DDR-SDRAM
    77475: 05/01/07: Re: signals inside a process
    77480: 05/01/07: Re: ise mapping options limited
    77483: 05/01/07: Re: How to change temperature in Xilnx Webpack with free starter Modelsim
    77526: 05/01/09: Re: constraints
    77571: 05/01/11: Beware of Vref pins becoming "unused" (Xilinx)
    77583: 05/01/11: Re: Beware of Vref pins becoming "unused" (Xilinx)
    77608: 05/01/12: Re: (d)ram interface
    77673: 05/01/13: Re: Doubts in XCF01S Programming.txt
    77698: 05/01/14: Re: Resetting FIFO
    77783: 05/01/17: Re: newbie question regarding netlist resource constraint (EDIF)
    77836: 05/01/18: Re: Time constraints in ISE, help required
    77894: 05/01/19: Re: Very Stupid XST verilog synthesis question...
    77990: 05/01/21: Re: How does a SDRAM controller work?
    77991: 05/01/21: Re: Configuring FPGA using PROM/uP
    78014: 05/01/22: Re: Configuring FPGA using PROM/uP
    78100: 05/01/24: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
    78142: 05/01/25: Re: Configuring FPGA using PROM/uP
    78209: 05/01/26: Re: Spartan 2E and SDRAM
    78231: 05/01/26: Re: 60Hz clock on XC9572
    78270: 05/01/27: Re: Pin Sort
    78295: 05/01/28: Re: LVDS without termination
    78296: 05/01/28: Re: Pin Sort
    78300: 05/01/28: Re: Xilinx ISE 6.3i compxlib freeze
    78384: 05/01/31: Re: LVDS without termination
    78385: 05/01/31: Re: Actel A54SX72A - FF with clear and preset? Necessary for triple redundant register
    78415: 05/01/31: Re: LVDS without termination
    78422: 05/01/31: Re: Temat:Re: Actel A54SX72A - FF with clear and preset? Necessary for triple redundant register
    78453: 05/02/01: Re: Input logic level on Spartan 3?
    78455: 05/02/01: Re: Asynchronous Inputs Question
    78457: 05/02/01: Re: gate/xilinx slice
    78465: 05/02/01: Re: gate/xilinx slice
    78483: 05/02/01: Re: Oscillator for Digilent Spartan 3 Starter Kit
    78528: 05/02/02: Re: Trouble with XilinxCoreLib\vhdl_analyze_order
    78578: 05/02/03: Re: Help on a FPGA design
    78579: 05/02/03: Re: LVDS without termination
    78593: 05/02/03: Re: LVDS without termination
    78595: 05/02/03: Re: Help on a FPGA design
    78621: 05/02/04: Re: Finding DDR SDRAM SODIMM(200 pin) socket.
    78625: 05/02/04: Re: How to locate a net in the design
    78746: 05/02/07: WARNING:Xst:382 - Why so many?
    78769: 05/02/07: Re: WARNING:Xst:382 - Why so many?
    78819: 05/02/08: Re: opb_ddr connection to DDR chips
    78876: 05/02/09: Re: Resetting FIFO
    79042: 05/02/11: Re: doubt on configuring FPGA
    79202: 05/02/15: Re: Any Altera FIFO not a power of 2?
    79317: 05/02/17: Re: Any Altera FIFO not a power of 2?
    79585: 05/02/21: Re: does anyone have a c compiler for the picoblaze
    79605: 05/02/21: Re: Jitter and Static Timing Analysis
    79881: 05/02/25: Re: IP unnecessarily using Spartan-3 DCM?
    79882: 05/02/25: Re: EC/ECP Map Problem
    80079: 05/03/01: Re: SR latches in Xilinx devices?
    80080: 05/03/01: Re: I2C protocol to communicate between FPGAs
    80281: 05/03/03: Re: HELP!!! Interfacing Virtex-4 FPGA with SDR SDRAM
    80321: 05/03/03: Re: programming ATF750 in ABEL
    80322: 05/03/03: Re: SR latches in Xilinx devices?
    80357: 05/03/04: Re: SR latches in Xilinx devices?
    80491: 05/03/07: Re: XST block ram init in include files
    80504: 05/03/07: Re: Help with 22v10 and WinCupl :(
    80559: 05/03/08: Re: Guideline for PCB routing for PCI signal
    80563: 05/03/08: Re: Good, affordable verilog simulator
    80591: 05/03/08: Re: Basic cheap fpga configuration
    80633: 05/03/09: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
    80634: 05/03/09: Re: SPROM for Spartan II
    80903: 05/03/14: Re: ISE build dependencies
    80904: 05/03/14: Re: Which HDL?
    80905: 05/03/14: Re: FPGA programming
    80937: 05/03/14: Re: seriel prom
    80970: 05/03/15: Re: Memory gate count in ASIC and in FPGA
    81015: 05/03/16: Re: Sensitivity list
    81678: 05/03/29: Re: ISE
    81823: 05/04/01: Re: ABEL alias names
    82512: 05/04/13: Re: Reading old F2.1i schematics
    82524: 05/04/13: Re: question using xapp333
    82798: 05/04/18: Re: increase in delay when a port was removed from design (Xilinx Project Navigator 5.2i)
    82882: 05/04/19: Re: re:Spartan 3 to tempsensor interface
    82952: 05/04/20: Re: OV6620 PCLK CLK
    83035: 05/04/21: Re: JTAG and SPROM for Spartan II-e
    83058: 05/04/22: Re: Timing Reports Xilinx.....Max. freq of operation?
    83159: 05/04/25: Re: re:Spartan 3 to tempsensor interface
    83262: 05/04/26: Re: "Implement Design" Error on ISE 6.3 webpack
    83297: 05/04/27: Re: Proper use of BUFGMUX and DCM in Spartan 3
    83303: 05/04/27: Re: Virtex slow clock multiply options?
    83362: 05/04/28: Re: Signal use from pin
    83383: 05/04/28: Re: Virtex slow clock multiply options?
    83414: 05/04/29: Re: Map Error: "RLOC not supported for simple gates"
    83564: 05/05/03: Re: 200+ MHz through a SCSI cable
    83908: 05/05/09: Re: Flagging XST to suppress the warning
    84013: 05/05/11: Re: Xilinx versus Elixent; other radically different concepts?
    84080: 05/05/12: Re: Minimum circuit to get Spartan-3 running
    84107: 05/05/12: Re: Xilinx ISE 6.3 verilog simulation problem
    84158: 05/05/13: Re: Update Picoblaze Code in Bitstream
    84159: 05/05/13: Re: Update Picoblaze Code in Bitstream
    84172: 05/05/13: Re: How to turn off auto bufg insertion in ISE 7.1 ???
    84269: 05/05/16: Re: floorplanning
    84324: 05/05/17: Re: delays
    84325: 05/05/17: Re: Universal logic modules vs NAND-like modules
    84397: 05/05/18: Re: An FPGA eval board at $49!!
    84408: 05/05/18: Re: Problems with Constraints (Xilinx, ISE 6.3)
    84486: 05/05/19: Coloring by clock?
    84492: 05/05/19: Re: Coloring by clock?
    84544: 05/05/20: Re: Universal logic modules vs NAND-like modules
    84634: 05/05/23: Re: FSM stops working
    84667: 05/05/24: Re: VHDL vs. Schematic Capture
    84668: 05/05/24: Re: Project Navigator mapping problem with CLK and BRAM
    84748: 05/05/25: Re: warning place and route ise7.1?
    84763: 05/05/26: Re: Project Navigator mapping problem with CLK and BRAM
    84799: 05/05/27: Re: ISE 7.1 small advice about project files (.ISE extension)
    84870: 05/05/31: Re: Problems with SDRAM and Altera Cyclone
    84894: 05/05/31: Re: FPGA Boards
    84898: 05/05/31: Re: Xilinx DDR output registers
    85008: 05/06/02: Re: UARTlite problem..!!!
    85189: 05/06/06: Re: Hope for OS X tools...
    85191: 05/06/06: Re: Magical Mystery Tour of ISE environment variables
    85194: 05/06/06: Re: Clock doubler to double an input 13.5 Mhz
    85271: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
    85273: 05/06/07: Re: FPGA I/O pin current sink
    85522: 05/06/10: Re: I2C clock stretching(XILINX reference design)
    85528: 05/06/10: Re: SPD interface(Serial presence detect)
    85667: 05/06/13: Re: SPD interface(Serial presence detect)
    85669: 05/06/13: Re: SPD interface(Serial presence detect)
    85818: 05/06/16: Re: re:Problem for xilinx!!!
    85820: 05/06/16: Re: question regarding "Add I/O buffers" option - SOS
    85876: 05/06/17: Re: comp.arch.fpga.<mfr>
    85879: 05/06/17: Re: Good FPGA introduction book ?
    85880: 05/06/17: Re: Xilinx MAP problem (>1 External Macro Output Pin on single net)
    86078: 05/06/21: Re: Real Example of Xilinx IPCore Instantiation
    86188: 05/06/22: Re: Xilinx MacFir5.0 - Block Ram requirenments
    86298: 05/06/24: Re: Good FPGA introduction book ?
    86315: 05/06/24: Re: State of unused pins in Spartan II.
    86646: 05/07/01: Re: Foundation 3.1 in WinXP machine Problems!
    86647: 05/07/01: Re: Clock buffering in VirtexE FPGA
    86796: 05/07/06: Re: Spartan II 2s200 PCI Board
    86799: 05/07/06: Re: PC104 (ISA) bus in FPGA (Spatan 2E)
    86960: 05/07/11: Re: Search for FPGA
    86962: 05/07/11: Re: output-value isn't stored
    86993: 05/07/12: Re: Xilinx Conversion 3.1 --> 6.1
    87010: 05/07/12: Re: Xilinx Conversion 3.1 --> 6.1
    87077: 05/07/14: Re: Why cann't this block be synthesized in top level
    87078: 05/07/14: Re: Doubts on Xilinx FPGA
    87105: 05/07/15: Re: Bus Macros
    87120: 05/07/15: Re: Bus Macros
    87160: 05/07/18: Re: Doubts on Xilinx FPGA
    87389: 05/07/22: Re: Place Error
    87531: 05/07/25: Re: Free 8 bit micro for fpga
    88061: 05/08/08: Re: Hiding data inside a FPGA
    88062: 05/08/08: Re: sequence detection using shift register approach
    88158: 05/08/10: Xilinx: Where has all the data gone?
    88159: 05/08/10: Re: Xilinx: Where has all the data gone?
    88184: 05/08/11: Re: Using an oscillator in a rugged environment
    88229: 05/08/12: Re: Regarding clock muxing
    88231: 05/08/12: Re: high speed image capture
    88365: 05/08/16: Re: XC5200 tool help needed
    88366: 05/08/16: Re: image sensor
    88537: 05/08/22: Re: What is the diffrences between lattice's FPGA and Xilinx's FPGA
    88640: 05/08/24: Re: Software simulation of hardware evolution
    88910: 05/08/31: Re: Gated clock for FPGA (verilog)???
    88911: 05/08/31: Re: Hi-Z input
    88980: 05/09/01: Xilinx and Lattice tools on one machine?
    89150: 05/09/06: Re: Reading internal signals through a testbench.
    89355: 05/09/13: Re: Reading a PAL fusemap with a microscope
    89421: 05/09/14: Re: Is a CPLD appropriate for this triple PWM application?
    89637: 05/09/21: Re: Count "1" bit in bit stream
    89685: 05/09/22: Re: Xilinx Webpack Schematic
    89716: 05/09/23: Re: Synchronizer Flip Flop / Metastability
    89776: 05/09/26: Re: Question on Metastability
    89777: 05/09/26: Re: Xilinx PAR -- WARNING:Route - CLK Net may have excessive skew...
    89892: 05/09/29: Re: Preloading SDRAM?
    89979: 05/09/30: Re: Xilinx and Lattice tools on one machine?
    90677: 05/10/18: Re: Carry Chain Design
    90873: 05/10/24: Re: Best Async FIFO Implementation
    91549: 05/11/08: Re: Internal signal to drive clock resources
    91552: 05/11/08: Re: Delay insertion in Xilinx Verilog
    91664: 05/11/10: Re: Coolrunner output pins stuck at 0V
    91760: 05/11/11: Re: Add files to Xilinx ISE Project w/script
    91861: 05/11/15: Re: Rise time/fall time for Spartan3 clock inputs
    91916: 05/11/16: Re: Lattice XP flash memory access.....
    91934: 05/11/17: Re: complexity of arithmetic
    91979: 05/11/18: Re: Setting the environment variable in ISE 7.1?
    92051: 05/11/21: Re: Sounds or other means to indicate end of compilation in Xilinx ISE
    92395: 05/11/29: Re: Cypress FX2 bandwidth problem
    92396: 05/11/29: Re: Xilinx 'unconstrained period' problem
    92475: 05/11/30: Re: Q-bus or Unibus bus transactions in FPGA?
    92476: 05/11/30: Re: grabbing PCI signals, rev-eng dev board
    92477: 05/11/30: Re: ISE 6.3 equivalent_register_removal off
    92810: 05/12/07: Re: FPGA development board with digital image camera
    93036: 05/12/12: Re: 3/2 with virtex 300
    93123: 05/12/14: Re: Can ISE 4.2 program Virtex 2 6000K devices?
    93125: 05/12/14: Re: Question about Progamming File generation report
    93390: 05/12/21: Re: Mean value filter
    94401: 06/01/11: Re: FPGA configuration time for PCI identification ?
    94404: 06/01/11: Re: SDRAM Clock Skew
    94450: 06/01/11: Re: SDRAM Clock Skew
    94405: 06/01/11: Re: Samples
    94484: 06/01/12: Re: UCF-File problem
    94483: 06/01/12: Re: Newbe Startup Time Question
    94543: 06/01/13: Re: PCI e clocking
    94545: 06/01/13: Re: PCI e clocking
    94683: 06/01/16: Re: New PCI extender
    94681: 06/01/16: Re: programming devices using other tools
    94884: 06/01/18: Re: FIFO in SDRAM
    94922: 06/01/19: Re: PCI arbiter (doubt in REQ signal)
    95407: 06/01/23: Re: V4 not packing registers into IOBs
    95426: 06/01/23: Re: V4 not packing registers into IOBs
    95429: 06/01/23: Re: need for a group FAQ?
    95469: 06/01/23: Re: need for a group FAQ?
    95576: 06/01/24: Re: help:dual-edge flip-flop possible using Verilog?
    95683: 06/01/25: Re: problem to synthetize with ISE
    96091: 06/01/30: Re: Acquiring video frames and processing pixels in Xilinx
    96317: 06/02/01: Re: BGA central ground matrix
    96541: 06/02/06: Re: Mixing and matching related clocks question.
    96655: 06/02/08: Re: I2C timing problem
    96665: 06/02/08: Re: NMEA Decoder/Display
    96720: 06/02/09: Lattice high-end devices announced after years of rumours...
    97094: 06/02/16: Re: DDR SDRAM Controller
    97095: 06/02/16: Re: pci express ac coupling
    97099: 06/02/16: Re: delay using integrator
    97103: 06/02/16: Re: CPLD-SPI_flash configuration system problem.
    97144: 06/02/17: Re: DDR SDRAM Controller
    97145: 06/02/17: Re: CPLD-SPI_flash configuration system problem.
    97367: 06/02/21: Re: help with VGA timings
    97391: 06/02/21: Re: Is FPGA code called gateware?
    97457: 06/02/22: Re: FPGA to ASIC migrate
    97502: 06/02/23: Re: DDR SDRAM Controller
    97761: 06/02/27: Re: FPGA to ASIC migrate
    97881: 06/03/01: Re: FPGA communication, I2C and DAC
    97901: 06/03/01: Re: problem with ISE versions
    97997: 06/03/02: Re: Assign FPGA pins to submodule
    98149: 06/03/06: Re: Pullup questions on Spartan3
    98351: 06/03/08: Re: problem
    98788: 06/03/16: Re: CSV files available for Xilinx FPGA parts pinouts?
    99390: 06/03/23: Re: FPGA : Spartan-3e configuration failure
    99697: 06/03/28: Re: Hand-drawn schematic symbols of ISE coregen cores revert to rectangles when underlying core parameters are changed!
    99803: 06/03/29: Re: Xilinx ISE DRC: An antenna found
    99857: 06/03/30: Re: PCB Bypass Caps
    100212: 06/04/05: Re: Dual-edge synthesizable D flip-flop - any pitfalls?
    100213: 06/04/05: Re: about the low power design
    100214: 06/04/05: Re: Lattice ispLever Starter Download
    100473: 06/04/10: Re: xilinx DCM Timing warning
    100788: 06/04/18: Re: Implementation of cascadable shift register in virtex FPGA
    100935: 06/04/21: Re: How to trsiate o/p pins?
    100937: 06/04/21: Re: Initializing array of BlockRAM instances in verilog
    100962: 06/04/21: Re: XST duplicate register option does not work
    100963: 06/04/21: Re: Initializing array of BlockRAM instances in verilog
    101106: 06/04/25: Re: Initializing array of BlockRAM instances in verilog
    101348: 06/04/29: Re: URGENT: Xilinx site
    101418: 06/04/30: Re: Xilinx PROM
    101542: 06/05/02: Re: bizzare unexplained random errors w/ Lattice 4256V CPLD
    101578: 06/05/03: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    102263: 06/05/12: Re: clock multiplier in spartan 2
    103285: 06/05/30: Re: Mains pick-up on I/O pins
    103286: 06/05/30: Re: Personalization of Xilinx ISE
    103340: 06/05/31: Re: Personalization of Xilinx ISE
    103538: 06/06/05: Re: ProjectMgmt WARNING from ISE 8.1i XST
    103546: 06/06/05: Re: Changing the random seed in Xilinx tools
    103547: 06/06/05: Re: Xilinx constraining : differential clocks and other details
    103669: 06/06/07: Re: ise8.1 picking local instead of global clk routing?
    104474: 06/06/28: Re: Preserve patent materials through a notary
    104561: 06/06/29: Re: Stopping the clock for power management
    104583: 06/06/30: Re: Carry-chain based tapped delay line in Spartan3 - resolution? PVT variability?
    104734: 06/07/05: Re: Weird timing failure
    104938: 06/07/10: Re: recognizing multiple fpga's
    104979: 06/07/11: Re: debouncing a switch (in hardware)
    105007: 06/07/11: Re: Development Boards -Your chance to suggest features
    105008: 06/07/11: Re: DLL in spartan2e
    105242: 06/07/18: Re: Partial shift register extraction in ISE
    105272: 06/07/19: Re: Partial shift register extraction in ISE
    105573: 06/07/26: Re: How to phase align a 10MHz clock using V4LX60 DCM
    105612: 06/07/27: Re: IOBDELAY and DCM
    105761: 06/07/31: Re: How do I create a clock with random starting phase?
    105768: 06/07/31: Re: large data access to SDRAM at fixed frequency
    106062: 06/08/07: Re: How do I treat "default" case which is useless?
    106217: 06/08/09: Re: Xilinx PCI Core & CardBus
    106240: 06/08/09: Re: Xilinx PCI Core & CardBus
    106309: 06/08/11: Re: TIG on Xilinx Asynch FIFO?
    106554: 06/08/15: Re: NgdBuild:604 error
    106758: 06/08/18: Re: Problems about the synthesis(XST)
    106918: 06/08/22: Re: Using multi-cycle contraint and simulate it correctly
    106919: 06/08/22: Re: OFFSET with DCM NET or derived NET?
    107488: 06/08/29: Re: Do I need to adjust sdram clk shift when i lower my system clock?
    107738: 06/08/31: Re: virtex xcv:no way to see TDO moving:
    107803: 06/09/01: Re: PCI/PCI-X IDSEL
    108096: 06/09/05: Re: Please help me with (insert task here)
    108125: 06/09/05: Re: FIFO with EBR
    108305: 06/09/07: Re: Synchronous Clocks
    108505: 06/09/12: Re: X4000 bad configuration
    108646: 06/09/14: Re: XIlinx Spartan 2E stuck in configuration mode
    108775: 06/09/16: Re: How to handle UCF file
    108864: 06/09/18: Re: Spartan3: Multiplier Madness
    108925: 06/09/19: Re: Lattice ECP2/M
    108926: 06/09/19: Re: ddr clock issues
    108979: 06/09/19: Re: ddr clock issues
    109143: 06/09/21: Re: ddr clock issues
    109144: 06/09/21: Re: DCM and domain crossing
    109250: 06/09/22: Re: Lattice .bit file format
    109251: 06/09/22: Re: X4000 bad configuration
    109408: 06/09/26: Re: state machine dead problem
    109475: 06/09/27: Re: Configuration of Spartan 3 devices
    110525: 06/10/17: Re: echo $LM_LICENCE_FILE not working
    110526: 06/10/17: Re: how to change cclk frequency ?
    110721: 06/10/20: Re: echo $LM_LICENCE_FILE not working
    110732: 06/10/20: Re: Getting info from XST, Homework Question, netlist, reports, etc...
    110800: 06/10/23: Re: Camera link specification
    110891: 06/10/25: Re: Camera link specification
    110892: 06/10/25: Re: Camera link specification
    110895: 06/10/25: Re: Single Bank Vs Multiple Banks in sdram
    111230: 06/10/31: Re: Xilinx Virtex4 Outputs for Camera Link
    111692: 06/11/08: Re: Graphics-2-FPGA
    111754: 06/11/09: Re: abel to vhdl converter
    111755: 06/11/09: Re: ZBT Bus
    111797: 06/11/10: Re: pin name misspelling error!
    111798: 06/11/10: Re: Field Programmable Object Array
    112059: 06/11/15: XCF02S + Spartan 2e JTAG config problems
    112139: 06/11/16: Re: XCF02S + Spartan 2e JTAG config problems
    112760: 06/11/28: Re: Spartan3 Configuration Puzzler
    112791: 06/11/29: Re: DVI clock generation
    112876: 06/11/30: Re: So who has used Lattice FPGAs recently?
    112942: 06/12/01: Re: So who has used Lattice FPGAs recently?
    112995: 06/12/04: Re: Digitally Controlled Impedance with Lattice ECP2M FPGA's
    113093: 06/12/06: Re: Readback Jtag Problem
    113108: 06/12/06: Re: Free Anydivider, Divide clock by any number
    113216: 06/12/08: Re: Problem with connecting higher order address lines of SDRAM to FPGA
    113231: 06/12/08: Re: Xilinx platform flash data sheet confusion (ds123) for clocking
    113233: 06/12/08: Re: FFT on Virtex-II Pro (how to download .dat file?)
    113241: 06/12/08: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
    113358: 06/12/11: Re: Free Anydivider, Divide clock by any number
    113382: 06/12/12: Re: Question about Verilog Semantics / Xilinx Synthesis of embedded EMAC
    113526: 06/12/15: Re: electrical interface problem LVPECL - LVDS multi-inputs
    113548: 06/12/15: Re: Xilins ISE Re-Creating Projects
    113615: 06/12/18: Re: unpredictable FPGA behaviour
    113689: 06/12/19: Re: PLL minimum input clock frequency
    113700: 06/12/19: Re: Need book for verilog on xc9536?
    113730: 06/12/20: Re: CPLD speed/temperature equivalent
    114291: 07/01/10: Re: Is this Multi-Cycle Path ?
    114593: 07/01/19: Re: Altera EP2S60 rebooting itself
    114676: 07/01/22: Re: Clock constraints
    114859: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
    114936: 07/01/26: Re: video buffering scheme, nonsequential access (no spatial locality)
    115068: 07/01/30: Re: video buffering scheme, nonsequential access (no spatial locality)
    115111: 07/01/31: Re: Global Clocks in Xilinx ISE
    115129: 07/01/31: Re: Question about simple design
    115174: 07/02/01: Re: Xilinx (without init value) has a constant value of 0?
    115176: 07/02/01: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
    115198: 07/02/02: Re: Xilinx (without init value) has a constant value of 0?
    115200: 07/02/02: Re: circle generation algorithm
    115503: 07/02/12: Re: Problem with floating inputs on LVDS ports
    115547: 07/02/13: Re: Which is your favorite FPGA language?
    115558: 07/02/13: Re: Typical clock frequencies of FPGA designs
    115566: 07/02/13: Re: Problem with floating inputs on LVDS ports
    115685: 07/02/16: Re: Lattice / M-LVDS
    116149: 07/03/02: Re: XST ucf timespec
    116329: 07/03/07: Re: Where do I find CMOS image sensors and lenses?
    116539: 07/03/12: Re: Dual edge detection
    116629: 07/03/14: Re: Heatsink on FPGA?
    116631: 07/03/14: Re: Xilinx FPGA, OFFSET OUT AFTER
    116633: 07/03/14: Re: interface ad9229 with altera stratix II
    116634: 07/03/14: Re: Xilinx Netlist
    116877: 07/03/20: Re: Xilinx ISE Inferred block rams
    117122: 07/03/23: Re: Flash memmory model
    117344: 07/03/28: Re: How is it possible to design a convolutional interleaver with sequential memory writes?
    117411: 07/03/30: Re: xilinx ise/edk/modelsim - what does compilation really do?
    117421: 07/03/30: Re: Another simple DCM question
    117429: 07/03/30: Re: Another simple DCM question
    117431: 07/03/30: Re: ModelSim VHDL Pragmas
    117488: 07/04/02: Re: Config PROM for Spartan II
    117604: 07/04/04: Re: Gray code in asynchronous FIFO design
    117628: 07/04/05: Re: suitability of systolic architecture on FPGA
    117774: 07/04/10: Re: is there any opensource alternatives to platformstudio and microblaze development?
    117834: 07/04/11: Re: Xilinx WebCase support
    117837: 07/04/11: Re: FIFO newbie question
    117853: 07/04/11: Re: OT. Re: POC at Element CXI
    117855: 07/04/11: Re: has anyone used mathstar field programmable object arrays?
    117876: 07/04/12: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
    118084: 07/04/17: Re: par [placer] consistency
    118118: 07/04/17: Re: Block RAM strange behavior, address off by one
    118201: 07/04/19: Re: Question about Xilinx ISE (problem with signals trimming)
    118250: 07/04/20: Re: FPGA Newbie
    118256: 07/04/20: Re: Looking for a spartan 3 board
    118305: 07/04/23: Re: DONE problems
    118353: 07/04/24: Re: FPGA and DAC for wave generation
    118448: 07/04/26: Re: Sscanf replacement for xilinx EDK
    118510: 07/04/28: Re: Placement error for adjacent pins
    118514: 07/04/28: Re: TigerSHARC TS201 to PLX 9656
    118516: 07/04/28: Re: Placement error for adjacent pins
    118528: 07/04/29: Re: Problem cascading 2 DCMs
    118703: 07/05/02: Re: prevent ROM inferration
    118704: 07/05/02: Re: Unused Pin setting on per-pin basis
    118791: 07/05/03: Re: Unused Pin setting on per-pin basis
    118800: 07/05/03: Re: Unused Pin setting on per-pin basis
    118801: 07/05/03: Re: Select pullup, pulldown or none via embedded S/W
    118805: 07/05/03: Re: Video scaler for Spartan 3E?
    118911: 07/05/07: Re: Disable Readback (XILINX)?
    119163: 07/05/14: Re: Camera Control
    119229: 07/05/15: Re: reading IDCODE from parallel bus?
    119294: 07/05/16: Re: Unable to scan JTAG chain
    119486: 07/05/21: Re: UART Receiver Parity Check
    119509: 07/05/21: Re: How to insert tab in Write() function in VHDL
    119588: 07/05/23: Re: SelectIO banking rules
    119593: 07/05/23: Re: System-synchronous interface clocking between FPGA's
    119661: 07/05/24: Re: Xilinx 8.2 : Multippass P&R
    119672: 07/05/24: Re: Xilinx 8.2 : Multippass P&R
    119743: 07/05/25: Re: VGA signal through breadboard?
    119969: 07/05/30: Re: Best use of DCM in Spartan-3A?
    119971: 07/05/30: Re: spartan-iie
    120243: 07/06/04: Re: TBUF and modular design flow on spartan
    120247: 07/06/04: Re: CoreGen Issues ??
    120809: 07/06/17: Xpower complains about Vccint for Spartan 3A
    120812: 07/06/17: Re: Xpower complains about Vccint for Spartan 3A
    120864: 07/06/19: Re: .xco file and vcs verilog compiler
    121189: 07/06/27: Re: Bidirectional LVDS
    121221: 07/06/28: Re: How to write constraints with a clock enable?
    121478: 07/07/05: Re: Doubt in Asynchronus Circuit design
    121493: 07/07/05: Re: Spartan-3A: 200A & 400A Image problems / variance...
    121516: 07/07/06: Re: Doubt in Asynchronus Circuit design
    121518: 07/07/06: Re: Doubt in Asynchronus Circuit design
    121632: 07/07/10: Re: slave serial configuration of Vertex FPGA using a microcontroller
    121659: 07/07/11: Re: ISE 9.1i - Process Map Fail without any Error messages
    121856: 07/07/13: Re: Seeing failures when clocking system-synchronous inter-FPGA interfaces at lower clock rates
    122073: 07/07/18: Re: 8B/10B decoding after serial transmission problem?
    122197: 07/07/23: Re: On I2C protocol
    122250: 07/07/24: Re: On I2C protocol
    122321: 07/07/25: Re: On I2C protocol
    122335: 07/07/25: Re: Altera or Xilinx
    122375: 07/07/26: Re: Programing Vertex 4 FPGA by PIC
    122376: 07/07/26: Re: verilog parser question about `defines
    122520: 07/07/30: Re: Restricting XST parameter widths from .mpd files?
    123019: 07/08/14: Re: Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438)
    123023: 07/08/14: Re: Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438)
    123058: 07/08/15: Re: SDRAM Controller
    123165: 07/08/17: Re: synthesis showing warning (replicated 1 time(s) to handle iob=true attribute.)
    123217: 07/08/20: Re: Voltage translation question
    123232: 07/08/20: Re: At what frequencies is it acceptable to generate a clock from a register?
    123350: 07/08/24: Re: Samtec PowerPoser power filtering solution.
    123351: 07/08/24: Re: Annoying
    123352: 07/08/24: Re: xilinx impact 9.2 problem
    123436: 07/08/28: Re: ANNC: FPGA Noise Fundamentals Webcast
    123437: 07/08/28: Re: PLL Power and m/n ratio
    123439: 07/08/28: Re: VHDL clocking scheme VS Verilog clocking scheme
    123441: 07/08/28: Re: Xilinx Virtex IOB Regiters and Noise???
    123445: 07/08/28: Re: PCB Layers
    123473: 07/08/28: Re: PCB Layers
    123509: 07/08/29: Re: Strange behaviour of a design
    123529: 07/08/29: Re: PCIe question
    123530: 07/08/29: Re: PLL Power and m/n ratio
    123565: 07/08/30: Re: New Xilinx forum.
    123567: 07/08/30: Re: Spartan3E and DDR termination
    123568: 07/08/30: Re: Strange behaviour of a design
    123570: 07/08/30: Re: Output signals not synchronized
    123578: 07/08/30: Re: Output signals not synchronized
    123581: 07/08/30: Re: Spartan3E and DDR termination
    123582: 07/08/30: Re: Reconfiguration of a XUP Board
    123652: 07/08/31: Re: PCIe question
    123760: 07/09/04: Re: ERROR:NgdBuild:604 with user ipcore
    123780: 07/09/04: Re: Spartan3E and DDR termination
    123783: 07/09/04: Re: Multiple CPLDs on a PCB.
    123819: 07/09/05: Re: clock skew problems
    123822: 07/09/05: Re: high bandwitch ethernet communication
    123893: 07/09/06: Re: Free downloadable PDF graph paper.
    124009: 07/09/10: Re: How to simple convert a hex or mif file from Altera to Xilinx coe file?
    124260: 07/09/17: Re: post translate and post PAR problems with XST and Modelsim
    124261: 07/09/17: Re: Virtex-4 PCB design
    124262: 07/09/17: Re: clock skew problems
    124287: 07/09/17: Re: Altera / Lattice / Xilinx CPLDs ?
    124309: 07/09/18: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
    124310: 07/09/18: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
    124443: 07/09/21: Re: Gated Clock Problems
    124521: 07/09/25: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
    124545: 07/09/26: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
    124588: 07/09/27: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
    124593: 07/09/27: Re: UCF Constraints: drive and slew
    124617: 07/09/28: Re: FPGA NTSC signal with 2 resistors and PWM
    124660: 07/09/29: Re: Never buy Altera!!!!
    124713: 07/10/01: Re: Count Leading Zero (CLZ) possible by MicroBlaze??
    124748: 07/10/02: Re: Test and Measurements - Large FPGA
    124754: 07/10/03: Re: Partial/Incorrect configuration of FPGA from flash PROM.
    124817: 07/10/05: Re: How to do one hot state machine in verilog for Xilinx V5 using XST
    124872: 07/10/09: Re: CY22393
    125203: 07/10/17: Re: FPGA to FPGA Bus
    125240: 07/10/18: Re: What to consider for source synchronous clocking?
    125274: 07/10/18: Re: What to consider for source synchronous clocking?
    125383: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
    125445: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
    125446: 07/10/25: Re: ISE PACE Question
    125480: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
    125481: 07/10/26: Re: Power supply filter capacitors
    125664: 07/10/31: Re: Updating my bookshelf
    125797: 07/11/05: Re: FPGA I/O Selection in UCF
    125825: 07/11/06: Re: not totally repulsive
    125826: 07/11/06: Re: May i program a Spartan 3 fpga with a 1,8 V Digilent cable?
    125919: 07/11/08: Re: FIFO interface design
    125921: 07/11/08: Re: Non-volatile FPGA in a small package
    126013: 07/11/12: Re: Spartan3E Slave Serial Daisy chain
    126027: 07/11/12: Re: Programming connection
    126050: 07/11/13: Re: Spartan3E Slave Serial Daisy chain
    126407: 07/11/21: Re: Xilinx XST 8.2, Error on multi-source, bug?
    126561: 07/11/27: Re: CPU design uses too many slices
    126910: 07/12/05: Re: Mixed language design
    127049: 07/12/10: Re: Xilinx ise 9.2i clean up project files
    127082: 07/12/11: Re: Xilinx ise 9.2i clean up project files
    127118: 07/12/12: Re: Xilinx ise 9.2i clean up project files
    127145: 07/12/12: Re: FPGA Board design basics
    127339: 07/12/18: Re: Xilinx DCM outputs for DDR
    127406: 07/12/20: Re: Xilinx Spartan 3 JTAG issues
    127609: 08/01/03: Re: Camera connection on XUPV2P
    127646: 08/01/04: Re: Camera connection on XUPV2P
    127647: 08/01/04: Re: Vendors of FPGA's
    127769: 08/01/07: Re: Camera connection on XUPV2P
    127819: 08/01/08: Re: Warning 'clock has been changed'
    127857: 08/01/09: Re: Using DDR SDRAM as single data rate ..?
    127860: 08/01/09: Re: Camera connection on XUPV2P
    127906: 08/01/10: Re: Camera connection on XUPV2P
    127910: 08/01/10: Re: Using DDR SDRAM as single data rate ..?
    127925: 08/01/10: Re: How to program and initialize Lattice XP devices
    128112: 08/01/15: Re: Question on FPGA
    128142: 08/01/16: Re: V5-SYSMON : MAX6043 suitable?
    128213: 08/01/18: Re: Xpower decoupling network summary
    128214: 08/01/18: Re: Xilinx ISE9.2 iMPACT manual
    128217: 08/01/18: Re: CPLD Pad File
    128231: 08/01/18: Re: ?FIR on GPU,CPU, FPGA, ASIC
    128273: 08/01/19: Re: VHDL Micron memorymodel.
    128429: 08/01/25: Re: Craignell FPGA DIP Module
    128510: 08/01/29: Re: equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera
    128511: 08/01/29: Re: Grisoft AVG false positve virus detection in Xilinx software.
    128547: 08/01/30: Re: Grisoft AVG false positve virus detection in Xilinx software.
    128550: 08/01/30: Re: Spartan3 I/O question
    128591: 08/01/31: Re: About 10-bit pixel datum from CMOS image sensor
    128592: 08/01/31: Re: Xilinx prom programming problem
    128619: 08/01/31: Re: Why does a 36 x 36 Multiplier in a Xilinx Spartan 3E require 9
    128620: 08/01/31: Re: Xpower
    128722: 08/02/05: Re: Minimum Oscillator Frequency
    128724: 08/02/05: Re: How to optimize my design area to fit?
    128728: 08/02/05: Re: Possible CRC error on XC3S400 - now what?
    128752: 08/02/05: Re: Possible CRC error on XC3S400 - now what?
    128833: 08/02/07: Re: Prom alternatives for xilinx
    129266: 08/02/19: Re: Virtex 4 package layout
    129508: 08/02/26: Re: Interview questions
    129650: 08/03/01: Re: FPGA's be afraid, very afraid, of my wife!
    129777: 08/03/05: Re: Is there any way to disable JTAG for Sptantan3AN
    129832: 08/03/06: Re: I could run my program at DDR Sdram.
    129858: 08/03/07: Re: Spartan-3E + SPI EEPROM
    129874: 08/03/07: Re: Spartan-3E + SPI EEPROM
    129875: 08/03/07: Re: SiliconBlue enters the FPGA fray
    129916: 08/03/10: Re: its regarding to the Max Frequency in xilinx FPGA
    130077: 08/03/14: Re: Design entries for FSM
    130160: 08/03/17: Re: Xilinx Tristate Registration
    130223: 08/03/18: Re: Xilinx Tristate Registration
    130392: 08/03/21: Re: verilog question, break while loop to avoid combinational
    131092: 08/04/10: Re: Specifying strict setup constraint in ISE
    131185: 08/04/14: Re: "Multi-source in Unit" Verilog synthesis woes
    131442: 08/04/21: Re: Xilinx DDR2 Interface
    131654: 08/04/28: Re: the order in which some switches are turned on
    131791: 08/05/02: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
    132278: 08/05/20: Re: HELP: a Funny asynchronous input design
    132403: 08/05/26: Re: timing constraint is impossible to meet
    132686: 08/06/05: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132687: 08/06/05: Re: JTAG + PROM error!
    132715: 08/06/05: Re: Your favourite DSP textbooks/websites?
    132852: 08/06/09: Re: Deskew Clock on Synchronous Bus
    132908: 08/06/10: Re: Deskew Clock on Synchronous Bus
    132909: 08/06/10: Re: fpga reprogrammable?
    132932: 08/06/10: Re: Cheating the FPGA clock speed
    132949: 08/06/11: Re: Dram Refresh Controller Tutorial wanted
    132966: 08/06/11: Re: Cheating the FPGA clock speed
    133412: 08/06/27: Re: Xilinx register inits
    133413: 08/06/27: Re: Xilinx and RAM/ROM monitoring
    133426: 08/06/28: Re: Standard forms for Karnaugh maps?
    133532: 08/07/02: Re: Translate problem
    133552: 08/07/03: Re: minipci breadboard with fpga
    133628: 08/07/07: Re: FiFo Help Needed
    133673: 08/07/09: Re: JTAG IR length detection
    133674: 08/07/09: Re: 2 BUFIOs in the same clock-capable pair?
    133675: 08/07/09: Re: What's wrong with this Virtex4 DCM?
    133702: 08/07/10: Re: Can I store the output of my FPGA logic inside FPGA memory for
    133738: 08/07/12: Re: Strange ddr controller bugs.
    133740: 08/07/12: Re: How to simulate baud rate generator?
    133758: 08/07/13: Re: Mismatch simulation & post sythese results
    133776: 08/07/14: Re: xilinx core generator
    133781: 08/07/14: Re: First CPLD project
    133797: 08/07/15: Re: xilinx v5 ddr2 controller
    133812: 08/07/16: Re: No open-drain in V5 to drive an external LED?
    133814: 08/07/16: Re: Fifo Simulation Error
    133896: 08/07/18: Re: XAPP240 - Design Files
    133901: 08/07/18: Re: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
    134097: 08/07/25: Re: Prevent synthesis optimizations/simplifications in Xilinx-ISE
    134105: 08/07/25: Re: Xilinx FPGA editor tips?
    134128: 08/07/26: Re: Opencores DDR2 SDRAM controller with spartan3e starter board
    134141: 08/07/27: Re: Opencores DDR2 SDRAM controller with spartan3e starter board
    134221: 08/07/31: Question on ModelSim wave viewer
    134247: 08/08/01: Re: xilinx FPGA "program failed"
    134262: 08/08/02: Re: cpu,fpga, clock, dac, initialize sequence
    134276: 08/08/04: Re: Schematic Capture tutorials/books?
    134281: 08/08/04: Re: Chipscope - Clock Error
    134284: 08/08/04: Re: AC coupling on GTX RocketIO clocks
    134330: 08/08/06: Re: Downsizing Verilog synthesization.
    134353: 08/08/07: Re: Downsizing Verilog synthesization.
    134397: 08/08/08: Re: RS232 Interface
    134591: 08/08/20: Xilinx extends Spartan 3A series
    134625: 08/08/21: Re: video timing with TFP410
    134636: 08/08/22: Re: Question on ModelSim wave viewer
    134661: 08/08/25: Re: Analog Imager interface to FPGA
    134667: 08/08/25: Re: need fast FPGA suggestions
    134768: 08/08/29: Re: How many mux input on a Xilinx V4 are pratical
    134770: 08/08/29: Re: need fast FPGA suggestions
    134775: 08/08/29: Re: need fast FPGA suggestions
    134780: 08/08/29: Re: Xilinx Multipass PPR
    134950: 08/09/08: Re: Some feedback on the Xilinx web site
    134951: 08/09/08: Re: No connect pins on xc4vfx20
    134954: 08/09/08: Re: Signed multiplication
    134979: 08/09/09: Re: Placing Verilog busses using Xilinx RPMs
    134980: 08/09/09: Re: Some feedback on the Xilinx web site
    135324: 08/09/26: Re: decimal to ieee 754 single precision floating point
    135414: 08/10/01: Re: Interfacing DDR RAM
    135416: 08/10/01: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
    135428: 08/10/01: Re: which FPGA chip to use for FFT?
    135447: 08/10/02: Re: Xilinx device not listed
    135524: 08/10/06: Re: A question about the use of FPGA
    135525: 08/10/06: Re: Spartan 3E overmapping problem
    135528: 08/10/06: Re: ISE Question - FPGA Program.jpg (1/1)
    135529: 08/10/06: Re: Xilinx cores with license
    135546: 08/10/07: Re: trigger problem with chipscope
    135557: 08/10/08: Re: Another problem....
    135559: 08/10/08: Re: Those FPGA boards
    135564: 08/10/08: Re: How to synthesize a delay of around 10 ns in FPGA?
    135595: 08/10/09: Re: how to share infered ROM memories in synplify?
    135596: 08/10/09: Re: Xilinx VHDL inferred RAMs
    135632: 08/10/10: Re: Virtex-5 clocking
    135705: 08/10/13: Re: DDR FLOP?
    135708: 08/10/13: Re: More Actel 'Funnies'
    135856: 08/10/17: Re: Using GCK pin as both clock and signal (Spartan 2)
    135933: 08/10/22: Re: Interesting EDK error !!!
    135950: 08/10/23: Re: Spartan 3 IO banking rules problem in ISE
    135974: 08/10/24: Re: Need Lattice FUSE TABLE --->> LOGIC conversion service. $$$
    135975: 08/10/24: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
    136026: 08/10/28: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
    136082: 08/10/30: Re: Polmaddie1 - For Traffic Lights Junkies
    136108: 08/11/01: Re: timing issue with ISE10 SP3
    136131: 08/11/03: Re: blockram init file in spartan 3E
    136133: 08/11/03: Re: classic Spartan-3 DDR2 and IOBs
    136192: 08/11/05: Re: RS-232 Bus controller design in VHDL
    136194: 08/11/05: Re: Tiny JTAG connector
    136255: 08/11/07: Re: led programming
    136360: 08/11/12: Re: Using the FF @ Port pin
    136387: 08/11/13: Re: How to stop using a signed subtractor
    136401: 08/11/14: Re: How to stop using a signed subtractor
    136449: 08/11/17: Re: Spartan-3E SDRAM interface
    136452: 08/11/17: Re: Digilent Spartan3e starter kit, Not working.
    136473: 08/11/18: Re: spartan specifications
    136474: 08/11/18: Re: spartan 3A dsp fpga memory
    136500: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136501: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136507: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136510: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136518: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136548: 08/11/21: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
    136556: 08/11/21: Re: Generate sample rate ...
    136599: 08/11/24: Re: Extracting data from a VCD waveform format.
    136600: 08/11/24: Re: IDELAYCTRL for Xilinx virtex 5
    136607: 08/11/25: Re: FMC/VITA 57
    136618: 08/11/26: Re: Deserializing Camerlink on Spartan XC3s400
    136660: 08/11/28: Re: EPLD - FPGA - Is there a difference
    136705: 08/12/02: Re: reading registers
    136741: 08/12/03: Re: CameraLink Deserilization and Module Constraint Files
    136742: 08/12/03: Re: Hold Time Requirement
    136763: 08/12/04: Re: Timing analysis of related clocks
    136773: 08/12/04: Re: Project/File corruption problem with ISE 10.1
    136800: 08/12/05: Re: is it a bug?(Xilinx Xapp859 reference design: DDR2 SDRAM
    136815: 08/12/06: Re: V5 JTAG download weirdness
    136816: 08/12/06: Re: hi all
    136841: 08/12/08: Re: ISE doesn't work after a crash
    136842: 08/12/08: Re: Inverting bus connection order in Verilog
    136844: 08/12/08: Re: Xilinx UNISIM/SIMPRIM libraries
    136848: 08/12/08: Re: ISE doesn't work after a crash
    136865: 08/12/09: Re: Xilinx UNISIM/SIMPRIM libraries
    136901: 08/12/11: Re: How to insert ChipScope
    136931: 08/12/14: Re: i2c interface
    136932: 08/12/14: Re: FIFO with External Memory
    136954: 08/12/15: Re: JTAG / IMPACT / VIRTEX
    137022: 08/12/19: Re: FPGA partial/catastrophic failure mode question
    137108: 08/12/23: Re: DFFR using DFF (only, may be extra gates)
    137112: 08/12/23: Re: EDK map error 1492 - incompatible programming error
    137117: 08/12/23: Re: DFFR using DFF (only, may be extra gates)
    137206: 09/01/02: Re: error in synthesizing in ise although correct behavioral
    137218: 09/01/03: Re: time limited netlist generation
    137245: 09/01/05: Re: beginner synthesize question - my debounce process won't
    137346: 09/01/09: Re: FPGA on the fly syntesis and other stuff
    137389: 09/01/13: Re: beginner synthesize question - my debounce process won't
    137403: 09/01/14: Re: beginner synthesize question - my debounce process won't
    137410: 09/01/14: Re: ttl compatible
    137443: 09/01/16: Re: Duty Cycle change effects on Internal reg's
    137460: 09/01/18: Re: Using memory blocks generated by CoreGen
    137472: 09/01/19: Re: Using memory blocks generated by CoreGen
    137479: 09/01/19: Re: Differential bidirectional in VHDL (Xilinx)
    137486: 09/01/20: Re: Camlink Deserialization XAPP485 Clocks
    137533: 09/01/21: Re: Translate error
    137595: 09/01/22: Re: Problems when I download and install Xilinx ISE 10.1. Help
    137629: 09/01/24: Re: Xilinx web broken again?
    137630: 09/01/24: Re: Spartan chip expulses an extrange substance
    137634: 09/01/24: Re: Xilinx web broken again?
    137656: 09/01/26: Re: dual MIG controller on spartan 3A DSP
    137671: 09/01/27: Re: What software do you use for PCB with FPGA ?
    137676: 09/01/27: Re: Spartan3: 3.3V IOB on 2.5V config lines
    137797: 09/01/29: Re: Spartan chip expulses an extrange substance
    137798: 09/01/29: Re: new source wizard doesn't seem to work.
    137902: 09/02/02: Re: Cameralink Big Help Needed
    137928: 09/02/02: Re: Find instance name of BUFG inside DCM
    138108: 09/02/06: Re: how to cope with read cycle latency in block ram on Xilinx device
    138111: 09/02/06: Re: How to divide clock frequency......
    138222: 09/02/09: Re: Is this phase accumulator trick well-known???
    138248: 09/02/10: Re: How to make P&R route specified wires first when instantiating
    138252: 09/02/10: Re: pulser problem
    138283: 09/02/12: Re: Read a PS2 Keyboard input
    138284: 09/02/12: Re: Implementing reset / enable in FPGA question
    138337: 09/02/16: Re: virtex 5 decoupling
    138338: 09/02/16: Re: Virtex 5 slave serial config
    138387: 09/02/18: Re: VHDL long elsif state machine
    138396: 09/02/19: Re: VHDL long elsif state machine
    138476: 09/02/24: Lattice announces ECP3
    141536: 09/06/26: Lattice Universal File Writer - command line problems
    143569: 09/10/16: Re: FSM-states after reconf.
    143636: 09/10/19: Re: How to inspect values in a Xilinx core FIFO with Modelsim?
    143637: 09/10/19: Re: where can price list of FPGA be found?
    143639: 09/10/19: Re: FSM-states after reconf.
    143640: 09/10/19: Re: problem while receiving negative integer in microblaze
    143655: 09/10/20: Re: problem while receiving negative integer in microblaze
    143833: 09/10/28: Re: ISe 10.1 nightmare bug
    143860: 09/10/30: Re: Simple state machine output question
    143862: 09/10/30: Re: Trouble in booting V5 FPGA from SPI flash.
    143881: 09/10/31: Re: Chipscope with Verilog
    143899: 09/11/02: Re: Need some help creating a ring oscillator on a Spartan-3AN
    143931: 09/11/03: Re: initialization issues on Spartan-3E after startup
    143932: 09/11/03: Re: ModelSim view internal signals in instantiated verilog modules
    143943: 09/11/04: Re: problem fpga aera optimization
    143951: 09/11/04: Re: initialization issues on Spartan-3E after startup
    143979: 09/11/05: Re: Does anyone ever use placement?
    144087: 09/11/10: Re: Dealing wiht multiple clock domain...cleanly?
    144106: 09/11/11: Re: Having trouble with Xilinx timing constraints
    144107: 09/11/11: Re: 1.8V LVDS on spartan3A DSP
    144118: 09/11/11: Re: XPLA3 coolrunner programming tool?
    144134: 09/11/12: Re: max. sinking current of XC95144xl cpld
    144141: 09/11/13: Re: An incomplete Mux and Latch?
    144147: 09/11/13: Re: An incomplete Mux and Latch?
    144149: 09/11/13: Re: New blog post on alphas in packagin
    144162: 09/11/15: Re: New blog post on alphas in packagin
    144163: 09/11/15: Re: New blog post on alphas in packagin
    144200: 09/11/19: Re: TimingAnalyzer -- Build Timing Diagrams directly from VHDL or
    144213: 09/11/20: Spartan 6 migration whitepaper points out some significant changes
    144216: 09/11/20: Re: ML605 Evaluation Kit and FPGA Mezzanine Connectors (FMC) ?
    144280: 09/11/24: Re: Deskew Reginal clock input
    144288: 09/11/24: Re: Deskew Reginal clock input
    144335: 09/11/27: Re: webpack crashed how do I get these things back?
    144345: 09/11/28: Re: vga in virtex 4
    144406: 09/12/04: Re: Problem with Xilinx ISE and Spartan3
    144414: 09/12/04: Re: very wide counter (42-bit)
    144421: 09/12/05: Re: BRAM usage in synplify pro
    144437: 09/12/07: Re: BRAM usage in synplify pro
    144444: 09/12/08: Re: Rotating priority encoder and shifters in XST
    144470: 09/12/09: Re: Measure accurate time with a 50MHz FPGA - what are the limits?
    144478: 09/12/09: Re: very wide counter (42-bit)
    144699: 09/12/24: Re: Problem with Xilinx ISE and Spartan3
    144847: 10/01/07: Re: new PC specs for Xilinx tools
    144930: 10/01/15: Re: Which WebPack for old Spartan and Spartan-2?
    144947: 10/01/16: Re: Simulation of VHDL code for a vending machine
    144957: 10/01/17: Re: Simulation of VHDL code for a vending machine
    144973: 10/01/18: Re: Simulation of VHDL code for a vending machine
    144974: 10/01/18: Re: DCM
    144998: 10/01/19: Re: XST is driving me mad.
    145000: 10/01/19: Re: compiler output to fpga.
    145027: 10/01/20: Re: Xilinx ISE 8.2 Issue: Pin Name N1, N2...
    145028: 10/01/20: Re: Easy PC software tool - Bad experience
    145054: 10/01/22: Re: offset constrain report confusion
    145084: 10/01/26: Re: Achronix FPGA
    145087: 10/01/26: Re: timing properties of fpga devices at sub-clock frequencies
    145092: 10/01/26: Re: timing properties of fpga devices at sub-clock frequencies
    145136: 10/01/29: Re: Xilinx DCM: Is CLKIN_PERIOD really required
    145137: 10/01/29: Re: DPA vs FPGA Security?
    145155: 10/01/29: Re: synthesizing a completely empty design for an FPGA to measure
    145252: 10/02/03: Re: Help Please - Xilinx message
    145317: 10/02/05: Re: DONE_cycle:6 setting neccessary in bitgen
    145318: 10/02/05: Re: Simulating Spartan 3A pins in ltspice
    145325: 10/02/05: Re: DONE_cycle:6 setting neccessary in bitgen
    145400: 10/02/08: Re: different JTAG programming cables
    145474: 10/02/11: Re: 10 layer stack for 1152 pin BGA routing (and decoupling)?
    145486: 10/02/11: Re: DONE_cycle:6 setting neccessary in bitgen
    145498: 10/02/12: Re: Test Post
    145507: 10/02/12: Re: Why is following Verilog code snipper considered a Latch
    145560: 10/02/14: Re: 28nm FPGAs are coming...
    145686: 10/02/18: Re: BRAM16 error
    145712: 10/02/20: Re: BRAM16 error
    146016: 10/03/03: Re: Using bidirectional pins in Verilog
    146091: 10/03/05: Re: Display Control Application Using Spartan FPGA
    146243: 10/03/09: Re: Spartan3AN DDR2 - bad writing zeros
    146591: 10/03/23: Re: Confusion in address generation for MIG generated DDR2 interface
    146598: 10/03/23: Re: Why hardware designers should switch to Eclipse
    146725: 10/03/26: Re: Ring Oscillator -> counter differences
    146855: 10/03/30: Re: desgin suspended
    146856: 10/03/30: Re: upgrading to ISE 11.x
    146961: 10/04/05: Re: How to convert Verilog in to VHDL code
    146978: 10/04/07: Re: Case with HEX value ...
    146996: 10/04/08: Re: Cannot download ELF; I-Side Memory Access Check Failed
    147022: 10/04/09: Re: ISE Timing Constraints
    147110: 10/04/14: Re: Implementing bidirectional bus inside the FPGA
    147111: 10/04/14: Re: Read from the compact flash
    147149: 10/04/15: Re: Implementing bidirectional bus inside the FPGA
    147169: 10/04/16: Re: Help needed regarding Vertex2 FPGA
    147182: 10/04/16: Re: Changing output pins slew&drive strength without re-run ISE
    147229: 10/04/19: Re: clock routing to generic IO pins?
    147366: 10/04/23: Re: OFFSET and OFFSET out
    147401: 10/04/26: Re: Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface
    147409: 10/04/26: Re: Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface
    147449: 10/04/27: Re: Question about PCB CAD for FPGA-based project
    147452: 10/04/27: Re: Question about PCB CAD for FPGA-based project
    147455: 10/04/27: Re: Question about PCB CAD for FPGA-based project
    147487: 10/04/28: Re: Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface
    147556: 10/05/01: Re: Cheap FPGAs for tutorial
    147562: 10/05/03: Re: ISE 11.1 - readmemh issues
    147564: 10/05/03: Re: ISE 11.1 - readmemh issues
    147569: 10/05/04: Re: FIFO Depth Calculation
    147574: 10/05/04: Re: FIFO Depth Calculation
    147641: 10/05/11: Re: Two PCIe Endpoints in one Virtex-6?
    147762: 10/05/22: Re: Debugging SDRAM interfaces
    147763: 10/05/22: Re: MIG v3.0 inputs signal
    147791: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
    147793: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
    147795: 10/05/24: Re: mux behavior
    147803: 10/05/25: Re: mux behavior
    147812: 10/05/25: Re: mux behavior
    147844: 10/05/26: Re: Help (Virtex 155 and 220 compatibility) !
    147867: 10/05/28: Re: Block RAM unusually long setup time ?
    147945: 10/06/03: Re: ISE Design Suite 11 will not evaluate 2's comp
    147955: 10/06/03: Re: OT and Newbie: SDRAM Auto Refresh
    147966: 10/06/07: Re: Burn to an internal prom Spartan-3an
    147979: 10/06/09: Re: Design passes synthesis and routing but fails on FPGA
    147981: 10/06/09: Re: How to Disable IP Core after Evaluation Period
    148015: 10/06/14: Re: Altera Quartus - how to create small roms & rams for Cyclone 3
    148035: 10/06/15: Re: Does Xilinx Spartan 6 support NAND flash?
    148036: 10/06/15: Re: How to detect a sync and start of a frame in an optimal way
    148049: 10/06/16: Re: Decoupling for Altera Cyclone II 2C8
    148062: 10/06/17: Re: Why is Google so F****** dense about SPAM?
    148069: 10/06/18: Re: Asynchronous FIFO in Spartan6
    148074: 10/06/18: Re: Xilinx Timing Constraings
    148077: 10/06/18: Re: Difficulty with Xilinx FPGA configuration using Platform Flash
    148084: 10/06/19: Re: Xilinx DCM Block Stability Issues
    148090: 10/06/20: Re: Xilinx DCM Block Stability Issues
    148094: 10/06/21: Re: Xilinx DCM Block Stability Issues
    148133: 10/06/22: Re: Xilinx Timing Constraings
    148153: 10/06/23: Re: Help with VGA controller in Verilog
    148160: 10/06/24: Re: Please suggest NON Volatile FPGA Devices
    148161: 10/06/24: Re: Help with VGA controller in Verilog
    148165: 10/06/24: Re: Help with VGA controller in Verilog
    148177: 10/06/25: Re: fooling the compiler
    148227: 10/06/30: Re: Automatic BUFG insertion on a non clock signal in ISE 12.1
    148230: 10/06/30: Re: Automatic BUFG insertion on a non clock signal in ISE 12.1
    148258: 10/07/02: Re: Xilinx xapp175, empty + full flag really synchronous?
    148296: 10/07/05: Re: Difference between DDR and DDR2
    148297: 10/07/05: Re: xilinx leadtimes
    148312: 10/07/06: Re: spartan 3xc3s4000 daisy chain help required
    148313: 10/07/06: Re: 6 kbytes BRAM and Xst:2260
    148343: 10/07/09: Re: Programming individual FPGAs in a daisy chain
    148351: 10/07/13: Re: WTD: WISHBONE SDRAM interface or some Vlog HDL synthesizing...
    148381: 10/07/16: =?ISO-8859-1?Q?Re=3A_DDR=E9_SDRAM_configuration?=
    148407: 10/07/19: =?ISO-8859-1?Q?Re=3A_DDR=E9_SDRAM_configuration?=
    148439: 10/07/22: Re: Using std_ulogic at synthesis level
    148492: 10/07/27: Re: RS-Latch
    148506: 10/07/28: Re: please help and advice : Error: Pack:1107 - Unable to combine the
    148507: 10/07/28: Re: Getting started with partial reconfiguration
    148508: 10/07/28: Re: problem in loading from flash to spartan-3 xc3s200
    148509: 10/07/28: Re: Announcing AjarDSP - an open source VLIW DSP
    148519: 10/07/29: Re: SDRAM AutoPrecharge and Refresh
    148534: 10/07/30: Re: DSP with sensor i2c interface
    148564: 10/08/02: Re: Modify UCF file generated with MIG
    148568: 10/08/02: Re: how to store data in i2c slave
    148575: 10/08/03: Re: Xilinx EasyPath Pricing
    148589: 10/08/04: Re: Logic implementation probelm
    148590: 10/08/04: Re: Vendor Tool Stability
    148602: 10/08/05: Re: Logic implementation probelm
    148634: 10/08/10: Re: Signal value clears for no reason [VHDL, ISE 10.1]
    148636: 10/08/10: Re: Instantiating non-global clock buffers (Xilinx ISE)
    148690: 10/08/17: Re: SDK example from Xilinx do not compile
    148711: 10/08/18: Re: Getting started with FPGA
    148712: 10/08/18: Re: SDK example from Xilinx do not compile
    148800: 10/08/26: Re: New Application Note: Multiple configurations for Altera FPGAs
    148805: 10/08/27: Re: Spartan-6 - What is the IODRP2_MCB??
    148853: 10/09/03: Re: Xilinx Series 7 device availability
    148926: 10/09/10: Re: Question about OC PCI Cores
    149011: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
    149025: 10/09/21: Re: Xilinx XST and a State Machine - A Mystery
    149035: 10/09/23: Re: Xilinx XST and a State Machine - A Mystery
    149036: 10/09/23: Re: Xilinx dropping Modelsim XE
    149056: 10/09/27: Re: Spartan 3 DCM problem
    149078: 10/09/29: Re: SDRAM for specific use - performance and timing questions
    149084: 10/09/29: Re: SDRAM for specific use - performance and timing questions
    149094: 10/09/30: Re: SDRAM for specific use - performance and timing questions
    149108: 10/10/01: Re: SDRAM for specific use - performance and timing questions
    149249: 10/10/11: Re: JTAG stops working!
    149259: 10/10/12: Re: JTAG stops working!
    149308: 10/10/15: Re: Newbie question IO pin and Spartan6
    149309: 10/10/15: Re: ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net
    149313: 10/10/15: Re: FPGA or CPLD?
    149316: 10/10/15: Re: FPGA or CPLD?
    149319: 10/10/15: Re: Old LOC constraint stuck somewhere
    149351: 10/10/18: Re: Regarding Synchronization of multiple control signals
    149383: 10/10/20: Re: Designing for Xilinx Spartan in 2010?
    149384: 10/10/20: Re: Designing for Xilinx Spartan in 2010?
    149393: 10/10/21: Re: IO pin question
    149406: 10/10/22: Re: Analysis of the same path by two different tools in ISE yields
    149412: 10/10/22: Re: Analysis of the same path by two different tools in ISE yields
    149421: 10/10/23: Re: xilinx spartan3e clock domain crossing or synchronizing two clocks
    149422: 10/10/23: Re: FPGA I/O Issues.
    149465: 10/10/27: Re: Simulating Xilinx FIFOs
    149475: 10/10/28: Re: using FPGA editor to add a new output pin
    149486: 10/10/29: Re: Virtex 5 GTP Simulation
    149527: 10/11/02: Re: Xilinx ConstraintSystem:59
    149544: 10/11/03: Re: Chance to win a SP601 board in Xcell Journal Caption Contest
    149581: 10/11/08: Re: Statemachine debugging with Chipscope
    149583: 10/11/08: Re: Statemachine debugging with Chipscope
    149596: 10/11/09: Re: Statemachine debugging with Chipscope
    149619: 10/11/11: Re: Spartan3 bidirectional 3.3V 5V level shifter
    149625: 10/11/12: Re: cool BGA pattern
    149655: 10/11/14: Re: cool BGA pattern
    149684: 10/11/17: Re: Spartan3 bidirectional 3.3V 5V level shifter
    149693: 10/11/17: Re: Signal is connected to multiple drivers
    149717: 10/11/20: Re: Spartan3 device with long availability
    149718: 10/11/20: Re: Huffman encoder/Decoder For Text data compression
    149745: 10/11/22: Re: FPGA-based implementation of Camera Link standard
    149750: 10/11/22: Re: Synthesis/place and route with Solid-State Drives
    149762: 10/11/23: Re: minimum clock period of a combinational circuit
    149763: 10/11/23: Re: Spartan3 device with long availability
    149770: 10/11/23: Re: Intel Atom + FPGA
    149875: 10/11/30: Re: Hi-Z Output Bug in Lattice ispLever
    149877: 10/11/30: Re: PCI Architecture Question for Data Acquisition Board
    149960: 10/12/03: Re: Opinions on Lattice ECP3
    149975: 10/12/04: Re: FPGA BOARD QUESTION
    150029: 10/12/06: Re: Lattice XO2 video
    150050: 10/12/07: Re: Lattice XO2 video
    150068: 10/12/09: Re: Interfacing DS92LV1021 with FPGA serdes
    150069: 10/12/09: Re: LPDDR on spartan-3e
    150071: 10/12/09: Re: LPDDR on spartan-3e
    150091: 10/12/10: Re: LPDDR on spartan-3e
    150100: 10/12/13: Re: Lattice XO2 video
    150125: 10/12/15: Re: ISIM simulation speed
    150127: 10/12/15: Re: spartan 3 xc3s4000 JTAG pins not pulled up
    150160: 10/12/21: Re: Simple ISE Microblaze with GPIO and custom logic example?
    150249: 11/01/05: Re: I Give Up!
    150250: 11/01/05: Re: I Give Up!
    150284: 11/01/07: Re: OT: Fast Circuits
    150340: 11/01/10: Re: Xilinx ML561 Schematics
    150352: 11/01/11: Re: deconvolution
    150382: 11/01/14: Re: Verilog Book for VHDL Users
    150420: 11/01/19: Re: Verilog Book for VHDL Users
    150484: 11/01/24: Re: Problem with iMpact
    150487: 11/01/24: Re: statement is not synthesizable since it does not hold its value
    150520: 11/01/25: Re: Problem with iMpact
    150532: 11/01/25: Re: Zero Padding Circuit Design
    150556: 11/01/26: Re: Interfacing with a 5v micro controller
    150557: 11/01/26: Re: Interfacing with a 5v micro controller
    150562: 11/01/26: Re: Problem with iMpact
    150588: 11/01/27: Re: Interfacing with a 5v micro controller
    150687: 11/02/03: Re: Dynamic Voltage switching for FPGA IO
    150691: 11/02/03: Re: Trivia: Where are you on the HDL Map?
    150706: 11/02/04: Re: Trivia: Where are you on the HDL Map?
    150710: 11/02/04: Re: FPGA pin re-configuration
    150714: 11/02/05: Re: FPGA pin re-configuration
    150793: 11/02/11: Re: Good FPGA dev kit for a student who is not a complete newbie?
    150878: 11/02/18: Re: why an FSM is not a counter?!
    150917: 11/02/21: Re: timing issues at high speed
    150928: 11/02/22: Re: timing issues at high speed
    150929: 11/02/22: Re: timing issues at high speed
    150979: 11/02/25: Re: How to keep iSE from grounding pins
    150987: 11/02/27: Re: DCM on S3A problem
    150988: 11/02/27: Re: Signal issues
    150993: 11/02/27: Re: DCM on S3A problem
    151006: 11/02/28: Re: Question regarding bitstream generation
    151009: 11/02/28: Re: Nanosecond pulse generator using Spartan-3E
    151019: 11/02/28: Re: Nanosecond pulse generator using Spartan-3E
    151053: 11/03/02: Re: Count bits in VHDL, with loop and unrolled loop produces
    151069: 11/03/03: Re: Xilinx FPGA Clocking resources and design implementation.
    151071: 11/03/03: Re: Count bits in VHDL, with loop and unrolled loop produces
    151086: 11/03/04: Re: Video Framebuffer using Nexys2 (Spartan-3E)
    151091: 11/03/04: Re: JTAG questions
    151095: 11/03/05: Re: IP Core Delivery Format Info
    151101: 11/03/06: Re: IP Core Delivery Format Info
    151102: 11/03/06: Re: Hidden SPI_ACCESS site in Spartan-6
    151126: 11/03/08: Re: Pull up/down resistors on Spartan-3E configuration inputs
    151234: 11/03/16: Re: Regfile access
    151241: 11/03/17: Re: Regfile access
    151251: 11/03/17: Re: Reg DCM_CLKGEN primitive for Spartan-6
    151276: 11/03/19: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
    151301: 11/03/21: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
    151330: 11/03/23: Re: pcb&bitstream
    151337: 11/03/24: Re: SRL as a synchroniser
    151377: 11/03/29: Re: Xilinx DDR3 controller: rewrite mode registers
    151429: 11/04/07: Re: What are the preferred Virtex5/Virtex6 configuration methods?
    151435: 11/04/07: Re: What are the preferred Virtex5/Virtex6 configuration methods?
    151439: 11/04/08: Re: Do people do this by hand?
    151485: 11/04/12: Re: Need PCIe Help
    151597: 11/04/25: Lattice Breakout Boards
    151785: 11/05/18: Re: Random behavior of xilinx simple dual port block ram
    151934: 11/06/09: Re: Variable Optimized Away
    151939: 11/06/10: Re: Variable Optimized Away
    151978: 11/06/16: Re: Xilinx or Altera
    152110: 11/07/07: Re: Spartan3DSP TphDCM spec question
    152133: 11/07/12: Re: XC6SLX150 Coprocessor Modules
    152204: 11/07/20: Re: Issues with Soft-Cores
    152206: 11/07/20: Re: Speed attained by virtex 6
    152213: 11/07/21: Re: FPGA not getting programmed
    152214: 11/07/21: Re: source synchronous DDR bus with non-continuous clock
    152252: 11/07/27: Re: VHDL horror in Xcell 76
    152269: 11/07/29: Re: die's in different packages
    152401: 11/08/18: Re: Spartan6 PCB debugging: how badly do you have to screw up for
    152449: 11/08/23: Re: Spartan6 PCB debugging: how badly do you have to screw up for
    152498: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
    152503: 11/08/29: Re: Boundary scan
    152699: 11/10/03: Re: most stable version of ISE ?
    152726: 11/10/11: Re: Microblaze Resources such as BRAMS, LUTS
    152732: 11/10/13: Re: Spartan changes in glitch sensitivity
    152777: 11/10/21: Re: FPGA development
    153115: 11/12/05: Re: Is it possible to save the FPGA state periodically?
    153151: 11/12/13: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
    153171: 11/12/30: Re: Xilinx virtex-5 pitfalls
    153174: 12/01/03: Re: DEBUG a FIFO output on Virtex5 using CHIPESCOPE
    153175: 12/01/03: Re: Verilog module in VHDL project - ISE 13
    153231: 12/01/13: Re: Virtex 5 GC clock pin vs GC//CC clock pins
    153251: 12/01/18: Re: ABEL to VHDL/Verilog converter
    153252: 12/01/18: Re: VCD to power consumption trace
    153258: 12/01/19: Re: balancing IIR filter (after adding extra registers)
    153272: 12/01/23: Re: balancing IIR filter (after adding extra registers)
    153289: 12/01/26: Re: FPGA not working after programming from EEPROM
    153291: 12/01/26: Re: FPGA not working after programming from EEPROM
    153346: 12/02/03: Re: Design Notation VHDL or Verilog?
    153394: 12/02/15: Re: problem with Global Clock pin and normal IO pin as Clock input
    153411: 12/02/18: Re: problem with Global Clock pin and normal IO pin as Clock input
    153459: 12/03/02: Re: JTAG to obsolete Lattice MACH131?
    153460: 12/03/02: Re: Migrating Spartan2 design (xnf)
    153464: 12/03/03: Re: Migrating Spartan2 design (xnf)
    153473: 12/03/06: Re: FPGA Area
    153487: 12/03/09: Re: Synchronizing Virtex-6 RocketIOs on RX path
    153538: 12/03/26: Re: FPGA + Mess o' RAM
    153539: 12/03/26: Re: Spartan 3A counter speed ?
    153540: 12/03/26: Re: Spartan 3A counter speed ?
    153662: 12/04/10: Re: LX9 and internal reset - Do I need one?
    153663: 12/04/10: Re: strange letter from Xilinx
    153755: 12/05/14: Re: Comparing virtex2 to spartan6
    153793: 12/05/23: Re: Spartan-6 66mhz pci
    153794: 12/05/23: Re: Xilinx ISE Multiple Drivers Error
    153805: 12/05/24: Re: Logic Glitches in Spartan-3?
    153848: 12/06/05: Re: Questions about LCMXO2280-B-EVN and LCMXO2-1200ZE-B-EVN ev kits
    153861: 12/06/08: Re: MPMC does not finish initialization in simulation
    153865: 12/06/14: Re: Virtex 4 Cameralink DCM Limitation
    153870: 12/06/15: Re: Virtex 4 Cameralink DCM Limitation
    153873: 12/06/18: Re: Virtex 4 Cameralink DCM Limitation
    153875: 12/06/19: Re: Virtex 4 Cameralink DCM Limitation
    153949: 12/07/02: Re: Generate a pulse with a definite width
    153959: 12/07/03: Re: Generate a pulse with a definite width
    153978: 12/07/06: Re: XC9500XL keeper ?
    154033: 12/07/17: Re: What is best/good way to create a small delay with LCMXO2-1200ZE
    154036: 12/07/17: Re: What is best/good way to create a small delay with LCMXO2-1200ZE
    154038: 12/07/18: Re: use differential I/O simultaneously
    154043: 12/07/19: Re: Xilinx UCF: Adding "Virtual Grounds"
    154048: 12/07/20: Re: Xilinx UCF: Adding "Virtual Grounds"
    154081: 12/07/31: Re: 3 to 1 mux with 4 bit inputs
    154083: 12/08/01: Re: how much costs the Artix 7 devices?
    154084: 12/08/01: Re: how much costs the Artix 7 devices?
    154086: 12/08/01: Re: how much costs the Artix 7 devices?
    154100: 12/08/07: Re: Burn to an internal prom Spartan-3an
    154104: 12/08/08: Re: spartan 6 ddr2 pinout
    154106: 12/08/08: Re: spartan 6 ddr2 pinout
    154117: 12/08/10: Re: Spartan 3AN prevent readback ?
    154120: 12/08/13: Re: My Spartan3 video
    154150: 12/08/21: Re: recruit FPGA design engineer in Scotland
    154161: 12/08/22: Re: recruit FPGA design engineer in Scotland
    154168: 12/08/24: Re: How do you do an incdir in Vivado
    154181: 12/08/29: Re: Simulating fixed point =?windows-1252?Q?multiplication_usi?=
    154185: 12/08/30: Re: General Build Question
    154190: 12/08/31: Re: Unconnected Done pin Virtex 6
    154201: 12/09/07: Re: Verilog file operations
    154206: 12/09/09: Re: Looking for an extremely cheap FPGA board (in quantity, academic
    154212: 12/09/09: Re: Looking for an extremely cheap FPGA board (in quantity, academic
    154235: 12/09/11: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
    154238: 12/09/12: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
    154239: 12/09/12: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
    154245: 12/09/12: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
    154292: 12/09/23: Re: multi-source errors
    154301: 12/09/24: Re: multi-source errors
    154307: 12/09/25: Re: Multiple IDELAYCTRLs in V-5: how, and why?
    154324: 12/09/27: Re: Replacing Logic with an FPGA/CPLD in a 510K device.
    154338: 12/10/04: Re: FPGA-Board for Ethernet
    154347: 12/10/11: Re: Spartan 6 MCB refresh timing
    154359: 12/10/14: Re: My First CPU but.. one problem
    154367: 12/10/15: Re: My First CPU but.. one problem
    154372: 12/10/16: Re: My First CPU but.. one problem
    154375: 12/10/16: Re: Phase 15.18 placement optimization
    154399: 12/10/24: Re: production life of Spartan3A ?
    154436: 12/10/31: Re: production life of Spartan3A ?
    154459: 12/11/05: Re: Xilinx XC3S400 reproducibility madness
    154483: 12/11/14: Re: viewing old aldec/xilinx foundation schematics
    154497: 12/11/19: Re: question about verilog ?, :
    154509: 12/11/21: Re: Spartan 3A startup
    154650: 12/12/11: Re: Where to move for an embedded software engineer.
    154662: 12/12/13: Re: MII SFD Detection with Shematics
    154735: 12/12/31: Re: picoblaze help
    154765: 13/01/04: Re: Constraints learning materials
    154936: 13/02/23: Re: about the always block in verilog
    154998: 13/03/24: Re: pullup in Xilinx ISE 10.1
    155001: 13/03/25: Re: Xilinx tools for XC3020???
    155257: 13/06/18: Re: Ask about finding maximum and second's maximum number in array
    155564: 13/07/19: Re: Metastability mitigation and I/O registers
    155634: 13/07/30: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155737: 13/08/24: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155841: 13/09/29: Re: Lattice diamond / MachXO2
    155893: 13/10/12: Re: extra reset pin should not be needed..
    155912: 13/10/15: Re: Lattice Diamond & tristate
    156020: 13/11/10: Re: how does PC communicate with FPGA?
    156035: 13/11/11: Re: legacy Xilinx software
    156129: 13/12/07: Re: MachXO breakout board as a programmer
    156130: 13/12/07: Re: Implementing multiple interrupts
    156136: 13/12/07: Re: Implementing multiple interrupts
    156192: 14/01/14: Re: Verilog, combinational logic and modules?
    156227: 14/01/18: Re: embedded RAM vs. registers
    156406: 14/03/30: Re: Xilinx ISERDESE2 deserializer primitive behaviour
    156467: 14/04/08: Re: on-chip bypass caps
    156468: 14/04/08: Re: on-chip bypass caps
    156574: 14/05/03: Re: Free alternatives to Xilinx iMPACT?
    156975: 14/08/10: Re: strange effect with tristate output
    157148: 14/10/18: Re: Fast and slow clocks
    157149: 14/10/18: Re: Fast and slow clocks
    157659: 15/01/21: Re: [RANT] XILINX, Are you freaking kidding me ?
    158001: 15/06/23: Re: Conditional Interpretation of VHDL
    159873: 17/04/12: Re: FPGA as heater
    159893: 17/04/15: Re: FPGA as heater
    159896: 17/04/24: Re: glitching AND gate
    159904: 17/04/24: Re: glitching AND gate
Gabor Szakacs:
    66373: 04/02/18: Re: ChipScope for ISE 6.1
    66425: 04/02/19: Re: Using 3.3V compliant FPGA for 5V PCI
    66844: 04/02/27: Re: Done Pin Remains Low after JTAG Configuration of V2Pro
    66935: 04/03/01: Re: cpu time of the computation
    66967: 04/03/02: Re: netlist tricks
    66969: 04/03/02: Re: SRAM Controller Problems
    67055: 04/03/04: Re: Xilinx : RLOC ORIGIN
    67194: 04/03/08: Re: Release asynchrounous resets synchronously
    67920: 04/03/22: Re: Help recognizing format
    67921: 04/03/22: Re: XC95108: Problem with state machine reset in ABEL -> now full posting...
    68191: 04/03/29: Re: rs232 interface on nios
    68320: 04/04/01: Re: maybe a stupid question
    68321: 04/04/01: Best price per I/O
    68339: 04/04/01: Re: How to advertise in www.fpga-faq.com/FPGA_Boards.shtml
    68340: 04/04/01: Re: XC18V master parallel configuration
    68530: 04/04/07: Re: timing constraints... again
    69257: 04/05/03: Re: programming the mach231
    69270: 04/05/03: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
    69415: 04/05/10: Re: SAA7111 YUV
    69416: 04/05/10: Re: SAA7111 YUV
    69502: 04/05/12: Re: SAA7111 YUV
    69572: 04/05/14: Re: Using a FDDRCPE primitive. VIRTEX-II
    69659: 04/05/17: Re: Xilinx Foundation [*.SCH -> *.VHD]
    69661: 04/05/17: Re: FPGA Timing question
    69710: 04/05/18: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
    69758: 04/05/19: Re: Webpack 6.1, ISEexamples, and CoreGen
    69771: 04/05/19: Re: Initialize Blockram from file
    69988: 04/05/26: Re: www.opencores.org ???
    70023: 04/05/27: Re: Driving fpga pin out over long cable
    71036: 04/07/06: Re: FPGA SDRAM prototyping
    71049: 04/07/06: Re: Why 18X18 Multipliers in Altera and Xilinx?
    71596: 04/07/23: Re: 32-channel PC-based logic analyzers
    71746: 04/07/29: Re: FPGA vs CPLD
    71747: 04/07/29: Re: VHDL file equation
    73857: 04/09/30: Re: Xilinx SRL16 test
    74932: 04/10/21: ModelSim is ungraceful with my stupidity...
    75291: 04/11/01: Re: Using Xilinx fpga pins on external connector
    74172: 04/10/05: Re: question on interfacing FPGA with a sensor
    74658: 04/10/15: Re: Xilinx VirtexE internal oscillator
    74759: 04/10/18: Re: Constrained Random Value in verilog
    74861: 04/10/20: Re: counter skrews up design
    74871: 04/10/20: Re: unstable fpga design
    74922: 04/10/21: Re: Experiences with SPARTAN3?
    75426: 04/11/05: Re: Number of FPGA users?
    75532: 04/11/08: Re: SDRAM sustained bursts
    75661: 04/11/11: Re: DDR Mux - how does it work?
    75714: 04/11/12: Re: DDR Mux - how does it work?
    75783: 04/11/15: Re: video camera interface to FPGA
    75862: 04/11/17: Re: video camera interface to FPGA
    76264: 04/11/29: Re: Pin connection doubts
    76267: 04/11/29: Re: XST question
    76303: 04/11/30: Re: Pin connection doubts
    158365: 15/10/24: Re: Found: an FPGA with internal tri-states
    158546: 15/12/20: Re: modulo 2**32-1 arith
    158548: 15/12/21: Re: modulo 2**32-1 arith
Gabor V. Gulyas:
    5127: 97/01/25: ABEL->AHDL
GaborSzakacs:
    154789: 13/01/10: Re: Lattice iCECube2 for iCE40 Devices
    154817: 13/01/15: Re: is this multicycle?
    154818: 13/01/15: Re: Combination loops and false paths
    154819: 13/01/15: Re: Data output constraint
    154837: 13/01/17: Re: Data output constraint
    154838: 13/01/17: Re: Data output constraint
    154852: 13/01/18: Re: Button clock
    154872: 13/01/22: Re: implementation of 8051 ip core on fpga
    154879: 13/01/25: Re: ip core implementation on fpga
    154928: 13/02/18: Re: ModelSim version numbers
    154940: 13/02/25: Re: about the always block in verilog
    154948: 13/03/01: Re: about the always block in verilog
    154949: 13/03/01: Re: about the always block in verilog
    154963: 13/03/04: Re: Farnell increased price on Spartan 6
    154967: 13/03/04: Re: about the always block in verilog
    154969: 13/03/05: Re: about the always block in verilog
    154971: 13/03/05: Re: about the always block in verilog
    154976: 13/03/07: Re: about the always block in verilog
    155019: 13/03/29: Re: xcv800 free design tools
    155118: 13/04/23: Re: FPGA for large HDMI switch
    155177: 13/05/22: Re: XILINX Artix-7 DDR2-RAM-Controller
    155219: 13/06/12: Re: problem with the GTX wrapper in questa
    155258: 13/06/19: Re: Ask about finding maximum and second's maximum number in array
    155262: 13/06/19: Re: comparing between Xilinx and altera
    155523: 13/07/15: Re: Low cost board with built-in USB for fast data transfer and lots
    155524: 13/07/15: Re: Floorplanning Literature
    155525: 13/07/15: Re: Low cost board with built-in USB for fast data transfer and lots
    155529: 13/07/15: Re: Low cost board with built-in USB for fast data transfer and lots
    155542: 13/07/16: Xilinx "Ultrascale" announcement leaves out low-cost devices
    155554: 13/07/18: Re: Metastability mitigation and I/O registers
    155557: 13/07/18: Re: Metastability mitigation and I/O registers
    155563: 13/07/18: Re: Metastability mitigation and I/O registers
    155575: 13/07/23: Re: Xilinx ISE GUI vs tcl script problem
    155581: 13/07/23: Re: FF Replication with Xilinx ISE
    155617: 13/07/30: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155621: 13/07/30: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155648: 13/07/31: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155713: 13/08/13: Re: [HELP]problem with asynchronous fifo ip
    155715: 13/08/16: Re: [HELP]problem with asynchronous fifo ip
    155752: 13/08/27: Re: Synthesis and mapping of ALU
    155785: 13/09/04: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155806: 13/09/18: Re: Legal Issues Reproducing Old CPU
    155810: 13/09/18: Re: Legal Issues Reproducing Old CPU
    155846: 13/09/30: Re: Lattice diamond / MachXO2
    155849: 13/09/30: Re: Lattice diamond / MachXO2
    155858: 13/10/04: Re: Lattice Diamond & tristate
    155867: 13/10/08: Re: Granularity of components for FPGA synthesis?
    155898: 13/10/14: Re: extra reset pin should not be needed..
    155900: 13/10/14: Re: extra reset pin should not be needed..
    155908: 13/10/15: Re: Xilinx tools for XC3020???
    155973: 13/10/30: Re: draw lines, circles, squares on FPGA by mouse and display on
    155990: 13/11/04: Re: Verilog Binary Division
    155995: 13/11/04: Re: Verilog module not working,binary division,shifting problem!!
    155999: 13/11/05: Re: Verilog module not working,binary division,shifting problem!!
    156012: 13/11/08: Re: built in adc in fpga????
    156040: 13/11/12: Re: legacy Xilinx software
    156042: 13/11/12: Re: legacy Xilinx software
    156196: 14/01/16: Re: Verilog, combinational logic and modules?
    156210: 14/01/17: Re: embedded RAM vs. registers
    156211: 14/01/17: Re: Math is hard
    156239: 14/01/21: Re: embedded RAM vs. registers
    156264: 14/01/29: Re: Programming a Digilent S6 Carrier (Spartan 6
    156266: 14/01/30: Re: Programming a Digilent S6 Carrier (Spartan 6
    156297: 14/02/11: Re: How to find power supply pins in Lattice Diamond projects
    156336: 14/03/11: Re: Ball-park price of Xilinx Virtex 7 FPGA?
    156347: 14/03/12: Re: Ball-park price of Xilinx Virtex 7 FPGA?
    156363: 14/03/18: Re: data read write to DDR2 SDRAM memory between microblaze and custom
    156381: 14/03/21: Re: Xilinx ISERDESE2 deserializer primitive behaviour
    156423: 14/04/03: Re: Simulation deltas
    156426: 14/04/04: Re: Tristates in synthesis
    156429: 14/04/04: Re: Simulation deltas
    156489: 14/04/10: Re: MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk)
    156557: 14/04/29: Re: Ethernet interfacing
    156561: 14/04/30: Re: Synthesis / PAR options mess up design functionality
    156599: 14/05/08: Re: DDR speed of the XUPV2P Board from Digilent
    156659: 14/05/27: Re: Trigger implementation on ADC-FPGA
    156666: 14/05/28: Re: Trigger implementation on ADC-FPGA
    156750: 14/06/16: Re: PLA? PAL? PLD? GAL?
    156766: 14/06/23: Re: problem with xc3s400 place and rout section
    156768: 14/06/24: Re: PLA? PAL? PLD? GAL?
    156784: 14/06/25: Re: problem with xc3s400 place and rout section
    156807: 14/07/03: Re: Transistor count
    156844: 14/07/08: Re: Using FPGA as dual ported ram
    156845: 14/07/08: Re: Perl + Xilinx + commandline = Module::Build::Xilinx
    156869: 14/07/14: Re: Help with Address load logic
    156957: 14/08/05: Re: How can Spartan-6 interface with 10/100 Mb/s Ethernet?
    157109: 14/10/13: Re: ISE 14.6 and picoblaze synthesis problem (translate_on/off directives
    157121: 14/10/14: Re: ISE 14.6 and picoblaze synthesis problem (translate_on/off directives
    157212: 14/11/04: Re: practical experience with GPL IP core in commercial product
    157283: 14/11/17: Re: disadvantages of inferring latches
    157296: 14/11/17: Re: disadvantages of inferring latches
    157304: 14/11/18: Re: disadvantages of inferring latches
    157307: 14/11/18: Re: disadvantages of inferring latches
    157308: 14/11/18: Re: disadvantages of inferring latches
    157415: 14/12/03: Re: Which Altera to buy?
    157456: 14/12/11: Re: VHDL Synchronization- two stage FF on all inputs?
    157493: 14/12/12: Re: VHDL Synchronization- two stage FF on all inputs?
    157494: 14/12/12: Re: Using FPGA to feed 80386
    157496: 14/12/12: Re: Using FPGA to feed 80386
    157498: 14/12/12: Re: VHDL Synchronization- two stage FF on all inputs?
    157545: 14/12/15: Re: VHDL Synchronization- two stage FF on all inputs?
    157561: 14/12/16: Re: VHDL Synchronization- two stage FF on all inputs?
    157564: 14/12/16: Re: Monitor connections
    157578: 14/12/17: Re: VHDL Synchronization- two stage FF on all inputs?
    157581: 14/12/17: Re: VHDL Synchronization- two stage FF on all inputs?
    157623: 15/01/07: Re: Image rotation
    157657: 15/01/21: Re: [RANT] XILINX, Are you freaking kidding me ?
    157670: 15/01/22: Re: Send a pulse across clocks
    157735: 15/02/25: Re: Microblaze problem with FSL core
    157738: 15/02/25: Re: Program Xilinx with Altera JTAG Programmer?
    157743: 15/02/26: Re: Program Xilinx with Altera JTAG Programmer?
    157757: 15/03/03: Re: IIC in microblaze
    157861: 15/04/23: Re: Xilinx Aurora link splitter
    157870: 15/05/01: Re: Spartan-3 starter kit
    157902: 15/05/12: Re: 16->5 "Sort"
    157906: 15/05/12: Re: 16->5 "Sort"
    157915: 15/05/12: Re: 16->5 "Sort"
    157958: 15/06/04: Re: Free timing diagram drawing software
    157960: 15/06/04: Re: Free timing diagram drawing software
    157994: 15/06/22: Re: Conditional Interpretation of VHDL
    158004: 15/06/24: Re: Conditional Interpretation of VHDL
    158017: 15/07/06: Re: What's the name of this circuit?
    158020: 15/07/10: Re: Distributed ram timing qurry
    158053: 15/07/29: Re: Image Compression in an FPGA
    158075: 15/07/31: Re: Picking the best synthesis result before implementation
    158275: 15/10/01: Re: Correlator of a big antenna array on FPGA
    158277: 15/10/02: Re: Correlator of a big antenna array on FPGA
    158329: 15/10/22: Re: error Xst:899
    158385: 15/10/26: Re: Found: an FPGA with internal tri-states
    158480: 15/12/02: Re: Simulation vs Synthesis
    158513: 15/12/15: Re: modulo 2**32-1 arith
    158514: 15/12/15: Re: modulo 2**32-1 arith
    158573: 16/01/04: Re: Programming waveshare core3s250e with Impact and ISE 14.1
    158662: 16/03/04: Re: How to define a counter whose width is big enough to hold integer
    158701: 16/03/28: Re: Vivado MIG says "Design entry" is VERILOG, how to change to VHDL?
    158703: 16/03/30: Re: FPGA Internal or external USB PHY/SIE ??
    158819: 16/04/14: Re: Atmels product selector
    158876: 16/05/13: Re: FPGA boards in egypt
    159027: 16/06/16: Re: J1 forth processor in FPGA - possibility of interactive work?
    159047: 16/07/08: Re: Lattice Diamond and VHDL-2008
    159053: 16/07/11: Re: Lattice Diamond and VHDL-2008
    159098: 16/07/28: Re: Vivado parses wicked slow
    159146: 16/08/25: Re: Four_Bit_Counter in VHDL
    159198: 16/09/01: Re: PALCE22v10 / GAL22v10 programming algorithms needed
    159395: 16/10/24: Re: verilog code
    159474: 16/11/21: Re: Phrasing!
    159511: 16/11/29: Re: Programming Problem
    159513: 16/11/29: Re: Programming Problem
    159582: 17/01/03: Re: Slightly OT: Digital watch circuits
    159597: 17/01/16: Re: I/O switching speed of Xilinx spartan 6 or Altera EP4CE10
    159601: 17/01/16: Re: Terminating an Aurora link in a PC
    159642: 17/01/25: Re: Anyone use 1's compliment or signed magnitude?
    159670: 17/01/27: Re: VHDL Editors (esp. V3S)
    159733: 17/02/16: Intel (Altera) announces Cyclone-10
    159739: 17/02/16: Re: Intel (Altera) announces Cyclone-10
    159781: 17/03/03: Re: designing a fpga
    159784: 17/03/03: Re: designing a fpga
    159796: 17/03/07: Re: designing a fpga
    159798: 17/03/07: Re: designing a fpga
    159808: 17/03/09: Re: Analog to digital converters
    159809: 17/03/09: Re: Analog to digital converters
    159810: 17/03/09: Re: Analog to digital converters
    159812: 17/03/10: Re: Analog to digital converters
Gabriel Caffarena:
    33634: 01/08/01: Re: computer science Vs Computer Enginnering
Gabriel Dos_Reis:
    14423: 99/01/29: Re: The development of a free FPGA synthesis tool
Gabriel Margarit:
    11015: 98/07/10: is the code for XC4000E burned on it or in EEPROM ?
    11023: 98/07/11: I need footprints for PCI & ISA (for Protel PCB)
Gabriel Robins:
    2948: 96/03/05: PDW'96
    3000: 96/03/11: PDW'96 Advance Program
    3042: 96/03/19: PDW'96 registration deadline is near
    3122: 96/04/08: PDW'96 Final Program
    3138: 96/04/11: PDW'96 Final Program
Gabriel Rusaneanu:
    12909: 98/11/04: Re: Need FPGA/VHDL designers in Balt/Washington area
Gabriel Tello González:
    16505: 99/05/26: SUMESE A NUESTRO EXITO!!!!
<gabriel_t@my-deja.com>:
    26106: 00/10/04: Boundary Scan and LVDS in Virtex E
    26167: 00/10/06: Re: Boundary Scan and LVDS in Virtex E
Gabriele Bucci:
    3139: 96/04/11: Xact and Viewlogic or Foundation Software Series?
Gabriele Buondonno:
    24779: 00/08/18: R: Yes but I want graphics.
Gabru:
    72688: 04/08/28: Nios Development Kit, STRATIX Edition
Gabry:
    19201: 99/12/06: NOT PCI TO PCI BUS....how it is possible with FPGA?
Gabster:
    87121: 05/07/15: Interface Wi-Fi with FPGA
:: Gabster :::
    58815: 03/08/01: Ground planes on 4-layer PCB
    58852: 03/08/02: Re: Ground planes on 4-layer PCB
    62564: 03/11/01: Using unused space on a PROM (configuration device) as an EEPROM
..:: Gabster ::..:
    57924: 03/07/09: PROM JTAG download cable for Xilinx Spartan II + Webpack
    57957: 03/07/10: Re: PROM JTAG download cable for Xilinx Spartan II + Webpack
    58013: 03/07/11: Graduation Day: My first 4-layer PCB
    58016: 03/07/11: Re: Graduation Day: My first 4-layer PCB
    58039: 03/07/13: Wanted: Orcad Capture symbol for Xilinx Spartan IIE XC2S300E PQ208
    58048: 03/07/13: Re: Wanted: Orcad Capture symbol for Xilinx Spartan IIE XC2S300E PQ208
    58104: 03/07/15: JTAG standard connector
    58123: 03/07/15: PROM size for spartan
    58137: 03/07/15: Re: PROM size for spartan
    58180: 03/07/16: Re: JTAG standard connector
    58182: 03/07/16: Re: Graduation Day: My first 4-layer PCB
    58481: 03/07/24: Buying Xilinx Platform Flash PROM
    58513: 03/07/25: Reseting the whole thing
    58544: 03/07/25: Re: Reseting the whole thing
gaby:
    49819: 02/11/21: Webpack : "others "
Gaby Jay:
    58609: 03/07/28: Spartan IIE max pin switching
gac1@ic.ac.uk:
    96480: 06/02/04: Re: FPGA growth vs. ASIC growth
Gacquer William:
    38227: 02/01/09: FPGA and CCD : any experience?
    38245: 02/01/09: Re: FPGA and CCD : any experience?
<gadav111@hotmail.com>:
    115330: 07/02/07: Actel FIFO in Synplify: blackbox is missing a user supplied timing model
    115396: 07/02/09: Re: Actel FIFO in Synplify: blackbox is missing a user supplied timing model
Gael Paul:
    134867: 08/09/04: Re: XST bug on illigal states of a FSM ?
    134902: 08/09/05: Re: XST bug on illigal states of a FSM ?
    135267: 08/09/23: Re: Use of divided clocks inside modules
    135325: 08/09/26: Re: Use of divided clocks inside modules
    135330: 08/09/26: Re: Use of divided clocks inside modules
    136367: 08/11/13: Re: How to constrain time-multiplexed pathes
    136911: 08/12/12: Re: How to insert ChipScope
    136952: 08/12/15: Re: BUFGMUX placement
    137062: 08/12/21: Re: Large BRAM synthesis
    138395: 09/02/19: Re: VHDL long elsif state machine
    138413: 09/02/20: Re: Troubleshooting fpga design
    138728: 09/03/06: Re: Troubleshooting fpga design
    141467: 09/06/25: Re: SRAM vs Flash based FPGA one more time
    141579: 09/06/28: Re: STA Problem on Asynchronous FIFO
    141586: 09/06/28: Re: STA Problem on Asynchronous FIFO
    143436: 09/10/11: Re: ASIC Prototyping using FPGA
    143504: 09/10/13: Re: ASIC Prototyping using FPGA
    143812: 09/10/27: Re: synplify question for FPGA
<gael.paul@gmail.com>:
    134857: 08/09/03: Re: XST bug on illigal states of a FSM ?
    134863: 08/09/04: Re: XST bug on illigal states of a FSM ?
Gaga:
    46615: 02/09/04: xilinx contact with regard to qpro
    52956: 03/02/26: XILINX MICROBLAZE ERRORS
    52984: 03/02/27: Re: XILINX MICROBLAZE ERRORS
    53331: 03/03/11: digikey d2e microblaze help
<gajhkajh@usa.net>:
    6628: 97/06/06: Cash Grant
gajju:
    38024: 01/12/31: Synplicity to Xilinx hierarchical net names
Galina Szakacs:
    158226: 15/09/25: Re: Xilinx Spartan2E options?
<gallant@nm.hsd.utc.com>:
    18589: 99/11/02: Input metastability
gallen:
    82094: 05/04/06: Modelsim simulations without ISE
    83100: 05/04/23: "Implement Design" Error on ISE 6.3 webpack
    83157: 05/04/25: Re: New FPGA Development Board
    83406: 05/04/29: Re: Sync + FIFO
    83426: 05/04/29: Re: signals in modelsim
    84354: 05/05/17: Which Simulators
    85135: 05/06/05: Re: Xilinx + ModelSim XE Linux
    86981: 05/07/11: Re: Announce: Impulse C-to-RTL Version 2 now available
    87891: 05/08/03: Re: XST and TCL support?
    88506: 05/08/20: Re: Could you tell me some other good forums or website related?
    88507: 05/08/20: Re: Could you tell me some other good forums or website related?
    88519: 05/08/21: real constants in XST
    88538: 05/08/22: Re: real constants in XST
    89008: 05/09/02: Re: CPLD - SimuCAD S/W CD
    89130: 05/09/06: Re: Modelsim XE and multi-file Verilog projects
    89582: 05/09/19: Re: Modelsim XE, what's the latest version?
    89626: 05/09/20: Re: Modelsim XE, what's the latest version?
    90398: 05/10/11: Re: 64 bit processor for FPGA workstation?
    90519: 05/10/15: Re: What is a "full custom" design?
    90832: 05/10/21: Re: Implementing five stage pipeline
    90848: 05/10/22: Re: Implementing five stage pipeline
    91424: 05/11/06: Re: icarus verilog
    92001: 05/11/18: Re: hi everyone, tell me something about Cyclone II.
    92019: 05/11/19: Re: hi everyone, tell me something about Cyclone II.
    92554: 05/12/01: Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
    92605: 05/12/02: Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
    96154: 06/01/30: Re: Analog FPGA Project -- VIdeo Router
    97963: 06/03/02: Re: I want to use UltraEdit as a text editor for ISE
    102441: 06/05/16: Re: getting good deals on small qty?
    103743: 06/06/09: Re: Anyone with Xilinx SP305-board ?
    104052: 06/06/17: Re: How to get lowest price for a ModelSim license?
    111194: 06/10/30: Re: A pre-emptive strike against blaming the chip
    114507: 07/01/17: Re: Generation of Divided-by-3 clock
gallenm:
    52369: 03/02/07: FFT Size and speed
    52456: 03/02/10: Re: FFT Size and speed
    53682: 03/03/19: Re: Quartus2 : assigning I/O pins
    54759: 03/04/17: Re: Advice on FPGA IIR Filter
GAM:
    15180: 99/03/11: Printing AHDL code from Max+plus2 in color???
gamer:
    121179: 07/06/27: Bit error counter - how to make it faster
<gamingnet@hotmail.com>:
    7865: 97/10/24: EMAIL BLASTER PROMOTION
Gamma Globulin:
    39258: 02/02/05: When is Xilinx going to have multi-gigabit serial PHY?
    39268: 02/02/05: Re: When is Xilinx going to have multi-gigabit serial PHY?
Gammaburst:
    70280: 04/06/11: Re: Stupid Xilinx Rubbish
GAMRAT Christian:
    2968: 96/03/07: Re: ECOLE - Architecture des Systemes et des Mac
    3674: 96/07/11: What about the XC6200 ?
Ganapathy Subbaraman:
    9439: 98/03/13: Please share ur knowledge of Multipliers ( datapath elements)
Ganesan:
    51067: 02/12/29: Xilinx Answer Record # 15857: input to an IBUF cannot be tied to ground!
    69001: 04/04/24: multiply by 1.5 in xilinx Virtex2 FPGA
Ganesh C. Gopalakrishnan:
    1252: 95/05/22: Projects, assignments, and exam.
    1254: 95/05/23: Re: Projects, assignments, and exam.
ganeshstha:
    142803: 09/09/02: Choice of Language for FPGA programming
    142836: 09/09/03: Re: Choice of Language for FPGA programming
Gang Li:
    11362: 98/08/06: AD: Reading Secured Devices
    11543: 98/08/22: AD: Reading Secured Devices
    11829: 98/09/11: AD: Reading Secured Devices
    13320: 98/11/25: AD: Reading Secured Devices
    14264: 99/01/22: AD: Reading Secured Devices
gangireddy.p:
    139615: 09/04/07: Xilinx user constraints with respect to output clock from the design
    139638: 09/04/08: Re: Xilinx user constraints with respect to output clock from the design
    139710: 09/04/10: Re: Xilinx user constraints with respect to output clock from the design
gantlord:
    88733: 05/08/26: Re: Best FPGA for floating point performance
Garden Gnome:
    62834: 03/11/09: Re: 0.13u device with 5V I/O
    62840: 03/11/09: Re: 0.13u device with 5V I/O
Gardovan:
    89188: 05/09/07: chipscope/core implementation
    89189: 05/09/07: re:chipscope and V2P problems
Gareth:
    31169: 01/05/14: Huffman decoders
Gareth Baron:
    4565: 96/11/14: Re: UART FOR FPGAS
    4657: 96/11/26: Re: Electronics question
    4668: 96/11/27: Re: FPGA TEST BOARDS
    4686: 96/11/29: Re: Reconfigurable FPGAs in Networking
    5994: 97/04/03: Re: Sole source
    6066: 97/04/09: Re: Chip Temperature (was:Re: Sole source)
    5971: 97/04/01: Re: Help on file format
    6171: 97/04/22: Re: palasm...
    6216: 97/04/29: Re: ISP CPLD from AMD or Cypress???
    6543: 97/06/02: Re: New Reconfigurable Computing newsgroup?
    6643: 97/06/09: Re: PCI how to
    7389: 97/09/05: Binary to Intel Hex
    7390: 97/09/05: Re: export pins from MAX+ to orcad schem symbol
    7510: 97/09/18: PIC Model
    9605: 98/03/25: Re: Looking for space qualified FPGAs/ASICs
    9606: 98/03/25: Verilog 2 VHDL
    9678: 98/03/30: Re: XactStep6 - The cure for a dongle
    9699: 98/03/31: Re: programming XC4000A
    9740: 98/04/02: Re: One time programmables
    9754: 98/04/03: Re: Choosing the right tools and company....
    9803: 98/04/06: Re: Counter problem ?
    9926: 98/04/14: Re: Xilinx Foundation Express
    9927: 98/04/14: Re: Event counting?
    9928: 98/04/14: Re: Someone with Foundation Express version 1.4, please help me
    9963: 98/04/17: Re: state machine
    10837: 98/06/24: Re: How to Double Clk Freq in the FPGA design
    10852: 98/06/25: Re: How to Double Clk Freq in the FPGA design
    11000: 98/07/09: Re: Configure with BIT file
    11054: 98/07/15: Re: Shift Invarient Bit Transform
    11130: 98/07/20: Re: CRC Implementation
    11185: 98/07/23: Re: Schematic Symbol Generation
    11241: 98/07/29: Re: Schematic Symbol Generation
    11698: 98/09/01: Re: Video 256 colors interface HELP!
    12000: 98/09/23: Re: easier testing for PCI cards??
    12017: 98/09/24: Re: fpga-asic
    12097: 98/09/28: Re: strange problem of 4028XL
    12283: 98/10/07: Re: Help Desperately Needed with Altera Microprocessor Design.
    12284: 98/10/07: Re: Help Desperately Needed with Altera Microprocessor Design.
    12357: 98/10/09: Re: clock divider chips
    12544: 98/10/15: Re: Library of boards
    12577: 98/10/16: Re: How to decrease the XC95144's work current?
    12600: 98/10/19: Re: Schematic entry?
Gareth Jones:
    17330: 99/07/21: Free Filter Synthesis Software
    17455: 99/07/29: FilterExpress Filter Synthesis Software
    20939: 00/02/29: FilterExpress version 3.0 now available
<gareth.powell@stsystems.co.uk>:
    12693: 98/10/23: GP logic machines (was Re: Schematic entry?)
Garett B Choy:
    303: 94/10/17: SRAM and antifuse for interconnects
    342: 94/10/25: Re: SRAM and antifuse for interconnects
    1057: 95/04/21: Is anybody using FPGA's to do PCI interfaces?
Garnet Brace:
    4867: 96/12/21: Xilinx loading problem?
    5830: 97/03/19: Sole source
Garnett Hamilton:
    2344: 95/11/21: Re: Vendors For Verilog On The PC
    6292: 97/05/09: Re: Quicklogic Input Only Pins
    6611: 97/06/05: Re: Fine Pitch PQFP : anyone any hassles?
    6629: 97/06/06: Re: Fine Pitch PQFP : anyone any hassles?
Garrett Mace:
    53153: 03/03/04: Re: Issues in Outsourcing?
    53196: 03/03/05: Re: Issues in Outsourcing?
    53990: 03/03/30: [Question] FPGA/PLX9054
    53997: 03/03/30: Re: [Question] FPGA/PLX9054
    54047: 03/03/31: Re: [Question] FPGA/PLX9054
    54058: 03/04/01: Re: [Question] FPGA/PLX9054
    54059: 03/04/01: Re: [Question] FPGA/PLX9054
    54096: 03/04/02: Re: [Question] FPGA/PLX9054
    54120: 03/04/02: Re: [Question] FPGA/PLX9054
    54121: 03/04/02: Re: Excel and FPGA's
    54151: 03/04/03: Re: Excel and FPGA's
    54220: 03/04/04: Re: PCB for Altera APEX20KE failed ?
    54273: 03/04/07: Re: Xilinx Impact and USB/LPT ports
    54394: 03/04/09: Re: OK, where does an FPGA newbie start?
    54506: 03/04/11: Re: Too early to throw away Parallel Cable III...
    55189: 03/04/29: Re: general: vhdl
    57285: 03/06/26: Re: I need a commercial PCI FPGA board, please help
    60097: 03/09/05: Re: New to FPGA, seeking advice
    60206: 03/09/08: Re: FPGA start?
    63114: 03/11/15: Re: getting started in FPGA
    66165: 04/02/13: Re: ARM+FPGA tiny board
Garrick:
    89542: 05/09/19: Generating Modelsim Verilog resource libraries - pointers/questions
    89573: 05/09/19: Re: Generating Modelsim Verilog resource libraries - pointers/questions
    89612: 05/09/20: Re: Generating Modelsim Verilog resource libraries - pointers/questions
    89614: 05/09/20: Re: Generating Modelsim Verilog resource libraries - pointers/questions
    103664: 06/06/07: Xilinx EDK: Connecting interrupt to MicroBlaze requires stdout?
Garrick Kremesec:
    16048: 99/04/29: Compiler ignores clock input??
    16132: 99/05/05: Re: Compiler ignores clock input??
    16558: 99/05/27: RAM for external/internal use
    16574: 99/05/28: Re: RAM for external/internal use
    16584: 99/05/28: Re: RAM for external/internal use
    16869: 99/06/15: Altera EPC1 replacement?
    16900: 99/06/16: Re: Altera EPC1 replacement?
Garritt:
    6889: 97/07/06: Re: Fast sampling techniques. Was: Fast scopes, How?
Garry Allen:
    9296: 98/03/06: Re: Questions about creating personal package
    9847: 98/04/09: Re: XactStep6 - The cure for a dongle
    10692: 98/06/11: Re: How about Lattice ispLSI?
    12424: 98/10/12: Re: clock divider chips
    14652: 99/02/08: Re: Off topic DRAM/SIMM question....
    28045: 00/12/20: Re: 3V -> 5V clock signal level conversion
    50675: 02/12/16: Re: Tiny Forth Processors
    50701: 02/12/17: Re: Tiny Forth Processors
    52225: 03/02/04: low pass FIR filter in FPGA
    52434: 03/02/09: Re: low pass FIR filter in FPGA
    60666: 03/09/18: ISE 6.1 and Redhat 9
    60751: 03/09/21: Re: ISE 6.1 and Redhat 9
    62152: 03/10/20: Re: please help, modelsim does not simulate
GaRY:
    70155: 04/06/06: Variable Frequency and Voltage Supply
    70181: 04/06/08: Re: Variable Frequency and Voltage Supply
Gary:
    68195: 04/03/29: Spartan3 hot-swap configuration issue
gary:
    23553: 00/06/29: MPEG audio questions...
    23661: 00/07/04: Re: MPEG audio questions...
    23825: 00/07/11: Re: MPEG audio questions...
    23826: 00/07/11: Re: MPEG audio questions...
    52571: 03/02/14: Re: Ip core pricing info
    104621: 06/07/02: component instantiation ISE7.1
    104629: 06/07/02: Re: component instantiation ISE7.1
    104673: 06/07/03: Re: component instantiation ISE7.1
    104773: 06/07/05: Re: component instantiation ISE7.1
    104899: 06/07/08: Re: component instantiation ISE7.1
    105011: 06/07/11: Re: component instantiation ISE7.1
    105644: 06/07/27: Re: component instantiation ISE7.1
Gary A. Gorgen:
    68645: 04/04/12: Re: Problem downloading with parallel converter
    98665: 06/03/14: Re: Why does Xilinx hate version control?
    98685: 06/03/14: Re: Why does Xilinx hate version control?
Gary Cook:
    1548: 95/07/13: AT&T FPGAs - Opinions needed
    15489: 99/03/26: Re: FPGA Express Synthesis Problem
    17786: 99/09/03: ALTERA Flex10K problems with lpm.
    18566: 99/11/01: Altera Reset Strategy?
    18588: 99/11/02: Re: Altera Reset Strategy?
    20856: 00/02/24: Re: Bit Serial Arithmetic De-mystified : On-Line Arithmetic
    23107: 00/06/14: Altera Output Timing Question
    25473: 00/09/12: Using U_SET/HU_SET in RPM's in Xilinx
    26159: 00/10/05: Altera Internal Error
    26426: 00/10/16: Re: Altera Internal Error
    26851: 00/11/01: Re: Alliance 3.2i
    27750: 00/12/06: Re: NGDBUILD/UCF Problem
    31050: 01/05/10: Re: Altera Consultant
    33386: 01/07/25: In-Circuit Power Supply Verification of Xilinx Chips
    33911: 01/08/08: Q: Revision and Database Control for FPGA Designs
    34090: 01/08/14: Re: Q: Revision and Database Control for FPGA Designs
    34093: 01/08/14: Re: Q: Revision and Database Control for FPGA Designs
Gary Crean:
    78233: 05/01/26: Re: ADPLL I Think ?
gary crothers:
    3764: 96/07/27: ANNOUNCE HDL Editor
    3801: 96/08/04: ANNOUNCE : HDL Editor
    4041: 96/09/05: DISTRIBUTORS
Gary Desrosiers:
    15727: 99/04/10: FPGA vs CPLD? Any Experts out there?
    15730: 99/04/10: Re: FPGA vs CPLD? Any Experts out there?
    15877: 99/04/17: Re: What's the best way to learn about fpga's?
    15909: 99/04/20: Okay, a really dumb Xilinx FPGA question.
    16106: 99/05/03: Anyone use 27256 for config?
    49656: 02/11/18: Re: looking for a VHDL imlementation of MD5 Hash algorithm.
    49963: 02/11/27: Re: Frequency multiplier with digital h/w
gary drummond:
    25193: 00/08/29: Re: Non-disclosures in job interviews, Round Two
GARY FRAGOZA:
    9159: 98/02/25: Need Simple DMA Cont. in VHDL or Verilog
    9183: 98/02/28: Simple DMA Core Needed
Gary Franco:
    5609: 97/02/28: Intel FLEX 780
Gary Helbig:
    10630: 98/06/07: Re: Example of 8051 codes to configure Xilinx fpga
    10691: 98/06/10: Re: AHDL vs. VHDL vs. Verilog HDl
    10739: 98/06/14: Re: How about Lattice ispLSI?
    11109: 98/07/19: Re: Too much advertising in this news group?
    37537: 01/12/13: Re: PC Cache size. Was: ModelSim performance on Solaris/sparc and Linux/x86
Gary Helbig (.):
    18349: 99/10/17: Re: Xilinx PCI Bridge
    18350: 99/10/17: Re: Pull plug quickly!
Gary Isliefson:
    9092: 98/02/19: Re: the problem about counter.
Gary J. Tait:
    78673: 05/02/05: Re: Exportability of EDA industry from North America?
Gary Lawman:
    410: 94/11/10: 322 MHz FPGA Counters
Gary Levin:
    8780: 98/01/26: Re: ALtera Devices.
    8982: 98/02/11: Devices and Prices
    8996: 98/02/12: Re: Devices and Prices
Gary Meakin:
    32379: 01/06/25: Xilinx Spartan - Power Rail Related Timing Problem
Gary Michels:
    70827: 04/06/29: Re: simprim X_FF component
Gary Miller:
    2460: 95/12/08: Help on boards using FPGA devices for hareware realisation
Gary Milliorn:
    13608: 98/12/11: Re: Lattice Pin Drive Capability
Gary Moneysmith:
    2290: 95/11/17: FYI: Flash memory data recording
Gary Morton:
    33337: 01/07/23: Re: Flex 10K10 prototyping system
Gary Olson:
    69353: 04/05/07: Muxes : 64X1
    69354: 04/05/07: Re: Muxes : 64X1
    69356: 04/05/07: Re: Muxes : 64X1
Gary Pace:
    69205: 04/04/30: Quartus II Schematic Capture
    69262: 04/05/03: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
    69362: 04/05/08: Re: SignalProbe in Quartus...
    70881: 04/06/30: Cyclone 5V Tolerance
    72903: 04/09/08: Quartus2 4.1 SP1 Hangs
    73212: 04/09/16: Programming Altera Config Device
    76531: 04/12/06: Re: internal tristates and busses
    77046: 04/12/21: Re: Using low-core-voltage devices in industrial applications
    78430: 05/02/01: Metastability MTBF in Cyclone
    79396: 05/02/18: Re: Is Altera Cyclone a good choice ?
    79594: 05/02/21: Re: cyclone's pll
    81660: 05/03/29: Custom compilation step in Quartus
    81682: 05/03/30: Re: Custom compilation step in Quartus
    82232: 05/04/08: Re: rules to assign pins to FPGA?
    84558: 05/05/21: VHDL vs. Schematic Capture
    85729: 05/06/15: Re: Somewhat OT - falling behind the times ...
    87311: 05/07/21: Re: Optimizing out a divide on altera cyclone fpga
    89043: 05/09/03: Long Multiplication
    89050: 05/09/04: Re: Long Multiplication
    90396: 05/10/12: Re: How many decoupling capacitors need on one device?
    90897: 05/10/25: Re: a few questions
    96852: 06/02/12: Re: using FPGA in control field
    127940: 08/01/10: Re: Place-and-Route : Intel vs AMD
    135617: 08/10/09: VHDL Training Course
    135630: 08/10/10: Re: VHDL Training Course
    137047: 08/12/20: Re: PLL and clock in altera cyclone 2 fpga
Gary Partis:
    49984: 02/11/27: Xilinx Virtex 2 BIT Files
    52731: 03/02/20: Inventra/Mentor USB
Gary Pearman:
    98304: 06/03/08: 5v Xilinx development board
Gary Seely:
    12784: 98/10/29: Re: Foundation 1.4 Export to VHDL?
    14877: 99/02/22: Re: Eval Activ-VHDL only for 30 day :(
Gary Spivey:
    20563: 00/02/14: Re: Advice please
    20565: 00/02/14: Re: Advice please
    20644: 00/02/16: Runtime Conditionals?
    20646: 00/02/16: Writing to STDOUT?
    21499: 00/03/23: Re: FPGA Design Productivity Metrics
    22028: 00/04/13: Re: A Question on Verilog
    22513: 00/05/10: Re: pipeline shiftreg in virtex
    22545: 00/05/11: Re: pipeline shiftreg in virtex
    26478: 00/10/17: Backannotated Simulation of Annapolis Microsystems Starfire
    26738: 00/10/26: Leonardo vs. FPGA Compiler 2
    27733: 00/12/05: Gate Level Simulation Questions
    33385: 01/07/25: ModelSim and Cygwin
    110873: 06/10/25: Simple multiply in Xilinx?
    110876: 06/10/25: Re: Simple multiply in Xilinx?
Gary Sugita:
    48437: 02/10/17: Re: AHDL Command Reference?
    49022: 02/10/29: Re: Quartus Run Time Error
    49023: 02/10/29: Re: Quartus LogicLock problem
    49100: 02/10/31: Re: Quartus LogicLock problem
Gary Tse:
    24407: 00/08/07: Re: Memory specification
Gary Watson:
    21295: 00/03/15: Re: Extremely fault tolerant strategies
    21318: 00/03/16: Is there a Xilink PCI or ISA demo board with external connector?
    21555: 00/03/24: Re: FPGA openness
    21480: 00/03/23: Re: FPGA openness
    21574: 00/03/25: Re: FPGA openness
    21700: 00/03/29: Re: FPGA & single point failure
    21707: 00/03/29: Hardware TCP/IP stack?
    21806: 00/04/01: Re: FPGA openness
    21813: 00/04/01: Re: FPGA openness
    21814: 00/04/01: Bitstream Format of Xilinx 4000 and Virtex Available for Download Here!
    21849: 00/04/04: Re: FPGA controlling S-7600A TCP/IP ...
    21937: 00/04/07: Re: FPGA Openness/ Summary
    22037: 00/04/14: Re: Demo - board
    22105: 00/04/24: Re: Virtex-E and LVDS
    22967: 00/06/06: Re: Virtex-E and SCSI
    23131: 00/06/15: Re: PCI for a fpga board
    23869: 00/07/13: Init time of Xilinx Virtex / Spartan II
    23923: 00/07/15: Re: Boundary-Scan Tests with JTAG Technologies Tools
    25150: 00/08/28: Re: Looks like Xilinx is at it again!
    25413: 00/09/11: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
    25414: 00/09/11: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
    25478: 00/09/12: Re: Anybody receiving Spartan II?
    25479: 00/09/12: Re: xilinx web site access
    25683: 00/09/17: Re: Virtex 'shutdown' phenomenon
    25714: 00/09/18: Safe voltage regulator for Xilinx XC2S150 part?
    25781: 00/09/20: Re: Safe voltage regulator for Xilinx XC2S150 part?
    25810: 00/09/21: Re: Safe voltage regulator for Xilinx XC2S150 part?
    25817: 00/09/21: Re: Safe voltage regulator for Xilinx XC2S150 part?
    25878: 00/09/24: Paranoid...
    25890: 00/09/25: Re: Dual monitor display possible with modelsim on a PC?
    26685: 00/10/25: Re: XILINX Download cable with USB
    27009: 00/11/07: Embed serial number in a FPGA?
    27016: 00/11/07: Re: ANNOUNCE: New article about Network Processors
    27036: 00/11/08: Re: unique serial nr
    27083: 00/11/10: Re: unique serial nr
    27377: 00/11/20: What happens to CCLK after config on Xilinx Spartan II?
    27753: 00/12/06: Re: Issues with Spartan II
    28569: 01/01/17: Re: Virtex-II officially launched
    28613: 01/01/18: Re: Virtex-II officially launched
    28618: 01/01/18: Re: Virtex-II officially launched
    28692: 01/01/21: Re: UK parts
<gary099g@erols.com>:
    6965: 97/07/17: FREE SEX SITE..password is.
<gary_hylton@ovalstrapping.com>:
    12453: 98/10/12: Re: Processor Cores
Garynlang:
    11467: 98/08/17: FPGA & ASIC positions in S.California
    11555: 98/08/23: ASIC, FPGA, DSP USA jobs (and work visa)
    12006: 98/09/24: US ASIC jobs+work visa
    12114: 98/09/29: USA EDA rel. jobs+work visa
    12676: 98/10/23: Re: Need VHDL tools for Win NT/ Win 95
    12844: 98/11/01: ASIC/FPGA designers for US/Canada+work visa
    13873: 98/12/30: US job:EDA SW, Firmware,Appl.Eng+VISA
    14222: 99/01/20: Several EDA jobs in US with Work visa
garyr:
    154721: 12/12/28: Re: Chisel as alternative HDL
<garyytyie@aol.com>:
    7224: 97/08/15: .Live .Sex .Video .5 Minutes Free!!!
Gaspar Sinai:
    65339: 04/01/24: FPGA machine-level specification?
Gaston Biessener:
    30075: 01/03/22: Looking for Processor Core info/advice
Gattu:
    101522: 06/05/02: ESL using Spartan 3/3E kits
gauckler:
    108834: 06/09/17: ISE Simulator Error 222: SuSE 10.1 Linux
    115399: 07/02/09: Re: ISE 9.1 Installation crash SuSE 10.2
gaurang4040:
    146861: 10/03/30: Using Verilog Macros with Arguments
Gaurav:
    42915: 02/05/06: FPGA in Storage
    42941: 02/05/07: Cellular Base stations
gaurav.vaidya2000@gmail.com:
    102195: 06/05/11: Re: can increase simulation run time while running modelsim?
    102196: 06/05/11: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
gaurav3110:
    154282: 12/09/23: Error while running implementation through unix command line
Gautam:
    35621: 01/10/11: Block RAMs
    35709: 01/10/14: PLLs & DLLs
    35742: 01/10/16: Re: PLLs & DLLs
<gavbiggs@yahoo.co.uk>:
    78944: 05/02/10: FPGA design problem
Gaven Miller:
    4933: 97/01/02: Re: What Does ASIC Stand For?
Gavin:
    91052: 05/10/27: Re: Avnet Technical Support Terrible!!!
    91082: 05/10/28: Re: ethernet phy- DP83847
    91152: 05/10/31: Re: Spartan-3E starter kit
    91217: 05/11/01: Re: can ethereal detect an ethernet packet for which crc is wrong
    91221: 05/11/01: Re: lenght/type not included
Gavin Brebner:
    1002: 95/04/12: I-Cube - contact information ?
Gavin Hurlbut:
    5827: 97/03/19: Re: Xilinx 4002 RAM Question
    5842: 97/03/20: Re: Xilinx 4002 RAM Question
    35053: 01/09/19: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
    35081: 01/09/20: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
    35130: 01/09/22: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
Gavin Melville:
    2674: 96/01/23: XILINX XACT 6.0.0 Tools flaky
    3443: 96/05/31: Re: EXOTIC DESTINATION
    3703: 96/07/17: (Another) XILINX XDE problem
    4223: 96/10/02: Has anyone changed from ViewLogic to Foundation [Q]
    4230: 96/10/02: Re: Viewlogic 4.1 (DOS) mouse alternatives?
    6465: 97/05/27: Re: Fine Pitch PQFP : anyone any hassles?
    7714: 97/10/07: Re: Need help for Xilinx Demo Board
    8525: 98/01/05: Re: Xilinx XACT 2.10 memory error
    9230: 98/03/03: Re: Help with ViewLogic 4
    9299: 98/03/06: Re: Help with ViewLogic 4
    10089: 98/04/27: Re: Make a delay in Xilinx FPGAs (Help)?
    13350: 98/11/30: Re: Will XILINX survive?
    63627: 03/11/27: Xilinx ISE 6.1 external editor
    86197: 05/06/23: Commercial Z180 / 64180 core
    101429: 06/05/01: Where has the ChipViewer gone
    115454: 07/02/12: Weird problem with WP 9.1sp1 and XC95144XL
Gavin Scott:
    75124: 04/10/26: Re: Webpack 6.3i support for Spartan 3
    84049: 05/05/11: Re: Xilinx versus Elixent; other radically different concepts?
    86182: 05/06/22: Re: Good FPGA introduction book ?
    104897: 06/07/08: Xilinx Xcell Journal received damaged
    123401: 07/08/27: Re: Annoying
    127571: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
    128243: 08/01/18: Re: Source of accurate frequency
    128495: 08/01/29: Re: Craignell FPGA DIP Module
    128555: 08/01/30: Re: define a new bust interface
    129015: 08/02/13: Re: Newbie looking for guidance
    129020: 08/02/13: Re: Spartan 3A starter kit
    129061: 08/02/13: Re: Newbie looking for guidance
    129065: 08/02/13: Re: When are FPGAs the right choice?
    130099: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
    131223: 08/04/15: Re: 64 bit WebPack
    131662: 08/04/28: Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY
    131908: 08/05/06: Re: FPGA dev kit with 4-8 Cyclones or Spartans
    131912: 08/05/06: Re: FPGA dev kit with 4-8 Cyclones or Spartans
    131925: 08/05/07: Re: FPGA dev kit with 4-8 Cyclones or Spartans
    133359: 08/06/25: Re: FPGA based database searching
    136085: 08/10/30: Re: Downsizing Verilog synthesization.
    137191: 08/12/31: Re: Xilinx QUIZ 2008
    138682: 09/03/04: Re: Warning Search Engine Links
    138690: 09/03/04: Re: Warning Search Engine Links
    139958: 09/04/20: Re: Dual-frequency quartz oscillator with a FPGA ?
    143186: 09/09/24: Re: Shift left arithmetic?
<gavin.melville@acclipse.co.nz>:
    115467: 07/02/12: Re: Weird problem with WP 9.1sp1 and XC95144XL
Gazelle:
    63016: 03/11/12: Frequency Doubler - VHDL/Verilog
<gazit@my-deja.com>:
    20582: 00/02/15: Xilinx - implementing macros
    20606: 00/02/16: Re: 100% slice utilization in Virtex FPGA
    20667: 00/02/17: Re: 100% slice utilization in Virtex FPGA
    20668: 00/02/17: Re: Simple (?) Question about FPGA Test/Demo Boards....
    20766: 00/02/21: Re: Passing multi-cycle timing constrains from Synplify to M1
    20823: 00/02/23: Re: Passing multi-cycle timing constrains from Synplify to M1
    22220: 00/05/02: Re: random integer
    26188: 00/10/07: Re: Problem Foundation 3.1 sp 3
    26688: 00/10/25: 155Mhz DDR in a programmable logic
    26785: 00/10/29: Re: 155Mhz DDR in a programmable logic
    26968: 00/11/06: Re: Spartan2 prototype boards
    27694: 00/12/03: which I/O pin belongs to each bank
    27724: 00/12/05: Re: which I/O pin belongs to each bank
    27729: 00/12/05: Re: which I/O pin belongs to each bank
    29055: 01/02/04: Re: Xilinx XCell is not on-line?
Gazza:
    45632: 02/07/30: Re: secure FPGA
GB:
    23222: 00/06/17: Re: Xilinx config over parallel port ?
    60180: 03/09/07: CMOS camera w/ USB2 -- crazy?
    60186: 03/09/07: Re: CMOS camera w/ USB2 -- crazy?
    60187: 03/09/07: Re: CMOS camera w/ USB2 -- crazy?
    116786: 07/03/18: how to transform Arun's LDPC code to max-product (Min-sum)?
<=?GB2312?B?R6iucnNraSBBZGFt?=>:
    124114: 07/09/12: Re: [Nios II] How fast the cpu in Nios II can reach in the Cycone
    131953: 08/05/08: Re: Quartus 7.2 and PCI Express
=?GB2312?B?y7y/vCAosfMp?=:
    126947: 07/12/06: Seeking help on xilkernel
=?GB2312?B?ybW5zw==?=:
    129482: 08/02/25: Does Altera has some analogous file like XDL of Xilinx?
<gbirot@yahoo.com>:
    86396: 05/06/27: Cant' make SignalTap works...
    86434: 05/06/28: Re: Cant' make SignalTap works...
<gburnore@databasix.com>:
    2457: 95/12/08: subscribe
<gburnore@netcom.com>:
    2458: 95/12/08: subscribe
<gburx@yahoo.com.au>:
    101235: 06/04/27: Development Platform for begginer
    101281: 06/04/28: Re: Development Platform for begginer
GC:
    57147: 03/06/24: Quartus II - Acex1k - Routing resources
    57177: 03/06/25: Re: Quartus II - Acex1k - Routing resources
Gcanderson:
    7993: 97/11/05: SPI implemented in an FPGA
    8043: 97/11/11: Re: Where can I find documents talking about constraining FPGA?
<gcarvajalb@gmail.com>:
    134580: 08/08/19: ML403 PPC and ISE tools: timestamp and <sysace_stdio.h>
    134599: 08/08/20: Re: ML403 PPC and ISE tools: timestamp and <sysace_stdio.h>
gcary:
    150087: 10/12/10: Re: How to find latches in Xilinx ISE 10.1
<GCAT@dorval.mpbtech.qc.ca>:
    906: 95/03/27: Re: 100MHz low power FPGAs
    1517: 95/07/06: re: 'romance' adds
    1691: 95/08/16: FPGAs with embedded RAM
    3063: 96/03/25: Re: Altera Classic Family
    3413: 96/05/27: re: WEIRD NOISE PROBLEM WITH XILINX XC3064
gcaw:
    57120: 03/06/23: Power sequencing on EP20K400E
    65630: 04/02/03: Tools for developing high-speed interfaces
gcurtis:
    3349: 96/05/17: Re: Windows NT & Xilinx & Cypress
gda:
    78364: 05/01/30: Re: Input registers in ispLEVER
<gdeych@my-deja.com>:
    21028: 00/03/03: Re: Extremely fault tolerant strategies
<gdk5249@vaxb.isc.rit.edu>:
    927: 95/03/30: SIS synthesist generation
GDR Enterprises:
    2082: 95/10/11: * WARNING * $1,000,000 in 90 Days!
ge:
    61355: 03/10/02: CUPL documentation?
    61356: 03/10/02: Re: CUPL documentation?
    61725: 03/10/09: cupl language reference?
    62002: 03/10/16: wincupl, winsim documentation?
gebirgeraider:
    69430: 04/05/11: instantiate an edf module with ise
Ged:
    139742: 09/04/11: buy XSA-50
    139872: 09/04/17: FPGA Buying
geeja:
    74201: 04/10/05: Re: XILINX FIX UP THE WEBPACK 6.3 DOWNLOAD !!!
geeko:
    47618: 02/10/01: TCP/IP in FPGA
    47632: 02/10/01: Re: TCP/IP in FPGA
    47992: 02/10/09: ebooks
    48033: 02/10/10: Re: TCP/IP in FPGA
    48709: 02/10/23: Flash Programmer
    51515: 03/01/15: Re: Student development board
    51602: 03/01/17: Re: Student development board
    51872: 03/01/24: AES(Rijindal) CTR with CBC MAC
    51874: 03/01/24: AMBA AHB compliant core
    52623: 03/02/17: SoC pheripheral Design Resouraces
    52647: 03/02/18: Re: SoC pheripheral Design
    53074: 03/03/03: Re: FPGA demo board schematic
    53079: 03/03/03: Design Flow --basic questions
    53080: 03/03/03: Bus Functional Model
    53652: 03/03/19: FPGA specs
    53654: 03/03/19: Excalibur bus functional model
    55532: 03/05/12: wire and reg and modelling of combinational logic
Geert Van Doorselaer:
    29343: 01/02/15: Configuration file of SpartanXL
    39022: 02/01/30: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
<geert.debaere28@gmail.com>:
    139863: 09/04/17: Re: Xilinx Impact cable not found
<geert@user1.be>:
    87698: 05/07/28: Logic lab programmer
Geezer:
    26455: 00/10/16: Re: ModelSim XE/Starter speed issues
Geiger Hope:
    43416: 02/05/21: military/industrial FPGA device suggestion request
    43591: 02/05/25: evaluation boards for virtex
Geir Atle Ward:
    38477: 02/01/15: Re: MSP430 + Xilinx via JTAG
Geir Botterli:
    65739: 04/02/05: A small clock synchronization challenge with Virtex E
    65825: 04/02/07: Re: A small clock synchronization challenge with Virtex E
    65841: 04/02/08: Re: A small clock synchronization challenge with Virtex E
    65899: 04/02/09: Re: A small clock synchronization challenge with Virtex E
Geir Ertzaas:
    940: 95/03/31: How do I connect an external crystal to a XC4000?
    4388: 96/10/23: Re: Xilinx xchecker.exe and Windows NT
Geir Frode Raanes:
    8075: 97/11/14: Re: scsi host adapter
    8214: 97/11/29: Re: AHDL vs. VHDL
    22494: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    31171: 01/05/14: Re: [Q]CardBus PC Card with PCI device
Geir Harris Hedemark:
    8833: 98/01/30: Re: VHDL vs schematics
    11585: 98/08/25: Re: Porn spamming
    12557: 98/10/16: Re: What's wrong at this Address decoder?
    12595: 98/10/19: Re: Schematic entry?
    14367: 99/01/27: Re: Ratings for Synplicity Synplify
    14380: 99/01/27: Re: Ratings for Synplicity Synplify
    14562: 99/02/04: Re: Ratings for Synplicity Synplify
    14806: 99/02/18: Re: Free circuit design
Geir Olav Berg:
    1472: 95/06/27: Lattice Semiconductor WWW ??
gen_vlsi:
    109024: 06/09/20: Tools that support ECO
    110878: 06/10/25: Stream cipher
    110961: 06/10/25: Re: Stream cipher
    112035: 06/11/15: How to configure Block RAMs with constant values
    112039: 06/11/15: Re: How to configure Block RAMs with constant values
    112046: 06/11/15: Re: How to configure Block RAMs with constant values
    112305: 06/11/19: false path
<gender\@ouwww.ou.edu>:
Gene N:
    16535: 99/05/27: Re: C to EDIF translator??Anyone?
Gene S. Berkowitz:
    56048: 03/05/27: Re: JTAG madness
    108252: 06/09/07: Re: Please help me with (insert task here)
    120949: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
Gene Wirchenko:
    146244: 10/03/09: Re: using an FPGA to emulate a vintage computer
<geneb@entropy.ultranet.com>:
    2270: 95/11/16: Re: Industry Trends
<geneb@ultranet.com>:
    10895: 98/06/29: Re: Xilinx file compression
General Schvantzkopf:
    126853: 07/12/04: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
    126864: 07/12/04: Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
    126890: 07/12/05: Re: can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation
    127059: 07/12/10: Re: GAL16V8
    127402: 07/12/20: Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
    133200: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
    133209: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
    133214: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
    133219: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
    133220: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
    133232: 08/06/21: Re: which commercial HDL-Simulator for FPGA?
    133315: 08/06/24: Re: Migrating to 9.2i from 8.2i
    133428: 08/06/28: Re: Standard forms for Karnaugh maps?
    135110: 08/09/16: Re: Xilinx build system
    135196: 08/09/19: Re: WebPack on CentOS 5 ?
    135713: 08/10/13: Re: How to synthesize a delay of around 10 ns in FPGA?
    135897: 08/10/20: Re: How to synthesize a delay of around 10 ns in FPGA?
General Schvantzkoph:
    64249: 03/12/22: Re: Hyperthreading vs. Dual proc
    69801: 04/05/20: Re: Malfunctioning dual port block ram.
    69987: 04/05/26: Re: What can I do if my chip can't meet timing?
    70319: 04/06/11: Re: Xilinx ParallelCable IV vs. Linux
    70500: 04/06/17: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
    70551: 04/06/20: Re: Is the Xilinix XC3020 atill supported?
    70772: 04/06/27: Running precision on Mandrake 10
    71002: 04/07/05: Re: Why 18X18 Multipliers in Altera and Xilinx?
    71142: 04/07/09: Re: comparison between FPGA and computer
    71538: 04/07/21: Re: Xilinx 6.2i ISE WebPACK running under wine?
    71613: 04/07/24: Re: VHDL model of Xilinx's Rocket I/O MGT
    71619: 04/07/25: Re: VHDL model of Xilinx's Rocket I/O MGT
    71708: 04/07/28: Re: FPGA vs CPLD
    71822: 04/08/01: Re: Spartan 3 prices
    71908: 04/08/03: Re: FPGA Selection--
    72028: 04/08/05: Re: How do I compare sizes of Altera vs Xilinx
    72130: 04/08/09: Re: Now I am really confused!
    72206: 04/08/11: Re: How important are software tools while choosing FPGA
    72531: 04/08/23: Re: Xilinx Swift interface Licence (?) problem
    73783: 04/09/29: Re: Virtex-II : Architecture
    73811: 04/09/29: Re: Pricing info for Synplify Pro Xilinx...
    73938: 04/10/01: Re: FPGA vs ASIC area
    73942: 04/10/01: Re: FPGA vs ASIC area
    73974: 04/10/01: Re: FPGA vs ASIC area
    73155: 04/09/14: Re: Virtex 4 released today
    74112: 04/10/04: Re: XST - undeterministic synthesis
    74343: 04/10/08: Re: 64 bit version of xilinx ISE
    74433: 04/10/11: Re: Student SATA project
    74438: 04/10/11: Re: Problem in Constraining Routing in Xilinx PAR
    74528: 04/10/13: Re: HDL-Models of CLB/Slice
    74584: 04/10/14: Re: 64 bit version of xilinx ISE
    75509: 04/11/08: Re: XST Question
    75891: 04/11/18: Re: Vccaux on Spartan 3
    75907: 04/11/18: Re: 5V inputs with series resistor on Spartan-3
    76132: 04/11/25: Re: how to evaluate the needed number of gate?
    78008: 05/01/22: Re: Copying/Reverse Engineering PAL
    78170: 05/01/25: Re: Another problem getting ISE 6.3i running on Linux
    82307: 05/04/10: Re: LVDS for lcd panel and RocketIO
    82643: 05/04/15: Re: Soft CPU vs Hard CPU's
    82695: 05/04/16: Re: Xilinx tools on Linux
    82713: 05/04/16: Re: Xilinx tools from the commandline
    115333: 07/02/07: Altera ByteBlaster and SignalTap on Fedora Core
    115339: 07/02/07: Re: Altera ByteBlaster and SignalTap on Fedora Core
    115369: 07/02/08: Re: Altera ByteBlaster and SignalTap on Fedora Core
    115661: 07/02/16: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
    116051: 07/02/28: Re: Altera Byte Blaster Cable on Linux
    116847: 07/03/19: Re: Xilinx ISE support for dual/quad core CPUs?
    118925: 07/05/07: License problems with Quartus 7.0 on Linux
    121456: 07/07/04: Can't get Actel tools to run on SL4.4 (RHEL 4.4)
    126022: 07/11/12: Re: newbie to 16v8
    126384: 07/11/20: Re: New Laptop for work
    137008: 08/12/18: iCore7 vs Core2 NCSim Performance?
    137150: 08/12/28: Re: FPGA > ASIC
    137706: 09/01/28: Re: XST Makes Odd Choice
    138125: 09/02/06: Re: Req for Recommendations: Modelsim vs IUS & VCS
    138486: 09/02/24: Re: XST hangs on HDL Analysis
    139987: 09/04/22: Re: ISE 11.1 still no MP support :(
    139989: 09/04/22: Re: ISE 11.1 still no MP support :(
    141045: 09/06/03: Re: BRAM/LUT Comparison
    141409: 09/06/23: Re: 10gbit phy interface
    141943: 09/07/18: Re: FPGA editor in Fedora 11 x86_64
    141964: 09/07/20: Re: FPGA editor in Fedora 11 x86_64
    141969: 09/07/20: Re: FPGA editor in Fedora 11 x86_64
    142063: 09/07/23: Re: FPGA development tools for FreeBSD?
    142065: 09/07/23: Re: FPGA development tools for FreeBSD?
    142068: 09/07/23: Re: FPGA development tools for FreeBSD?
    142073: 09/07/23: Re: FPGA development tools for FreeBSD?
    142075: 09/07/23: Re: FPGA development tools for FreeBSD?
    142135: 09/07/26: iCore7 vs Core2 simulation & FPGA tool performance?
    142156: 09/07/27: Re: Xilinx ISE 11.x lossage
    142181: 09/07/28: Re: iCore7 vs Core2 simulation & FPGA tool performance?
    142188: 09/07/28: Re: iCore7 vs Core2 simulation & FPGA tool performance?
    142364: 09/08/06: Re: iCore7 vs Core2 simulation & FPGA tool performance?
    142422: 09/08/10: Re: iCore7 vs Core2 simulation & FPGA tool performance?
    143710: 09/10/22: Re: OS for Xilinx tools
    143765: 09/10/24: Re: Generating delay using logic gates
    143810: 09/10/27: Re: synplify question for FPGA
    143831: 09/10/28: Re: synplify question for FPGA
    144846: 10/01/07: Re: new PC specs for Xilinx tools
    144849: 10/01/07: Re: new PC specs for Xilinx tools
    144864: 10/01/08: Re: new PC specs for Xilinx tools
    144868: 10/01/08: Re: new PC specs for Xilinx tools
    144936: 10/01/16: Re: Altera Quartus II on Debian GNU/Linux
    144937: 10/01/16: Re: Altera Quartus II on Debian GNU/Linux
    144950: 10/01/17: Re: Altera Quartus II on Debian GNU/Linux
    144952: 10/01/17: Re: Altera Quartus II on Debian GNU/Linux
    144954: 10/01/17: Re: Altera Quartus II on Debian GNU/Linux
    144965: 10/01/17: Re: Altera Quartus II on Debian GNU/Linux
    144976: 10/01/18: Re: Altera Quartus II on Debian GNU/Linux
    145151: 10/01/29: Re: In system memory editor of Altera for Xilinx
    145211: 10/02/01: Re: In system memory editor of Altera for Xilinx
    145249: 10/02/03: Re: What is the most area efficient CRC method
    145566: 10/02/14: Can the Altera USB cable attach to a KVM XP VM?
    145576: 10/02/14: Re: Can the Altera USB cable attach to a KVM XP VM?
    145595: 10/02/15: Re: Can the Altera USB cable attach to a KVM XP VM?
    145599: 10/02/15: Re: Can the Altera USB cable attach to a KVM XP VM?
    146007: 10/03/03: Re: Laptop for FPGA design?
    146174: 10/03/07: Re: Laptop for FPGA design?
    146179: 10/03/07: Re: Laptop for FPGA design?
    146305: 10/03/11: Compiling a design in Quartus that doesn't fit
    146309: 10/03/11: Re: Compiling a design in Quartus that doesn't fit
    146547: 10/03/22: Re: Why hardware designers should switch to Eclipse
    147262: 10/04/21: Re: Xilinx no longer ships with Modelsim MXE?
    147517: 10/04/29: Re: Large Fanout
    147590: 10/05/05: Signal name display in SignalTap
    147591: 10/05/05: Re: Signal name display in SignalTap
    147604: 10/05/06: Re: FPGA Compilation Time Windows vs Linux
    147610: 10/05/06: Re: FPGA Compilation Time Windows vs Linux
    147614: 10/05/07: Re: FPGA Compilation Time Windows vs Linux
    147978: 10/06/09: Re: How to Disable IP Core after Evaluation Period
    148018: 10/06/14: Re: Altera Quartus - how to create small roms & rams for Cyclone 3
    148451: 10/07/24: Re: Is Tier Logic doomed ? :-/
    148721: 10/08/18: Re: CE compliance testing
    148971: 10/09/16: New release of HDLmaker
    148973: 10/09/17: Re: New release of HDLmaker
    148978: 10/09/17: Re: New release of HDLmaker
    148982: 10/09/18: Re: New release of HDLmaker
    148986: 10/09/19: Re: New release of HDLmaker
    150221: 11/01/02: Re: I Give Up!
    150251: 11/01/05: Re: I Give Up!
    150608: 11/01/27: V6 SerDes simulation
    151074: 11/03/03: Altera vs Xilinx PCIe cores
    151075: 11/03/03: Altera vs Xilinx PCIe cores
    151172: 11/03/13: FPGA boards
    151273: 11/03/19: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of
    152339: 11/08/10: Is there a utility to peek and poke PCIe devices
    152350: 11/08/11: Re: Is there a utility to peek and poke PCIe devices
    152353: 11/08/11: Re: Is there a utility to peek and poke PCIe devices
    152562: 11/09/14: Can't get the Xilinx cable drivers installed on SL6.1 (RHEL 6.1)
    152565: 11/09/15: Re: Can't get the Xilinx cable drivers installed on SL6.1 (RHEL
    152575: 11/09/15: Re: Can't get the Xilinx cable drivers installed on SL6.1 (RHEL
    152757: 11/10/19: USB hangs on the Xilinx USB II Cable
    152762: 11/10/19: Re: USB hangs on the Xilinx USB II Cable
    152939: 11/11/02: Re: Xilinx USB II Cable driver under Gentoo Linux
    153070: 11/11/25: Re: XC7V2000T, the perfect Thanksgiving gift
    153338: 12/02/02: Virtex6HXT PCIe doesn't come up to Gen2 on Sandy Bridge systems
    153520: 12/03/22: Virtex6HXT PCIe 8X Gen2 timing closure problem
    154164: 12/08/23: How do you do an incdir in Vivado
    154167: 12/08/24: Re: How do you do an incdir in Vivado
Genio Kronauer:
    19550: 99/12/30: XC9500 0,5u Mask: Errors?
genius:
    50025: 02/11/28: Re: Finding MPEG1 & MPEG2 codec chips?
genlock:
    80189: 05/03/02: PLL code
    80245: 05/03/02: Re: PLL code
    80367: 05/03/04: Re: PLL code
    80438: 05/03/05: Re: PLL code
    81667: 05/03/29: Dividing a 24 bit std_logic_vector by a decimal number
    81674: 05/03/29: Re: Dividing a 24 bit std_logic_vector by a decimal number
    81679: 05/03/29: Re: Dividing a 24 bit std_logic_vector by a decimal number
    81777: 05/03/31: Re: Dividing a 24 bit std_logic_vector by a decimal number
    81778: 05/03/31: Re: Dividing a 24 bit std_logic_vector by a decimal number
    81779: 05/03/31: Re: Dividing a 24 bit std_logic_vector by a decimal number
    81787: 05/03/31: Re: Dividing a 24 bit std_logic_vector by a decimal number
Gennadij Volkov:
    18069: 99/09/27: SAA7146A SDK
Genome:
    87902: 05/08/03: Re: System Engineering in the R/D World
    87954: 05/08/04: Re: System Engineering in the R/D World
    99818: 06/03/29: Re: deglitching a clock
    104047: 06/06/17: Re: Hold margin for asynchronous Interface
    107973: 06/09/03: Re: Performance Appraisals
    112291: 06/11/19: Re: board - T562.jpg
    114204: 07/01/07: Re: Basic questions about digital phase locked loop
gentel:
    143894: 09/11/02: Problem integrating EDK project in ISE 9.1
    143906: 09/11/02: probelms in EDK/ISE
    143913: 09/11/03: Re: probelms in EDK/ISE
    143914: 09/11/03: Re: probelms in EDK/ISE
    143917: 09/11/03: Re: probelms in EDK/ISE
    143919: 09/11/03: Re: probelms in EDK/ISE
    143940: 09/11/04: Data2MEM Error - 33 : Matching ADDRESS_SPACE not found
    143956: 09/11/04: Re: Data2MEM Error - 33 : Matching ADDRESS_SPACE not found
    144349: 09/11/29: chipscope in edk
    144350: 09/11/29: chipscope in edk
    144358: 09/11/30: user ip in edk
    144883: 10/01/12: Timing errors in Post route simulation in modelsim
    144884: 10/01/12: Timing errors in Post route simulation in modelsim
    144896: 10/01/12: Re: Timing errors in Post route simulation in modelsim
    145033: 10/01/21: user ip in edk
gentel86:
    143887: 09/11/02: xilinx ise and edk work together
    143888: 09/11/02: xilinx ise and edk work together
<gentrysm1@gmail.com>:
    157457: 14/12/11: Re: difference between fpga and epld
geo:
    52868: 03/02/24: AHB
GEO:
    95651: 06/01/25: Re: Webpack 8.1i size
    95797: 06/01/26: Re: Webpack 8.1i size
    95787: 06/01/25: Re: open source fpga programmer programs
    96522: 06/02/05: hprep crash with ISE 8.1i, service pack1
    96586: 06/02/06: Re: please let me know what hardware is generated for this piece of verilog code
geobsd:
    151134: 11/03/09: pcb&bitstream
    151140: 11/03/10: Re: Pull up/down resistors on Spartan-3E configuration inputs
    151141: 11/03/10: Re: pcb&bitstream
    151142: 11/03/10: Re: pcb&bitstream
    151147: 11/03/11: Re: pcb&bitstream
    151148: 11/03/11: Re: Anti-benchmarking clauses
    151149: 11/03/11: Re: Nanosecond pulse generator using Spartan-3E
    151156: 11/03/12: Re: pcb&bitstream
    151159: 11/03/12: Re: pcb&bitstream
    151160: 11/03/12: Re: pcb&bitstream
    151161: 11/03/12: Re: pcb&bitstream
    151162: 11/03/12: Re: pcb&bitstream
    151165: 11/03/12: Re: pcb&bitstream
    151167: 11/03/12: Re: pcb&bitstream
    151168: 11/03/12: Re: pcb&bitstream
    151171: 11/03/13: Re: pcb&bitstream
    151174: 11/03/13: Re: pcb&bitstream
    151181: 11/03/14: Re: pcb&bitstream
    151186: 11/03/14: Re: pcb&bitstream
    151202: 11/03/15: Re: pcb&bitstream
    151239: 11/03/17: Re: pcb&bitstream
    151245: 11/03/17: Re: pcb&bitstream
    151246: 11/03/17: Re: pcb&bitstream
    151257: 11/03/18: Re: pcb&bitstream
    151260: 11/03/18: Re: pcb&bitstream
    151263: 11/03/18: Re: pcb&bitstream
    151272: 11/03/19: Re: pcb&bitstream
    151287: 11/03/20: Re: pcb&bitstream
geoerge:
    75353: 04/11/02: hostid for Actel Designer
    75358: 04/11/03: Re: "frying" FPGAs
    75453: 04/11/05: Re: hostid for Actel Designer
    75619: 04/11/10: Re: hostid for Actel Designer
geof:
    4579: 96/11/17: Re: Just try this SCAM FOR $$$$
Geoff Rubner:
    1492: 95/06/29: aynchronous ripple counter
    1557: 95/07/14: Re: aynchronous ripple counter
Geoff Yarbrough:
    17907: 99/09/16: speeding up place and route
Geoffrey Bostock:
    4992: 97/01/09: Re: FAQ
    5026: 97/01/14: Re: Any PEEL22CV10A replacements with more capacity?
    5179: 97/01/29: Re: Synthesizing fast counter (carry look ahead adder)
    5326: 97/02/07: Re: Duplicate PLD?
    5701: 97/03/08: Re: Reverse Engineering FPGAs
    5780: 97/03/14: Re: pld 74hc195 equiv
    5993: 97/04/03: Re: XC2018
    5995: 97/04/03: Re: New Technology
Geoffrey Brown:
    821: 95/03/07: Implementing Asynchronous Circuits
    1035: 95/04/19: re: free hardware
    2981: 96/03/08: Re: Reconfigurable Computing Languages
    2990: 96/03/09: Re: Reconfigurable Computing Languages
    69843: 04/05/21: Re: Nios II Going Live...
geoffrey brown:
    70186: 04/06/08: Nios II really available ?
Geoffrey Furman:
    48758: 02/10/23: Xilinx POS Power On Surge Current
    48789: 02/10/24: Re: Xilinx POS Power On Surge Current
    48790: 02/10/24: Re: Who has some Lecture materialson I2C Bus?
    49016: 02/10/29: Re: Xilinx POS Power On Surge Current (... the Starbucks connection)
Geoffrey G. Rochat:
    20464: 00/02/11: Re: Altera vs Cypress?
    24297: 00/08/02: Re: 8251A USART
    27166: 00/11/13: Re: Spartan-II with 5V ISA bus
    27253: 00/11/16: Re: Spartan-II with 5V ISA bus
    28672: 01/01/20: Re: How to be a more efficient productive FPGA designer ?
    30485: 01/04/10: Re: small, fast, w/ PECL?
    49291: 02/11/07: Re: Instruction sets to implement instruction sets
    61866: 03/10/14: Re: FPGA/CPLD With Analog Functions?
Geoffrey Liersch:
    2062: 95/10/09: Re: FFT in FPGAs ?
Geoffrey Mortimer:
    62296: 03/10/24: Re: The Luddite Needs Reference Books...
    69117: 04/04/27: Strange message from Xilinx 6.2.01i
Geoffrey Wall:
    71755: 04/07/29: pci X open core
    71911: 04/08/03: PCI express FPGA board
    72781: 04/09/01: virtex II on pci bus devboard
    74044: 04/10/02: best way to perform multiplies in vhdl
    73047: 04/09/12: altera stratix II dev boards
    74256: 04/10/06: 64 bit version of xilinx ISE
    75521: 04/11/08: alpha data v2 ADP-DRC-II board
    76905: 04/12/15: storing convolution coeeff's Xilinx V2 8000
    78104: 05/01/24: trouble setting up ISE 6.3i in linux
geoffrey wall:
    69580: 04/05/14: best fpga development board?
    69586: 04/05/14: Re: best fpga development board?
    81882: 05/04/03: PLX-9656 Controller interface
    82165: 05/04/07: xilinx embedded MAC
    83894: 05/05/09: dcm's for increasing clock speed
    86173: 05/06/22: simple SRAM memory controller Avnet V2P development board
    86251: 05/06/23: XILINX DCMs and synthesis results
    86407: 05/06/27: experiences with Summit Visual Elite
    86600: 05/06/30: Avnet V2P development kit woes
    86641: 05/07/01: vhdl source code cross reference tool
    87654: 05/07/27: No clock signals found in this design... XST V2P
    87696: 05/07/28: chipscope and V2P problems
    87977: 05/08/04: xilinx nallatech v4 extreme dsp development boards
    88014: 05/08/05: Virtex 4 development boards
    88597: 05/08/23: chipscope problems
    88651: 05/08/24: Re: chipscope problems
    89317: 05/09/12: reducing the number of IOBS in a design
    89973: 05/09/30: fixed point dot product with log2(n) pipe stages in vhdl
    90001: 05/10/01: for...generate loop with generics, constants (vhdl)
Geogle:
    84140: 05/05/12: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
    84198: 05/05/13: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
    84243: 05/05/16: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
    84371: 05/05/17: Detaching the schematic viewer under ISE Webpack
    84527: 05/05/20: Re: Detaching the schematic viewer under ISE Webpack
    84561: 05/05/20: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
    84604: 05/05/22: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
    84655: 05/05/24: Re: more and more and more issues with Xilinx tools
Georg:
    48452: 02/10/17: Re: How assingment of IOE by Quratus Ver2.1
Georg Acher:
    1471: 95/06/27: Re: Place-n-Route service
    2315: 95/11/19: Re: Xilinx XACT Windows Version
    3009: 96/03/13: Re: Xact6.o too slow
    3667: 96/07/10: Re: FPGA - RAM interfacing
    5347: 97/02/09: Re: Anyone for Linux ?
    6644: 97/06/09: Re: PCI how to
    9504: 98/03/19: Re: Strange Xilinx question?
    16263: 99/05/12: Re: Fancy Dram problem
    18002: 99/09/22: Re: Programming Spartan XL
    26527: 00/10/19: Re: Synopsys FPGA Compiler II on Solaris
    28137: 00/12/22: Re: driving color VGA from FPGA ??
    28360: 01/01/10: Re: Alliance for Linux
    35743: 01/10/16: Xilinx coregen and Linux (success)
    36050: 01/10/27: Re: S/PDIF interface for FPGA
    37184: 01/12/03: Re: PCI card - 2 layers versus four layers
    38600: 02/01/18: Re: Audio time delay circuit
    40151: 02/02/28: Re: Synopsys Design Compiler
    40214: 02/03/02: Re: Synopsys Design Compiler
    40620: 02/03/12: Re: spartan2e startup module not being expanded
    40777: 02/03/15: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
    40782: 02/03/15: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
    41163: 02/03/21: Re: coregen under Solaris
    41191: 02/03/22: Re: coregen under Solaris
    41956: 02/04/11: Re: Price List ?
    42285: 02/04/19: Re: 1000 I/O Pins -- What is cheapest FPGA?
    42414: 02/04/23: Re: Factor of 2 problem while using xilinx multiplier core
    46936: 02/09/12: Re: XILINX FPGA output not right
    47252: 02/09/21: Re: Xilinx ISE5.1 and Windows NT
    54147: 03/04/03: Re: More FFT Questions
    54183: 03/04/04: Re: More FFT Questions
    54184: 03/04/04: Re: More FFT Questions
    54287: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
    54288: 03/04/07: Re: price of fpga chips
    54416: 03/04/10: Re: ieee1284
    61588: 03/10/07: Re: Installing Xilinx 6.1 under Linux
    61655: 03/10/08: Re: Installing Xilinx 6.1 under Linux
    62066: 03/10/17: Re: ISE5.2 to ISE6.1
    62886: 03/11/10: Re: Home grown CPU core legal?
    72750: 04/08/31: Re: From good-old ISA bus cards to PCI bus
    72762: 04/08/31: Re: From good-old ISA bus cards to PCI bus
    75506: 04/11/08: Re: XST Question
    80878: 05/03/13: Re: Which HDL?
    88101: 05/08/09: Re: MPEG-2 links please
    90015: 05/10/02: Re: Xilinx/Linux: sch2vhdl not working very hard
    92405: 05/11/29: Re: Cypress FX2 bandwidth problem
    95829: 06/01/26: Re: ISE8.1 on Linux, first impressions
    95594: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    110433: 06/10/15: Re: SPAM - Re: Platform USB Cable schematic
    111601: 06/11/06: Re: surprised output of Xilinx Virtex-4
    113112: 06/12/06: Re: Free Anydivider, Divide clock by any number
    114951: 07/01/27: Re: On-chip randomness (V4FX)
    115014: 07/01/29: Re: On-chip randomness (V4FX)
    115044: 07/01/30: Re: USB 2.0 Streaming using FPGAs
    115502: 07/02/12: Re: Picobalze in the FPGA
    115662: 07/02/16: Re: Do you like Virtex-5 ?
    118006: 07/04/16: Re: Xilinx ISE 9.1
    118023: 07/04/16: Re: Xilinx ISE 9.1
    119174: 07/05/14: Lockup with Xilinx mch_opb_ddr
    119327: 07/05/16: Re: Lockup with Xilinx mch_opb_ddr
    121102: 07/06/25: Re: Xilinx FPGA: "after 10ns" constraint
    121886: 07/07/14: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
    122597: 07/08/01: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
    122602: 07/08/01: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
    122628: 07/08/01: Re: Xilinx/ModelSim bug ? Clocking headache ...
    122802: 07/08/07: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122819: 07/08/07: Re: SDR SDRAM controller for Xilinx Spartan-3E
    127464: 07/12/27: Re: Xilinx XST questions
    130515: 08/03/26: Re: counterfeit Xilinx ?
    130564: 08/03/27: Re: counterfeit Xilinx ?
    131329: 08/04/19: Re: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff
    137966: 09/02/03: Re: Spartan-6
    139558: 09/04/03: Re: delays in XC95144XL CPLD
    149245: 10/10/11: Re: matched filter(root raised cosine)
Georg Berliner:
    20960: 00/03/01: Re: Xilinx Tools Vs Altera tools
    22504: 00/05/10: Re: Altera Megafunction in Exemplar Leonardo
    27052: 00/11/08: Re: renoir, acex + dpram
    27109: 00/11/11: Re: Leonardo for Altera
Georg Diebel:
    6931: 97/07/10: Simulating large VHDL design (FPGA backannotated)
    6939: 97/07/11: Re: VHDL Synthesis in Xilinx Foundation Series
    10497: 98/05/25: Re: Partitioning an a large design in Altera's Max+Plus II
    18152: 99/10/04: Re: Does anyone have a Altera BitBlaster shematic? (0)
Georg Heinrich:
    26302: 00/10/11: Constraints in FPGA Comp. II
    26367: 00/10/13: Re: VHDL synthesis with synopsys
    27061: 00/11/09: Expirience with FPSLIC
    43612: 02/05/27: ALtera SOPC Builder
    46181: 02/08/21: "Tall Thin Engineer"
Georg Heinrich, Student:
    26264: 00/10/10: Difference FPGA Compiler 1/2 from SYNOPSYS
George:
    6157: 97/04/18: Re: Pentium Pro Worth it for Altera Max Plus?
    13776: 98/12/24: about using Mentor and Foudation together
    13819: 98/12/28: How to import EDIF file in Foundation Software?
    17734: 99/08/27: test!
    17735: 99/08/27: PLL cascading in VIRTEX
    17950: 99/09/18: test
    18101: 99/09/30: Fine grain vs. Coarse grain
    18109: 99/09/30: Re: Fine grain vs. Coarse grain
    18777: 99/11/14: test
    19099: 99/11/29: FPGA vs DSP vs PENTIUM MMX
    19127: 99/12/01: Re: FPGA vs DSP vs PENTIUM MMX
    19688: 00/01/08: XC4000 Configuration Bitstream structure
    19761: 00/01/11: Re: XC4000 Configuration Bitstream structure
    19965: 00/01/20: Xilinx vs. other FPGAs manufactrers
    20077: 00/01/26: EEPROM based FPGAs
    20339: 00/02/06: Availability of Virtex E Series
    20340: 00/02/06: FG1156 package for non-E XCV1000
    20341: 00/02/06: Re: Availability of Virtex E Series
    20465: 00/02/11: RLOC_RANGE property.
    20466: 00/02/11: RLOC_RANGE property.
    20467: 00/02/11: RLOC_RANGE property.
    20504: 00/02/12: Re: RLOC_RANGE property.
    20588: 00/02/15: Re: Is EDIF format adopted by all FPGA manufacturers???
    20998: 00/03/02: restrictions due to signal types of Global Clock inputs for Virtex
    21680: 00/03/29: VHDL at RTL level vs. floorplanning.
    21712: 00/03/29: Re: VHDL at RTL level vs. floorplanning.
    22186: 00/04/30: Help!
    36804: 01/11/20: I need a Xilinx Spartan PCI Development Board
    47127: 02/09/18: Re: Can I run a 3.3V CPLD off of 3V?
    59874: 03/08/30: Shift register
    62318: 03/10/26: SDRAM Controller
    62341: 03/10/27: Re: SDRAM Controller
    63908: 03/12/08: Re: NIOS: Running code from flash
    63909: 03/12/08: Re: Quartus-II question
    63910: 03/12/08: Re: increase NIOS processor clock speed on APEX20K200E device
    64621: 04/01/09: FLASH memory programming with Altera NIOS and same question for Xilinx
    64622: 04/01/09: Re: Large/Fast static RAM
    64640: 04/01/09: Re: FLASH memory programming with Altera NIOS and same question for Xilinx
    65628: 04/02/03: Re: 4 bit divisor with flip-flop ?
    67491: 04/03/12: Altera Quartus II 4.0 won't talk to ByteBasterMV
    68048: 04/03/25: Altera NIOS SOPC Builder---- Can I edit a text file
    68183: 04/03/29: ISE and EDK Incompatible?
    68284: 04/03/31: Re: XAPP134's VHDL code
    68689: 04/04/14: Re: Yet Another Altera Online Support Is USELESS Rant...
    69256: 04/05/03: Best way to handle multiple common data busses in Altera FPGA (and others)
    69280: 04/05/04: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
    69347: 04/05/07: Re: Mutiple Quartus Instances?
    69877: 04/05/22: Re: More fun with VHDL
    70067: 04/06/01: NIOS 2 memory limitations
    70073: 04/06/01: Re: NIOS 2 memory limitations
    70075: 04/06/01: NIOS I memory usage
    71552: 04/07/21: FPGA Selection--
    71570: 04/07/22: Re: Changing directory name in Quartus
    71623: 04/07/25: Re: Image export from Quartus?
    71799: 04/07/30: Altera Configuration Device
    72897: 04/09/07: Re: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
    75007: 04/10/24: Re: Nios & off-chip memory
    75054: 04/10/25: Viewing/Controling C-Build Outputs
    98760: 06/03/16: Purchasing Virtex-4 FPGAs
    128310: 08/01/21: bi-phase decoding
    128515: 08/01/29: HDLC
    129511: 08/02/26: Re: Does Altera has some analogous file like XDL of Xilinx?
    129541: 08/02/27: Re: Does Altera has some analogous file like XDL of Xilinx?
    143196: 09/09/25: Weird DDR Addressing problem
    143198: 09/09/25: Re: Weird DDR Addressing problem
    143199: 09/09/25: Re: Weird DDR Addressing problem
    143208: 09/09/25: Re: Weird DDR Addressing problem
    146799: 10/03/29: Re: Wrong DDR communication
george:
    99428: 06/03/24: dai
George (Lingkan) Gong:
    154417: 12/10/27: RTL simulation of Dynamic Partial Reconfiguration and Dynamically
George Boudreau:
    142867: 09/09/04: Re: Spartan-6 boards now REALLY in online shops
George Brims:
    3105: 96/04/02: Re: Ethernet and GPS WWW sites ??
George Carlson, CPC:
    83382: 05/04/28: FPGA applications in RFID
George Constantinides:
    36187: 01/11/01: Xilinx multiplier core - problem
    36189: 01/11/01: Xilinx Foundation: Generation of EDIF from VHDL in Batch Mode
George Cooper:
    16781: 99/06/08: Re: Any free timing diagram tools?
George Coulouris:
    28273: 01/01/04: Re: Nondeterministic FSMs in hardware?
    28309: 01/01/05: Re: Nondeterministic FSMs in hardware?
George D:
    156581: 14/05/04: in my xps implementaion elf file is not generated only the linker
George Davis:
    22305: 00/05/04: Product Applications Engineer
    22308: 00/05/04: Mixed Signal Design
    22302: 00/05/04: RF System Design Engineer
George E. Smith, Jr:
    14066: 99/01/11: Re: I2C core
    15757: 99/04/12: One hot comes up cold
George Eccles:
    46809: 02/09/09: atmel CPLD documentation
    46814: 02/09/09: Re: atmel CPLD documentation
    46883: 02/09/10: Re: atmel CPLD documentation
George Fang:
    10316: 98/05/11: Chicken & egg problem in PCI/CardBus designs using FPGA
    54314: 03/04/07: Q: Constraints for high speed I/O signals.
    54365: 03/04/09: Re: Q: Constraints for high speed I/O signals.
George Gallant:
    15749: 99/04/12: SUBSCRIBE
George Herbert:
    4776: 96/12/13: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4912: 96/12/29: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5154: 97/01/27: Re: ASICs Vs. FPGA in Safety Critical Apps.
    7012: 97/07/22: Re: PCI burst transfers
    7013: 97/07/22: Re: PCI burst transfers
George Hodges:
    42030: 02/04/13: Slave serial loading of spartan II bitstream
George Jefferson:
    146498: 10/03/20: Re: Xilinx only on Avnet now
George Karypis:
    8823: 98/01/29: Announcing hMETIS, A Circuit Partitioning Package
    10820: 98/06/23: ANNOUNCE: hMETIS 1.5, A Circuit Partitioning Package
George Kiss:
    306: 94/10/17: Re: in circuit programming
George Koukouras:
    26271: 00/10/10: Delay locked loop in a Spartan II
    26300: 00/10/11: Re: Delay locked loop in a Spartan II
George Lurker:
    6498: 97/05/28: Technical Recruiters
George Mercury:
    80811: 05/03/11: Interfacing Compact Flash with Spartan 3
    80821: 05/03/11: Re: Interfacing Compact Flash with Spartan 3
    82732: 05/04/17: Spartan 3E slower that Spartan 3?
    87588: 05/07/26: The new IOBUF in Spartan-3E
George Mills:
    3680: 96/07/11: Check out this Logic Design/Simulator (Free Alpha)
    3679: 96/07/11: Re: emulation software
George Neuner:
    22581: 00/05/12: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    25866: 00/09/23: Re: hardware compatibility and patent infringement
    147321: 10/04/22: Re: Need to run old 8051 firmware
George Noten:
    1794: 95/09/04: Re: timing constraints in xilinx
    2100: 95/10/14: Re: * WARNING * $1,000,000 in 90 Days!
    2101: 95/10/14: Re: Needed: Suggestions for FPGA design CAD
    2222: 95/11/05: Re: AT&T vs. Xilinx
    2426: 95/12/04: Re: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
    2735: 96/01/31: Re: XILINX XACT 6.0.0 Tools flaky
    3372: 96/05/22: Re: Xilinx and Viewlogic
    4370: 96/10/21: Re: VHDL for Xilinx designs?
    4444: 96/10/30: Re: VHDL for Xilinx designs?
    5155: 97/01/27: Re: Altera support better than Xilinx
    5181: 97/01/29: Re: Altera support better than Xilinx
    5182: 97/01/29: Re: FPGAs with internal Tri-state busses ?
    5210: 97/01/31: Re: Altera support better than Xilinx
    5211: 97/01/31: Re: Altera support better than Xilinx
    5754: 97/03/12: Re: A viewlogic story
    5634: 97/03/03: Re: Customizing Viewdraw in Workview Office 7.3 ... Is it possible?
    6302: 97/05/12: Re: Desperate college students need help!!!
    7020: 97/07/23: Re: VHDL Synthesis in Xilinx Foundation Series
    7329: 97/08/27: Re: VHDL Synthesis for Linux?
    8824: 98/01/29: VHDL vs schematics
George Orwell:
    102008: 06/05/09: Max operating freq in a breadboard
George P. Burdell:
    29453: 01/02/22: Virtex USB solution
George P. Kosmopoulos:
    37399: 01/12/09: Re: Altera pin drivers
George Patrick:
    3810: 96/08/05: Re: Job posting
George Pontis:
    4964: 97/01/05: Serial download to Altera & Xilinx ?
    5097: 97/01/22: Altera support better than Xilinx
    5125: 97/01/24: Re: Altera support better than Xilinx
    8261: 97/12/03: Xilinx M1, NT, and 5200
    8284: 97/12/05: Capture 7.0 design entry for Xilinx M1 ?
    11097: 98/07/18: Xilinx Dynatext and NTFS ?
    12728: 98/10/26: Re: FPGA Decouple Capacitor values
    24316: 00/08/03: PWM implementation suggested sought for Spartan FPGA
    26971: 00/11/06: Need help locking pins for Spartan XL
    27006: 00/11/07: Re: Need help locking pins for Spartan XL
George Russell:
    20862: 00/02/24: Re: Bit Serial Arithmetic De-mystified
George Schmitt:
    35: 94/08/02: Re: How pricey is FPGA development?
    1637: 95/08/09: external connections for efficient internal routing
    1664: 95/08/12: Re: external connections for efficient internal routing
George Shin:
    575: 95/01/09: [shin]OrCad .sch to Xilinx .xdf conversion seeking
    653: 95/01/29: [shin]Synthesis tools ported to Linux available???
    672: 95/02/02: [shin]Anyone ported or have patches for OCTTOOLS to Linux?
George Smith:
    70982: 04/07/04: uClinux on MicroBlaze
George Tzanatos:
    7184: 97/08/12: Re: Are 2 PCs better than One?
George Un-Spam Schmitt:
    43586: 02/05/24: Xilinx "Real PCI-X" core capabilities
<George.Y.Ma@gmail.com>:
    105093: 06/07/13: Universal Scan with Xilinx's ML403
    105106: 06/07/13: Re: Universal Scan with Xilinx's ML403
<george_granata@hotmail.com>:
    114886: 07/01/25: OrCAD symbol for the Xilinx V5LX50 FF676 device
Georges Konstantinidis:
    65487: 04/01/30: asynchronous counter an Xilinx FPGA for a newbie
    65515: 04/01/31: Re: asynchronous counter an Xilinx FPGA for a newbie
    65564: 04/02/02: Re: asynchronous counter an Xilinx FPGA for a newbie
    65565: 04/02/02: Re: asynchronous counter an Xilinx FPGA for a newbie
    65594: 04/02/03: Re: asynchronous counter an Xilinx FPGA for a newbie
Georgi Beloev:
    15641: 99/04/06: newbie: FPGA suggestion
    20304: 00/02/04: OE in hierachial ABEL design
    22906: 00/05/31: Re: search PCB programmer VHDL
    49021: 02/10/29: Re: Xilinx FPGA <> CPLD implementation "mis-match"
    49704: 02/11/19: Re: What combinational logic will produce a falling edge only.
    51205: 03/01/06: Re: asynchronous inputs
    63969: 03/12/10: Re: Soldering of FPGAs
    65789: 04/02/06: Re: need desperate help!
    65875: 04/02/09: Re: need desperate help!
    67908: 04/03/22: Re: Help recognizing format
    70910: 04/07/01: Re: Xilinx $99 Spartan-3 kit
    72540: 04/08/23: DSP/FPGA/video board?
    72649: 04/08/27: Re: DSP/FPGA/video board?
    77880: 05/01/19: Re: video decoder for altera dev. board
    77885: 05/01/19: LVDS through connectors
    77925: 05/01/20: Re: LVDS through connectors
    77927: 05/01/20: Re: LVDS through connectors
    77986: 05/01/21: Re: How does a SDRAM controller work?
    78306: 05/01/28: Re: LVDS through connectors
    78423: 05/01/31: Re: Active HIGH / Active LOW
    78469: 05/02/01: Re: Synchronizing multibit bus - 2
    79897: 05/02/25: Re: VIE in electronic and FPGA design
Georgios Pouiklis:
    99095: 06/03/20: Looking for a V4FX development board
Georgios Sidiropoulos:
    90313: 05/10/10: VHDL : Use concatenation on port mapping
    90314: 05/10/10: Re: VHDL : Use concatenation on port mapping
    90576: 05/10/17: Re: VHDL : Use concatenation on port mapping
    92043: 05/11/21: Modelsim Verification : Retain FSM state names
Gerald:
    94004: 06/01/04: ISE Evaluation version
Gerald B:
    31293: 01/05/17: cPCI upper clamp diode
    32758: 01/07/07: Re: Large Power up Current on Spartan2
    32885: 01/07/10: Re: Large Power up Current on Spartan2
    34206: 01/08/16: Re: Help with ACEX1K100 device
Gerald Bretschneider:
    55438: 03/05/08: Design Protection Spartan2
Gerald Coe:
    7015: 97/07/23: Re: free FPGA software from actel
    7846: 97/10/22: Re: generic library for lattice isp
    7847: 97/10/22: Re: generic library for lattice isp
    11280: 98/08/01: Re: how much ? prices of Xilinx chips
    11611: 98/08/26: Re: CPLD/FPGA software
    11658: 98/08/29: Re: CPLD/FPGA software
    11979: 98/09/23: Re: Efficient max-function architecture?
    12404: 98/10/11: PCI target code
    13535: 98/12/08: Re: The best PLD?
    14156: 99/01/15: Re: AT40K popularity and available tools...
    35660: 01/10/12: Re: Lattice discontinues all smaller MACH circuits and other devices
    35688: 01/10/13: Re: Lattice discontinues all smaller MACH circuits and other devices
gerald coe:
    15090: 99/03/05: Re: Looking for advice on CPLD's
    17553: 99/08/10: Re: XILINX Implementation Problem
    21323: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
    21612: 00/03/26: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
    22669: 00/05/17: Re: SMT 7 segment display ??
Gerald Shin:
    14477: 99/01/31: Espresso logic tool
Gerald T. Caracciolo:
    2027: 95/10/03: Generic use of Serial Configuration EPROMs
Gerald Weile:
    37342: 01/12/07: Re: Synplify to Actel clkbuf problems
    60113: 03/09/05: Q: Xilinx PROM file generation
<geraldwilliams@hotmail.com>:
    7896: 97/10/27: DSP functions on FPGAs
Gerard:
    26912: 00/11/03: New (worse!) timing parameters in Quartus 2000.09 for APEX devices
    43674: 02/05/29: Re: XACT - Xilinx design editor for a 2018 design desperately needed ...
    57138: 03/06/24: Re: regarding I2C protocols
Gerard Auclair:
    21463: 00/03/22: Re: Clock nets using non-dedicated resources
gerard Thierry:
    61114: 03/09/29: Re: Xilinx ISE 6.1i DCM is dead
Gerard van Soest:
    2966: 96/03/07: Query re Xilink PCI Interface in XC3164A - App note
Gerard Williams III:
    2051: 95/10/06: VHDL and Xilinx (Hard/Soft) Macros
    2074: 95/10/10: Re: VHDL and Xilinx (Hard/Soft) Macros
Gerardo Sosa:
    53476: 03/03/13: Integrating an VHDL component in a project in Handel-C
    53651: 03/03/18: Re: Integrating an VHDL component in a project in Handel-C
    53766: 03/03/21: Re: Integrating an VHDL component in a project in Handel-C --- it works!!!!
    62012: 03/10/16: Blocks RAM in HandelC
    62024: 03/10/16: Re: Blocks RAM in HandelC
    62813: 03/11/07: Capturing Video with RC200E board of Celoxica
<gerbil@zip.com.au>:
    32346: 01/06/24: Re: Help needed: New user with Xilinx WebPack and XC9572 counter design - how to do basic things
Gerd:
    71665: 04/07/27: Re: 1GHz FPGA counters
    71672: 04/07/27: Re: 1GHz FPGA counters
    71783: 04/07/30: Re: NCD difference
    71842: 04/08/02: Re: 1GHz FPGA counters
    72036: 04/08/06: Re: EDK tutorial?????
    72202: 04/08/11: SelectMAP problem
    72327: 04/08/15: Re: Can PPC in V2P reconfig the FPGA slices?
    72349: 04/08/16: Re: Can PPC in V2P reconfig the FPGA slices?
    72366: 04/08/17: Re: Can PPC in V2P reconfig the FPGA slices?
    72372: 04/08/17: Re: Can PPC in V2P reconfig the FPGA slices?
    72376: 04/08/17: Re: Can PPC in V2P reconfig the FPGA slices?
    72504: 04/08/21: Re: Can PPC in V2P reconfig the FPGA slices?
    72522: 04/08/23: Re: XC2V250 protoboard
    72574: 04/08/25: Re: XC2V250 protoboard
    76538: 04/12/06: Re: HWICAP
    111735: 06/11/09: Re: Microblaze : FSL bus
    112175: 06/11/17: ML405: Board support package
gerd:
    110792: 06/10/23: Microblaze : FSL bus
Gerd B.:
    63100: 03/11/14: Re: Color STN LCD controller
    63117: 03/11/15: Re: Altera's EPCS programming algorithm
    63136: 03/11/16: Re: Altera's EPCS programming algorithm
    63558: 03/11/25: Re: any FPGA design for video frame memory control?
Gerd Beil:
    14195: 99/01/19: Q:Hardware debugging with Xilinx M1.4
    14525: 99/02/03: Q:EEPROM for Xilinx XC4k
Gerd Rausch:
    18450: 99/10/25: interface effort
Gerd Reichle:
    71346: 04/07/15: connecting a fifo to avalon bus
Gerd Van Zegbroeck:
    1685: 95/08/15: Re: Need information on MACH,FLEXlogix,ISPlsi
Geremy F.:
    4939: 97/01/02: Re: What Does ASIC Stand For?
Gergo:
    156127: 13/12/07: MachXO breakout board as a programmer
<gergo.santha@gmail.com>:
    156743: 14/06/13: MachXO primary clock example (PCLK)
Gerhard Fohler:
Gerhard Griessnig:
    21636: 00/03/27: Communication FPGA & MII
    22021: 00/04/13: DSP - FPGA
    25070: 00/08/25: Re: create a RAM in a Virtex
    25224: 00/08/31: SYNOPSYS using BLOCK RAM (VIRTEX)
    24962: 00/08/23: create a RAM in a Virtex
    28990: 01/02/01: More then 4 Clocks
    29020: 01/02/02: Re: More then 4 Clocks
Gerhard Hoffmann:
    2363: 95/11/23: Re: XBLOX: the good, the bad and the shocking
    3245: 96/05/02: Re: FPGA for Space Application
    4697: 96/12/02: Re: In Search of Xilinx Routing Statistics
    4855: 96/12/20: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5449: 97/02/17: Re: HELP: XC4000 download cable
    5649: 97/03/04: Re: Place and Route on Pentium Pro Benchmark?
    6706: 97/06/17: Re: XCHECKER Download to Xilinx 9500 CPLDs
    9125: 98/02/23: Re: Atmel SPROMs for Xilinx
    9900: 98/04/12: Re: XactStep6 - The cure for a dongle
    10217: 98/05/05: Re: Xilinx Foundation and Linux
    10301: 98/05/11: Re: Xilinx Configuration Problem
    10302: 98/05/11: Re: Xilinx Foundation and Linux
    12678: 98/10/23: Re: gray code counter in a Xilinx fpga???
    15264: 99/03/17: Re: Problems with foundation
    92252: 05/11/24: accessing the phase accumulator in Xilinx DDS 5.0
    92293: 05/11/25: access to phase accumulator in Xilinx DDS 5.0
    96924: 06/02/14: Re: Rocketio, modelsim xe
    100382: 06/04/07: Re: Virtex-4 RocketIO and G.709 OTU-2
    101054: 06/04/25: Re: ISE 8.1 Sub module Synthesis
    106305: 06/08/11: Re: NgdBuild:604 error
    106476: 06/08/14: Re: NgdBuild:604 error
    106842: 06/08/21: Re: Warningmessage in ISE
    107320: 06/08/26: Re: Why isn't there a thermal diode on large FPGAs?
    110897: 06/10/25: Re: ISE 8.2 freeze
    112108: 06/11/16: Re: 8080 FSGA model in an FPGA
    114830: 07/01/24: Re: ML403 board - VGA schematics - wrong pins
    120424: 07/06/07: Re: Virtex4 CLKX2 DCM Jitter
    120439: 07/06/07: Re: Virtex4 CLKX2 DCM Jitter
    122972: 07/08/13: Re: edk+uclinux ??? <about make dep>
    123012: 07/08/14: Re: xst fails...
    129612: 08/02/29: Re: Picoblaze enhencement and assembler
    133841: 08/07/17: defunct Platform USB cable
    138217: 09/02/09: Re: Is this phase accumulator trick well-known???
    138239: 09/02/10: Re: Is this phase accumulator trick well-known???
    141582: 09/06/28: Re: Virtex-6 shipping?
    146614: 10/03/24: Re: Finally, selling my old Xilinx/Viewlogic software package
    146615: 10/03/24: Re: Finally, selling my old Xilinx/Viewlogic software package
    146631: 10/03/24: Re: Finally, selling my old Xilinx/Viewlogic software package
    150812: 11/02/14: Re: Xilinx USB programming cable.
    151587: 11/04/22: Re: Xilinx ML605 Demo Qusstion
    156034: 13/11/12: Re: legacy Xilinx software
    156492: 14/04/10: Re: on-chip bypass caps
Gerhard Mesenich:
    15040: 99/03/04: Looking for advice on CPLD's
Gerhard Vogt:
    7266: 97/08/19: Re: MaxPlusII from Altera.
Gerhard Wiesinger:
    3809: 96/08/05: Re: Designing Dual Port RAM with 4000 series.
    5313: 97/02/06: Problems with SYNOPSYS - XILINX Interface
    5677: 97/03/06: Problem with Synopsys/Altera interface
Gerhard Zipfel:
    9381: 98/03/08: ISR Programming Cable for FLASH370i from CYPRESS
<gerizamir@my-deja.com>:
    20573: 00/02/15: BCH Implementation
<german_acosta@my-deja.com>:
    17787: 99/09/03: Re: Problem with VHDL in MAX+Plus II / Flex10k
Germán Fabregat:
    15816: 99/04/15: Looking for 6200 FPGA
Gernot Frisch:
Gernot Koch:
    63754: 03/12/03: Xilinx Virtex-II: DCM int & ext feedback
Gernot Koch (remove digits from user):
    63788: 03/12/04: Re: Command line in Windows?
Geronimo Stempovski:
    105396: 06/07/21: XMatchPRO algorithm on FPGA
    115055: 07/01/30: 1 Gbps - state of the art?
    115312: 07/02/07: question about power dissipation
    115320: 07/02/07: Re: question about power dissipation
    115462: 07/02/12: Building Coaxial transmission line on PCB?
    115472: 07/02/12: Re: Building Coaxial transmission line on PCB?
    115550: 07/02/13: Re: Building Coaxial transmission line on PCB?
    115615: 07/02/15: Loss Diagram
    115653: 07/02/16: Re: Loss Diagram
    115673: 07/02/16: Re: Loss Diagram
    119084: 07/05/11: power consumption of integrated circuit in 0.13µm CMOS technology
    120018: 07/05/31: data compression algorithms on FPGA
    120023: 07/05/31: Re: data compression algorithms on FPGA
    121740: 07/07/12: Designing the right clock tree for a multi-FPGA setup
    121786: 07/07/13: Re: Designing the right clock tree for a multi-FPGA setup
    121821: 07/07/13: Re: Designing the right clock tree for a multi-FPGA setup
    121824: 07/07/13: Re: Designing the right clock tree for a multi-FPGA setup
    121945: 07/07/16: Re: Designing the right clock tree for a multi-FPGA setup
<geronimojones@my-deja.com>:
    19397: 99/12/19: Re: Dumb question springing from a discussion about chess on a chip...
Gerr:
    88173: 05/08/10: Delays in verilog
    100647: 06/04/14: Xilinx USB Platform Cable not working anymore (linux)
    100787: 06/04/18: Re: Xilinx USB Platform Cable not working anymore (linux)
Gerrit Telkamp:
    194: 94/09/17: Partly reconfigurable FPGAs
    425: 94/11/14: Re: about downloading FPGAs
    580: 95/01/10: Re: Motorola FPGA
    2773: 96/02/05: PIC16C71 CORE for XC4000 ?
Gerrit VdV:
    69216: 04/04/30: Xilinx ISE 6.2 on Debian
Gerry:
    128742: 08/02/05: Sythesisable subset of VHDL
    128771: 08/02/06: Simple Memory Read problem, help appreciated
    128772: 08/02/06: Re: Simple Memory Read problem, help appreciated
    128775: 08/02/06: Re: Simple Memory Read problem, help appreciated
    128779: 08/02/06: Re: Simple Memory Read problem, help appreciated
    128790: 08/02/06: Re: Simple Memory Read problem, help appreciated
    128793: 08/02/06: Re: Simple Memory Read problem, help appreciated
    128830: 08/02/07: Re: Simple Memory Read problem, help appreciated
    128858: 08/02/07: Weired Distributed Memory behaviour
    128882: 08/02/08: Re: Weired Distributed Memory behaviour
Gerry Belanger:
    1831: 95/09/07: Re: Help Needed-FPGA Apps Eng.-AllentownPA.-Recruiter
    2159: 95/10/23: Re: PLD in small package ?? anyone
    2742: 96/02/01: Re: GAL programming for hobby use...Is there no hope?
    5902: 97/03/25: Re: Sole source
    5929: 97/03/27: Re: Sole source
Gerry Schneider:
    17001: 99/06/23: Re: DS2 and E2 Framer???
Gerry_MAN:
    140869: 09/05/27: Old School Altera MAX 7000
    140871: 09/05/27: Re: Old School Altera MAX 7000
    140873: 09/05/27: Re: Old School Altera MAX 7000
    140900: 09/05/28: Re: Old School Altera MAX 7000
    144480: 09/12/09: Altera LP6 Logic Programming Card Acquired!
    144484: 09/12/09: Altera LP6 Logic Programming Card - Supplier
Gert Baars:
    90887: 05/10/24: a few questions
    90890: 05/10/25: Re: a few questions
gert1999:
    139849: 09/04/16: Xilinx Impact cable not found
    140514: 09/05/15: Coolrunner II: what's wrong up here ?
    140538: 09/05/16: Re: Coolrunner II: what's wrong up here ?
    140546: 09/05/16: Re: Coolrunner II: what's wrong up here ?
    140840: 09/05/27: Re: Coolrunner II: what's wrong up here ?
    140909: 09/05/29: Re: Coolrunner II: what's wrong up here ?
    141103: 09/06/05: Re: Coolrunner II: what's wrong up here ?
Gery:
    109582: 06/09/29: Xilinx ISE 8.1i asks me to recover work?
    109635: 06/10/02: Help with ISE WebPack 8.2i (moving project files)
    109637: 06/10/02: Re: Help with ISE WebPack 8.2i (moving project files)
geschma:
    114600: 07/01/20: How can I make xst to infer BlockRAM instead of Distributed RAM
<get2venu@gmail.com>:
    112251: 06/11/18: master support for OPB device
gf0570:
    3158: 96/04/15: What's the lowest-priced FPGA?
    3273: 96/05/07: Is XC7336 the least expensive CPLD?
<gfang@pop.slkc.uswest.net>:
    12041: 98/09/25: CardBus CIS useless?
    12047: 98/09/25: Re: CardBus CIS useless?
gfd:
    151647: 11/04/30: Re: Picoblaze C Compiler
<86gfd@dscg8.com>:
    17402: 99/07/24: 18+ ONLY 27425
ggang1:
    36012: 01/10/26: Using xsvf file configures Xilinx FPGA
<ggd@reivax.com.br>:
    24003: 00/07/20: IRIG decoder and accurate time
ggg fff:
    14832: 99/02/19: testing, just testing
<ggli@dictaphone.com>:
    15167: 99/03/10: Actel FPGA
<ggqnkj@nowhere.com>:
Ghazal:
    134489: 08/08/12: Microblaze Projects
    134609: 08/08/20: Image input
    134809: 08/09/01: Re: Image input
Ghazan Haider:
    75851: 04/11/16: ISO Free cores repository
    75880: 04/11/17: Re: ISO Free cores repository
GHEDWHCVEAIS@spammotel.com:
    97149: 06/02/17: Re: opencores.org ?
    97151: 06/02/17: Re: Communication between FPGA and PC with ethernet
    99107: 06/03/20: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
    99136: 06/03/20: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
    99137: 06/03/20: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
    99227: 06/03/21: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
    99269: 06/03/22: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
ghelbig:
    133055: 08/06/16: Re: WARP
    133080: 08/06/17: Re: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
    133082: 08/06/17: Re: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
    133221: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
    133358: 08/06/25: Re: FPGA area use by module?
    134056: 08/07/23: Re: Quartus2 pin assignment
    134078: 08/07/24: Re: Quartus2 pin assignment
    134118: 08/07/26: Re: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming
    134517: 08/08/15: Re: Q: Demo Altera NIOS II SOPC limitations
    134853: 08/09/03: Re: what is the maximum number of DDR controllers
    135977: 08/10/24: Re: Soft core processor + CAD choose.Again
    144593: 09/12/18: Trouble with Xilinx DCM - Spartan3
    144598: 09/12/19: Re: Trouble with Xilinx DCM - Spartan3
    144693: 09/12/23: Re: Trouble with Xilinx DCM - Spartan3
    144933: 10/01/15: Re: Which WebPack for old Spartan and Spartan-2?
    144991: 10/01/18: XST is driving me mad.
    145008: 10/01/19: Re: XST is driving me mad.
    145442: 10/02/09: Re: DONE_cycle:6 setting neccessary in bitgen
    148187: 10/06/25: Re: fooling the compiler
    149488: 10/10/29: Can't migrate from 11.5 to 12.3
    149490: 10/10/29: Re: Can't migrate from 11.5 to 12.3
    149496: 10/10/29: Re: Can't migrate from 11.5 to 12.3
    150113: 10/12/14: Re: ISE 11.5 to ISE 12.3 migration problem
    150126: 10/12/15: Xilinx support makes me want to scream
    150131: 10/12/15: Re: Xilinx support makes me want to scream
    150478: 11/01/24: Problem with iMpact
    150495: 11/01/24: Re: Problem with iMpact
    150530: 11/01/25: Re: Problem with iMpact
    150560: 11/01/26: Re: Problem with iMpact
    150561: 11/01/26: Re: ISE 12.4
<ghelbig@gmail.com>:
    102055: 06/05/09: Re: Interrupt signal sampling (Level or edge?)
    125261: 07/10/18: Re: FPGA pin swapping utility
    125262: 07/10/18: Re: R: Xilinx:is it possible to install Impact 9.1only?
    132642: 08/06/04: Re: Xilinx Fifo Generator Direct Instantiation?
    132697: 08/06/05: Re: Spartan3 interface with DDR SDRAM
<ghelbig@lycos.com>:
    92880: 05/12/08: Re: Simulating Post-Synthesis Model on Xilinx FPGA
    92894: 05/12/08: Re: Simulating Post-Synthesis Model on Xilinx FPGA
    97384: 06/02/21: Re: Is FPGA code called firmware?
    97927: 06/03/01: Re: System crashes when configuring altera stratix pci board
    98378: 06/03/09: Re: problem
    98996: 06/03/18: Re: Historical Fpga Resources
    99002: 06/03/18: Re: Support software for XC3042
    99027: 06/03/19: Re: Historical Fpga Resources
    99835: 06/03/29: Re: spartan FPGA with PLCC package
    100275: 06/04/05: Re: done pin didn't go high
    100653: 06/04/14: Re: Spartan 3 chips in power up
    100804: 06/04/18: Re: blowfish encryption algorithm
    100911: 06/04/20: Re: Xilinx PCIe core vs. Icarus Verilog
    101058: 06/04/24: Re: vhdl cpu emulator (any interest?)
    101338: 06/04/28: Re: How to see *.vcd file outported from ChipScope from different computer
    102136: 06/05/10: Re: Interrupt signal sampling (Level or edge?)
    102415: 06/05/15: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102470: 06/05/16: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102501: 06/05/16: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102964: 06/05/23: Re: Verilog vs VHDL
    103470: 06/06/02: Re: Adding a USB interface to Linksys WRT54G wifi router
    103485: 06/06/03: Re: VHDL code For Floating point adder and Multiplier
    103593: 06/06/06: Re: Jtag Programmer
    104038: 06/06/16: Re: Floppy to FPGA?
    104092: 06/06/18: Re: Floppy to FPGA?
    104284: 06/06/22: Re: newbie:my ISE doesn't include old xcs30 spartan how........
    105974: 06/08/03: Re: Microblaze Sierro RTOS is no longer available??
    106658: 06/08/16: Re: Quartus and source control (continued)
    109214: 06/09/21: Re: Spartan-3E USB for I/O?
    109276: 06/09/22: Re: Spartan-3E USB for I/O?
    109592: 06/09/29: Re: Little help needed with FT2232L USB demo board
    109697: 06/10/03: Re: How to create a library for a Xilinx project
    109814: 06/10/05: Re: a clueless bloke tells Xilinx to get a move on
    110850: 06/10/24: Re: Please Help
    110851: 06/10/24: Re: How to check if ROM got inferred from synth reports
    110899: 06/10/25: Meta-stable problem with MAX-II ?
    110947: 06/10/25: Re: Meta-stable problem with MAX-II ?
    110954: 06/10/25: Re: Xilinx documentation typos
    111181: 06/10/30: Re: Programming Virtex II Pro Eval Board
    112711: 06/11/27: Re: problems with verilog SDRAM models
    112828: 06/11/29: Re: XC3020-50 board documentation
    115511: 07/02/12: Re: Setting VHDL standard in Xilinx ISE
    115616: 07/02/14: Re: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
    116855: 07/03/19: Re: alliance tooset on Linux
    118018: 07/04/16: Re: Why 166Mhz DDR?
    118391: 07/04/25: Re: Take verilog code from Xilinx Core generator
    120064: 07/05/31: Re: Cyclone 3 Starter Board Question
    120414: 07/06/06: Re: XILINX IPCore
    121050: 07/06/24: Re: Cadence TestBuilder
    121201: 07/06/27: Re: Coding style of verilog for FPGA synthesis
    121412: 07/07/03: Re: Coding style of verilog for FPGA synthesis
    121754: 07/07/12: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121927: 07/07/15: Re: Which embedded O/S for a 32-bit RISC microcontroller?
    121970: 07/07/16: Re: New board JTAG problem.
    122032: 07/07/18: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    122611: 07/08/01: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
    122615: 07/08/01: Re: Xilinx Webpack for Linux 64 bit?
    122932: 07/08/10: Re: Webpack 9.1 and Samba
    122950: 07/08/12: Re: SDR SDRAM controller for Xilinx Spartan-3E
    123025: 07/08/14: Re: Xilinx Spartan FPGA : Strange Errors
    123259: 07/08/21: Re: help to sort out the errors
    123676: 07/08/31: Re: Xilinx ML40x Mouse VHDL Wanted
    124004: 07/09/10: Question about Virtex-4 DCM
    124092: 07/09/12: Re: Question about Virtex-4 DCM
    124282: 07/09/17: Re: Altera / Lattice / Xilinx CPLDs ?
    124487: 07/09/24: Re: Answer: maximum number of state machines in a current chip: > 500k
    124770: 07/10/03: Re: XUPV2P serial connection through serial-to-usb cable
    124836: 07/10/06: Re: Opteron performance tuning (for Quartus / Linux)?
    124848: 07/10/08: Re: JTAG interconnect testing, prototypes
    124862: 07/10/09: Re: kicad or orcad virtex5 symbol
    124909: 07/10/10: Re: Compiler Options
    124985: 07/10/14: Re: Quartus II Web Edition License - SOPC Builder generation?
    125133: 07/10/16: Re: Quartus II Web Edition License - SOPC Builder generation?
    125205: 07/10/17: Re: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES
    125302: 07/10/19: Re: Files produced by Quartus II compiler
    125332: 07/10/22: Re: microprocessor on fpga problems
    125343: 07/10/22: Re: microprocessor on fpga problems
    125745: 07/11/02: Re: Xilinx EDK and Windows Vista?
    125863: 07/11/07: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
    125881: 07/11/07: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
    126107: 07/11/14: Re: Block-ram FIFO in Xilinx
    126302: 07/11/19: Re: Microblaze books
    126303: 07/11/19: Re: Update to Xilinx ISE 9.2
    126517: 07/11/26: Re: Converting a ByteBlasterMV into a ByteBlaster II?
    126825: 07/12/03: Re: Configuration via JTAG using an Embedded Controller
    126895: 07/12/05: Re: Spartan 3e and SDRAM
    126943: 07/12/06: Re: student requiring assistance :)
    126944: 07/12/06: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
    127095: 07/12/11: Re: Craignell and Darnaw1 Website Updates
    127894: 08/01/09: Re: Using DDR SDRAM as single data rate ..?
    127974: 08/01/11: Re: Is it possible to define an Integer so it could be incremented
    128106: 08/01/15: Re: help me about this error
    128144: 08/01/16: Re: Basic FPGA question about Reset
    128178: 08/01/17: Re: Basic FPGA question about Reset
    128247: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
    128309: 08/01/21: Re: VHDL Micron memorymodel.
    128602: 08/01/31: Re: new to NIOS II
    129997: 08/03/12: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
    130033: 08/03/13: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
    130034: 08/03/13: Re: Problem with Spartan 3 StarterKit
    130041: 08/03/13: Re: simulating Xilinx cores
    130288: 08/03/19: Re: Optimizing an inferred counter
    130380: 08/03/21: Re: Synoplify ???
    130752: 08/03/31: Re: Xilinx and Modelsim?
    131017: 08/04/08: Re: Avalon Bus <-> Wishbone Bus
    131201: 08/04/15: Re: Simulation tools for Xilinx ISE
    131240: 08/04/16: Re: asic gate count
    131533: 08/04/24: Re: will there be any problem with diffrent version of sysgen & EDK
    131577: 08/04/25: Re: ATF750 for Proteus
    131592: 08/04/25: Re: will there be any problem with diffrent version of sysgen & EDK
    131761: 08/05/01: Re: NIOS II CFI interface
    131864: 08/05/05: Re: NIOS II CFI interface
    131956: 08/05/08: Re: Quartus 7.2 and PCI Express
    131957: 08/05/08: Re: EDK for spartan2?
    132121: 08/05/14: Re: demo board under 500usd
    132126: 08/05/14: How do I get Xilinx EDK to load a 'custom' XBD file?
    132145: 08/05/15: Re: How do I get Xilinx EDK to load a 'custom' XBD file?
    132191: 08/05/16: Re: Incorporating FPGAs on PCBs
    132244: 08/05/19: Re: SKEW greater than Time period of CLK
    132549: 08/05/30: Re: DATA0 pin in Cyclone III device
    132863: 08/06/09: Re: how to prevent timer code firmware running on Microblaze from
<ghori.asad@gmail.com>:
    130609: 08/03/28: JavaBotics Marmaduke board
Ghostboy:
    144549: 09/12/14: Video Processing
    144603: 09/12/19: Memory Latency
    144608: 09/12/20: Re: Memory Latency
    144618: 09/12/21: Re: Memory Latency
    144772: 10/01/01: Re: Video Processing
    144791: 10/01/03: Re: Video Processing
    144802: 10/01/05: Re: Video Processing
    144805: 10/01/05: Re: Video Processing
    144833: 10/01/07: Re: Video Processing
    147560: 10/05/03: PCI Interrupt
    147568: 10/05/04: Re: PCI Interrupt
<ghuardian@gmail.com>:
    132587: 08/06/02: Problem with Xilinx 9.2i and Modelsim 6.0
Ghys:
    44549: 02/06/23: Clock enable & Synplify 7.1
    44556: 02/06/23: Re: Clock enable & Synplify 7.1
    44635: 02/06/25: Re: Clock enable & Synplify 7.1
Giaccaglini Giorgio:
    50791: 02/12/19: Programming ACEX1K from FlashEprom
    52299: 03/02/06: NIOS and ACEX1K
    62735: 03/11/06: Smart card ISO 7816 and NIOS Altera
<giachella.g@laben.it>:
    84294: 05/05/17: Registers replication on Xilinx IOBs
    88953: 05/09/01: Discrepancies in area estimation (Precision RTL vs Xilinx ISE Map)
Gian:
    57395: 03/06/29: Parallel processing
Giando:
    55473: 03/05/09: Info about development kit
Giang Thach Nguyen:
    12115: 98/09/29: Maxplus2 Timing Analyzer
Giani:
    78624: 05/02/04: How to locate a net in the design
Gianluca:
    8631: 98/01/14: Byteblaster
Gianluigi:
    129513: 08/02/26: Re: set_input_delay min and max (timequest)
Gianni Comoretto:
    15787: 99/04/14: Obsolete Xilinx series - how to use them?
GianniG:
    83885: 05/05/09: TRACE and Modelsim Timing Help
    83947: 05/05/10: Re: TRACE and Modelsim Timing Help
Gianpaolo Scassellati:
    6758: 97/06/25: Info on VHDL
    6979: 97/07/18: Clock generator
gianzi:
    41795: 02/04/08: XST Synthesis tool
    42288: 02/04/19: Re: Simulating Unisim
    42348: 02/04/21: VIRTEX & JTAG
    42350: 02/04/21: Re: Programming Spartan2 and external clock
    42585: 02/04/28: How can I test a downloaded design?
    42702: 02/05/01: How can I test a downloaded design?
    42960: 02/05/08: Problem when simulating post P&R, with SDF
    43568: 02/05/24: Re: FPGA and VHDL: question about RAM initialization
<gibson@innocon.com>:
    7922: 97/10/30: Re: [Reposted due to Enlow UCE cancel]: PROM for FLEX10K
    8570: 98/01/09: Re: ALTERA Global Signal
<gibsond@bournemouth.ac.uk>:
    10811: 98/06/22: Xilinx carry logic (XC4000)
    16819: 99/06/11: Place & Route Xilinx F1.5 Student ed.
    16823: 99/06/11: Re: Place & Route Xilinx F1.5 Student ed.
    16824: 99/06/11: Re: Place & Route Xilinx F1.5 Student ed.
    16827: 99/06/11: Re: Place & Route Xilinx F1.5 Student ed.
    16850: 99/06/14: Re: Place & Route Xilinx F1.5 Student ed.
    16862: 99/06/15: Re: Place & Route Xilinx F1.5 Student ed.
Gideon Amir:
    1058: 95/04/22: GATRAN - Retargetting tool
    1076: 95/04/25: Re: Sunrise ???
    1107: 95/04/30: ASIC group ?
    1459: 95/06/25: What about Veribest?
GieTeGie:
    76782: 04/12/11: [Altera] lpm_decode works great, but where is lpm_encode ???
giga_super_man:
    40558: 02/03/10: Re: DPRAM implementation in altera
Giggio:
    37336: 01/12/07: Translating....
    37404: 01/12/10: Re: Translating....
    37445: 01/12/11: Re: Translating....
Giki:
    125358: 07/10/23: Which demo board
Gil Chilton:
    10158: 98/04/30: Job Positions Avaiable 5/1/98
Gil Golov:
    28367: 01/01/10: Xilinx Spartan II - PQ208 Orcad symbols
    29131: 01/02/07: Spartan II/Virtex DLL with Exemplar - help
    29187: 01/02/09: Virtex XCV2000E-6 BG560C - Orcad capture symbol
    29199: 01/02/09: Re: what exactly is the dff between fpga and cpld?
    29543: 01/02/26: Re: VDHL Book recomendation please. Xilinx designer.
    29545: 01/02/26: Re: cpul vs vhdl
    30106: 01/03/23: Re: Do I need to tie unused CPLD pins to GND?
Gil Herbeck:
    41966: 02/04/11: prototyping an ASIC
    41969: 02/04/12: Re: prototyping an ASIC
    41975: 02/04/12: Re: prototyping an ASIC
    41981: 02/04/12: Re: prototyping an ASIC
    42002: 02/04/12: Re: prototyping an ASIC
    42003: 02/04/12: Re: prototyping an ASIC
    56126: 03/05/29: Re: 20 to 5 encoder optimization?
<gil@radix20.com>:
    128359: 08/01/22: data capture
    140019: 09/04/23: FPGA board with ARM9
    140037: 09/04/24: Re: FPGA board with ARM9
    140038: 09/04/24: Re: FPGA board with ARM9
    140075: 09/04/27: Re: FPGA board with ARM9
    140076: 09/04/27: Re: FPGA board with ARM9
Gilad Cohen:
    51356: 03/01/11: Re: internal nets
    54990: 03/04/23: Re: how to synthesize Xilinxcorelib in leonardo or ISE 5.1
    55110: 03/04/27: Two RAMs in one slice
    55157: 03/04/29: Re: general: vhdl
    55229: 03/05/01: Re: Two RAMs in one slice
    55499: 03/05/10: Re: global buffer and the dll
    56778: 03/06/15: Automatic testing
    56840: 03/06/17: Automatic FPGA testing
    56856: 03/06/17: Simple FEC algorithm
    56877: 03/06/17: Re: Automatic FPGA testing
    57578: 03/07/02: Re: Combining Distributed RAM and Block RAM
    57580: 03/07/02: Re: VirtexII bitstream relocation
    58028: 03/07/12: Re: Post-fit simulation question
    58108: 03/07/14: Re: Post-fit simulation question
Gilbates:
    125255: 07/10/18: Wishbone Specification in Action
gilbert:
    67154: 04/03/07: strange error
Gilbert H. Herbeck:
    20782: 00/02/22: Re: Distributed Arithmetic De-mystified
    24099: 00/07/26: Re: Variable shifting
    24104: 00/07/27: Re: Variable shifting
<gilbert1219com@gmail.com>:
    124426: 07/09/21: Using PlanAhead for Partial Reconfiguration
    124481: 07/09/24: partial reconfiguration, par error
gilles:
    72198: 04/08/11: Re: Xilinx PowerPC simulation problems
    72200: 04/08/11: ISE 6.2 : Place problem with V2PRO
    72246: 04/08/12: Re: ISE 6.2 : Place problem with V2PRO
Gilles:
    146476: 10/03/19: Re: Any Experiences with the GN4124 PCI Express - FPGA bridge?
Gilles GEORGES:
    94250: 06/01/09: Xilinx USB Platform Cable not working anymore
    94288: 06/01/09: Re: Xilinx USB Platform Cable not working anymore
    104422: 06/06/27: Synplify & Fedora core 5
    104432: 06/06/27: Re: Synplify & Fedora core 5
    104442: 06/06/27: Re: Synplify & Fedora core 5
Gimmemore1:
    11443: 98/08/14: Comp Central
<ginger987@aol.com>:
    17070: 99/06/29: 18+ 62321
Gints:
    141920: 09/07/16: FPGA to PC connection
    141986: 09/07/20: Re: FPGA to PC connection
    142300: 09/08/02: Ethernet PHY and Endianness
giohdl@netscape.net:
    91463: 05/11/07: BRAMs readback
Giorgio Poli:
    29460: 01/02/22: Re: Second Source For ALTERA EPC1 ?
Giorgos P.:
    80569: 05/03/08: Xilinx vs Altera high-end solutions
    80771: 05/03/11: Xilinx vs Altera high-end product solutions?
Giorgos Tzampanakis:
    144934: 10/01/16: Altera Quartus II on Debian GNU/Linux
    144948: 10/01/17: Re: Altera Quartus II on Debian GNU/Linux
    145039: 10/01/22: Icarus Verilog opinions
    145181: 10/01/31: Quartus Web Edition on Linux - no simulation?
    145287: 10/02/04: Quartus II - Generating Verilog from MegaWizard plugins
    145723: 10/02/21: State machines in Quartus
    145894: 10/02/27: Quartus - How to get a vector waveform file longer than 1000ns?
    145895: 10/02/27: Re: Quartus - How to get a vector waveform file longer than 1000ns?
    146013: 10/03/03: Using bidirectional pins in Verilog
    146073: 10/03/05: Is an inout reg allowed
    147950: 10/06/03: OT and Newbie: SDRAM Auto Refresh
    148150: 10/06/23: Help with VGA controller in Verilog
    148157: 10/06/23: Re: Help with VGA controller in Verilog
    148162: 10/06/24: Re: Help with VGA controller in Verilog
    148163: 10/06/24: Re: Help with VGA controller in Verilog
    148164: 10/06/24: Re: Help with VGA controller in Verilog
    148193: 10/06/26: Free bitmap font
    148196: 10/06/26: Re: Free bitmap font
    148201: 10/06/27: Re: Free bitmap font
    148354: 10/07/15: Verilog in Quartus and assignments in blocks
    148362: 10/07/15: Re: Verilog in Quartus and assignments in blocks
    148550: 10/08/01: Differences between Verilog versions
<giorgos.puiklis@gmail.com>:
    125740: 07/11/02: Synthesizing with specific primitive-elements
    128718: 08/02/05: MG Leonardo Synthesis Options
    129105: 08/02/14: Reprogramming Proms,before the fpga boots from them (Avnet
    131108: 08/04/11: Xilinx ISE synthesis error (error:3524 Unexpected end of line.)
    134095: 08/07/25: Prevent synthesis optimizations/simplifications in Xilinx-ISE
    134144: 08/07/27: Re: Prevent synthesis optimizations/simplifications in Xilinx-ISE
    136729: 08/12/03: Back-annotated simulation for Xilinx devices
Giorgos_P:
    136759: 08/12/04: Xilinx-ISE nets names after placement & routing
    136774: 08/12/04: Re: Xilinx-ISE nets names after placement & routing
    136793: 08/12/05: Re: Xilinx-ISE nets names after placement & routing
    136961: 08/12/16: Leonardo scl05u synthesis-library datasheet
    136964: 08/12/16: Re: Leonardo scl05u synthesis-library datasheet
    143463: 09/10/12: Xilinx post-routing signal names
    149431: 10/10/25: Using LVPECL_25 inputs in Spartan3e problem
    149442: 10/10/25: Re: Using LVPECL_25 inputs in Spartan3e problem
Giovanni:
    56268: 03/06/02: Help an Italian Student
Giovanni Ferrante:
    60169: 03/09/06: Cpu Generator rel.1.00 released
    66980: 04/03/02: CpuGen 2.0 released
Giovanni Galiero:
    46796: 02/09/09: Evaluating FPGA for FFT
Giox:
    84088: 05/05/12: High radix multiplier
    84467: 05/05/19: Re: High radix multiplier
    85788: 05/06/16: LUT, how to?
    85792: 05/06/16: Re: LUT, how to?
    85800: 05/06/16: Re: LUT, how to?
    85851: 05/06/17: Re: LUT, how to?
    86813: 05/07/07: about fast adder
    86826: 05/07/07: Re: about fast adder
    86831: 05/07/07: Re: about fast adder
    86839: 05/07/07: Re: about fast adder
    86842: 05/07/07: Re: about fast adder
    87506: 05/07/25: How to look inside a RAM memory
    87565: 05/07/25: Re: How to look inside a RAM memory
    89254: 05/09/09: Post synthesis simulation errors
    89300: 05/09/12: Re: Post synthesis simulation errors
    89352: 05/09/13: Re: Post synthesis simulation errors
    89353: 05/09/13: Re: Post synthesis simulation errors
    89691: 05/09/22: Hints for efficient 32 bit multiplier
    89712: 05/09/23: Re: Hints for efficient 32 bit multiplier
    90532: 05/10/16: Implementing I2C master
    96848: 06/02/11: Simulation problem using CONV_INTEGER
Girl:
    40165: 02/02/28: Re: APEX-II vs VIRTEX-II
    41242: 02/03/22: Re: Altera Stratix compared to Xilinx Virtex
    41595: 02/04/02: Re: [HELP] Can't Install Altera QuartusII 2.0 SP1
    41596: 02/04/02: Re: floorplanning for FPGA
girl_aj:
    135502: 08/10/05: Barrel Shifter: Newbie's Attempt
    135504: 08/10/05: Barrel Shifter: Newbie's Attempt
    135521: 08/10/06: Barrel Shifter: Newbie's Attempt
    135672: 08/10/11: Newbie attempt with ALU
<girmann@gmail.com>:
    104167: 06/06/20: Re: Xilinx ISE 8.1i Trouble
Giuliano Cardinali:
    6689: 97/06/14: Re: Verilog Simulation and Synthesis for FPGA Devices
Giulio Ferro:
    40270: 02/03/04: quest for info
Giunt:
    4519: 96/11/08: behavioural VHDL "BUS MATCHING"
giuseppe:
    22167: 00/04/28: xilinx prom 2nd source.
    26372: 00/10/13: PROM 17512
    26483: 00/10/18: R: source PROM 17512
Giuseppe Baruffa:
    22979: 00/06/07: Info on Ballynuey 2
giuseppe giachella:
    18617: 99/11/03: Fpga Compiler Altera Edition & Leonardo Spectrum
    18744: 99/11/11: Altera Files vho and sdo too big
    18761: 99/11/12: Pin locking problem in Altera fpga
    19372: 99/12/17: R: constraints between clock domains: can't advance
    19945: 00/01/20: Altera Quartus vs Xilinx Place and Route tools (help needed)
    20076: 00/01/26: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    21887: 00/04/05: ASIC synthesys using Leonardo Spectrum: any suggestion ?
Giuseppe Marullo:
    130358: 08/03/21: Spartan 3E intefacing for dummies
    130398: 08/03/22: Re: Spartan 3E intefacing for dummies
    130406: 08/03/22: Re: Spartan 3E intefacing for dummies
    133034: 08/06/14: Re: Using ethernet on a Xilnx board (Help appreciated)
    134616: 08/08/21: How to "propagate" a serial signal
    134626: 08/08/22: Re: How to "propagate" a serial signal
    137345: 09/01/09: FPGA on the fly syntesis and other stuff
    137347: 09/01/09: Re: FPGA on the fly syntesis and other stuff
    138261: 09/02/11: Logic Analyzer
    138297: 09/02/13: Re: Logic Analyzer
    138299: 09/02/13: Re: Logic Analyzer
    138310: 09/02/15: Re: Logic Analyzer
    138334: 09/02/16: Re: Logic Analyzer
    138348: 09/02/17: Re: Logic Analyzer
    138422: 09/02/21: Re: Logic Analyzer
    142284: 09/08/02: [newbie] Verilog test bench with automatic verification
    142297: 09/08/03: Re: [newbie] Verilog test bench with automatic verification
    142298: 09/08/03: Re: [newbie] Verilog test bench with automatic verification
    143353: 09/10/05: Post route simulation and real implementation
    143612: 09/10/18: Re: Getting started...
    148361: 10/07/15: 1-wire question
    150191: 10/12/30: Timing violation when initializing "some" FSMs and not others
    150253: 11/01/05: Re: Timing violation when initializing "some" FSMs and not others
    150344: 11/01/11: Re: FPGA to PHY/MAC chip
    152410: 11/08/20: Testbench in verilog ps and human interactions don't mix
    152428: 11/08/22: Re: Testbench in verilog ps and human interactions don't mix
    152476: 11/08/28: Very cheap Spartan3 board that can be configured by simple USB
    152490: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
    152496: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
    152511: 11/08/30: Re: Very cheap Spartan3 board that can be configured by simple USB
    153074: 11/11/27: Compatible Xilinx USB Cables: worth to bother?
    153076: 11/11/27: Re: Compatible Xilinx USB Cables: worth to bother?
    153078: 11/11/28: Re: Compatible Xilinx USB Cables: worth to bother?
    153082: 11/11/28: Re: Compatible Xilinx USB Cables: worth to bother?
    153084: 11/11/28: Re: Compatible Xilinx USB Cables: worth to bother?
    153089: 11/11/28: Re: Compatible Xilinx USB Cables: worth to bother?
    153090: 11/11/28: Re: Compatible Xilinx USB Cables: worth to bother?
    153091: 11/11/28: Re: Compatible Xilinx USB Cables: worth to bother?
    153139: 11/12/12: D-Type Flip flop with negated Q in Webise for a schematic capture
    153146: 11/12/12: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
    153147: 11/12/12: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
    153614: 12/04/05: LX9 and internal reset - Do I need one?
    153638: 12/04/09: Re: LX9 and internal reset - Do I need one?
    153712: 12/04/29: Smallest GPL UART
    153715: 12/04/29: Re: Smallest GPL UART
    153723: 12/05/01: Re: Smallest GPL UART
    153775: 12/05/17: Re: Smallest GPL UART
<giuseppe.marullo@iname.com>:
    138279: 09/02/12: Re: Logic Analyzer
    138287: 09/02/12: Re: Logic Analyzer
Giuseppeł:
    45454: 02/07/24: Re: How to implement efficient wide word comparator?
    46663: 02/09/05: Re: Xilinx's ISE 5.1i
    47119: 02/09/18: Xilinx ISE5.1 and Windows NT
    47232: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
    47244: 02/09/21: Re: Xilinx ISE5.1 and Windows NT
    47658: 02/10/01: Re: Where can i buy xilinx fpga online?
    48839: 02/10/25: Re: Xilinx FPGA troubles
    52440: 03/02/10: Re: JTAG Download Problems iMPACT and Insight parallel cable
    52597: 03/02/15: Re: Xilinx Flex License Utility
    53432: 03/03/13: Re: Homemade Xilinx Parallel JTAG Download Cable
    54315: 03/04/08: Re: 2.5V switching regulator for Spartan 2
    55280: 03/05/02: Re: IP Core for CAN communication
    57787: 03/07/07: Re: QuartusII software licencing
    57813: 03/07/07: ISE 5.1/5.2 Error
    59046: 03/08/07: Re: Does Xilinx Webpack 5.2 work on WinNT SP6?
    60101: 03/09/05: Re: Disable Pull up
    60536: 03/09/16: Re: Xilinx ISE 6.1i
    60537: 03/09/16: Re: Xilinx ISE 6.1i
    62854: 03/11/10: Re: ISE 5.2 to 6.1
    65082: 04/01/20: ISE 6.1 and Win2000 sp4
    65614: 04/02/03: Re: 4 bit divisor with flip-flop ?
    65649: 04/02/04: Re: 4 bit divisor with flip-flop ?
    70106: 04/06/03: Three-phase PWM generator in VHDL
    70112: 04/06/03: Re: Three-phase PWM generator in VHDL
gja:
    75843: 04/11/17: Re: Help with Virtex II and 5v TTL
    76869: 04/12/14: Virtex2 I/O standards
    76896: 04/12/15: Re: Virtex2 I/O standards
    76912: 04/12/15: Xilinx ISE 6.3.03i service pack size
    77418: 05/01/06: How to change temperature in Xilnx Webpack with free starter Modelsim
    77436: 05/01/06: Re: How to change temperature in Xilnx Webpack with free starter Modelsim
    77449: 05/01/06: Re: How to change temperature in Xilnx Webpack with free starter Modelsim
    77851: 05/01/18: Re: How to change temperature in Xilnx Webpack with free starter Modelsim
    80306: 05/03/03: Re: problem with Modelsim 5.8 Xilinx Edition
    80308: 05/03/03: ISE guide mode broken?
    81978: 05/04/05: ucf timing constraint question
    82442: 05/04/12: Re: 5V PCI interface
    82443: 05/04/12: Re: Global buffer feeding non clock pins in VIRTEX II
    82527: 05/04/13: Re: 5V PCI interface
    82539: 05/04/13: Re: 5V PCI interface
    82601: 05/04/14: Re: 5V PCI interface
    82615: 05/04/14: Re: Global buffer feeding non clock pins in VIRTEX II
    83599: 05/05/03: Re: 5V PCI interface
    94047: 06/01/04: Virtex 2 configuration problem
    94099: 06/01/05: Re: Virtex 2 configuration problem
gk7eong:
    25621: 00/09/16: MAX PLUS 2
    25661: 00/09/17: Re: MAX PLUS 2
    25662: 00/09/17: Re: MAX PLUS 2
gkirilov:
    80274: 05/03/03: PLB IPIF + Master + DMA
    80763: 05/03/11: re:PLB IPIF + Master + DMA
    90997: 05/10/26: Optimizing a State Machine
    90998: 05/10/26: re:SDRAM in EDK
    91034: 05/10/27: re:Optimizing a State Machine
    91155: 05/10/31: re:hex rep. in VHDL
    91537: 05/11/08: re:Using inout ports in VHDL
GKnittel:
    124381: 07/09/20: Multi-cycle paths in VHDL libraries
gkonstan:
    143401: 09/10/09: Re: MCS -> BIT
    143449: 09/10/12: FPGA ruined (?)
    143452: 09/10/12: FPGA ruined (?)
    143455: 09/10/12: Re: FPGA ruined (?)
    143487: 09/10/13: Re: FPGA ruined (?)
<gks.1981@hotmail.com>:
    124407: 07/09/20: hardware software codesign
GL:
    69367: 04/05/08: downloading a non-volitle design (xilinx)
    76550: 04/12/06: quartus and pll
    76554: 04/12/06: Re: quartus and pll
    76572: 04/12/06: Re: quartus and pll
    76855: 04/12/14: altera cyclone and fifo synchronisation
    78120: 05/01/25: bi-dimensional array
    78128: 05/01/25: Re: bi-dimensional array
    78133: 05/01/25: Re: bi-dimensional array
    78134: 05/01/25: Re: bi-dimensional array
    79582: 05/02/21: cyclone's pll
Gladiator:
    86547: 05/06/29: PPC405 Question
    86550: 05/06/29: PPC405 Question
    87477: 05/07/24: Re: Xilinx software update?
    87756: 05/07/30: Re: How to import a netlist in VHDL
    87866: 05/08/02: Re: How to manage user 'reset' for post-synthesis simulation
Gladys:
    147747: 10/05/21: can I do image processing using 8bit color output FPGA board?
    148026: 10/06/15: Does Xilinx Spartan 6 support NAND flash?
    148143: 10/06/23: altshift_taps for Xilinx?
    148146: 10/06/23: Re: altshift_taps for Xilinx?
    148148: 10/06/23: Re: altshift_taps for Xilinx?
    148224: 10/06/30: Re: altshift_taps for Xilinx?
    148253: 10/07/02: SPI Flash configuration and data access rate
    148255: 10/07/02: Re: SPI Flash configuration and data access rate
    148358: 10/07/15: =?ISO-8859-1?Q?DDR=E9_SDRAM_configuration?=
    148405: 10/07/19: =?ISO-8859-1?Q?Re=3A_DDR=E9_SDRAM_configuration?=
    148408: 10/07/19: =?ISO-8859-1?Q?Re=3A_DDR=E9_SDRAM_configuration?=
    148418: 10/07/21: =?ISO-8859-1?Q?Re=3A_DDR=E9_SDRAM_configuration?=
    148427: 10/07/22: =?ISO-8859-1?Q?Re=3A_DDR=E9_SDRAM_configuration?=
    148443: 10/07/23: Spartan 6 MCB arcitecture
    148532: 10/07/30: DSP with sensor i2c interface
    148535: 10/07/30: Re: DSP with sensor i2c interface
    148566: 10/08/02: how to store data in i2c slave
glallenjr:
    144186: 09/11/18: ML 403 hardware implementation
    144364: 09/12/01: Simulation of VHDL code for a vending machine
<glass2301@gmail.com>:
    156695: 14/06/05: who that have used xfuzzy create vhdl ip to edk build gpio ip?
Glen Atkins:
    9231: 98/03/03: Re: Debugging question.
    34514: 01/08/28: Re: FPGA : USB in an FPGA, has anyone done it before?
glen herrmannsfeldt:
    12003: 98/09/23: Re: Dynamic pattern matching in Xilinx FPGAs
    12004: 98/09/23: Re: Efficient max-function architecture?
    13184: 98/11/19: Re: Big-Endian vs Little-Endian
    13301: 98/11/24: Re: Big-Endian vs Little-Endian
    14004: 99/01/07: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    14044: 99/01/09: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    14519: 99/02/03: Re: Off topic DRAM/SIMM question....
    17058: 99/06/28: Re: 100 Billion operations per sec.!
    18825: 99/11/18: Re: implementing TCP/IP on PLD
    18998: 99/11/23: Re: implementing TCP/IP on PLD
    19037: 99/11/25: Re: implementing TCP/IP on PLD
    19236: 99/12/08: Re: AM2901 bit slice processor
    20652: 00/02/16: Re: [NEED HELP] Carry Select Adder?
    21505: 00/03/23: Re: FPGA openness
    21508: 00/03/23: Re: FPGA openness
    22092: 00/04/20: Re: Java to HDL compiler, Free Beta
    23534: 00/06/28: Re: IDE-Interface for FPGA
    24066: 00/07/25: Re: Xilinx Logic Cell counts and carry chains
    25350: 00/09/07: Re: XC3000A Configuration data
    27320: 00/11/17: Re: Can FPGA perform float point calculation?
    27407: 00/11/21: Re: Can FPGA perform float point calculation?
    27429: 00/11/21: Re: What is the fundamental limitation factor for FPGA clock rate
    27466: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
    27917: 00/12/14: Re: Verilog or VHDL
    29241: 01/02/10: Re: double precision floating point arithmetic
    29288: 01/02/12: Re: double precision floating point arithmetic
    29315: 01/02/14: Re: double precision floating point arithmetic
    29330: 01/02/14: Re: IEEE & Floating point
    29700: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
    30193: 01/03/27: Re: frequency measurement?
    30646: 01/04/20: Re: clocking on both edges
    31228: 01/05/16: Re: SRAM fpga cell
    31229: 01/05/16: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
    31301: 01/05/17: Re: SRAM fpga cell
    31412: 01/05/22: Re: fast divider
    31829: 01/06/06: Re: Xilinx Configuration Bitstream
    31832: 01/06/06: Re: Help in FIFO design
    31879: 01/06/07: Re: Xilinx Configuration Bitstream
    32329: 01/06/23: Re: LFSR Taps for 64 bit registers?
    32440: 01/06/26: Re: Stupid Xilinx Patent
    32640: 01/07/03: Re: Asynchronous design in Virtex FPGA => sleepless nights
    32711: 01/07/05: Re: poor man's floating point...
    33811: 01/08/06: Re: I needs a saturable adder.
    33856: 01/08/07: Re: I needs a saturable adder.
    34318: 01/08/20: Re: hardware damage to a Virtex or Spartan-II?
    34335: 01/08/21: Re: hardware damage to a Virtex or Spartan-II?
    34369: 01/08/22: Re: hardware damage to a Virtex or Spartan-II?
    35395: 01/10/02: Re: Barrel Shifter
    35922: 01/10/24: Re: LUT Glitches
    36006: 01/10/25: Re: LUT Glitches
    36031: 01/10/26: Re: LUT Glitches
    36041: 01/10/26: Re: How to make an implementable big counter?
    36066: 01/10/27: Re: LUT Glitches
    36068: 01/10/27: Re: How to make an implementable big counter?
    36069: 01/10/27: Re: Cloning someone else's IP core
    36232: 01/11/02: Re: XC6000
    37094: 01/11/30: Re: Creating a jitter free clock
    37096: 01/11/30: Re: 128-bit scrambling and CRC computations
    37137: 01/12/01: Re: 128-bit scrambling and CRC computations
    37138: 01/12/01: Re: Is there a full open-source synthesis path for any FPGA?
    37210: 01/12/04: Re: Phase noise (jitter) of XILINX logic elements - ?
    37299: 01/12/06: Re: where is designed FPGA for apple II computer...?
    37300: 01/12/06: Re: Where can I find the implemention of block float multiplier?
    37426: 01/12/10: Re: where is designed FPGA for apple II computer...?
    37738: 01/12/19: Re: MIPS or MOPS?
    37752: 01/12/19: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
    37974: 01/12/28: Re: CRC-32 verilog source code
    38668: 02/01/21: Re: Signal processing using FPGAs
    39688: 02/02/15: Re: oscillation
    39707: 02/02/17: Re: Handel-C, System-C, Formal verification ???
    40526: 02/03/08: Re: exceeding 2GB limits in xilinx
    41319: 02/03/26: Re: Pipelined sorting algorithms...
    41537: 02/04/01: Re: Data Compression in FPGAs
    41574: 02/04/02: Re: Data Compression in FPGAs
    43031: 02/05/09: Re: Transistor Counts for Xilinx FPGAs
    43040: 02/05/10: Re: More C things
    43179: 02/05/15: Re: Architecture for high-level reconfigurable computing
    44386: 02/06/19: Re: systolic Vs pipelined
    45739: 02/08/02: Re: a chip which can trans ethenet data through E1 interface
    45762: 02/08/05: Re: a chip which can trans ethenet data through E1 interface
    45848: 02/08/07: Re: Programming bits reverse engineering
    46844: 02/09/10: Re: Metastability numbers
    46845: 02/09/10: Re: Metastability numbers
    46898: 02/09/11: Re: Metastability numbers
    47839: 02/10/05: Re: TCP/IP in FPGA
    48836: 02/10/25: Re: C to verilog
    49113: 02/11/01: Re: Concepts: What is "Clock Edge"?
    49114: 02/11/01: Re: Metastability results are finally posted
    49325: 02/11/09: Re: new to fpga, what language is better to start with
    49326: 02/11/09: Re: LU-decomposition
    49360: 02/11/11: Re: LU-decomposition
    49417: 02/11/12: Re: LU-decomposition
    49418: 02/11/12: Re: LU-decomposition
    49526: 02/11/14: Re: LU-decomposition
    49529: 02/11/14: Re: How much to build this? xvga to ntsc uhf broadcaster
    49847: 02/11/22: Re: LUT Consumption in Virtex-2
    49848: 02/11/22: Re: how to use carry chain in Virtexe
    50052: 02/11/29: Re: Metastability in FPGAs
    50053: 02/11/29: Re: Metastability in FPGAs
    50054: 02/11/29: Re: hardware image processing - log computation
    50095: 02/12/02: Re: string to int conversion
    50241: 02/12/06: Re: meaning of system gates vs. logic gates?
    50260: 02/12/06: Re: meaning of system gates vs. logic gates?
    50562: 02/12/12: Re: what makes an implementation a patent?
    50711: 02/12/18: Re: what makes an implementation a patent?
    50869: 02/12/21: Re: thermal issues on FPGA
    50871: 02/12/21: Re: FPGA Supercomputing opportunity
    50962: 02/12/24: Re: FPGA Supercomputing opportunity
    51479: 03/01/14: Re: Open FPGA please!
    51920: 03/01/26: Re: What's the difference between LUT and RAM?
    51995: 03/01/28: Re: What's the difference between LUT and RAM?
    51998: 03/01/28: Re: 1024bit Adder
    51999: 03/01/28: Re: PCI protocol - assigning an address to my device
    52025: 03/01/29: Re: Random number generator
    63320: 03/11/19: Re: 400 Mb/s ADC
    63570: 03/11/25: Re: Slightly unmatched UART frequencies
    63644: 03/11/27: Re: Slightly unmatched UART frequencies
    63722: 03/12/02: Re: Exact Timing Constraints vs. Over-Constraining
    63741: 03/12/02: Re: Exact Timing Constraints vs. Over-Constraining
    64048: 03/12/14: Re: advantages of ethernet MAC ip core
    64208: 03/12/20: Re: advantages of ethernet MAC ip core
    64841: 04/01/15: Thermal characteristics of FPGA
    65005: 04/01/18: Re: Send Ethernet traffic from an FPGA
    65758: 04/02/06: Re: asynchronous counter an Xilinx FPGA for a newbie
    65856: 04/02/09: Re: Online debate: Programmable Logic vs ASIC vs Gate Array
    65894: 04/02/09: Re: iteration Vs LUT table entry vs accuracy in Cordic
    66065: 04/02/12: Re: negative hold time
    66117: 04/02/12: Re: Sine Wave Generation
    66193: 04/02/13: Re: regarding opto isolators
    66718: 04/02/25: Re: difference btw H/W & S/W implementations !!
    67994: 04/03/24: Re: Bus width between registers in IIR
    67996: 04/03/24: Re: Bus width between registers in IIR
    68020: 04/03/24: Re: Bus width between registers in IIR
    68065: 04/03/25: Re: Clock divider preserving duty-cycle ?
    68121: 04/03/27: Re: Homework Questions: where to find the best answers the fastest
    68199: 04/03/29: Re: study verilog or vhdl?
    68397: 04/04/03: Re: Metastablility
    68398: 04/04/03: Re: Metastablility
    68399: 04/04/03: Re: rs232 interface on nios
    68408: 04/04/03: Re: study verilog or vhdl?
    68926: 04/04/22: Re: calculate the number of logic gate in FPGA
    68958: 04/04/23: Re: Issues on Shift Register in a Clockless UART
    68959: 04/04/23: Re: What is MPGA?
    69237: 04/05/02: Re: Connecting a crystal to a Cyclone or Max PLD
    69275: 04/05/04: Re: Connecting a crystal to a Cyclone or Max PLD
    69289: 04/05/05: Re: Connecting a crystal to a Cyclone or Max PLD
    69716: 04/05/18: Webpack 6.1, ISEexamples, and CoreGen
    69720: 04/05/18: Re: Webpack 6.1, ISEexamples, and CoreGen
    69729: 04/05/19: Re: How to select an FPGA size (beginner)
    69730: 04/05/19: Re: Webpack 6.1, ISEexamples, and CoreGen
    69733: 04/05/19: Re: Inversion of signals on synthesis
    70194: 04/06/08: Re: comp.arch.fpga: reset strategy
    70311: 04/06/11: Re: comp.arch.fpga: reset strategy
    70428: 04/06/16: Re: >Math Skills = >Engineer ?
    70830: 04/06/29: Re: Family Photo Album
    71418: 04/07/18: Re: Is the Xilinix XC3020 atill supported?
    71478: 04/07/19: Re: twos to ones and ones to twos compliments
    71490: 04/07/20: Re: Spartan 3 termination question (DCI)
    71524: 04/07/21: Re: Low Power Applications - enumerate
    71587: 04/07/23: Re: Converting High Rise Time clock to Low Rise time clock - Chellenge!
    71775: 04/07/30: Re: 1GHz FPGA counters
    71811: 04/07/31: Re: 1GHz FPGA counters
    72317: 04/08/14: Re: 1GHz FPGA counters
    73711: 04/09/28: Re: fast adder and equal
    73730: 04/09/28: Re: High speed counters on Xilinx CoolRunner-II
    73787: 04/09/29: Re: FPGA for OCR processing
    73789: 04/09/29: Re: High speed counters on Xilinx CoolRunner-II
    73913: 04/09/30: Re: FPGA vs ASIC area
    73958: 04/10/01: Re: FPGA vs ASIC area
    73959: 04/10/01: Re: unbreakable conmbination cycle in Handel C
    72902: 04/09/07: Re: 1GHz FPGA counters
    72905: 04/09/07: Re: a newbie question
    73075: 04/09/13: Re: Altera Quartus FSM Simulation Delay?
    73076: 04/09/13: Re: Need some help with some technical claims...
    73078: 04/09/13: Re: why systemc?
    73082: 04/09/13: Re: Need some help with some technical claims...
    73126: 04/09/14: Re: Need some help with some technical claims...
    73153: 04/09/14: Re: Virtex 4 released today
    73244: 04/09/16: Re: adder VS increment
    73246: 04/09/16: Re: Burning Questions- FPGA architecture, packing, LUTs....
    73265: 04/09/17: Re: Synthesis problems with while and non-constant terminal point.
    73266: 04/09/17: Re: VHDL Design for running sorter
    73313: 04/09/19: Re: adder VS increment
    73314: 04/09/19: Re: USER RESET in XILINX FPGA
    73348: 04/09/20: Re: Verilog vs VHDL for Loops
    73414: 04/09/21: Re: Mr. Greenfield, spare us the propaganda !
    73424: 04/09/21: Re: Mr. Greenfield, spare us the propaganda !
    73428: 04/09/21: Re: Mr. Greenfield, spare us the propaganda !
    73441: 04/09/21: Re: XST vhdl adder with carry out : broken carry chain
    73511: 04/09/22: Re: How To Synchronize FPGAs
    73591: 04/09/24: Re: Nios Addressing
    73616: 04/09/26: Re: altera quartus II handbook is wrong??
    74943: 04/10/21: Re: Async reset
    75192: 04/10/28: Re: Low-power FPGAs?
    75193: 04/10/28: Re: synthesizeble Wait Statement in Procedure
    75301: 04/11/01: Re: "frying" FPGAs
    74094: 04/10/04: Re: FPGA vs ASIC area
    74136: 04/10/04: Re: Removing set/reset logic for shift register (HDL ADVISOR )
    74206: 04/10/06: Re: Sine function implementation in FPGA??
    74250: 04/10/06: Re: DCM and CLKFX - is this allowed?
    74253: 04/10/06: Re: Hash algorithm for hardware?
    74273: 04/10/06: Re: Removing set/reset logic for shift register (HDL ADVISOR )
    74355: 04/10/08: Re: FPGA for OCR processing
    74489: 04/10/12: Re: direct calculation of the modulus ?
    74495: 04/10/12: Re: Interfacing from the analogue domain
    74762: 04/10/18: Re: How many Altera LE's to Xilinx Slices????
    74798: 04/10/19: Re: spartan 3 on 4 layers
    74803: 04/10/19: Re: spartan 3 on 4 layers
    74809: 04/10/19: Re: spartan 3 on 4 layers
    74815: 04/10/19: Re: spartan 3 on 4 layers
    74884: 04/10/20: Re: Async reset
    74917: 04/10/21: Re: Async reset
    75599: 04/11/10: Re: Xilinx Tshirts in football package.....
    75798: 04/11/15: Re: Digital LP filter in multiplier free FPGA
    75804: 04/11/15: Re: Soft Processor Core
    75934: 04/11/19: Re: digital analog conversion
    75936: 04/11/19: Re: RocketIO success?
    75944: 04/11/19: Re: RocketIO success?
    75947: 04/11/19: Re: RocketIO success?
    76017: 04/11/22: Re: Spartan 3 output voltage level
    76094: 04/11/24: Re: Choice of FPGA device
    76255: 04/11/29: Re: PCI interrupt negation
    76283: 04/11/29: Re: Verilog newbie with clocking question
    76338: 04/11/30: Re: Verilog newbie with clocking question
    76345: 04/11/30: Re: CMOS capacitive loads, transition probabilities and FPGAs
    76353: 04/11/30: Re: CMOS capacitive loads, transition probabilities and FPGAs
    76354: 04/11/30: Re: two I/O markers on the same wire
    76446: 04/12/02: Re: FF/Latch trimming : Xilinx ISE 6.3 i
    76569: 04/12/06: Re: Connecting a spartan2 FPGA to an ISA bus
    76571: 04/12/06: Re: how to start with development of eda tools
    76712: 04/12/09: Re: making an fpga hot
    76716: 04/12/09: Re: Software controllable clock generator, Xilinx Virtex-II
    76736: 04/12/09: Re: Software controllable clock generator, Xilinx Virtex-II
    76766: 04/12/10: Re: 30bit - adder performance improvement
    76767: 04/12/10: Re: Lookup table simulation problems
    76777: 04/12/10: Re: Lookup table simulation problems
    76858: 04/12/14: Re: Cyclone device misteriously overheats
    76895: 04/12/15: Re: Cylone Problem with Large Shift Register
    76897: 04/12/15: Re: Quartus II Graphic Editor Anomaly?
    76952: 04/12/16: Re: Digital clock synthesis
    77048: 04/12/20: Re: making an fpga hot
    77069: 04/12/21: Re: making an fpga hot
    77077: 04/12/21: Re: Using low-core-voltage devices in industrial applications
    77324: 05/01/04: Re: Algorithm to Hardware ?
    77326: 05/01/04: Re: EU patent debate, any effects on FPGA-design?
    77332: 05/01/04: Re: EU patent debate, any effects on FPGA-design?
    77589: 05/01/11: Re: (d)ram interface
    77594: 05/01/11: Re: Clock Domains with PLL
    77614: 05/01/12: Re: Beware of Vref pins becoming "unused" (Xilinx)
    77635: 05/01/12: Re: Programming and copyright
    77848: 05/01/18: Re: Problems in timing simulations
    77881: 05/01/19: eric
    77905: 05/01/20: Re: LVDS through connectors
    77947: 05/01/20: Re: Xilinx Sum in VHDL
    77981: 05/01/21: Re: Xilinx Sum in VHDL
    78087: 05/01/24: Re: 60Hz clock on XC9572
    78226: 05/01/26: Re: 60Hz clock on XC9572
    78416: 05/01/31: Re: Active HIGH / Active LOW
    78569: 05/02/03: Re: MP3 Player Project
    78600: 05/02/03: Re: See Peter's High-Wire Act next Tuesday
    78631: 05/02/04: Benchmarks or not.
    78644: 05/02/04: Re: Benchmarks or not.
    78655: 05/02/04: Re: Benchmarks or not.
    78761: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
    78917: 05/02/10: Re: second flop in asyn reset distribution
    79231: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
    79335: 05/02/17: Re: Simple counter
    79336: 05/02/17: Re: 2 microblaze access same BRAM ?
    79361: 05/02/17: Re: Make program stop
    79642: 05/02/22: Re: Tristate Discussion
    79644: 05/02/22: Re: Make program stop
    79656: 05/02/22: Re: Make program stop
    79666: 05/02/22: Re: Hardcopy Vs ASIC
    79713: 05/02/23: Re: Tristate Discussion
    79716: 05/02/23: Re: Make program stop
    79811: 05/02/24: Re: Multiple additions
    79818: 05/02/24: Re: Multiple addition(2)
    79824: 05/02/24: Re: Fast 28x28 multiplier + adder in Virtex4
    79910: 05/02/25: Re: Fast 28x28 multiplier + adder in Virtex4
    80020: 05/02/28: Re: block adder for Altera!
    80039: 05/02/28: Re: I2C protocol to communicate between FPGAs
    80092: 05/03/01: Re: Fast 28x28 multiplier + adder in Virtex4
    80371: 05/03/04: Re: Xilinx/Howard Johnson's crosstalk web seminar
    80386: 05/03/04: Re: VHDL Instantiation
    80399: 05/03/04: Re: SR latches in Xilinx devices?
    80499: 05/03/07: Re: Asynchronous processor !?!
    80602: 05/03/08: Re: Async FIFO problem...
    80717: 05/03/10: Re: Xilinx vs Altera high-end solutions
    81102: 05/03/17: Re: Newbie: Slow FPGAs
    81318: 05/03/21: Re: Free simulator
    81324: 05/03/21: Re: Altera free web FPGA software license question
    84128: 05/05/12: Re: High radix multiplier
    84129: 05/05/12: Re: float computing: how to add libm.a
    84130: 05/05/12: Re: How to implement this C function in FPGA
    84132: 05/05/12: Re: Median Filter for floating points
    87420: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    88695: 05/08/25: Re: "Tbufs don't exist"
    88697: 05/08/25: Re: Best FPGA for floating point performance
    88698: 05/08/25: Re: Design is too large for the device! xc3s400
    88699: 05/08/25: Re: Design is too large for the device! xc3s400
    88701: 05/08/25: Re: Ones Count 64 bit on Xilinx in VHDL
    89204: 05/09/07: Re: 8087 co-processor
    89205: 05/09/07: Re: Best FPGA for floating point performance
    89208: 05/09/07: Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;
    89209: 05/09/07: Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;
    89274: 05/09/09: Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;
    89279: 05/09/09: Re: Best FPGA for floating point performance
    112919: 06/12/01: Re: Avoiding meta stability?
    113250: 06/12/08: Re: FPGA application field
    113251: 06/12/08: Re: FPGA application field
    113253: 06/12/08: Re: Avoiding meta stability?
    113457: 06/12/13: Re: . What is the sign-and-magnitude of the following 4's complement
    113458: 06/12/13: Re: Ones' complement addition
    113459: 06/12/14: Re: Avoiding meta stability?
    113461: 06/12/14: Re: Question about metastability that's been on my mind for a while
    113563: 06/12/16: Re: Timing constraings: min delay?
    113636: 06/12/18: Re: Frequency divider?
    113641: 06/12/19: Re: solder mask for fpga dissipation
    113703: 06/12/19: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
    113708: 06/12/19: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
    114227: 07/01/08: Re: Ones' complement addition
    114343: 07/01/12: Re: Ones' complement addition
    114344: 07/01/12: Re: ethernet checksum nightmare
    114345: 07/01/12: Re: ethernet checksum nightmare
    114346: 07/01/12: Re: ethernet checksum nightmare
    114562: 07/01/19: Re: "Gate" = ???
    114563: 07/01/19: Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO
    114564: 07/01/19: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational
    114565: 07/01/19: Re: ethernet checksum nightmare
    114964: 07/01/28: Re: On-chip randomness (V4FX)
    115045: 07/01/29: Re: Problem with verilog program
    115047: 07/01/29: Re: Problem with verilog program
    115091: 07/01/30: Re: how does z-transforms (basically the mathematical techniques
    115100: 07/01/30: Re: Minimal design for xilinx?
    115512: 07/02/12: Re: 1 Gbps - state of the art?
    115560: 07/02/13: Re: audio low pass filtering in FPGA
    115804: 07/02/21: Re: audio low pass filtering in FPGA
    115923: 07/02/25: Re: Loss Diagram
    116425: 07/03/08: Re: Large power planes vs. power islands vs. slits for decoupling
    116440: 07/03/08: Re: Large power planes vs. power islands vs. slits for decoupling
    116555: 07/03/12: Re: Estimating number of FPGAs needed for an application
    116556: 07/03/12: Re: Estimating number of FPGAs needed for an application
    116702: 07/03/15: Re: .bit file to VHDL/verilog source code
    116704: 07/03/15: Re: Clearing fpga internal memory...
    116896: 07/03/20: Re: Clearing fpga internal memory...
    116897: 07/03/20: Re: FPGA vs. GPP anyone?
    117047: 07/03/22: Re: FPGA with 5V and PLCC package
    117048: 07/03/22: Re: FPGA with 5V and PLCC package
    117149: 07/03/23: Re: FPGA with 5V and PLCC package
    117150: 07/03/23: Re: FPGA with 5V and PLCC package
    119369: 07/05/17: Re: 64 bit matrix multplication
    119371: 07/05/17: Re: Seeking the solutions of high speed interconnection for the long
    119372: 07/05/17: Re: Seeking the solutions of high speed interconnection for the long
    119373: 07/05/17: Re: Fortran to matlab infuriating problem
    119423: 07/05/18: Re: Power Consumption near Timing Failure Point
    119425: 07/05/18: Re: Seeking the solutions of high speed interconnection for the long
    119466: 07/05/20: Re: How to insert tab in Write() function in VHDL
    119568: 07/05/22: Re: How to insert tab in Write() function in VHDL
    120059: 07/05/31: Re: Inverse of a matrix
    120359: 07/06/05: Re: Topics and Ideas for BS Project
    120942: 07/06/20: Re: Interesting problems about high performance computing
    121327: 07/07/02: Re: Topics and Ideas for BS Project
    121602: 07/07/09: Re: Bit error counter - how to make it faster
    121603: 07/07/09: Re: Bit error counter - how to make it faster
    121610: 07/07/09: Re: Interesting problems about high performance computing
    122633: 07/08/01: Re: Best CPU platform(s) for FPGA synthesis
    122636: 07/08/01: Re: Interesting problems about high performance computing
    123410: 07/08/27: Re: tricking bitgen into creating rom-like behavior
    123678: 07/08/31: Re: Is it possible to make bit files generated by Xilinx ISE readable?
    123752: 07/09/03: Re: FPGA CPU
    123779: 07/09/04: Re: PCB Impedance Control
    123781: 07/09/04: Re: Beginning FPGA programming
    123834: 07/09/05: Re: FPGA CPU
    123836: 07/09/05: Re: high bandwitch ethernet communication
    123838: 07/09/05: Re: How to deal with the tempary coefficient in the FPGA design
    123840: 07/09/05: Re: PCB Impedance Control
    123841: 07/09/05: Re: PCB Impedance Control
    123844: 07/09/05: Re: PCB Impedance Control
    123845: 07/09/05: Re: PCB Impedance Control
    123854: 07/09/05: Re: FPGA CPU
    123928: 07/09/06: Re: high bandwitch ethernet communication
    123929: 07/09/06: Re: PCB Impedance Control
    123930: 07/09/06: Re: PCB Impedance Control
    123931: 07/09/06: Re: PCB Impedance Control
    123932: 07/09/06: Re: PCB Impedance Control
    123933: 07/09/06: Re: PCB Impedance Control
    123966: 07/09/08: Re: high bandwitch ethernet communication
    124018: 07/09/10: Re: Minimize power consumption
    124051: 07/09/11: Re: How to deal with the tempary coefficient in the FPGA design
    124084: 07/09/11: Re: Uses of Gray code in digital design
    124099: 07/09/11: Re: What is called carry chain structure in FPGA is called in IC?
    124243: 07/09/16: Re: Physical Design Contribution to FPGA/CPLD success
    124283: 07/09/17: Re: Guess: what is the largest number of state machines in a current
    124288: 07/09/17: Re: Physical Design Contribution to FPGA/CPLD success
    124323: 07/09/18: Re: Guess: what is the largest number of state machines in a current
    124324: 07/09/18: Re: Tristate bus on spartan FPGA
    124326: 07/09/18: Re: Guess: what is the largest number of state machines in a current
    124337: 07/09/18: Re: Population Count circuit
    124338: 07/09/18: Re: Tristate bus on spartan FPGA
    124340: 07/09/18: Re: Population Count circuit
    124367: 07/09/19: Re: Guess: what is the largest number of state machines in a current
    124410: 07/09/20: Re: Guess: what is the largest number of state machines in a current
    124432: 07/09/21: Re: Clock boundary crossing
    124434: 07/09/21: Re: Guess: what is the largest number of state machines in a current
    124435: 07/09/21: Re: Gated Clock Problems
    124436: 07/09/21: Re: Looking for fast AES cores with low latency
    124448: 07/09/21: Re: Guess: what is the largest number of state machines in a current
    124465: 07/09/22: Re: Looking for fast AES cores with low latency
    124715: 07/10/01: Re: Count Leading Zero (CLZ) possible by MicroBlaze??
    124741: 07/10/02: Re: FPGA NTSC signal with 2 resistors and PWM
    124781: 07/10/04: Re: FPGA NTSC signal with 2 resistors and PWM
    124838: 07/10/06: Re: Optimized bitcounting on FPGA
    125046: 07/10/15: Re: FPGA quiz: what can be wrong
    125148: 07/10/16: Re: FPGA quiz: what can be wrong
    125401: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
    125458: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
    125459: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
    125508: 07/10/26: Re: Power supply filter capacitors
    125520: 07/10/27: Re: Changing refresh rate for DRAM while in operation?
    125521: 07/10/27: Re: Power supply filter capacitors
    125631: 07/10/30: Re: FPGA vs ASIC
    125633: 07/10/30: Re: Power supply filter capacitors
    125635: 07/10/30: Re: Power supply filter capacitors
    125735: 07/11/02: Re: FPGA vs ASIC
    126279: 07/11/19: Re: Quartus II warning: "pass-through logic has been added"
    126492: 07/11/25: Re: using fpga as programmable connection
    126493: 07/11/25: Re: converter
    126494: 07/11/25: Re: Measuring setup and hold time in Lab
    126570: 07/11/27: Re: can't read/load memory contents
    126749: 07/11/30: Re: CPU design uses too many slices
    126750: 07/11/30: Re: Pipelining of FPGA code
    126862: 07/12/04: Re: What's the difference for VHDL code between simulation and synthesis?
    126919: 07/12/05: Re: What's the difference for VHDL code between simulation and synthesis?
    126920: 07/12/05: Re: Mixed language design
    126960: 07/12/06: Re: What's the difference for VHDL code between simulation and synthesis?
    127322: 07/12/18: Re: Why the core dynamic power isn't 0 when the toggle rate is 0
    127547: 08/01/02: Re: Split Plane
    127565: 08/01/02: Re: Split Plane
    127656: 08/01/04: Re: Split Plane
    127664: 08/01/04: Re: Split Plane
    127667: 08/01/04: Re: Split Plane
    127700: 08/01/05: Re: Split Plane
    127734: 08/01/06: Re: Ethernet on recent FPGAs
    127746: 08/01/06: Re: MicroBlaze floating point precision issues
    127767: 08/01/07: Re: Ethernet on recent FPGAs
    127768: 08/01/07: Re: MicroBlaze floating point precision issues
    127770: 08/01/07: Re: Ethernet on recent FPGAs
    127820: 08/01/08: Re: Real examples of metastability causing bugs
    127822: 08/01/08: Re: Split Plane
    127874: 08/01/09: Re: Real examples of metastability causing bugs
    127877: 08/01/09: Re: Real examples of metastability causing bugs
    127887: 08/01/09: Re: Real examples of metastability causing bugs
    127943: 08/01/10: Re: Can you help me about SAS IP core implementing
    128027: 08/01/13: Re: Place-and-Route : Intel vs AMD
    128028: 08/01/13: Re: Real examples of metastability causing bugs
    128150: 08/01/16: Re: speed... CORDIC vs. pure arithmetic expression
    128157: 08/01/16: Re: Quartus II Incremental compilation?
    128221: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
    128382: 08/01/23: Re: FPGA decoupling calculation
    128414: 08/01/24: Re: Random Number Generation in VHDL
    128435: 08/01/25: Re: Random Number Generation in VHDL
    128442: 08/01/25: Re: Random Number Generation in VHDL
    129025: 08/02/12: Re: how to implement this...
    129962: 08/03/11: Re: BRAM synthesis question
    129963: 08/03/11: Re: BRAM synthesis question
    129964: 08/03/11: Re: XC3S50-4VQ100C fpga chip
    129965: 08/03/11: Re: Need info on systolic arrays in actual use
    129968: 08/03/11: Re: Convert some table into combinatorial circuit + optimization
    130187: 08/03/17: Re: implementing ethernet FCS code in verilog
    130242: 08/03/18: Re: dual clock fifo
    130428: 08/03/23: Re: A Challenge for serialized processor design and implementation
    130924: 08/04/05: Re: A Challenge for serialized processor design and implementation
    130939: 08/04/05: Re: problem with synthesis of a state machine
    131070: 08/04/09: Re: Serial Transmission w/o 8B/10B encoding
    131155: 08/04/13: Re: Serial Transmission w/o 8B/10B encoding
    131367: 08/04/20: Re: Problem writing quadrature decoder
    131368: 08/04/20: Re: Very simple VHDL problem
    131595: 08/04/25: Re: Problem writing quadrature decoder
    131596: 08/04/25: Re: the order in which some switches are turned on
    131920: 08/05/07: Re: Forking in One-Hot FSMs
    132019: 08/05/09: Re: Problem writing quadrature decoder
    132101: 08/05/13: Re: 5 V oscillator output to GCLK
    132103: 08/05/13: Re: Problem writing quadrature decoder
    132200: 08/05/16: Re: Resetting FPGA Without watch dog timer
    132201: 08/05/16: Re: Incorporating FPGAs on PCBs
    132353: 08/05/22: Re: asic gate count
    132380: 08/05/24: Re: asic gate count
    132456: 08/05/27: Re: Downloading external data file to FPGA
    132578: 08/06/01: Re: Combinatorial logic delay plus routing delay exceeds clock period
    132650: 08/06/04: Re: Using ethernet on a Xilnx board (Help appreciated)
    132652: 08/06/04: Re: Checksums
    132849: 08/06/09: Re: HDL tricks for better timing closure in FPGAs
    132850: 08/06/09: Re: FPGA clock frequency
    132883: 08/06/09: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    132900: 08/06/10: Re: where is the IP address assigned to the fpga in Trimode Ethernet
    133021: 08/06/13: Re: FPGA clock frequency
    133022: 08/06/13: Re: fpga reprogrammable?
    133024: 08/06/13: Re: Digital VSB (Vestigial Side Band) Modulator for Analog TV
    133025: 08/06/13: Re: where is the IP address assigned to the fpga in Trimode Ethernet
    133026: 08/06/13: Re: FSM running with unstable clock
    133066: 08/06/16: Re: FPGA clock frequency
    133281: 08/06/23: Re: Image Sensor Interface.
    133296: 08/06/23: Re: Image Sensor Interface.
    133321: 08/06/24: Re: Image Sensor Interface.
    133360: 08/06/25: Re: FPGA area use by module?
    133361: 08/06/25: Re: FPGA based database searching
    133972: 08/07/20: Re: No open-drain in V5 to drive an external LED?
    134058: 08/07/23: Re: audio serial port i2s
    134059: 08/07/23: Re: audio serial port i2s
    134175: 08/07/28: Re: vhdl code for debouncing push button
    134288: 08/08/04: Re: fixed FFT point implementation woes
    134289: 08/08/04: Re: fixed FFT point implementation woes
    134389: 08/08/08: Re: RTL Schematic as EDIF
    134391: 08/08/08: Re: Downsizing Verilog synthesization.
    134392: 08/08/08: Re: Downsizing Verilog synthesization.
    134398: 08/08/08: Re: RTL Schematic as EDIF
    134456: 08/08/11: Re: Downsizing Verilog synthesization.
    134887: 08/09/04: Re: Genode FPGA graphics project launched
    134888: 08/09/04: Re: crazy patent
    135077: 08/09/13: Re: need fast FPGA suggestions
    135197: 08/09/19: Re: Clock Enable safe?
    135198: 08/09/19: Re: interview questions ........
    135274: 08/09/23: Re: duty cycle significance
    135318: 08/09/25: Re: duty cycle significance
    135383: 08/09/29: Re: Sending UDP packets over Ethernet
    135386: 08/09/29: Re: Sending UDP packets over Ethernet
    135402: 08/09/30: Re: Sending UDP packets over Ethernet
    135404: 08/09/30: Re: Sending UDP packets over Ethernet
    135429: 08/10/01: Re: which FPGA chip to use for FFT?
    135459: 08/10/02: Re: floating point round off errors
    135466: 08/10/02: Re: floating point round off errors
    135767: 08/10/15: Re: Literature on 100Base-TX request
    135939: 08/10/22: Re: Literature on 100Base-TX request
    135940: 08/10/22: Re: Literature on 100Base-TX request
    135941: 08/10/22: Re: A couple of CPLD design challenges for the group
    137029: 08/12/19: Re: FPGA partial/catastrophic failure mode question
    137031: 08/12/19: Re: FPGA partial/catastrophic failure mode question
    137040: 08/12/20: Re: PLL and clock in altera cyclone 2 fpga
    137122: 08/12/24: Re: which HLL for HPC applications implementation?
    137159: 08/12/29: Re: FPGA > ASIC
    137425: 09/01/15: Re: Creating a core from my VHDL code
    137448: 09/01/17: Re: Duty Cycle change effects on Internal reg's
    137467: 09/01/18: Re: Using memory blocks generated by CoreGen
    137552: 09/01/22: Re: How to add some SDRAM to a FPGA board ?
    137559: 09/01/22: Running 32 bit ISE on 64 bit linux
    137588: 09/01/22: Re: Altera Stratix II can support Floating point operators?
    137593: 09/01/23: Re: How to add some SDRAM to a FPGA board ?
    137622: 09/01/24: Re: How to add some SDRAM to a FPGA board ?
    137742: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
    137743: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
    137764: 09/01/29: Re: XST Makes Odd Choice
    137765: 09/01/29: Re: XST Makes Odd Choice
    137772: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
    137773: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
    137808: 09/01/30: Re: UART RS232 "hello world" program trial and terror.
    137828: 09/01/30: Re: UART RS232 "hello world" program trial and terror.
    137853: 09/02/01: Re: LUT design / Transmission gates or pass transistors?
    137858: 09/02/01: Re: Selecting a starter FPGA board
    137877: 09/02/01: Re: Selecting a starter FPGA board
    137882: 09/02/01: Re: Selecting a starter FPGA board
    137921: 09/02/02: Re: FFT core has reversed output data
    137922: 09/02/02: Re: Why the second flip-flop in Virtex-6?
    137939: 09/02/02: Re: Why the second flip-flop in Virtex-6?
    137987: 09/02/03: Re: Why the second flip-flop in Virtex-6?
    137998: 09/02/03: Re: Why the second flip-flop in Virtex-6?
    138019: 09/02/04: Re: Why the second flip-flop in Virtex-6?
    138020: 09/02/04: Re: Sixteen serial ports ?
    138058: 09/02/05: Re: dual processor PC for PPR - are they worth the extra cost?
    138769: 09/03/09: Re: Image loading into FPGA - from computer
    138773: 09/03/09: Re: Image loading into FPGA - from computer
    138942: 09/03/15: Re: inout pins use in fpga
    138968: 09/03/17: Re: Zero operand CPUs
    139029: 09/03/18: Re: Xilinx XAPP052 LFSR and its understanding
    139043: 09/03/19: Re: Xilinx XAPP052 LFSR and its understanding
    139070: 09/03/19: Re: Xilinx XAPP052 LFSR and its understanding
    139072: 09/03/19: Re: Xilinx XAPP052 LFSR and its understanding
    139103: 09/03/20: Re: How big is my vhdl and am I approaching some size limitation on the chip.
    139182: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on ?the chip.
    139210: 09/03/23: Re: Silicon Blue last datesheet correct URL
    139212: 09/03/23: Re: Using Floating Point Unit in Virtex 2 pro
    139240: 09/03/24: Re: Xilinx XAPP052 LFSR and its understanding
    139241: 09/03/24: Re: Silicon Blue last datesheet correct URL
    139248: 09/03/24: Re: Silicon Blue last datesheet correct URL
    139270: 09/03/24: Re: FPGAs in automotive apps (was Re: Silicon Blue last datesheet ?correct URL)
    139423: 09/03/29: Re: added jitter on FPGAs
    139644: 09/04/08: Re: Two stage synchroniser,how does it work?
    139645: 09/04/08: Re: Two stage synchroniser,how does it work?
    139649: 09/04/08: Re: Two stage synchroniser,how does it work?
    139705: 09/04/09: Re: How to understand the Nearest Even mode of Xilinx in quantization
    139830: 09/04/15: Re: S3A starterkit weird behaviou (mini quiz)
    139831: 09/04/15: Re: What is the minimum acceptable slack on a signal
    139896: 09/04/18: Re: Why is XST optimizing away my registers and how do I stop it?
    139934: 09/04/20: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA ?)
    139941: 09/04/20: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA ?)
    139947: 09/04/20: Re: fpga locks up with slow signal, spartan chip, pin type issues.
    139948: 09/04/20: Re: ISE 10.1 installation troubles on windows Vista 32bit
    140045: 09/04/25: Re: About those TIEOFF primitives ...
    140069: 09/04/27: Re: I have some doubts in verilog
    140098: 09/04/28: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
    140112: 09/04/29: Re: a basics question: using input pins, pullup, short to ground vs ?driven signal.
    140117: 09/04/29: Re: I have some doubts in verilog
    140154: 09/04/30: Re: FPGA simulator for face recognition
    140192: 09/05/02: Re: Spartan3E Starter Kit MISO and Flash pin shared
    140194: 09/05/02: Re: Spartan3E Starter Kit MISO and Flash pin shared
    140206: 09/05/04: Re: High-speed signals crossing a split-ground
    140218: 09/05/04: Re: High-speed signals crossing a split-ground
    140221: 09/05/04: Re: High-speed signals crossing a split-ground
    140229: 09/05/04: Re: High-speed signals crossing a split-ground
    140271: 09/05/07: Re: board with 2 gigabit ethernet connectors?
    140290: 09/05/07: Re: FPGAs and Cryptography
    140318: 09/05/08: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by ?FPGA
    140319: 09/05/08: Re: FPGAs and Cryptography
    140430: 09/05/13: Re: How to improve maximum operating frequency of a design using DSP 48E?
    140431: 09/05/13: Re: connecting FPGA with PC using ethernet MAC layer only
    140537: 09/05/16: Re: Cheap Ethernet PHY boards?
    140579: 09/05/18: Re: XILINX license model restricts longtime availability
    140635: 09/05/21: Re: Online tool that generates parallel CRC and Scrambler
    140907: 09/05/29: Re: Online tool that generates parallel CRC and Scrambler
    141006: 09/06/02: Re: the reach of VHDL
    141107: 09/06/05: Re: digital RGB Video to Analog VGA triple DAC question
    141253: 09/06/12: Re: Verilog "for loop" - exit by setting i to exit value?
    141254: 09/06/12: Re: NTSC/PAL Encoder using FPGA and DAC
    141394: 09/06/22: Re: Question on FPGA driver
    141526: 09/06/26: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141532: 09/06/26: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141541: 09/06/27: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141635: 09/07/01: Re: FPGA as FM RADIO transmitter
    141738: 09/07/06: Re: Math Integral operation in FPGA
    141739: 09/07/06: Re: Math Integral operation in FPGA
    141754: 09/07/06: Re: Math Integral operation in FPGA
    141755: 09/07/06: Re: Math Integral operation in FPGA
    141774: 09/07/08: Re: Multipliers and CORDIC cores
    141780: 09/07/08: Re: Multipliers and CORDIC cores
    141799: 09/07/10: Re: Multipliers and CORDIC cores
    141803: 09/07/10: Re: Multipliers and CORDIC cores
    141825: 09/07/10: Re: How to implementa an FSM in block ram
    141829: 09/07/11: Re: pullup
    141874: 09/07/14: Re: Adder size vs Register size
    141875: 09/07/14: Re: Minimal size 1-bit adder....
    141883: 09/07/15: Re: HELP required floating point multiplier on FPGA
    141913: 09/07/17: Re: How to implementa an FSM in block ram
    141925: 09/07/17: Re: How to implementa an FSM in block ram
    141926: 09/07/17: Re: FPGA to PC connection
    141948: 09/07/18: Re: FPGA editor in Fedora 11 x86_64
    141950: 09/07/18: Re: FPGA editor in Fedora 11 x86_64
    142064: 09/07/23: Re: FPGA development tools for FreeBSD?
    142066: 09/07/23: Re: FPGA development tools for FreeBSD?
    142343: 09/08/05: Re: AES encryption of bitstream - is my design secure?
    142346: 09/08/05: Re: AES encryption of bitstream - is my design secure?
    142347: 09/08/05: Re: AES encryption of bitstream - is my design secure?
    142348: 09/08/05: Re: AES encryption of bitstream - is my design secure?
    142355: 09/08/05: Re: AES encryption of bitstream - is my design secure?
    142365: 09/08/06: Re: AES encryption of bitstream - is my design secure?
    142367: 09/08/06: Re: AES encryption of bitstream - is my design secure?
    142371: 09/08/07: Re: AES encryption of bitstream - is my design secure?
    142390: 09/08/08: Re: Peter Alfke
    142407: 09/08/09: Re: Spartan-6 Boards - Your Wish List
    142420: 09/08/10: Re: Spartan-6 Boards - Your Wish List
    142427: 09/08/10: Re: Spartan-6 Boards - Your Wish List
    142438: 09/08/11: Re: Spartan-6 Boards - Your Wish List
    142440: 09/08/11: Re: algorithm implementation in IC
    142444: 09/08/11: Re: algorithm implementation in IC
    142479: 09/08/12: Re: Spartan-6 Boards - Your Wish List
    142480: 09/08/12: Re: Spartan-6 Boards - Your Wish List
    142505: 09/08/13: Re: Spartan-6 Boards - Your Wish List
    142535: 09/08/16: Re: Soft Processor IP core report
    142670: 09/08/25: Re: Timing properties of FPGA devices at sub-clock frequencies
    142673: 09/08/25: Re: Timing properties of FPGA devices at sub-clock frequencies
    142677: 09/08/25: Re: Timing properties of FPGA devices at sub-clock frequencies
    142685: 09/08/26: Re: Reading from ADC and writing to DAC at same time
    142712: 09/08/27: Re: Is free-to-use IP included with downloadable FPGA tools?
    142848: 09/09/03: Re: Choice of Language for FPGA programming
    142981: 09/09/11: Re: Behavior of crystal oscillator?
    142997: 09/09/14: Re: Behavior of crystal oscillator?
    143006: 09/09/14: Re: Everything in single clock cycle.
    143008: 09/09/14: Re: Everything in single clock cycle.
    143088: 09/09/19: Re: FPGA for acoustic adaptive beamforming
    143107: 09/09/21: Re: timing simulation performance
    143120: 09/09/22: Re: VHDL question
    143156: 09/09/23: Re: Shift left arithmetic?
    143167: 09/09/23: Re: VHDL question
    143184: 09/09/24: Re: Shift left arithmetic?
    143316: 09/10/01: Re: Up-counter with async load/clear and overflow detection (Verilog)
    143323: 09/10/02: Re: Up-counter with async load/clear and overflow detection (Verilog)
    143354: 09/10/05: Re: Post route simulation and real implementation
    143357: 09/10/05: Re: Multiplier design with carry-save adder + Booth encoding
    143360: 09/10/05: Re: Implement ARM cores on a FPGA chip?
    143368: 09/10/06: Re: Ideas for a pulse programmer needed
    143377: 09/10/07: Re: Implement ARM cores on a FPGA chip?
    143407: 09/10/09: Re: ASIC Prototyping using FPGA
    143522: 09/10/14: Re: What is the basis on flip-flop replaced by a latch
    143526: 09/10/14: Re: What is the basis on flip-flop replaced by a latch
    143533: 09/10/15: Re: What is the basis on flip-flop replaced by a latch
    143536: 09/10/15: Re: How to get clocks from DCM that the duty cycle is not 1:1
    143550: 09/10/15: Re: What is the basis on flip-flop replaced by a latch
    143565: 09/10/16: Re: How to get clocks from DCM that the duty cycle is not 1:1
    143566: 09/10/16: Re: FSM-states after reconf.
    143568: 09/10/16: Re: FSM-states after reconf.
    143572: 09/10/16: Re: FSM-states after reconf.
    143576: 09/10/16: Re: problem while receiving negative integer in microblaze
    143581: 09/10/17: Re: What is the basis on flip-flop replaced by a latch
    143585: 09/10/17: Re: What is the basis on flip-flop replaced by a latch
    143592: 09/10/17: Re: problem while receiving negative integer in microblaze
    143594: 09/10/17: Re: Any interest in a group Xilinx FPGA board build/buy ??
    143596: 09/10/17: Re: Any interest in a group Xilinx FPGA board build/buy ??
    143599: 09/10/17: Re: problem while receiving negative integer in microblaze
    143601: 09/10/17: Re: problem while receiving negative integer in microblaze
    143605: 09/10/18: Re: Any interest in a group Xilinx FPGA board build/buy ??
    143619: 09/10/18: Re: Any interest in a group Xilinx FPGA board build/buy ??
    143625: 09/10/19: Re: Any interest in a group Xilinx FPGA board build/buy ??
    143669: 09/10/20: Re: problem while receiving negative integer in microblaze
    143671: 09/10/20: Re: problem while receiving negative integer in microblaze
    143692: 09/10/21: Re: License issues
    143745: 09/10/23: Re: problem while receiving negative integer in microblaze
    143845: 09/10/29: Re: save data from adc in text file
    143903: 09/11/02: Re: Need some help creating a ring oscillator on a Spartan-3AN
    144030: 09/11/08: Re: Sinewave generation
    144158: 09/11/14: Re: New blog post on alphas in packagin
    144189: 09/11/18: Re: NIOS and ftoa()
    144204: 09/11/19: Re: NIOS and ftoa()
    144379: 09/12/02: Re: domain crossing and clock synchronisation for a high frequency timer
    144503: 09/12/11: Re: very wide counter (42-bit)
    144516: 09/12/12: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
    144528: 09/12/13: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
    144531: 09/12/13: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
    144535: 09/12/13: Re: Does a 1-bit mux glitch if only one input is known to change at ?one time?
    144667: 09/12/22: Re: Please help, Xilinx FIFO problem!
    144728: 09/12/29: Re: How to protect my Virtex5 design without battery?
    144769: 10/01/01: Re: verilog multiplexer
    144787: 10/01/02: Re: NOR-based Flash Memory - Design
    144788: 10/01/02: Re: ASM hardware language definition file for Altera/Xilinx
    145056: 10/01/23: Re: Spartan 3E Starter Kit - Power problem
    145129: 10/01/29: Re: DPA vs FPGA Security?
    145164: 10/01/30: Re: synthesizing a completely empty design for an FPGA to measure ?quiescent current
    145226: 10/02/02: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for ?RS232 communication?
    145232: 10/02/02: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for ??RS232 communication?
    145233: 10/02/02: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for ?RS232 communication?
    145237: 10/02/02: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for ?RS232 communication?
    145245: 10/02/03: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for RS232 communication?
    145276: 10/02/04: Re: Matching hadware and software CRC
    145326: 10/02/05: Re: Board layout for FPGA
    145327: 10/02/05: Re: Board layout for FPGA
    145328: 10/02/05: Re: Board layout for FPGA
    145329: 10/02/05: Re: using an FPGA to emulate a vintage computer
    145341: 10/02/06: Re: Board layout for FPGA
    145353: 10/02/06: Re: Board layout for FPGA
    145367: 10/02/06: Re: Board layout for FPGA
    145368: 10/02/06: Re: Board layout for FPGA
    145369: 10/02/06: Re: using an FPGA to emulate a vintage computer
    145373: 10/02/07: Re: Board layout for FPGA
    145388: 10/02/08: Re: Board layout for FPGA
    145412: 10/02/08: Re: using an FPGA to emulate a vintage computer
    145419: 10/02/08: Re: using an FPGA to emulate a vintage computer
    145441: 10/02/09: Re: Board layout for FPGA
    145457: 10/02/10: Re: Reading UDP with FPGA
    145459: 10/02/10: Re: Reading UDP with FPGA
    145489: 10/02/12: Re: Synplify out of memory
    145491: 10/02/12: Re: What is the basis on flip-flops replaced by a latch
    145509: 10/02/12: Re: Why is following Verilog code snipper considered a Latch
    145537: 10/02/13: Re: What is the basis on flip-flops replaced by a latch
    145580: 10/02/15: Re: To get higher clock frequencies at output using propagation delays.
    145582: 10/02/15: Re: optimal no of inputs to be given in a test bench
    145605: 10/02/15: Re: To get higher clock frequencies at output using propagation delays.
    145606: 10/02/15: Re: optimal no of inputs to be given in a test bench
    145612: 10/02/16: Re: The more you read, the more you are confused: about Intel's a patent
    145629: 10/02/16: Re: Board layout for FPGA
    145632: 10/02/17: Re: What is the basis on flip-flops replaced by a latch
    145635: 10/02/17: Re: Board layout for FPGA
    145636: 10/02/17: Re: What is the basis on flip-flops replaced by a latch
    145754: 10/02/22: Re: using an FPGA to emulate a vintage computer
    145760: 10/02/22: Re: using an FPGA to emulate a vintage computer
    145793: 10/02/24: Re: using an FPGA to emulate a vintage computer
    145817: 10/02/25: Re: using an FPGA to emulate a vintage computer
    145845: 10/02/25: Re: using an FPGA to emulate a vintage computer
    145852: 10/02/26: Re: using an FPGA to emulate a vintage computer
    145861: 10/02/26: Re: using an FPGA to emulate a vintage computer
    145885: 10/02/26: Re: using an FPGA to emulate a vintage computer
    146050: 10/03/04: Re: using an FPGA to emulate a vintage computer
    146111: 10/03/05: Re: using an FPGA to emulate a vintage computer
    146112: 10/03/05: Re: using an FPGA to emulate a vintage computer
    146113: 10/03/05: Re: FSM in BlockRAM
    146126: 10/03/06: Re: using an FPGA to emulate a vintage computer
    146142: 10/03/06: Re: FSM in BlockRAM
    146154: 10/03/07: Re: using an FPGA to emulate a vintage computer
    146183: 10/03/07: Re: using an FPGA to emulate a vintage computer
    146251: 10/03/10: Re: Modelsim PE vs. Aldec Active-HDL (PE)
    146274: 10/03/10: Re: Why doesn't this situation generate a latch?
    146278: 10/03/10: Re: Why doesn't this situation generate a latch?
    146325: 10/03/12: Re: Comparing FPGA with ASIC implementations
    146392: 10/03/15: Re: Awkward Arithmetic
    146520: 10/03/21: Re: Digilent Nexys2 board
    146542: 10/03/22: Re: Finally, selling my old Xilinx/Viewlogic software package
    146543: 10/03/22: Re: Finally, selling my old Xilinx/Viewlogic software package
    146544: 10/03/22: Re: Finally, selling my old Xilinx/Viewlogic software package
    146644: 10/03/25: Re: Ring Oscillator -> counter differences
    146664: 10/03/25: Re: EMC discussion
    146668: 10/03/25: Re: EMC discussion
    146676: 10/03/25: Re: EMC discussion
    146688: 10/03/26: Re: EMC discussion
    146689: 10/03/26: Re: Newbie Coding Question
    146698: 10/03/26: Re: baud rates etc
    146716: 10/03/26: Re: Ring Oscillator -> counter differences
    146718: 10/03/26: Re: Newbie Coding Question
    146719: 10/03/26: Re: baud rates etc
    146727: 10/03/26: Re: Any advice on which is the best book on CMOS digital circuit ?design?
    146728: 10/03/26: Re: EMC discussion
    146741: 10/03/27: Re: Multipliers in CoolRunner Series?
    146752: 10/03/27: Re: Multipliers in CoolRunner Series?
    146756: 10/03/27: Re: Multipliers in CoolRunner Series?
    146830: 10/03/29: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
    146868: 10/03/30: Re: Which is the most beautiful and memorable hardware structure in a CPU?
    146883: 10/03/31: Re: Which is the most beautiful and memorable hardware structure in a CPU?
    146907: 10/04/01: Re: Which is the most beautiful and memorable hardware structure in a CPU?
    146914: 10/04/01: Re: Predefined MACRO's in XST v11.5
    146923: 10/04/02: Re: Which is the most beautiful and memorable hardware structure in a CPU?
    146948: 10/04/03: Re: Which is the most beautiful and memorable hardware structure in a ?CPU?
    146949: 10/04/03: Re: Is there a way to implement division by variables other than 2 in single clock with XST ?
    146952: 10/04/03: Re: Is there a way to implement division by variables other than 2 in ?single clock with XST ?
    147025: 10/04/09: Re: I'd rather switch than fight!
    147093: 10/04/14: Re: Read from the compact flash
    147098: 10/04/14: Re: Implementing bidirectional bus inside the FPGA
    147102: 10/04/14: Re: Read from the compact flash
    147106: 10/04/14: Re: Implementing bidirectional bus inside the FPGA
    147119: 10/04/14: Re: Read from the compact flash
    147124: 10/04/14: Re: Read from the compact flash
    147131: 10/04/15: Re: I'd rather switch than fight!
    147177: 10/04/16: Re: I'd rather switch than fight!
    147179: 10/04/16: Re: I'd rather switch than fight!
    147199: 10/04/17: Re: I'd rather switch than fight!
    147248: 10/04/20: Re: I'd rather switch than fight!
    147259: 10/04/21: Re: I'd rather switch than fight!
    147282: 10/04/22: Re: Quartus II under Windows7?
    147285: 10/04/22: Re: Absolute value of a two's complement number
    147292: 10/04/22: Re: Absolute value of a two's complement number
    147350: 10/04/23: Re: Quartus II under Windows7?
    147411: 10/04/26: Re: Inferring mutipliers
    147418: 10/04/26: Re: Booting Linux from my own bootloader
    147420: 10/04/26: Re: Quartus II under Windows7?
    147446: 10/04/27: Re: Booting Linux from my own bootloader
    147582: 10/05/05: Re: FIFO Depth Calculation
    147592: 10/05/05: Re: FIFO Depth Calculation
    147593: 10/05/05: Re: FIFO Depth Calculation
    147618: 10/05/08: Re: Floating Point Division
    147787: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
    147792: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
    147797: 10/05/25: Re: mux behavior
    147806: 10/05/25: Re: mux behavior
    147820: 10/05/25: Re: Advice on Xilinx Spelunking
    147897: 10/05/31: Re: Effect of fanout on route delay (Spartan3)
    147927: 10/06/02: Re: Job experience? How?
    147970: 10/06/09: Re: How to Disable IP Core after Evaluation Period
    147976: 10/06/09: Re: How to Disable IP Core after Evaluation Period
    147982: 10/06/09: Re: How to Disable IP Core after Evaluation Period
    148011: 10/06/14: Re: Altera Quartus - how to create small roms & rams for Cyclone 3
    148170: 10/06/25: Re: fooling the compiler
    148197: 10/06/26: Re: Free bitmap font
    148208: 10/06/29: Re: Using Xilinx TFT controller IP for normal VGA port on Spartan 3E 1600 ?starter Kit
    148238: 10/07/01: Re: Xilinx xapp175, empty + full flag really synchronous?
    148257: 10/07/02: Re: SPI Flash configuration and data access rate
    148265: 10/07/02: Re: SPI Flash configuration and data access rate
    148270: 10/07/03: Re: carrier tracking over zero frequency point
    148286: 10/07/05: Re: xilinx leadtimes
    148392: 10/07/17: Re: HDL float to string (sprintf %.3E)?
    148567: 10/08/02: Re: DMA operation to 64-bits PC platform (continued)
    148680: 10/08/17: Re: Getting started with FPGA
    148726: 10/08/18: Re: Getting started with FPGA
    148732: 10/08/18: Re: FPGA PCI BOARD .. Few Questions
    148793: 10/08/24: Re: Text compression Huffman Encoder and Decoder
    148832: 10/09/01: Re: dct verilog
    148889: 10/09/08: Re: Divide clock by 4/5 in Spartan 3A?
    148903: 10/09/09: Re: Want to get into FPGA
    148910: 10/09/09: Re: Want to get into FPGA
    148916: 10/09/10: Re: Want to get into FPGA
    149015: 10/09/21: Re: Xilinx XST and a State Machine - A Mystery
    149055: 10/09/27: Re: FPGA For Image Processing[Economical]
    149083: 10/09/29: Re: SDRAM for specific use - performance and timing questions
    149087: 10/09/29: Re: SDRAM for specific use - performance and timing questions
    149096: 10/09/30: Re: SDRAM for specific use - performance and timing questions
    149144: 10/10/04: Re: Starting a career with FPGAs
    149441: 10/10/25: Re: 0x80000000 Integer not supported??
    149445: 10/10/25: Re: 0x80000000 Integer not supported??
    149553: 10/11/05: Re: combinatorial process not simulating correctly
    149588: 10/11/08: Re: Statemachine debugging with Chipscope
    149690: 10/11/17: Re: Signal is connected to multiple drivers
    149726: 10/11/21: Re: Huffman encoder/Decoder For Text data compression
    149737: 10/11/22: Re: Network stack on Xilinx, Alterra ?
    149771: 10/11/23: Re: Synthesis/place and route with Solid-State Drives
    149797: 10/11/24: Re: minimum clock period of a combinational circuit
    149834: 10/11/25: Re: Multiple clock domains
    149865: 10/11/30: Re: Multiple clock domains
    149916: 10/12/02: Re: Brain Cramps...
    149934: 10/12/02: Re: Help help help on Huffman Encoder
    149979: 10/12/04: Re: Concurrent Logic Timing
    150020: 10/12/06: Re: FSM single process...BIG question
    150285: 11/01/08: Re: OT: Fast Circuits
    150298: 11/01/08: Re: OT: Fast Circuits
    150302: 11/01/09: Re: OT: Fast Circuits
    150334: 11/01/10: Re: FPGA to PHY/MAC chip
    150354: 11/01/11: Re: FPGA to PHY/MAC chip
    150355: 11/01/11: Re: deconvolution
    150361: 11/01/12: Re: FPGA to PHY/MAC chip
    150401: 11/01/16: Re: Location constraints questions
    150403: 11/01/16: Re: Location constraints questions
    150405: 11/01/17: Re: Location constraints questions
    150425: 11/01/20: Re: Overview for non-technicals.
    150427: 11/01/20: Re: Overview for non-technicals.
    150435: 11/01/20: Re: Overview for non-technicals.
    150444: 11/01/21: Re: Overview for non-technicals.
    150607: 11/01/27: Re: tft lcd with xilinx fpga
    150614: 11/01/28: Re: How to place some delay blocks adjacent to each other after Xilinx ISE P&R tool?
    150707: 11/02/04: Re: Trivia: Where are you on the HDL Map?
    150708: 11/02/04: Re: FPGA pin re-configuration
    150805: 11/02/14: Re: Simple clock question
    150816: 11/02/14: Re: why an FSM is not a counter?!
    150857: 11/02/16: Re: PLD suggestions for classroom use
    150858: 11/02/16: Re: PLD suggestions for classroom use
    150862: 11/02/16: Re: PLD suggestions for classroom use
    150883: 11/02/19: Re: Mathematical definition of an FPGA
    150940: 11/02/24: Re: How to keep iSE from grounding pins
    151005: 11/02/28: Re: Question regarding bitstream generation
    151007: 11/02/28: Re: Nanosecond pulse generator using Spartan-3E
    151011: 11/02/28: Re: Simulating mutiplication of 'X' with '0'
    151039: 11/03/02: Re: Count bits in VHDL, with loop and unrolled loop produces different results
    151043: 11/03/02: Re: Count bits in VHDL, with loop and unrolled loop produces different results
    151055: 11/03/02: Re: Count bits in VHDL, with loop and unrolled loop produces different results
    151059: 11/03/02: Re: Count bits in VHDL, with loop and unrolled loop produces different results
    151063: 11/03/03: Re: Count bits in VHDL, with loop and unrolled loop produces different results
    151073: 11/03/03: Re: Count bits in VHDL, with loop and unrolled loop produces different results
    151096: 11/03/06: Re: IP Core Delivery Format Info
    151144: 11/03/11: Re: Nanosecond pulse generator using Spartan-3E
    151166: 11/03/12: Re: pcb&bitstream
    151195: 11/03/15: Re: pcb&bitstream
    151196: 11/03/15: Re: pcb&bitstream
    151198: 11/03/15: Re: pcb&bitstream
    151203: 11/03/15: Re: pcb&bitstream
    151231: 11/03/16: Re: pcb&bitstream
    151232: 11/03/16: Re: pcb&bitstream
    151233: 11/03/16: Re: pcb&bitstream
    151247: 11/03/17: Re: Regfile access
    151255: 11/03/18: Re: pcb&bitstream
    151279: 11/03/20: Re: pcb&bitstream
    151295: 11/03/21: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
    151299: 11/03/21: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
    151305: 11/03/22: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
    151307: 11/03/22: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
    151320: 11/03/22: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
    151321: 11/03/22: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
    151329: 11/03/23: Re: pcb&bitstream
    151331: 11/03/23: Re: pcb&bitstream
    151464: 11/04/12: Re: Source of Dynamic Power Consumption in FPGAs
    151472: 11/04/12: Re: Source of Dynamic Power Consumption in FPGAs
    151479: 11/04/12: Re: Source of Dynamic Power Consumption in FPGAs
    151483: 11/04/12: Re: Source of Dynamic Power Consumption in FPGAs
    151719: 11/05/09: Re: fpga
    151821: 11/05/21: Re: Can a glitch-free mux be designed in an FPGA?
    151841: 11/05/23: Re: comparator fast implementation
    151893: 11/06/02: Re: FFT using logic gates only
    151904: 11/06/02: Re: Microblaze and PowerPC
    151905: 11/06/02: Re: How could I get LUT-level netlist in Xilinx ISE?
    151941: 11/06/11: Re: Area Optimization
    151954: 11/06/14: Re: Area Optimization
    151970: 11/06/15: Re: Area Optimization
    151975: 11/06/16: Re: Area Optimization
    152224: 11/07/22: Re: Post-map simulation: timing violation and delays
    152285: 11/08/03: Re: Regarding process time calculation
    152295: 11/08/04: Re: Regarding process time calculation
    152303: 11/08/05: Re: Regarding process time calculation
    152318: 11/08/08: Re: Newbie PCB
    152321: 11/08/08: Re: Newbie PCB
    152325: 11/08/09: Re: ISE bug?
    152327: 11/08/09: Re: LUT glitches (was Re: ISE bug?)
    152329: 11/08/09: Re: LUT glitches (was Re: ISE bug?)
    152341: 11/08/10: Re: Xilinx Coregen, command not found java error
    152349: 11/08/11: Re: Is there a utility to peek and poke PCIe devices
    152358: 11/08/11: Re: to sell: Nallatech H101-PCIXM PCI-X FPGA Accelerator Card (used)
    152359: 11/08/11: Re: Help needed to emulate a microcontroller.
    152380: 11/08/17: Re: extracting D from 1 / D*D
    152385: 11/08/17: Re: extracting D from 1 / D*D
    152392: 11/08/18: Re: extracting D from 1 / D*D
    152400: 11/08/18: Re: extracting D from 1 / D*D
    152433: 11/08/22: Re: MAXDELAY constraint
    152504: 11/08/29: Re: Boundary scan
    152552: 11/09/14: Re: FPGA acceleration v.s. GPU acceleration
    152556: 11/09/14: Re: The Manifest Destiny of Computer Architectures
    152573: 11/09/15: Re: The Manifest Destiny of Computer Architectures
    152617: 11/09/19: Re: The Manifest Destiny of Computer Architectures
    152658: 11/09/24: Re: Registers at I/O
    152662: 11/09/24: Re: Registers at I/O
    152676: 11/09/26: Re: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA (EP4CE22F17C6N) apples to apples.
    152706: 11/10/04: Re: FPGA acceleration v.s. GPU acceleration
    152729: 11/10/13: Re: Spartan changes in glitch sensitivity
    152736: 11/10/15: Re: Spartan changes in glitch sensitivity
    152746: 11/10/17: Re: Doulos training courses at Xilinx
    152749: 11/10/18: Re: Doulos training courses at Xilinx
    152800: 11/10/24: Re: Spartan changes in glitch sensitivity
    152802: 11/10/24: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152812: 11/10/25: Re: FPGA functional flow..please help!
    152840: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152841: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152844: 11/10/27: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152850: 11/10/27: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152855: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152870: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152883: 11/10/29: Re: FPGA development
    152884: 11/10/29: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152912: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152919: 11/11/01: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152933: 11/11/02: Re: draw lines, circles, squares on FPGA by mouse and display on VGA ( not use NIOS)
    152983: 11/11/07: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152986: 11/11/07: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152999: 11/11/10: Re: ASIC design job vs FPGA design job
    153002: 11/11/10: Re: ASIC design job vs FPGA design job
    153005: 11/11/10: Re: ASIC design job vs FPGA design job
    153073: 11/11/25: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    153145: 11/12/12: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
    153149: 11/12/13: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
    153154: 11/12/13: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
    153163: 11/12/21: Re: Clock distribution for ADC and jitter
    153184: 12/01/04: Re: Beginner question on FIFO in "FPGA prototyping by VHDL examples"
    153186: 12/01/05: Re: Beginner question on FIFO in "FPGA prototyping by VHDL examples"
    153193: 12/01/06: Re: Handling overflow in a self-repeating frequency counter
    153197: 12/01/06: Re: Handling overflow in a self-repeating frequency counter
    153205: 12/01/06: Re: Handling overflow in a self-repeating frequency counter
    153206: 12/01/06: Re: Handling overflow in a self-repeating frequency counter
    153209: 12/01/07: Re: Handling overflow in a self-repeating frequency counter
    153215: 12/01/08: Re: voltage drop on STRATIX FPGA supply planes
    153235: 12/01/15: Re: balancing IIR filter (after adding extra registers)
    153239: 12/01/16: Re: Effective square root algorithms implemented on FPGAs already
    153242: 12/01/16: Re: Effective square root algorithms implemented on FPGAs already
    153243: 12/01/16: Re: Effective square root algorithms implemented on FPGAs already
    153279: 12/01/25: Re: slow edge on clk inputs
    153312: 12/01/30: Re: Design Notation VHDL or Verilog?
    153314: 12/01/30: Re: Design Notation VHDL or Verilog?
    153329: 12/02/01: Re: Design Notation VHDL or Verilog?
    153337: 12/02/02: Re: Design Notation VHDL or Verilog?
    153399: 12/02/16: Re: LUT6 FPGAs and Carry Logic
    153402: 12/02/16: Re: LUT6 FPGAs and Carry Logic
    153405: 12/02/17: Re: LUT6 FPGAs and Carry Logic
    153407: 12/02/17: Re: LUT6 FPGAs and Carry Logic
    153436: 12/02/24: Re: What is a PLD/FPGA with serial or Ethernet port logic or block built in
    153438: 12/02/24: Re: What is a PLD/FPGA with serial or Ethernet port logic or block built in
    153441: 12/02/25: Re: What is a PLD/FPGA with serial or Ethernet port logic or block built in
    153467: 12/03/03: Re: Migrating Spartan2 design (xnf)
    153472: 12/03/06: Re: FPGA Area
    153495: 12/03/13: Re: Internal BUS design: MUX or OR-GATE?
    153498: 12/03/14: Re: Internal BUS design: MUX or OR-GATE?
    153500: 12/03/15: Re: Internal BUS design: MUX or OR-GATE?
    153530: 12/03/25: Re: Digital Tachometer VHDL
    153536: 12/03/26: Re: Spartan 3A counter speed ?
    153576: 12/03/30: Re: Spartan 3A counter speed ?
    153585: 12/04/02: Re: Low latency FPGA options
    153591: 12/04/03: Re: Expectations from newly minted EE?
    153592: 12/04/03: Re: Expectations from newly minted EE?
    153599: 12/04/03: Re: Expectations from newly minted EE?
    153600: 12/04/03: Re: Expectations from newly minted EE?
    153605: 12/04/03: Re: Expectations from newly minted EE?
    153611: 12/04/04: Re: Very poor Xilinx experience
    153615: 12/04/05: Re: Very poor Xilinx experience
    153640: 12/04/09: Re: Best FPGA for algorithmic acceleration
    153647: 12/04/09: Re: Best FPGA for algorithmic acceleration
    153650: 12/04/10: Re: Best FPGA for algorithmic acceleration
    153726: 12/05/01: Re: Smallest GPL UART
    153730: 12/05/02: Re: Smallest GPL UART
    153745: 12/05/04: Re: Smallest GPL UART
    153759: 12/05/16: Re: Synthesis Problem
    153763: 12/05/16: Re: Synthesis Problem
    153777: 12/05/17: Re: Smallest GPL UART
    153799: 12/05/24: Re: Logic Glitches in Spartan-3?
    153804: 12/05/24: Re: Logic Glitches in Spartan-3?
    153807: 12/05/24: Re: Logic Glitches in Spartan-3?
    153811: 12/05/24: Re: Logic Glitches in Spartan-3?
    153837: 12/06/01: Re: PRNG
    153843: 12/06/01: Re: PRNG
    153851: 12/06/05: Re: PRNG
    153860: 12/06/08: Re: FPGA Interconnect
    153904: 12/06/28: Re: The definition of comnatorial prcess?
    153908: 12/06/29: Re: The definition of comnatorial prcess?
    153919: 12/06/29: Re: Replacement for XC4005E
    153931: 12/07/01: Re: The definition of comnatorial prcess?
    153933: 12/07/01: Re: The definition of comnatorial prcess?
    153940: 12/07/01: Re: The definition of comnatorial prcess?
    153942: 12/07/01: Re: The definition of comnatorial prcess?
    153986: 12/07/09: Re: The definition of comnatorial prcess?
    153987: 12/07/09: Re: accumulator (again)
    153988: 12/07/09: Re: accumulator (again)
    153989: 12/07/09: Re: accumulator (again)
    153990: 12/07/09: Re: accumulator (again)
    153991: 12/07/09: Re: accumulator (again)
    153999: 12/07/10: Re: The definition of comnatorial prcess?
    154000: 12/07/10: Re: accumulator (again)
    154002: 12/07/10: Re: accumulator (again)
    154005: 12/07/10: Re: accumulator (again)
    154014: 12/07/11: Re: Completely puzzled: Strange shift register behaviour
    154018: 12/07/12: Re: Completely puzzled: Strange shift register behaviour
    154028: 12/07/13: Re: Completely puzzled: Strange shift register behaviour
    154029: 12/07/13: Re: Completely puzzled: Strange shift register behaviour
    154031: 12/07/13: Re: Completely puzzled: Strange shift register behaviour
    154068: 12/07/26: Re: Strange behavior with counter (decreases instead of increasing)
    154080: 12/07/31: Re: 3 to 1 mux with 4 bit inputs
    154128: 12/08/15: Re: "Decimals" word in binary space
    154130: 12/08/15: Re: "Decimals" word in binary space
    154142: 12/08/20: Re: "Decimals" word in binary space
    154172: 12/08/27: Re: recruit FPGA design engineer in Scotland
    154182: 12/08/29: Re: Simulating fixed point multiplica???tion using floating point core v5.0 on Virtex-6 LX75T ISE 13.4
    154184: 12/08/30: Re: General Build Question
    154229: 12/09/11: Re: New(?) fast binary counter for FPGAs without carry logic (e.g. Actel) -- Request For Comment
    154231: 12/09/11: Re: New(?) fast binary counter for FPGAs without carry logic (e.g. Actel) -- Request For Comment
    154233: 12/09/11: Re: New(?) fast binary counter for FPGAs without carry logic (e.g. Actel) -- Request For Comment
    154234: 12/09/11: Re: New(?) fast binary counter for FPGAs without carry logic (e.g. Actel) -- Request For Comment
    154261: 12/09/19: Re: Global Reset using Global Buffer
    154266: 12/09/19: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
    154272: 12/09/19: Re: Global Reset using Global Buffer
    154286: 12/09/23: Re: How to estimate PEAK power consumption on Xilinx FPGA ?
    154293: 12/09/24: Re: multi-source errors
    154335: 12/10/03: Re: fft in fpga using polar form
    154336: 12/10/03: Trigonometry in degrees, was: fft in fpga using polar form
    154346: 12/10/11: Re: Spartan 6 MCB refresh timing
    154358: 12/10/14: Re: My First CPU but.. one problem
    154405: 12/10/26: Re: production life of Spartan3A ?
    154418: 12/10/28: Re: Altera delivery
    154421: 12/10/28: Re: Altera delivery
    154425: 12/10/29: Re: TMDS CML PCB
    154432: 12/10/29: Re: Using LVDS Input for Delta Sigma ADC
    154450: 12/11/04: Re: help
    154490: 12/11/18: Re: question about verilog ?, :
    154493: 12/11/18: Re: question about verilog ?, :
    154496: 12/11/19: Re: A total beginner, wondering about determining hardware specs. requirements
    154511: 12/11/22: Re: Set-up and hold times and metastability
    154518: 12/11/22: Re: Set-up and hold times and metastability
    154527: 12/11/23: Re: Set-up and hold times and metastability
    154528: 12/11/23: Re: Set-up and hold times and metastability
    154529: 12/11/23: Re: Set-up and hold times and metastability
    154530: 12/11/23: Re: Set-up and hold times and metastability
    154586: 12/11/30: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
    154589: 12/11/30: Re: VHDL expert puzzle
    154590: 12/11/30: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
    154600: 12/11/30: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
    154613: 12/12/01: Re: VHDL expert puzzle
    154621: 12/12/02: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
    154625: 12/12/03: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
    154658: 12/12/13: Re: MII SFD Detection with Shematics
    154666: 12/12/14: Re: MII SFD Detection with Shematics
    154687: 12/12/17: Re: DC fifo behaviour at underflow/overflow
    154701: 12/12/20: Re: USB power and debug signals on micro USB connector
    154717: 12/12/28: Re: Which to learn: Verilog vs. VHDL?
    154720: 12/12/29: Re: Which to learn: Verilog vs. VHDL?
    154743: 13/01/03: Re: Which to learn: Verilog vs. VHDL?
    154745: 13/01/03: Re: Which to learn: Verilog vs. VHDL?
    154761: 13/01/04: Re: Which to learn: Verilog vs. VHDL?
    154762: 13/01/04: Re: Chisel as alternative HDL
    154763: 13/01/04: Re: Chisel as alternative HDL
    154771: 13/01/06: Re: Chisel as alternative HDL
    154841: 13/01/17: Re: Combination loops and false paths
    154846: 13/01/18: Re: Combination loops and false paths
    154847: 13/01/18: Re: Combination loops and false paths
    154856: 13/01/19: Re: full tcp offload solution with tcp session setup/teardown support
    154859: 13/01/19: Re: full tcp offload solution with tcp session setup/teardown support
    154860: 13/01/19: Re: Combination loops and false paths
    154861: 13/01/19: Re: Combination loops and false paths
    154889: 13/01/28: Re: Sometimes I Just Don't Get the Tools
    154896: 13/02/01: Re: Combination loops and false paths
    154942: 13/02/25: Re: about the always block in verilog
    154943: 13/02/25: Re: add-compare-select
    154952: 13/03/02: Re: about the always block in verilog
    154953: 13/03/02: Re: about the always block in verilog
    155005: 13/03/26: Re: What a Xilinx fpga could do in 1988
    155010: 13/03/27: Re: What a Xilinx fpga could do in 1988
    155021: 13/03/29: Re: MISC - Stack Based vs. Register Based
    155028: 13/03/31: Re: MISC - Stack Based vs. Register Based
    155033: 13/04/02: Re: MISC - Stack Based vs. Register Based
    155038: 13/04/02: Re: MISC - Stack Based vs. Register Based
    155042: 13/04/02: Re: MISC - Stack Based vs. Register Based
    155046: 13/04/04: Re: MISC - Stack Based vs. Register Based
    155053: 13/04/04: Re: MISC - Stack Based vs. Register Based
    155054: 13/04/04: Re: MISC - Stack Based vs. Register Based
    155060: 13/04/04: Re: MISC - Stack Based vs. Register Based
    155065: 13/04/04: Re: MISC - Stack Based vs. Register Based
    155070: 13/04/05: Re: MISC - Stack Based vs. Register Based
    155078: 13/04/05: Re: MISC - Stack Based vs. Register Based
    155143: 13/04/26: Re: DEP function development on a low budget
    155185: 13/05/24: Re: Die size of BRAM/DSP48 in CLBs
    155329: 13/06/24: Re: New soft processor core paper publisher?
    155333: 13/06/24: Re: New soft processor core paper publisher?
    155335: 13/06/24: Re: New soft processor core paper publisher?
    155339: 13/06/24: Re: New soft processor core paper publisher?
    155354: 13/06/24: Re: VHDL syntheses timestamp
    155362: 13/06/24: Re: New soft processor core paper publisher?
    155373: 13/06/24: Re: New soft processor core paper publisher?
    155392: 13/06/25: Re: New soft processor core paper publisher?
    155397: 13/06/25: Re: New soft processor core paper publisher?
    155411: 13/06/25: Re: New soft processor core paper publisher?
    155413: 13/06/26: Re: New soft processor core paper publisher?
    155416: 13/06/26: Re: New soft processor core paper publisher?
    155426: 13/06/26: Re: New soft processor core paper publisher?
    155450: 13/06/29: Re: New soft processor core paper publisher?
    155479: 13/07/01: Re: New soft processor core paper publisher?
    155485: 13/07/01: Re: New soft processor core paper publisher?
    155562: 13/07/18: Re: Metastability mitigation and I/O registers
    155565: 13/07/20: Re: Metastability mitigation and I/O registers
    155601: 13/07/29: Re: serial protocol specs and verification
    155603: 13/07/29: Re: serial protocol specs and verification
    155606: 13/07/30: Re: serial protocol specs and verification
    155609: 13/07/30: Re: seperate high speed rules for HDL?
    155646: 13/07/31: Re: seperate high speed rules for HDL?
    155706: 13/08/12: Re: Is a block spoof IP filter in hardware is required
    155718: 13/08/21: Re: Cascaded floating-point reduction?
    155726: 13/08/22: Re: Cascaded floating-point reduction?
    155728: 13/08/23: Re: Cascaded floating-point reduction?
    155743: 13/08/26: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155751: 13/08/27: Re: Actel Designer Warning: CMP201: Net drives no load
    155788: 13/09/04: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155791: 13/09/05: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155795: 13/09/05: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155814: 13/09/19: Re: Legal Issues Reproducing Old CPU
    155817: 13/09/19: Re: Legal Issues Reproducing Old CPU
    155829: 13/09/27: Re: Legal Issues Reproducing Old CPU
    155874: 13/10/10: Re: Book recommendation
    155881: 13/10/11: Re: Book recommendation
    155884: 13/10/11: Re: reset strategy FPGA Igloo
    155947: 13/10/19: Re: draw lines, circles, squares on FPGA by mouse and display on VGA ( not use NIOS)
    155951: 13/10/20: Re: draw lines, circles, squares on FPGA by mouse and display on VGA ( not use NIOS)
    155969: 13/10/30: Re: draw lines, circles, squares on FPGA by mouse and display on VGA ( not use NIOS)
    155979: 13/11/02: Re: Partnership Request
    155984: 13/11/02: Re: Partnership Request
    155986: 13/11/03: Re: Partnership Request
    155989: 13/11/04: Re: Verilog Binary Division
    155991: 13/11/04: Re: Verilog Binary Division
    155992: 13/11/04: Re: Verilog Binary Division
    156000: 13/11/05: Re: Verilog Binary Division
    156002: 13/11/05: Re: Verilog Binary Division
    156097: 13/11/22: Re: Mill: FPGA version?
    156115: 13/11/27: Re: FPGA Cryptosystem
    156116: 13/11/27: Re: LCD test on Spartan 3E FPGA
    156123: 13/12/01: Re: Use of hardware adders with long words to perform multiple additions in parallel
    156133: 13/12/07: Re: Implementing multiple interrupts
    156134: 13/12/07: Re: Implementing multiple interrupts
    156150: 13/12/19: Re: ppc405 communication with custom ip ml403
    156154: 13/12/23: Re: Use of latches in FSMs
    156164: 14/01/03: Re: Optimising pin allocation
    156172: 14/01/06: Re: register naming
    156176: 14/01/08: Re: addsubs on FPGA
    156179: 14/01/09: Re: addsubs on FPGA
    156184: 14/01/10: Re: addsubs on FPGA
    156186: 14/01/10: Re: addsubs on FPGA
    156187: 14/01/10: Re: addsubs on FPGA
    156193: 14/01/14: Re: Verilog, combinational logic and modules?
    156200: 14/01/17: Re: Math is hard
    156207: 14/01/17: Re: Math is hard
    156214: 14/01/17: Re: Math is hard
    156244: 14/01/21: Re: embedded RAM vs. registers
    156245: 14/01/21: Re: Math is hard
    156247: 14/01/21: Re: Math is hard
    156259: 14/01/25: Re: embedded RAM vs. registers
    156270: 14/02/01: Re: Verilog (Xilinx): Virtual tristate or muxes?
    156274: 14/02/03: Re: Verilog (Xilinx): Virtual tristate or muxes?
    156294: 14/02/10: Re: How to synchronize register bank used in the IP Core
    156307: 14/02/13: Re: Monostable multivibrator
    156341: 14/03/11: Re: Ball-park price of Xilinx Virtex 7 FPGA?
    156345: 14/03/11: Re: Ball-park price of Xilinx Virtex 7 FPGA?
    156358: 14/03/17: Re: [cross-post]path verification
    156432: 14/04/05: Re: Tristates in synthesis
    156436: 14/04/06: Re: Tristates in synthesis
    156437: 14/04/06: Re: Tristates in synthesis
    156464: 14/04/08: Re: on-chip bypass caps
    156485: 14/04/09: Re: on-chip bypass caps
    156509: 14/04/13: Re: on-chip bypass caps
    156620: 14/05/14: Re: Undriven outputs of a module in Quartus II Synthesis
    156689: 14/06/04: Re: ECG signals Compression/Decompression
    156690: 14/06/04: Re: Partial Reconfiguration clock enable problem
    156693: 14/06/04: Re: ECG signals Compression/Decompression
    156700: 14/06/05: Re: ECG signals Compression/Decompression
    156701: 14/06/05: Re: ECG signals Compression/Decompression
    156704: 14/06/06: Re: ECG signals Compression/Decompression
    156709: 14/06/06: Re: ECG signals Compression/Decompression
    156713: 14/06/06: Re: ECG signals Compression/Decompression
    156714: 14/06/06: Re: ECG signals Compression/Decompression
    156721: 14/06/08: Re: HELP: Edge triggering of mode register, Verilog
    156736: 14/06/09: Re: 22V10 programmer
    156762: 14/06/19: Re: PLA? PAL? PLD? GAL?
    156774: 14/06/24: Re: PLA? PAL? PLD? GAL?
    156775: 14/06/24: Re: A new domain for FPGAs ? Function approximation
    156785: 14/06/25: Re: problem with xc3s400 place and rout section
    156788: 14/06/25: Re: problem with xc3s400 place and rout section
    156804: 14/07/03: Re: Transistor count
    156872: 14/07/15: Re: Help with Address load logic
    156891: 14/07/22: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
    156933: 14/07/29: Re: Primitive debuggable UART interface to a Nios within a multi-Nios system
    156948: 14/08/01: Re: floating point synthesis on Xilinx FPGAs using ISE Webpack
    156952: 14/08/03: Re: Could you give me an example on synthesis techniques?
    156981: 14/08/10: Re: Basic question: sequence of execution within FPGAs
    156985: 14/08/11: Re: LVDS problem - Black magic anyone?
    157030: 14/09/03: Re: Know any good public FPGA projects to contribute to?
    157052: 14/09/17: Re: Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification
    157054: 14/09/17: NetCPU or DotNetCPU DB200 anyone?
    157056: 14/09/17: Re: NetCPU or DotNetCPU DB200 anyone?
    157062: 14/09/19: Re: NetCPU or DotNetCPU DB200 anyone?
    157078: 14/09/23: Re: Some newbe questions.
    157089: 14/10/09: Re: looking for systemC/TLM 2.0 courses
    157110: 14/10/13: Re: Need ideas for FYP
    157125: 14/10/15: Re: Need ideas for FYP
    157128: 14/10/16: Re: Need ideas for FYP
    157131: 14/10/16: Re: Need ideas for FYP
    157134: 14/10/16: Re: Need ideas for FYP
    157157: 14/10/20: Re: Need ideas for FYP
    157220: 14/11/05: Re: practical experience with GPL IP core in commercial product
    157242: 14/11/06: Re: practical experience with GPL IP core in commercial product
    157267: 14/11/10: Re: practical experience with GPL IP core in commercial product
    157274: 14/11/13: Re: practical experience with GPL IP core in commercial product
    157287: 14/11/17: Re: disadvantages of inferring latches
    157288: 14/11/17: Re: disadvantages of inferring latches
    157295: 14/11/17: Re: disadvantages of inferring latches
    157298: 14/11/18: Re: disadvantages of inferring latches
    157301: 14/11/18: Re: disadvantages of inferring latches
    157303: 14/11/18: Re: disadvantages of inferring latches
    157306: 14/11/18: Re: disadvantages of inferring latches
    157329: 14/11/23: Re: disadvantages of inferring latches
    157338: 14/11/24: Re: Bypass Xilinx flexlm license check
    157372: 14/12/02: Re: Which Altera to buy?
    157382: 14/12/02: Re: Which Altera to buy?
    157439: 14/12/10: Re: VHDL Synchronization- two stage FF on all inputs?
    157451: 14/12/11: Re: VHDL Synchronization- two stage FF on all inputs?
    157455: 14/12/11: Re: VHDL Synchronization- two stage FF on all inputs?
    157479: 14/12/12: Re: VHDL Synchronization- two stage FF on all inputs?
    157480: 14/12/12: Re: Using FPGA to feed 80386
    157515: 14/12/15: Re: Using FPGA to feed 80386
    157593: 14/12/22: Re: How to automatically allocate multiple bit fields into constant length registers?
    157605: 14/12/28: Re: Prime number in verilog
    157618: 15/01/06: Re: Parallel execution of Systemc code
    157655: 15/01/21: Re: [RANT] XILINX, Are you freaking kidding me ?
    157673: 15/01/23: RS Flip-flops, was: Send a pulse across clocks
    157740: 15/02/26: Re: Program Xilinx with Altera JTAG Programmer?
    157804: 15/03/30: Re: Interpret a VHDL statement within a serial to paralell port
    157842: 15/04/16: Re: Division by a constant
    157846: 15/04/17: Re: Division by a constant
    157875: 15/05/02: Re: Spartan-3 stater kit
    157888: 15/05/11: Re: ZYNQ temperature
    157900: 15/05/12: Re: 16->5 "Sort"
    157903: 15/05/12: Re: 16->5 "Sort"
    157905: 15/05/12: Re: 16->5 "Sort"
    157946: 15/05/20: Re: AHDL VS. VHDL
    157965: 15/06/06: Re: Is it possible to have a parameterized verilog module name in verilog or systemverilog?
    157993: 15/06/22: Re: Conditional Interpretation of VHDL
    157996: 15/06/22: Re: Conditional Interpretation of VHDL
    158000: 15/06/23: Re: Conditional Interpretation of VHDL
    158002: 15/06/24: Re: Conditional Interpretation of VHDL
    158006: 15/06/24: Re: Conditional Interpretation of VHDL
    158015: 15/07/05: Re: What's the name of this circuit?
    158024: 15/07/10: Re: Dynamic Array in VHDL
    158026: 15/07/10: Re: Distributed ram timing qurry
    158029: 15/07/10: Re: Distributed ram timing qurry
    158066: 15/07/30: Re: fifo or sdram bug?
    158068: 15/07/30: Re: fifo or sdram bug?
    158091: 15/08/05: Re: Finally! A Completely Open Complete FPGA Toolchain
    158093: 15/08/06: Re: Finally! A Completely Open Complete FPGA Toolchain
    158106: 15/08/10: Re: Finally! A Completely Open Complete FPGA Toolchain
    158182: 15/09/11: Re: Why is this group so quiet?
    158186: 15/09/12: Re: Why is this group so quiet?
    158187: 15/09/12: Re: low-level vs. high-level
    158192: 15/09/12: Re: low-level vs. high-level
    158196: 15/09/12: Re: low-level vs. high-level
    158197: 15/09/12: Re: low-level vs. high-level
    158199: 15/09/13: Re: low-level vs. high-level
    158202: 15/09/13: Re: low-level vs. high-level
    158203: 15/09/13: Re: low-level vs. high-level
    158206: 15/09/13: Re: low-level vs. high-level
    158247: 15/09/29: Re: Automatic latency balancing in VHDL-implemented complex pipelined systems
    158254: 15/09/29: Re: Automatic latency balancing in VHDL-implemented complex pipelined systems
    158307: 15/10/08: Re: Custom FPGA routing
    158316: 15/10/20: Re: Sum of 8 numbers in FPGA
    158320: 15/10/20: Re: Sum of 8 numbers in FPGA
    158325: 15/10/22: Re: Sum of 8 numbers in FPGA
    158339: 15/10/22: Re: DC Blocker
    158373: 15/10/25: Re: Found: an FPGA with internal tri-states
    158374: 15/10/25: Re: ML405 Xilinx ISE 14.7
    158389: 15/10/27: Re: Found: an FPGA with internal tri-states
    158446: 15/11/30: Re: Simulation vs Synthesis
    158447: 15/11/30: Re: Simulation vs Synthesis
    158448: 15/11/30: Re: Simulation vs Synthesis
    158470: 15/12/02: Re: Simulation vs Synthesis
    158471: 15/12/02: Re: Simulation vs Synthesis
    158472: 15/12/02: Re: Simulation vs Synthesis
    158489: 15/12/03: Re: Simulation vs Synthesis
    158490: 15/12/03: Re: Simulation vs Synthesis
    158496: 15/12/03: Re: Simulation vs Synthesis
    158497: 15/12/03: Re: Simulation vs Synthesis
Glen Herrmannsfeldt:
    52781: 03/02/21: Re: end-around-carry
    53191: 03/03/06: Re: Square root implementation
    53411: 03/03/13: Re: Help understanding 7408 and gate chip
    53557: 03/03/16: Re: write a single byte in to DRAM
    53558: 03/03/16: Re: Help understanding 7408 and gate chip
    53559: 03/03/16: Re: blockram optimized away
    53697: 03/03/20: Re: Help understanding 7408 and gate chip
    53699: 03/03/20: Re: write a single byte in to DRAM
    53700: 03/03/20: Re: Conversion of Xilinx bit file
    53701: 03/03/20: Re: Increased Wafer yield by row adjusted placement
    53767: 03/03/22: Re: FPGA FFT Questions
    53768: 03/03/22: Re: Using FPGAs as coprocessors in a PC
    53778: 03/03/22: Re: FPGA FFT Questions
    53876: 03/03/26: Re: FPGA specs
    53896: 03/03/26: Re: How to avoid this Latch
    53934: 03/03/27: Re: FPGA specs
    53968: 03/03/28: Re: XILINX FPGA as SUN Sparc coprocessor
    54249: 03/04/05: Re: More FFT Questions
    54830: 03/04/19: Re: LFSR MAXIMUM LENGTH
    55083: 03/04/25: Re: Altera Flex 8K not holding configuration after power down.
    55292: 03/05/02: Re: Thermal Data for Logic Devices
    55323: 03/05/04: Re: Thermal Data for Logic Devices
    55396: 03/05/06: Re: Thermal Data for Logic Devices
    55778: 03/05/19: Re: smallest embedded cpu....and the most pain?
    55780: 03/05/19: Re: Output switching time
    56242: 03/06/01: Re: power consumption in CMOS..
    56267: 03/06/02: Re: power consumption in CMOS..
    56459: 03/06/05: Re: power consumption in CMOS..
    56740: 03/06/13: Re: How to Capture a VGA display EXTERNALLY
    56757: 03/06/13: Re: Problem with tristate-inout-pins of PS/2-Host
    56758: 03/06/13: Re: Power consumed in a non configured FPGA?
    56860: 03/06/17: Re: Logic removal
    57534: 03/07/02: Re: How to get 27MHz from 10 MHz in FPGA???
    57542: 03/07/02: Re: 48bit adder won't fit
    57562: 03/07/02: Re: ASIC divider in FPGA?
    57563: 03/07/02: Re: Everything need a reset?
    57564: 03/07/02: Re: Does anyone know about hardware implementaions of the SVD ?
    57920: 03/07/09: Re: division
    57980: 03/07/11: Re: division
    58036: 03/07/13: Re: Graduation Day: My first 4-layer PCB
    58198: 03/07/17: Re: Digital Root circuit using tree of 4-bit CLA's with Cout fed into Cin
    58323: 03/07/21: Re: CRC questions
    58330: 03/07/21: Re: CRC questions
    58376: 03/07/22: Re: asynchronous FIFO
    58579: 03/07/27: Re: CRC questions
    58604: 03/07/28: Re: CRC questions
    58635: 03/07/30: Re: binary to BCD assistance
    58637: 03/07/30: Re: binary to BCD assistance
    58684: 03/07/30: Re: Multi Cycle path and False paths
    58690: 03/07/31: Re: binary to BCD assistance
    58758: 03/08/01: Re: Multi Cycle path and False paths
    59807: 03/08/28: Re: Thinking out loud about metastability
    59825: 03/08/29: Re: Thinking out loud about metastability
    59909: 03/09/01: Re: Thinking out loud about metastability
    59978: 03/09/03: Re: Thinking out loud about metastability
    60031: 03/09/04: Re: Thinking out loud about metastability
    60038: 03/09/04: Re: Thinking out loud about metastability
    60066: 03/09/04: Re: New to FPGA, seeking advice
    60072: 03/09/04: Re: New to FPGA, seeking advice
    60095: 03/09/05: Re: New to FPGA, seeking advice
    60275: 03/09/09: Re: pipelined divider
    60327: 03/09/10: Re: pipelined divider
    60343: 03/09/11: Re: Crystal Input to FPGA
    60394: 03/09/12: Re: pipelined divider
    60395: 03/09/12: Re: Crystal Input to FPGA
    60410: 03/09/12: Re: pipelined divider
    60668: 03/09/19: Re: divide by on spartan3?
    60794: 03/09/22: Re: Transistor count
    60795: 03/09/22: Re: Synchronous counter enable pulse length
    60802: 03/09/23: Re: Synchronous counter enable pulse length
    60803: 03/09/23: Re: Synchronous counter enable pulse length
    60812: 03/09/23: Re: Synchronous counter enable pulse length
    60874: 03/09/24: Re: Synchronous counter enable pulse length
    60899: 03/09/24: Re: Synchronous counter enable pulse length
    60911: 03/09/24: Re: Synchronous counter enable pulse length
    60949: 03/09/25: Re: Synchronous Binary counter question.
    61063: 03/09/26: Re: FPGA implementation of a lexer and parser - feasible?
    61093: 03/09/27: Re: FPGA implementation of a lexer and parser - feasible?
    61135: 03/09/29: Re: Counting ones
    61169: 03/09/29: Re: Counting ones
    61991: 03/10/16: Re: To our future engineers, smart and otherwise...
    62444: 03/10/29: Re: How to protect fpga based design against cloning?
    62458: 03/10/30: Re: How to protect fpga based design against cloning?
    62494: 03/10/30: Re: WebPACK 6.1 tutorials
    62498: 03/10/31: Re: How to protect fpga based design against cloning?
    62500: 03/10/31: Re: WebPACK 6.1 tutorials
    62516: 03/10/31: Re: How to protect fpga based design against cloning?
    62528: 03/10/31: Re: How to protect fpga based design against cloning?
    62529: 03/10/31: Re: How to protect fpga based design against cloning?
    62530: 03/10/31: Re: Floating Point support
    62550: 03/11/01: Re: Convert verilog to VHDL??
    62573: 03/11/02: Re: Using unused space on a PROM (configuration device) as an EEPROM
    62728: 03/11/06: Re: Linux and FPGA compatibility
    62767: 03/11/07: Re: Arithmetics with carry
    62800: 03/11/07: Re: Arithmetics with carry
    62819: 03/11/08: Re: Arithmetics with carry
    62952: 03/11/11: Re: Home grown CPU core legal?
    62985: 03/11/12: Re: Arithmetics with carry
    136219: 08/11/06: Re: TCP/IP 3 way handshake
    136220: 08/11/06: Re: RS-232 Bus controller design in VHDL
    136476: 08/11/18: Re: rank beginner here, need to know where to start to get RS232
    136477: 08/11/18: Re: vga interfacing for image display
    136479: 08/11/18: Re: opinion about various code generators
    136516: 08/11/19: Re: vga interfacing for image display
    136532: 08/11/20: Re: vga interfacing for image display
    136726: 08/12/03: Re: Dynamical alteration of signal path
    136782: 08/12/04: Re: Equivalent ASIC Gate Estimate
    136809: 08/12/06: Re: Invalid devices when initialising scan chain with Nexys2
    138123: 09/02/06: Re: Precedence of signal assignment in a clocked process
    138133: 09/02/06: Re: clk synchronization of reset signal
    138171: 09/02/08: Re: Is this phase accumulator trick well-known???
    138177: 09/02/08: Re: Is this phase accumulator trick well-known???
    138184: 09/02/08: Re: Is this phase accumulator trick well-known???
    138349: 09/02/16: Re: "Type of xxx is incompatible with type of yyy." typecasting
    138388: 09/02/18: Re: VHDL long elsif state machine
    138449: 09/02/23: Re: MIG 2.0 for DDR - Spartan3E
    138463: 09/02/23: Opencores DDR controller
    138470: 09/02/24: Re: Opencores DDR controller
    138479: 09/02/24: Re: Configure FPGA via PCIe
    138481: 09/02/24: Re: XST hangs on HDL Analysis
    138487: 09/02/24: Re: Opencores DDR controller
    138550: 09/02/26: Re: MIG 2.0 for DDR - Spartan3E
    138597: 09/03/01: Re: New person to CPLD programming
    138600: 09/03/01: Re: New person to CPLD programming
    138602: 09/03/01: Re: Character generator ROM and VGA controller for Spartan 3E
    138609: 09/03/01: Re: Character generator ROM and VGA controller for Spartan 3E
    138614: 09/03/02: Re: Character generator ROM and VGA controller for Spartan 3E
    138647: 09/03/02: Re: Character generator ROM and VGA controller for Spartan 3E
    138661: 09/03/03: Re: Re-synthesizing with minor changes
    138663: 09/03/03: Re: Re-synthesizing with minor changes
    138685: 09/03/04: Re: 32x32 -> 64 multiplier in virtex-5
    138708: 09/03/05: Re: writing current date to a register
    138709: 09/03/05: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
    138711: 09/03/05: Re: writing current date to a register
    138714: 09/03/05: Re: DDR access on Spartan 3E 500 Starter Kit
    138720: 09/03/05: Re: DDR access on Spartan 3E 500 Starter Kit
Glen Rosendale:
    6661: 97/06/10: Re: ATMEL 17Cxxx ISP function
<glenapp@charlotte.glenayre.com>:
    1346: 95/06/03: Glenayre Job Postings
Glenn:
    97529: 06/02/23: How to use a .coe file for rom/ram in system generator
Glenn Baddeley:
    81122: 05/03/18: Re: How much current does an LED take?
Glenn Brown:
    1924: 95/09/20: Satellite Video Conference: User Interface Strategies '96
Glenn Carl:
    5333: 97/02/07: Serial Communication Controller Design
Glenn Courtright:
    3991: 96/08/29: HELP:preserve state signal syntax in Exemplar .ctr file
Glenn Courtright 7650:
    1225: 95/05/18: Is anybody using FPGA's to do PCI interfaces?
Glenn E. Hunt:
    12694: 98/10/23: Re: Schematic entry?
Glenn Eng:
    8744: 98/01/23: Re: ALtera Devices.
    9068: 98/02/18: Re: Simulator & Synthesis Engine Comparisons
    9644: 98/03/27: Re: VHDL shareware editor?
    11234: 98/07/29: Re: TRISTATE in FPGA
    18027: 99/09/24: Re: Fineline BGAs
Glenn Fasnacht:
    6937: 97/07/10: Re: Generating Sine/Cosine digitally
Glenn Heraty:
    66251: 04/02/15: Re: Random logic verilog gate netlist generator
Glenn Jennings:
    476: 94/11/30: Bit Serial ?
Glenn Jones:
    93265: 05/12/17: Re: Avnet hav2 s3e starter kit?
glenn kubota:
    13078: 98/11/14: Xilinx Foundation vs. Altera Max Plus
    13077: 98/11/14: Xilinx Foundation vs. Altera Max Plus II
GlennH:
    57299: 03/06/27: Re: I need a commercial PCI FPGA board, please help
    68291: 04/03/31: simulation time
gliss:
    89671: 05/09/21: re:Modelsim XE, what's the latest version?
glnazar:
    142186: 09/07/28: Different behavior of FSM in same simulation
    142243: 09/07/30: Re: Different behavior of FSM in same simulation
glostec2:
    48851: 02/10/25: Re: Xilinx ISE 4.2i Student edition on Windows XP
GLOW:
    144688: 09/12/23: Re: Please help, Xilinx FIFO problem!
gm:
    137857: 09/02/01: Selecting a starter FPGA board
    137868: 09/02/01: Re: Selecting a starter FPGA board
GM:
    137954: 09/02/03: Re: Selecting a starter FPGA board
GMM50:
    77438: 05/01/06: Altera Quartus Error How to track donw.
    77467: 05/01/07: Re: Altera Quartus Error How to track donw.
    77477: 05/01/07: Re: Altera Quartus Error How to track donw.
    77519: 05/01/08: Re: Altera Quartus Error How to track donw.
    83989: 05/05/10: Re: Altera Quartus Timing Models
    84405: 05/05/18: Re: CORDIC bit-serial vs. bit-parallel
    84487: 05/05/19: Re: Jam Byte-Code Player for 8051
    84579: 05/05/21: Re: Reading the contents of a FPGA in-circuit.
    84879: 05/05/31: Re: Problems with SDRAM and Altera Cyclone
    85445: 05/06/09: Re: Motion controller design with CPLD
    85446: 05/06/09: Re: In-system configuration
    86073: 05/06/21: Re: 5 Volt tolerance - Altera
    87011: 05/07/12: Re: QII simulation annoyance
    87447: 05/07/24: Re: Fastest way to compute floating point log and exp
    88363: 05/08/16: Re: Altera NIOSII IDE problem???
    88739: 05/08/26: Altera NIOS in a Cyclone
    89644: 05/09/21: Re: FPGA's in bulk and pricing
    89645: 05/09/21: Cyclone and NIOS II
    90078: 05/10/04: Re: Altera NIOS PIO interrupt problem
    94843: 06/01/18: FPGA interface to FLASH
    94860: 06/01/18: Re: FPGA interface to FLASH
    117517: 07/04/03: Re: re-assemble bootloader for NIOS Processor
    128927: 08/02/10: Re: microblaze firmware + UART handshaking blues
    128961: 08/02/11: Re: microblaze firmware + UART handshaking blues
    129033: 08/02/13: Re: microblaze firmware + UART handshaking blues
GN:
    63682: 03/11/28: Digilent Inc.
    63703: 03/12/01: Re: Digilent Inc.
gnathita:
    96533: 06/02/06: Re: porting linux on ml403
GNEEC:
    2606: 96/01/10: Re: Career value: VHDL or Verilog?
<gnippiks@my-deja.com>:
    21731: 00/03/30: Re: New Place and Route Software for Non-Commercial Research (Academic VPR 4.30 Available)
    21780: 00/03/31: Re: Adrian Thompson's and GA work on Xilinx
    21783: 00/03/31: Re: VGA interface and VHDL
gnirre:
    149783: 10/11/24: Re: Atom 6000C perspective, anyone?
    149835: 10/11/26: Re: Atom 6000C perspective, anyone?
Gnuge:
    845: 95/03/11: Re: FPGA multi-chip modules ?
    874: 95/03/17: Re: How to partitions the design by ppr ?
    876: 95/03/18: Re: FPGA multi-chip modules ?
    877: 95/03/18: Re: Free Viewlogic design kits?
    1173: 95/05/11: Re: Compression algo's for FPGA's
    1432: 95/06/22: Re: XNF (XC2018) to ABEL translator available???
    2871: 96/02/21: Re: Altera Simulation
gnupun:
    59885: 03/08/30: Re: Shift register
<go@prepaidonline.com>:
Gob Stopper:
    92508: 05/11/30: Re: Looking for manual for logic analyzer module 16750A.
    98095: 06/03/04: Re: about Xilinx Chipscope
    100984: 06/04/22: Re: Microblaze & Linux tools. (repost)
<godmom@pagesz.net>:
    7835: 97/10/21: cmsg cancel <KiWfB*f8e@aargh.mayn.de>
Gog:
    80953: 05/03/15: [Newbie] Microblaze and uC/OS-II on Spartan3
    81065: 05/03/17: Re: [Newbie] Microblaze and uC/OS-II on Spartan3
    81066: 05/03/17: Re: [Newbie] Microblaze and uC/OS-II on Spartan3
gokulaka:
    154280: 12/09/23: JTAG3-parallel cable on SPARTAN-3 digilent Starter kit
golchehreh sohrab:
    42946: 02/05/08: unused I/O(Vref)
    49342: 02/11/09: Back annotation initialization problem
<goldenorfe@gmail.com>:
    103147: 06/05/26: Agility - user experiences? (newbie)
Goli:
    126915: 07/12/05: Re: clock lines
    127575: 08/01/03: Xilinx, How to generate PAD file, from the UCF file
    127747: 08/01/06: Re: Xilinx, How to generate PAD file, from the UCF file
    127909: 08/01/10: Re: Multiple UCF support in Xilinx ISE
    127942: 08/01/10: Power up Behavior of Virtex5 IOs
    128413: 08/01/24: Re: How to choose an FPGA for High speed applications
    128505: 08/01/29: Re: equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera
    128688: 08/02/04: Server configuration for Virtex5
    128740: 08/02/05: Re: Server configuration for Virtex5
    128822: 08/02/07: Re: Virtex5 not for SONET or SDH
    129329: 08/02/20: ADPCM IP Core
    129616: 08/02/28: Is there any way to disable JTAG for Sptantan3AN
    129673: 08/03/02: Re: Is there any way to disable JTAG for Sptantan3AN
    131164: 08/04/13: XST support for User Defined Primitives
    131983: 08/05/09: Vritex2PRO: LVDCI for inputs?
    132059: 08/05/12: value of the weak pull up resistor on IOBs of Virtex5
    132427: 08/05/27: Re: signal value at power up
    133578: 08/07/04: Single ended interface at 70Mhz for FPGAs
    133622: 08/07/06: Re: Single ended interface at 70Mhz for FPGAs
    133627: 08/07/07: Re: Serial Pheripheral Interface for XILINX FPGA
    133791: 08/07/15: Re: Xilinx tools in Windows or Linux - Suggestions
    134215: 08/07/31: Re: Is there a totally command-line driven way to use Xilinx Webpack?
    135317: 08/09/25: Having problems with using flash in EDK
    135619: 08/10/10: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    139237: 09/03/23: Using SelectIO LVDS to drive 40 inch backplane trace
gollum:
    105458: 06/07/24: ROM implementation
    105740: 06/07/31: Re: ROM implementation
<golov@sony>:
    35901: 01/10/23: ModelSim SE vs. PE in terms of speed?
<gomez66@eucmax.sim.ucm.es>:
    2847: 96/02/16: BDD Help
    4831: 96/12/18: Help: FPGA for fast digital signal processing
GomoX:
    119344: 07/05/16: VHDL newbie: building sequential circuits with basic gates
gomsi:
    113652: 06/12/18: jtag reset seq
    113654: 06/12/19: Re: jtag reset seq
    113666: 06/12/19: Re: jtag reset seq
    113715: 06/12/19: Re: jtag reset seq
    113721: 06/12/20: Re: jtag reset seq
Gonzalo Arana:
    30289: 01/03/31: Re: fpga from linux/hc11
    30290: 01/03/31: Free VHDL PCI Interface?
    30293: 01/04/01: IDE-PCI question
    31398: 01/05/22: xilinx webpack problem
    31418: 01/05/22: Re: xilinx webpack problem
    31466: 01/05/26: Re: xilinx webpack problem
    31496: 01/05/28: silly question (xilinx - webpack - mask file)
    31505: 01/05/28: Re: High resolution time measurement?
    31622: 01/05/31: gated clock: simple question
    31495: 01/05/28: Re: xilinx webpack warning !!
    32635: 01/07/03: uart rs232? (for free)
    32916: 01/07/11: WebPACK problem
    32922: 01/07/11: Re: WebPACK problem
    33064: 01/07/16: Re: Book Recommendation (bit different)
    33205: 01/07/19: Re: Book Recommendation (bit different)
    33215: 01/07/19: UART problems
    33231: 01/07/19: xilinx web pack problem
    33418: 01/07/25: Simple question
<gonzo@res114.dana01.swarthmore.edu>:
    5257: 97/02/02: Re: Altera PCI experience anyone?
    5338: 97/02/08: Re: Anyone for Linux ?
<goodfolks@firmware.com>:
    25336: 00/09/08: 1A215966 Visio for Linux
GoodKook:
    11690: 98/09/01: Microprocessorlerr MicroMouse with FPGA/VHDL....
goodkook:
    19606: 00/01/04: Re: Using internal RAM in Altera Flex 10KE
    19618: 00/01/05: Re: HDL to graphic conversion
<goodkook@csvlsi.kyunghee.ac.kr>:
    12437: 98/10/12: Re: Software tool
GoodLadonna18:
    149792: 10/11/24: Re: ucf impact to synplify pro
<google@becanus.nl>:
    127042: 07/12/10: Re: usb cable driver
<google@gornall.net>:
    80497: 05/03/07: Re: adding SDRAM to the S3 starter kit
    80825: 05/03/11: Re: Xilinx eagle package (PQ208)
    83199: 05/04/25: Re: New FPGA Development Board
    91417: 05/11/05: Re: icarus verilog
    92738: 05/12/05: Re: Quick question, how do I supply +-5V?
    102391: 06/05/15: Re: Virtex 5 announced and sampling ... and real!
    106282: 06/08/10: Re: Real-world soft-cpu performance
    108737: 06/09/15: Re: USB programming cables
    108738: 06/09/15: Parallel P&R
<google@kleinmatze.de>:
    138468: 09/02/24: Re: Opencores DDR controller
<google@schwarzers.de>:
    136882: 08/12/10: Xilinx ISE 10.1 SP3 MPMC NPI VHDL simple sample needed
google_comp.arch.fpga@47110815.com:
    88068: 05/08/08: Re: virtex 4 : how can I know the clock region coverage?
google_guy:
    66785: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
    66815: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
    66867: 04/02/27: Re: Stratix 2 ALUT architecture patented ?
    71963: 04/08/04: Re: Need StateCAD 4.11!
GoogleGoonsAreClueless:
    150930: 11/02/22: Re: timing issues at high speed
Googleguy:
    74858: 04/10/20: Re: Experiences with SPARTAN3?
googler:
    110804: 06/10/23: Re: Synopsys's VMM and Mentor's AVM
    136924: 08/12/13: new to FPGA
    138191: 09/02/09: Learning backend stuff
    152997: 11/11/09: ASIC design job vs FPGA design job
    153003: 11/11/10: Re: ASIC design job vs FPGA design job
googlie:
    92273: 05/11/25: Re: simulating code loading in memory and jumping to memory
    92276: 05/11/25: Re: simulating code loading in memory and jumping to memory
googlinggoogler@hotmail.com:
    113904: 06/12/28: Re: system ace - ERROR: IMPACT:477 - what is this?
<googlinggoogler@hotmail.com>:
    84599: 05/05/22: spartan 3 designing board
    87747: 05/07/30: ISE webpack doesnt support Spartan xcs10, solution??
    87751: 05/07/30: Re: ISE webpack doesnt support Spartan xcs10, solution??
    87753: 05/07/30: Re: ISE webpack doesnt support Spartan xcs10, solution??
    113188: 06/12/07: Re: Recursive component instantiation
    113256: 06/12/09: Using Jtag for general Communications
Goose:
    72344: 04/08/16: Re: PCI express FPGA board
<goouse99@gmail.com>:
    154262: 12/09/18: Re: picoblaze help
    154495: 12/11/18: Re: A total beginner, wondering about determining hardware specs. requirements
    155139: 13/04/25: Re: FPGA Development Board with hard PowerPC
    155216: 13/06/11: Re: problem with the GTX wrapper in questa
    155572: 13/07/22: Re: Xilinx ISE GUI vs tcl script problem
    155698: 13/08/09: Re: [cross-post] vlib, vmap, vcom, how it all works...
    155707: 13/08/12: Re: [cross-post] vlib, vmap, vcom, how it all works...
<goouse99@googlemail.com>:
    153699: 12/04/25: Re: FPGA circuit simulator
    153859: 12/06/07: Re: FPGA Interconnect
    153909: 12/06/29: Re: The definition of comnatorial prcess?
    153964: 12/07/04: Re: The definition of comnatorial prcess?
    154046: 12/07/19: Re: FPGA + HDMI 1080P
    154055: 12/07/22: Re: FPGA + HDMI 1080P
    154077: 12/07/30: Re: 3 to 1 mux with 4 bit inputs
    154078: 12/07/30: Re: 3 to 1 mux with 4 bit inputs
<goouse@twinmail.de>:
    138431: 09/02/22: Re: Very fast counter in VirtexII
    138620: 09/03/02: Re: Antti-Brain issue 6 released
    138650: 09/03/02: Re: ODDR output to use internally
    138699: 09/03/05: Re: synchronization problem
    138757: 09/03/09: Re: Regarding to the "change in duty Cycle"
    138827: 09/03/12: Re: I2C EEPROM
    139281: 09/03/25: Re: Antti Processor
    139588: 09/04/05: Re: Modulo-10 counter
    139606: 09/04/07: Re: Modulo-10 counter
    140140: 09/04/29: Re: prohibit global clock designation
    140300: 09/05/07: Re: FPGAs and Cryptography
    140386: 09/05/12: Re: I don't like Xilinx
    140407: 09/05/12: Re: how i can use the external SRAM of FPGA
    140827: 09/05/26: Re: URGENT help with a CPLD and LCD display chip SED1278F
    141037: 09/06/02: Re: BRAM/LUT Comparison
Gopal Iyer:
    17535: 99/08/06: help!
gopal_amlekar:
    144696: 09/12/24: Altera FPGA configuration using JTAG
    144700: 09/12/24: Re: Altera FPGA configuration using JTAG
    144940: 10/01/16: CPLD programming sequence XC9500
    145244: 10/02/03: Spartan 3 configuration
    145246: 10/02/03: Re: Spartan 3 configuration
<gopfdm@hotmail.com>:
Gopi:
    96191: 06/01/31: Wanted Help on All Digital PLL
Goran:
    29155: 01/02/08: Re: help need to make a clock multiplier
    29435: 01/02/21: clock divider by 1.5
    52803: 03/02/22: VHDL & FPGA Design tools
    52825: 03/02/24: Re: VHDL & FPGA Design tools
    53120: 03/03/04: Re: VHDL & FPGA Design tools
    56791: 03/06/16: Re: Are there any free DSP core?
    64156: 03/12/18: powering spartan IIe
goran:
    29058: 01/02/04: help need to make a clock multiplier
    29816: 01/03/12: Re: clock divider by 1.5
    29834: 01/03/13: Re: clock divider by 1.5
    29858: 01/03/13: how to use both edges of clock
Goran Bilski:
    31932: 01/06/08: Re: Help in FIFO design
    32538: 01/06/29: obfuscated tools
    32552: 01/06/29: Re: obfuscated tools
    32900: 01/07/11: Re: Virtex2: Is it possible to place distributed DPRAM
    32901: 01/07/11: Re: Need to speed up VHDL accumulator on Xilinx
    32944: 01/07/12: Re: Virtex2: Is it possible to place distributed DPRAM
    34984: 01/09/17: Re: Problems with Xilinx App Note 223 (UART with Internal 16-Byte
    38037: 02/01/02: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
    39628: 02/02/14: Re: Lean serial communication processor
    40149: 02/02/28: Re: microblaze
    40195: 02/03/01: Re: microblaze
    41088: 02/03/20: Re: Missing Timing by 30,000 ns
    41297: 02/03/25: Re: Missing Timing by 30,000 ns
    44715: 02/06/27: Re: Generate loop and RLOC
    45104: 02/07/12: Re: FPGA CPU?
    45117: 02/07/12: Re: FPGA CPU?
    45175: 02/07/15: Re: FPGA CPU?
    45536: 02/07/25: Re: ALU in VHDL and a bunch of questions
    46080: 02/08/16: Re: MicroBlaze processor core
    46100: 02/08/19: Re: V2PRO PowerPC floating point
    46156: 02/08/20: Re: BRAM simulation model error?
    46732: 02/09/06: Re: Synthesis problem, my inputs are never used?
    47965: 02/10/08: Re: Why can Xilinx sw be as good as Altera's sw?
    48282: 02/10/15: Re: Xilinx microblaze vs. picoblaze
    48293: 02/10/15: Re: Xilinx microblaze vs. picoblaze
    48300: 02/10/15: Re: Xilinx microblaze vs. picoblaze
    48312: 02/10/15: Re: Xilinx microblaze vs. picoblaze
    48338: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48345: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48352: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48354: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48364: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48378: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48380: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48389: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48393: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48658: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
    48788: 02/10/24: Re: Microblaze
    49435: 02/11/12: Re: LU-decomposition
    49499: 02/11/13: Re: LU-decomposition
    52081: 03/01/30: Re: Microblaze - triggering exceptions
    52098: 03/01/31: Re: Microblaze - triggering exceptions
    53763: 03/03/21: Re: Using FPGAs as coprocessors in a PC
    54290: 03/04/07: Re: Confused at Xilinx V2P OCM usage
    54600: 03/04/14: Re: NIOS 3.0 Fmax and other Issues
    54680: 03/04/15: Re: NIOS 3.0 Fmax and other Issues
    54719: 03/04/16: Re: NIOS 3.0 Fmax and other Issues
    54949: 03/04/22: Re: NIOS 3.0 Fmax and other Issues
    55136: 03/04/28: Re: NIOS 3.0 Fmax and other Issues
    55692: 03/05/15: Re: smallest embedded cpu.
    56279: 03/06/02: Re: MicroBlaze and Spartan3
    60540: 03/09/16: Re: MICROBLAZE: Using external instruction memory
    61370: 03/10/02: Re: Digesting runs of ones or zeros "well"
    61410: 03/10/03: Re: MicroBlaze size
    61412: 03/10/03: Re: Digesting runs of ones or zeros "well"
    61426: 03/10/03: Re: Digesting runs of ones or zeros "well"
    61494: 03/10/06: Re: MicroBlaze size
    61496: 03/10/06: Re: Digesting runs of ones or zeros "well"
    61584: 03/10/07: Re: More RPM / RLOC fun
    61593: 03/10/07: Re: More RPM / RLOC fun
    61638: 03/10/08: Re: More RPM / RLOC fun
    61699: 03/10/09: Re: More RPM / RLOC fun
    62043: 03/10/17: Re: microblaze data transfer
    62733: 03/11/06: Re: Building the 'uber processor'
    62777: 03/11/07: Re: Building the 'uber processor'
    62847: 03/11/10: Re: Building the 'uber processor'
    62861: 03/11/10: Re: Home grown CPU core legal?
    62868: 03/11/10: Re: Home grown CPU core legal?
    62879: 03/11/10: Re: Home grown CPU core legal?
    62885: 03/11/10: Re: Home grown CPU core legal?
    62910: 03/11/11: Re: Implementing a very fast counterin VirtexII
    63215: 03/11/18: Re: microblaze as submodule
    63389: 03/11/20: Re: State Machines....
    63412: 03/11/21: Re: Xilinx microblaze : SRAM external mem controller
    63414: 03/11/21: Re: State Machines....
    63903: 03/12/08: Re: MicroBlaze - how much memory?
    64911: 04/01/16: Re: Can nios_gnupro support file system?
    65155: 04/01/21: Re: microblaze reg_addr and new_reg_value outputs
    65159: 04/01/21: Re: Trouble using ChipsCope Pro with MicroBlaze
    66427: 04/02/19: Re: Microblaze instruction timings
    66572: 04/02/23: Re: Dhrystone figures - Was: Microblaze instruction timings
    69172: 04/04/29: Re: Xilinx edk/modelsim/ VHDL question
    69734: 04/05/19: Re: Nios II Going Live...
    69770: 04/05/19: Re: Nios II Going Live...
    69931: 04/05/25: Re: Nios II = Microblaze
    69937: 04/05/25: Re: Nios II = Microblaze
    69946: 04/05/25: Re: Nios II = Microblaze
    70004: 04/05/26: Re: Nios II = Microblaze
    70394: 04/06/15: Re: pulse generation using SRL16E on a Virtex-II
    70395: 04/06/15: Re: pulse generation using SRL16E on a Virtex-II
    70403: 04/06/15: Re: pulse generation using SRL16E on a Virtex-II
    70418: 04/06/16: Re: pulse generation using SRL16E on a Virtex-II
    70670: 04/06/23: Re: Problems with a Virtex-II Engineering Sample
    73945: 04/10/01: Re: FSL link beginner question
    73952: 04/10/01: Re: FSL link beginner question
    73107: 04/09/14: Re: Virtex 4 released today
    73164: 04/09/15: Re: Virtex 4 released today
    73169: 04/09/15: Re: Virtex 4 released today
    74121: 04/10/04: Re: FSL Read Data Out Problem
    74134: 04/10/04: Re: FSL Read Data Out Problem
    74169: 04/10/05: Re: FSL Read Data Out Problem
Goran Olsson, Plasma Physics, KTH:
    576: 95/01/09: Actel + Mentor Graphics
    840: 95/03/10: Re: Can I implement a digital PLL in an FPGA??
Goran Salamuniccar:
    15158: 99/03/10: Re: VLSI Design on random number genrator
<Goran.Bilski@enator.se>:
    10899: 98/06/29: DAC Experience
    11949: 98/09/21: Re: Dynamic pattern matching in Xilinx FPGAs
    13217: 98/11/20: Re: Synthesizeablel fifo
Goran_Bilski:
    136650: 08/11/28: Re: timer interrupt problem: microblaze
    138982: 09/03/17: Re: Zero operand CPUs
    139083: 09/03/20: Re: Documenting a simple CPU
    139087: 09/03/20: Re: Documenting a simple CPU
    141202: 09/06/10: Re: Error in FSL Bus
    141241: 09/06/12: Re: Error in FSL Bus
    143737: 09/10/22: Re: problem while receiving negative integer in microblaze
    143761: 09/10/24: Re: problem while receiving negative integer in microblaze
    144069: 09/11/10: Re: Microblaze performance in V6
    144566: 09/12/14: Re: multiprocessors MB and shared BRAM
    144670: 09/12/22: Re: multiprocessor on spartan 3
    145190: 10/02/01: Re: In system memory editor of Altera for Xilinx
    145192: 10/02/01: Re: In system memory editor of Altera for Xilinx
    148215: 10/06/30: Re: MicroBlaze - how to instantiate/connect more BRAM to the LMB
    148218: 10/06/30: Re: MicroBlaze - how to instantiate/connect more BRAM to the LMB
    153270: 12/01/23: Re: MicroBlaze MCS Error.
Gord Wait S-MOS Systems Vancouver Design Center:
    2129: 95/10/18: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
<gordanic2003@yahoo.com.sg>:
    77228: 04/12/31: Inter FPGA communication
Gordon:
    71902: 04/08/03: Xilinx Spartan-3 Supply Issues?
    71931: 04/08/03: Re: Xilinx Spartan-3 Supply Issues?
    72380: 04/08/17: XC3S50 DCI Application
    72395: 04/08/17: Re: XC3S50 DCI Application
Gordon Brebner:
    6607: 97/06/05: Re: New Reconfigurable Computing newsgroup?
    17333: 99/07/21: Special Issue on Reconfigurable Systems
    21432: 00/03/22: Re: FPGA openness
Gordon Coulson McNaughton:
    11600: 98/08/26: Re: New Evolutionary Electronics Book
Gordon Freeman:
    117512: 07/04/02: Implement IIR Filter on FPGA
    117556: 07/04/03: Re: Implement IIR Filter on FPGA
    117617: 07/04/04: Re: Implement IIR Filter on FPGA
    118330: 07/04/24: Take verilog code from Xilinx Core generator
    118340: 07/04/24: Re: Take verilog code from Xilinx Core generator
    118746: 07/05/02: Re: Take verilog code from Xilinx Core generator
    118903: 07/05/07: About DDR SDRAM
    118949: 07/05/07: Re: About DDR SDRAM
    118993: 07/05/08: About memory interface generater 007 tool
Gordon Friend:
    52112: 03/01/31: Virtex2 PCI and 5V
    90298: 05/10/09: Bus master DMA and cache coherency
gordon hlavenka:
    921: 95/03/30: Re: Excuse me while I vent about Data I/O & Abel...
Gordon Hollingworth:
    17496: 99/08/02: Xilinx Readback Problems
    17660: 99/08/20: Jbits
    18363: 99/10/19: Virtex Readback
    18380: 99/10/21: Virtex Partial Reconfiguration
    19045: 99/11/25: LOC's RLOC's and Virtex
    53957: 03/03/28: Re: Pin failure detection
Gordon McGregor:
    3749: 96/07/25: Re: What about the XC6200 ?
    4606: 96/11/20: ViewLogic PRO series under win95
Gordon Stoll:
    23949: 00/07/17: Java API for Boundary Scan (JTAG)
gordon sumner:
    149539: 10/11/03: Good Dev Board
<gordon.haddow@eev.com>:
    23364: 00/06/23: Atmel bidirectional pins problem
Gorgo:
    55521: 03/05/11: Information about XC9536 ?
    55594: 03/05/13: XC9536 - how to make my own programing device for this chip ?
    56244: 03/06/01: Xilinx and webpack!
    56257: 03/06/01: Xilinx and programind mode !
Gorker:
    74875: 04/10/20: Real numbered operations
    74876: 04/10/20: Re: Real numbered operations
<gorkw@my-deja.com>:
    17686: 99/08/24: Re: JTAG 1149 Info
gosensgo@goober_lumictech.com:
    43584: 02/05/24: Re: Xilinx Pull Ups/Dpwns
    43619: 02/05/27: Re: Synchronous Single Clock Designs
goss:
    109818: 06/10/05: Open protocol USB JTAG cable
Got Me Lucky Charms:
    24753: 00/08/17: Re: Non-disclosures in job interviews
Goteb:
    39083: 02/01/31: ProcWizard by Gidel
    44030: 02/06/10: Information about FPGA
gouaich:
    121998: 07/07/17: Req: (Free) Embedded Platforms for Education
<gouaich@lirmm.fr>:
    122203: 07/07/23: Re: Req: (Free) Embedded Platforms for Education
Gouindarajulu Venkatesh:
    1126: 95/05/03: Need Information on a paper
Goulas George:
    23118: 00/06/15: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
    23120: 00/06/15: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
    24391: 00/08/06: Circuit Drawing
gouri:
    146983: 10/04/07: VHDL coding
<governer@gmail.com>:
    79743: 05/02/23: cheapest CPLD
    79839: 05/02/24: Re: cheapest CPLD
Govind Kharbanda:
    46428: 02/08/29: Handel-C data widths
    46515: 02/09/02: Re: Handel-C data widths
    46607: 02/09/04: Handel-C: Undeclared identifier
    46609: 02/09/04: Handel-C: Undeclared identifier: take2
    46667: 02/09/05: Re: Handel-C: Undeclared identifier: take2
    46677: 02/09/05: HAndel-C types not matching
    46710: 02/09/06: Re: HAndel-C types not matching
    46711: 02/09/06: Re: HAndel-C types not matching
    46714: 02/09/06: Handel-C: a bit of a funny 'for loop'
    47128: 02/09/18: Re: Handel-C: a bit of a funny 'for loop'
    47129: 02/09/18: Handel-C: Unhandled exception: uncaught exception in compiler
GOVJOBS:
    14188: 99/01/18: GOVJOBS.COM - JOB BANK - private sector opportunities in high-technologies only!
GOVJOBS.COM:
    14665: 99/02/09: FPGA - Ground Unit Design Engineering
    14688: 99/02/11: FPGA - Ground Unit Design Engineering
    14692: 99/02/11: GOVJOBS.COM - JOB BANK - private sector opportunities in high-technologies only!
    14716: 99/02/12: FPGA - Ground Unit Design Engineering
    14717: 99/02/12: FPGA - Digital Flight Unit Design Engineering
    14718: 99/02/12: FPGA - Digital Flight Unit Design Engineering
    14719: 99/02/12: Communications Systems Engineering
    17085: 99/06/29: FPGA - Ground Unit Design Engineering
GPE:
    88252: 05/08/12: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
    88295: 05/08/14: ISE 7.1 'improvements' plus meandering....
    88301: 05/08/14: Re: ISE 7.1 'improvements' plus meandering....
    88303: 05/08/15: Re: ISE 7.1 'improvements' plus meandering....
    88619: 05/08/23: Re: xilinx or digilent
    88621: 05/08/24: Re: xilinx or digilent
    88668: 05/08/24: Re: xilinx or digilent
    89624: 05/09/20: Re: JTAG USB Circuit
    89672: 05/09/21: Re: JTAG USB Circuit
    89745: 05/09/23: Question on Metastability
    89755: 05/09/24: Re: Question on Metastability
    89756: 05/09/24: Re: Question on Metastability
    89797: 05/09/26: Re: Question on Metastability
    90528: 05/10/15: Re: 3.3v<->5V
    90555: 05/10/16: Re: Anyone remember the really early Xilinx FPGAs?
    91301: 05/11/02: Re: Spartan-3E starter kit
    92212: 05/11/23: Re: XC2000
    92445: 05/11/29: Re: Q-bus or Unibus bus transactions in FPGA?
    92459: 05/11/30: Re: Q-bus or Unibus bus transactions in FPGA?
    110039: 06/10/10: CPLD's and labels
    110090: 06/10/10: Re: CPLD's and labels
GPG:
    63544: 03/11/25: Re: Slightly unmatched UART frequencies
    63587: 03/11/25: Re: Slightly unmatched UART frequencies
<gpnyqwax@usacurrency.com>:
    11825: 98/09/11: Financial Art, FAQ and un-cut money
<gpqevl@nowhere.com>:
gps:
    53194: 03/03/05: Need help! Any experienced Handel-C user?
GpsBob:
    57198: 03/06/25: Microblaze uP as component
    57696: 03/07/04: Difficulty with OPB bus and user IP
<gquan@altera.com>:
    132418: 08/05/26: Re: Incremental compilation problem
<gr6@ukc.ac.uk>:
    30862: 01/05/01: USB CORE IN VHDL
Gra:
    88990: 05/09/02: OT: CPLD - SimuCAD S/W CD
Grad. Lee Dae-Hee:
    2918: 96/02/29: How to multiple-download with Xilinx 4005 ?
grad_student:
    34803: 01/09/08: SOS : A Question about synthesizng ROM
Graeme:
    53677: 03/03/19: Re: FPGA specs
Graeme Durant:
    11397: 98/08/10: Re: Security
    12336: 98/10/09: Re: Xilinx F1.5/FPGA Express wackiness
    13106: 98/11/16: Re: Xilinx COREgen and Leonardo troubles...
    17864: 99/09/14: Re: Opinions Wanted
    18241: 99/10/08: Re: Capacity metrics for Virtex
    19328: 99/12/14: Re: Virtex hard macro
Graeme Gill:
    627: 95/01/23: Re: pci source code
    2594: 96/01/10: Re: [q][Reverse Engineering Protection]
    3187: 96/04/22: Re: On FPGAs as PC coprocessors
    6033: 97/04/07: Re: PCI Bus Problems
    6115: 97/04/13: Re: PCI Bus Problems
    6116: 97/04/13: Re: PCI Bus Problems
    8278: 97/12/05: Re: what is metastability time of a flip_flop
    8313: 97/12/08: Re: what is metastability time of a flip_flop
    8635: 98/01/15: Re: Jam - Anyone using it ?
    9150: 98/02/25: Re: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
    9510: 98/03/20: Re: Ideas for an FPGA Project?
    10718: 98/06/12: Re: AHDL vs. VHDL vs. Verilog HDl
    42367: 02/04/22: Re: RAM function in Altera device
Graeme Houston BSc:
    148864: 10/09/05: PCI Dragon + PCI Logic Analyser
Graeme Robertson:
    7192: 97/08/13: Re: Any one getting 125MHz out of XILINX CPLDs?
    7996: 97/11/06: Small FIFO in CPLD
    13342: 98/11/27: Actel PCI Cores
<graffitici@yahoo.com>:
    135995: 08/10/26: PSpice model for Virtex-II Pro
    136014: 08/10/27: PSpice model for Virtex-II Pro
Graham Eastwood:
    10425: 98/05/18: Re: XC5200s and Foundation 1.4
    16969: 99/06/21: Viewdraw + Foundation Express design flow
Graham Millar:
    18711: 99/11/09: Re: Virtex Board
Graham Rhodes:
    6477: 97/05/27: Re: Cypress WARP question
    7237: 97/08/18: Re: ISP Stories
    7280: 97/08/21: Re: ISP Stories
Graham Seaman:
    291: 94/10/13: PALASM versions?
    487: 94/12/02: FPGA boards available?
    842: 95/03/10: Re: Inverse-Fourier waveform synthesis
    1140: 95/05/04: FPGA price trends?
    5510: 97/02/21: replicating structure in MaxPlus
    18490: 99/10/27: Re: Announcing Free VHDL Simulator for Windows
    18718: 99/11/09: orcad synthesis for simplepld
    18740: 99/11/11: Re: orcad synthesis for simplepld
    18772: 99/11/13: Re: orcad synthesis for simplepld
    19755: 00/01/11: CPLD interconnect?
    19957: 00/01/20: Re: Patent licenses for circuits in FPGA
    21831: 00/04/03: Re: Adrian Thompson's and GA work on Xilinx
    21912: 00/04/06: FPGA Openness/ Summary
    21926: 00/04/07: Re: FPGA Openness/ Summary
Graham Smart:
    42155: 02/04/17: Re: Virtex Development Board with a 4M or more gates
    53008: 03/02/28: Re: Extend PCI slot to outside PC
<Graham>:
    34729: 01/09/05: DLL locks with no clock present
    35739: 01/10/16: Re: PLLs & DLLs
    36027: 01/10/26: Re: How to make an implementable big counter?
<graham_moss@my-deja.com>:
    25957: 00/09/28: atmel verses altera
Grahame Kelly:
    89031: 05/09/03: Re: CPLD - SimuCAD S/W CD
    89289: 05/09/12: Re: Which JTAG cable for Xilinx & Linux?
    90351: 05/10/11: iVerilog / VVP output to GTKwave.
    90403: 05/10/12: Re: iVerilog / VVP output to GTKwave.
gralsto:
    84609: 05/05/23: FSM stops working
    84645: 05/05/23: re:FSM stops working
    84646: 05/05/23: re:FSM stops working
GRANADO:
    2967: 96/03/07: ECOLE - Architecture des Systemes et des Machines Informatique - 21 au 26 Avril 1996 - Cauterets
Grant Edwards:
    92647: 05/12/02: Re: Quick question, how do I supply +-5V?
    93509: 05/12/23: Re: RTL for Z8000 series CPU?
    93536: 05/12/24: Re: RTL for Z8000 series CPU?
    93956: 06/01/04: Re: RTL for Z8000 series CPU?
    113699: 06/12/19: Re: interrupt handling using microblaze with XPS
    115494: 07/02/12: Re: Building Coaxial transmission line on PCB?
    115663: 07/02/16: Re: Building Coaxial transmission line on PCB?
    115668: 07/02/16: Re: Building Coaxial transmission line on PCB?
    123875: 07/09/06: Re: high bandwitch ethernet communication
    123876: 07/09/06: Re: high bandwitch ethernet communication
    149207: 10/10/07: Re: Driving a design via TCP/IP
Grant Likely:
    116476: 07/03/09: Re: Xilinx Platform cable USB and impact on linux without windrvr
Grant Sargent:
    17672: 99/08/23: Altera MAX2PLUS/MAX700s BIDIR problem...
    19308: 99/12/13: Re: hobbyist friendly pld?
Grant Stockly:
    112141: 06/11/16: Spartan 3/3E to Standard TTL/Low power devices
    112152: 06/11/17: Re: Spartan 3/3E to Standard TTL/Low power devices
    112359: 06/11/21: Re: 8080 FSGA model in an FPGA
    112397: 06/11/21: Re: 8080 FSGA model in an FPGA
    112419: 06/11/21: Re: 8080 FSGA model in an FPGA
    112461: 06/11/22: Re: 8080 FSGA model in an FPGA
    112467: 06/11/22: Re: 8080 FSGA model in an FPGA
    120436: 07/06/07: A first FPGA project
    132506: 08/05/29: Xilinx Clock Doubler
    132508: 08/05/29: Re: Xilinx Clock Doubler
    132525: 08/05/29: Re: Xilinx Clock Doubler
    132530: 08/05/29: Re: Xilinx Clock Doubler
grant0920:
    129461: 08/02/25: About John Williams' ICAP driver?
    129922: 08/03/10: Re: About John Williams' ICAP driver?
    130746: 08/03/31: Partial reconfiguration by using ICAP
    130967: 08/04/07: FPGA configuration mode on ML310
    130969: 08/04/07: Re: FPGA configuration mode on ML310
    131053: 08/04/08: Re: FPGA configuration mode on ML310
    133297: 08/06/24: 1D or 2D Placement for dynamically partially reconfigurable
    133401: 08/06/26: Re: 1D or 2D Placement for dynamically partially reconfigurable
    134739: 08/08/28: How to disable the static routing to cross through the PRR?
<grantb@ecn.ab.ca>:
    21916: 00/04/06: SpartanII BSDL file/JTAG Pgmr
<granville@decus.org.nz>:
    1349: 95/06/05: 80x51 in FPGA anyone ?
    1406: 95/06/17: summary: 80x51 in FPGA anyone?
    1505: 95/07/05: Re: Low Power 22V10, market needs...
    1615: 95/07/31: PLD's with Hystersis ?
    1705: 95/08/18: Re: FPGAs with embedded RAM
    1942: 95/09/22: Re: palce16v8hd obsolescence
    1977: 95/09/28: Re: FPGA for a 20k gates micro-controller.
    2391: 95/11/28: Lattice GAL16VP8 -is it real ?
    3101: 96/04/02: Re: sigma delta analog to digital conversion
    4211: 96/09/27: Re: Q: PLD vs. FPGA
    4377: 96/10/22: Re: Seeking 16V8: Vcc=3.0-5.0V: Zero standby power.
    4434: 96/10/29: Re: VHDL for Xilinx designs?
Grao:
    157151: 14/10/18: Re: Fast and slow clocks
    157153: 14/10/18: Re: Fast and slow clocks
Grason Curtis:
    3220: 96/04/29: Re: FPIC
    6148: 97/04/17: Re: Pentium Pro Worth it for Altera Max Plus?
Grata:
    102837: 06/05/22: MicroBlaze and IIC
Gravis:
    149876: 10/11/30: What should I use for highspeed/low latency communication beteen PC and FPGA?
Gray Creager:
    4149: 96/09/18: *** finding datasheets and chipmakers on the web ***
    4659: 96/11/26: ### Chipmaker URLs (almost 300!) and other resources for finding data sheets ###
    4996: 97/01/09: Are you looking for CHIP MANUFACTURER websites ???
    5382: 97/02/12: @@ it's very easy to find chipmaker websites (approx. 350 valid sites listed here) @@
    5981: 97/04/01: @@ it's still very easy to find chipmaker websites (approx. 380 valid sites isted here) @@
    6242: 97/05/02: @@ it's very easy to find chipmaker websites (currently 395 valid sites listed here) @@
    6741: 97/06/22: @@ finding data sheets and chipmaker websites (403 valid sites currently) @@
    7359: 97/08/31: ** here's how to find chipmaker websites (currently 436 valid sites on Gray's Semiconductor Pages) **
    8749: 98/01/23: ## how to find chipmaker websites? (currently 528 valid sites) ##
<grcook@my-dejanews.com>:
    14541: 99/02/04: ASIC or Digital Board Design in the UK - choice?
GreateWhite.DK:
    69388: 04/05/10: Bootloader question
    69541: 04/05/13: Anyone who has worked with Altera Cyclone???
    69566: 04/05/14: Re: Anyone who has worked with Altera Cyclone???
    69899: 04/05/24: HOWTO calculate the binary size of a .hexout/.flash/.germs file
    69941: 04/05/25: Re: HOWTO calculate the binary size of a .hexout/.flash/.germs file
Greatin Baby:
    58072: 03/07/14: Xilinx Spartan 2E Clock generator selection
Greegor:
    150479: 11/01/24: Phil and Archie?
    150483: 11/01/24: Xilinx news, David Brown and ""Xenophobia"" (see H1b FRAUD!)
    150489: 11/01/24: Re: Xilinx news
    150490: 11/01/24: Re: Xilinx news
green:
    142621: 09/08/21: Re: Soft Processor IP core report
    142661: 09/08/24: Re: Soft Processor IP core report
greenaum:
    156767: 14/06/24: Re: PLA? PAL? PLD? GAL?
greenlean@gmail.com:
    137020: 08/12/19: Re: Custom IP Core DMA (Xilinx Virtex II Pro)
greenplanet:
    79961: 05/02/26: I2C protocol to communicate between FPGAs
    80050: 05/02/28: Re: I2C protocol to communicate between FPGAs
    80333: 05/03/03: Displays an image in the XS Board RAM on a VGA monitor
    80407: 05/03/04: Re: Displays an image in the XS Board RAM on a VGA monitor
    82390: 05/04/12: question using xapp333
    86719: 05/07/05: PS/2 interface
    86811: 05/07/06: Re: PS/2 interface
    86873: 05/07/07: Re: PS/2 interface
    87054: 05/07/13: Reading a PS/2 mouse
    87073: 05/07/14: Re: Reading a PS/2 mouse
    87099: 05/07/14: Re: Reading a PS/2 mouse
    87131: 05/07/16: Re: Reading a PS/2 mouse
Greenwood Systems:
    11074: 98/07/17: VHDL contract company
    11141: 98/07/21: Re: Too much advertising in this news group?
Greg:
    41991: 02/04/12: DDR SDRAM Controller
    43057: 02/05/10: Re: problem installing xilinx foundation 3.1 on a P4
    43251: 02/05/17: Spartan II Proto. Board
    74720: 04/10/17: Re: a pci implemenation problem, thanks
    75869: 04/11/17: Newbie FPGA Qs
greg:
    73973: 04/10/02: FPGA+ggiabit ethernet and protocols
    73197: 04/09/15: problem with ALtera CPLD
    73307: 04/09/18: gigabit ethernet
    73329: 04/09/20: Re: Where are the Cyclones2
    73330: 04/09/20: Re: EPM7160SLC84 ex-stock in UK?
    74065: 04/10/03: Re: FPGA+ggiabit ethernet and protocols
Greg Alexander:
    19886: 00/01/16: Re: HW resources increased
    19887: 00/01/16: Re: HW resources increased
    19893: 00/01/16: Re: HW resources increased
    21403: 00/03/22: Re: Virtex DLL inoperability
    21406: 00/03/22: FPGA openness
    21428: 00/03/22: Re: FPGA openness
    21439: 00/03/22: Re: FPGA openness
    21445: 00/03/22: Re: Virtex DLL inoperability
    21455: 00/03/22: Re: FPGA openness
    21457: 00/03/22: Re: No- FPGA openness
    21458: 00/03/22: Re: 4000XLA bitgen problem?
    21459: 00/03/23: Re: FPGA openness
    21460: 00/03/23: Re: No- FPGA openness
    21467: 00/03/23: Re: FPGA openness
    21478: 00/03/23: Re: FPGA openness
    21489: 00/03/23: Re: FPGA openness
    21491: 00/03/23: Re: FPGA openness
    21492: 00/03/23: Re: No- FPGA openness
    21498: 00/03/23: Re: FPGA openness
    21500: 00/03/23: Re: FPGA openness
    21501: 00/03/23: Re: FPGA openness
    21502: 00/03/23: Re: No- FPGA openness
    21503: 00/03/23: Re: FPGA - CPU's
    21506: 00/03/23: Re: FPGA openness
    21507: 00/03/23: Re: FPGA openness
    21521: 00/03/24: Re: FPGA openness
    21522: 00/03/24: Re: No- FPGA openness
    21523: 00/03/24: Re: No- FPGA openness
    21524: 00/03/24: Re: FPGA openness
    21531: 00/03/24: Re: No- FPGA openness
    21532: 00/03/24: Re: No- FPGA openness
    21533: 00/03/24: Re: FPGA openness
    21539: 00/03/24: Re: FPGA openness
    21585: 00/03/26: Re: FPGA & single point failure
    21586: 00/03/26: Re: FPGA openness
    21587: 00/03/26: Re: FPGA openness
    21589: 00/03/26: Re: No- FPGA openness
    21591: 00/03/26: Re: FPGA openness
    21592: 00/03/26: Re: FPGA openness
    21595: 00/03/26: Re: No- FPGA openness
    21596: 00/03/26: Re: FPGA openness
    21607: 00/03/26: Re: FPGA openness
    21608: 00/03/26: Re: FPGA openness
    21611: 00/03/26: Re: FPGA openness
    21617: 00/03/26: Re: FPGA openness
    21693: 00/03/29: Re: FPGA openness
    21714: 00/03/29: Re: FPGA openness
    21717: 00/03/29: Re: FPGA openness
    21745: 00/03/30: Re: FPGA openness
    21761: 00/03/30: Re: FPGA openness
    21762: 00/03/30: Re: FPGA openness
    21769: 00/03/31: Re: Adrian Thompson's and GA work on Xilinx
    21770: 00/03/31: Re: FPGA openness
    21800: 00/03/31: Re: FPGA openness
Greg Ansley:
    5559: 97/02/24: Xilinx + Orcad + XBlox ????
Greg Berchin:
    81081: 05/03/17: Re: Xilinx System Generator
    81082: 05/03/17: Re: Xilinx System Generator, Gateways not implemented
    81161: 05/03/18: Re: Xilinx System Generator, Gateways not implemented
    86864: 05/07/07: Re: Resampling in FPGA with irrational or large rational ratios
Greg Bezjak:
    21815: 00/04/01: Xilinx Foundation PAR hangs
Greg Brown:
    6835: 97/07/01: Re: Verilog Simulation and Synthesis for FPGA Devices
    96695: 06/02/08: Re: question for the EDK users out there...
Greg Cary:
    31540: 01/05/29: Peripheral for Microcontroller
Greg Clifford:
    3152: 96/04/15: Actel ACT1 Slow Rise Time
greg clifford:
    17639: 99/08/17: New Product Announcement: Flash Based XILINX Configurator
Greg Comeau:
    43530: 02/05/22: Re: fpga cpu
Greg Crocker:
    120385: 07/06/06: Re: LocalLink TEMAC Data Corruption
    121306: 07/07/02: Re: intermitent boot in V4
Greg Daughtry:
    135433: 08/10/01: Re: Xilinx Timing constraint problems
Greg Deuerling:
    30809: 01/04/30: Re: Multiple state machines in altera AHDL
    30842: 01/05/01: Re: Multiple state machines in altera AHDL
    30883: 01/05/02: Re: Multiple state machines in altera AHDL
    44957: 02/07/08: Re: 3.3 volt tolerance in Virtex-II Pro?
    45687: 02/08/01: Re: VirtexE : OrCAD capture part symbol
    52448: 03/02/10: Re: Silly Quartus Question
    52881: 03/02/25: Re: Xilinx FPGA on PCI board
    53078: 03/03/03: Re: Programming Altera EPC1 with ByteBlaster
    53123: 03/03/04: Re: Programming Altera parts in situ.
Greg Deych:
    20930: 00/02/29: Extremely fault tolerant strategies
    20940: 00/02/29: Re: Extremely fault tolerant strategies
Greg Hoffman:
    8616: 98/01/13: Implementing Altera FIFOs without EABs
Greg Holdren:
    8966: 98/02/10: Re: Free FPGA tools???
    13534: 98/12/08: Re: ALTERA isp cable
Greg Kramer:
    152277: 11/08/02: Re: die's in different packages
Greg Lara:
    77490: 05/01/07: Re: San Jose job offer - need advice
Greg Menke:
    146019: 10/03/03: Re: using an FPGA to emulate a vintage computer
    146071: 10/03/04: Re: using an FPGA to emulate a vintage computer
    146167: 10/03/07: Re: using an FPGA to emulate a vintage computer
    146240: 10/03/09: Re: using an FPGA to emulate a vintage computer
    146242: 10/03/09: Re: using an FPGA to emulate a vintage computer
Greg Miller:
    17590: 99/08/11: Jedec to VHDL
Greg Neff:
    17886: 99/09/15: Re: xilinx v2.1i
    17908: 99/09/16: Re: xilinx v2.1i
    17920: 99/09/17: Re: Xilinx XC4005E
    18105: 99/09/30: Re: Need help programming Spartan FPGA with Atmel serial EEPROM
    18620: 99/11/03: Re: Input metastability
    18638: 99/11/04: Re: Input metastability
    18639: 99/11/04: Re: Input metastability
    18651: 99/11/05: Re: Input metastability
    18652: 99/11/05: Re: Xilinx M2.1i SP2?
    18662: 99/11/05: Re: Input metastability
    18747: 99/11/11: Re: orcad synthesis for simplepld
    18748: 99/11/11: FPGA Expess vs. Synplify vs. Leonardo Spectrum
    18955: 99/11/22: VHDL vs. schematic entry
    18956: 99/11/22: VHDL vs. schematic entry
    18966: 99/11/23: Re: VHDL vs. schematic entry
    18990: 99/11/23: Re: VHDL vs. schematic entry
    19017: 99/11/24: Re: VHDL vs. schematic entry
    19031: 99/11/25: Re: VHDL vs. schematic entry
    19049: 99/11/25: Re: VHDL vs. schematic entry
    19100: 99/11/29: Re: VHDL vs. schematic entry
    19195: 99/12/05: Re: Synplify vs. FPGA Compiler II (v3.3)
    19801: 00/01/12: Re: Xilinx Spartan2
    19834: 00/01/13: Re: Xilinx Spartan2
    19838: 00/01/13: Re: Reliability of programming SRAM FPGAs
    19867: 00/01/14: Re: Xilinx Spartan2
    19871: 00/01/14: Re: Xilinx Spartan2
    19910: 00/01/17: Re: Xilinx Spartan2
    20364: 00/02/07: Re: Virtex Fine Pitch BGA pcb layout
    20397: 00/02/08: Re: Spartan II availability and pricing
    20592: 00/02/15: Re: Multiple GND & VCC Instances
    20781: 00/02/22: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
    20806: 00/02/23: FAA doc on FPGA/ASIC design/test
    20947: 00/02/29: Re: Extremely fault tolerant strategies
    21324: 00/03/16: Re: Xilinx configuration current
    21330: 00/03/16: Re: Xilinx configuration current
    21618: 00/03/26: Re: FPGA & single point failure
    21639: 00/03/27: Re: FPGA & single point failure
    21643: 00/03/27: Re: FPGA & single point failure
    21676: 00/03/28: Re: FPGA & single point failure
    21956: 00/04/09: Re: Shuttle Backup Computers and "Diverse Design"
    22093: 00/04/21: Re: Fast (> 100Mb) serial link to PC
    22100: 00/04/22: Re: Virtex-E and LVDS
    22107: 00/04/24: Re: Virtex-E and LVDS
    22137: 00/04/26: Re: Xilinx Virtex problem (schematic)
    22139: 00/04/26: Re: Xilinx Virtex problem (schematic)
    22171: 00/04/28: Re: xilinx prom 2nd source.
    22234: 00/05/02: Re: How to Prevent theft of FPGA design
    22244: 00/05/02: Re: How to Prevent theft of FPGA design
    22264: 00/05/03: Re: How to Prevent theft of FPGA design
    22413: 00/05/08: Re: Non-BGA High Pin Count FPGA/CPLD
    22512: 00/05/10: Re: SpartanXL driving 5V CMOS input
    22549: 00/05/11: Re: SpartanXL driving 5V CMOS input
    23185: 00/06/16: Re: Hand soldering a PQ208 - It looks tough to do.
    23241: 00/06/19: Re: Hand soldering a PQ208 - It looks tough to do.
    23240: 00/06/19: Re: Hand soldering a PQ208 - It looks tough to do.
    23648: 00/07/04: Re: BIST in FPGAs?
    23656: 00/07/04: Re: BIST in FPGAs?
    23681: 00/07/05: Re: BIST in FPGAs?
    23848: 00/07/12: Re: hold time errors in FPGA's ?
    23944: 00/07/17: Re: hold time errors in FPGA's ?
    23981: 00/07/19: Re: FPGAs in AC Magnetic Field
    24040: 00/07/24: Re: jedec ???
    24051: 00/07/24: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
    24131: 00/07/27: Re: Viewlogic Licencing
    24137: 00/07/27: Re: Spartan-II power consumption
    24152: 00/07/27: Re: Spartan-II power consumption
    24459: 00/08/09: Re: Viewlogic Licencing
    24487: 00/08/10: Re: Deterministic FPGA routing?
    24894: 00/08/21: Re: Looks like Xilinx is at it again!
    25186: 00/08/30: Re: Xilinx and CD databooks (rant)
    24911: 00/08/22: Re: Looks like Xilinx is at it again!
    26890: 00/11/02: Re: OT: Xilinx T-Shirt
    26997: 00/11/07: Re: ViewLogic ViewDraw questions
    27319: 00/11/17: Re: Schematics & VHDL
    27430: 00/11/21: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
    27457: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
    27463: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
    27468: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
    27484: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
    27731: 00/12/05: Re: ORCAD EXPRESS / Synplicity (feeling stuck)
    27988: 00/12/19: Re: Setup violation
    28018: 00/12/19: Re: Setup violation
    28019: 00/12/19: Re: Question about Xilinx pins at high-frequency
    28021: 00/12/19: Re: 3V -> 5V clock signal level conversion
    28031: 00/12/19: Re: 3V -> 5V clock signal level conversion
    28037: 00/12/19: Re: 3V -> 5V clock signal level conversion
    28041: 00/12/19: Re: 3V -> 5V clock signal level conversion
    28120: 00/12/21: Re: Help with encoder/decoder
    28189: 00/12/27: Re: Newbie question on clock timing generation
    28276: 01/01/05: Re: Nondeterministic FSMs in hardware?
    28302: 01/01/05: Re: Nondeterministic FSMs in hardware?
    28311: 01/01/05: Re: Nondeterministic FSMs in hardware?
    28688: 01/01/21: Re: xc95108 funny behaviour
    28725: 01/01/22: Re: xc95108 funny behaviour
    28924: 01/01/29: Re: Xilinx JEDEC files to SVF format
    28931: 01/01/30: Re: Encryption is supported in new Virtex II but.....
    30568: 01/04/17: XC9500XL Internal Noise Immunity
    30575: 01/04/17: Re: Download Cable Mystery Solved
    30599: 01/04/18: Re: XC9500XL Internal Noise Immunity
    32461: 01/06/27: Re: Stupid Xilinx Patent
    33363: 01/07/24: Re: Homemade Xilinx parallel cable problem
    33390: 01/07/25: Re: Homemade Xilinx parallel cable problem
    33437: 01/07/26: Re: PQFP sockets
    37651: 01/12/18: Re: ISP by JTAG using a microcontroller
    37663: 01/12/18: Re: ISP by JTAG using a microcontroller
    37665: 01/12/18: Re: ISP by JTAG using a microcontroller
    37668: 01/12/18: Re: Spartan-IIE schematic symbol?
    37848: 01/12/21: Re: annoying problem and "simple and clever solution"
    40411: 02/03/06: Mutual Clock Synchronization
    40420: 02/03/06: Re: Mutual Clock Synchronization
    40465: 02/03/07: Re: Mutual Clock Synchronization
    40468: 02/03/07: Re: Mutual Clock Synchronization
    42221: 02/04/18: Xilinx Programmable World 2002 - Review
    42286: 02/04/19: Re: Xilinx Programmable World 2002 - Review
    42777: 02/05/02: Re: Xilinx Download Cable III
    70496: 04/06/17: Re: compressing Xilinx bitstreams
    70578: 04/06/21: Re: Spartan/SpartanXL Device Selection
    77955: 05/01/20: Re: LVDS through connectors
    78275: 05/01/27: Re: XC4005-6PQ160C datasheet
    81609: 05/03/28: Re: cheap Xilinx tricks
    85118: 05/06/05: Re: *.mcs format file can't contain over 1Mbyte data?
    90687: 05/10/18: WANTED: Contract Verilog Designer
    102342: 06/05/15: Re: Power for Spartan 3
    102539: 06/05/17: Re: Power for Spartan 3
    103359: 06/05/31: Re: Configuring Spartan 3
    116595: 07/03/13: Re: Heatsink on FPGA?
Greg Nichols:
    58317: 03/07/20: Instantiating pins on Virtex-II Pro
    58319: 03/07/20: Re: Instantiating pins on Virtex-II Pro
    58328: 03/07/20: Re: Instantiating pins on Virtex-II Pro
Greg Omond:
    1845: 95/09/09: Protel Libs,XC2000,XC3000
    1846: 95/09/09: Protel Libs,XC2000,XC3000
    1847: 95/09/09: Protel Libs,XC2000,XC3000
    1849: 95/09/09: Protel Libs,XC2000,XC3000
    1848: 95/09/09: Protel Libs,XC2000,XC3000
    1850: 95/09/09: Protel Libs,XC2000,XC3000
Greg Otto:
    40957: 02/03/18: Xilinx : Altera pin compatibility
Greg Peek:
    2760: 96/02/02: Re: Xilinx or Altera for Newbie?
    2841: 96/02/15: Re: re-routing with locked pinout
    3135: 96/04/10: Re: FPGA->ASIC conversion
    4868: 96/12/21: Re: CPLD / VHDL question
    13565: 98/12/09: Re: computer requirements for CAE systems
Greg Pfister:
    28304: 01/01/05: Re: Nondeterministic FSMs in hardware?
Greg Prior:
    9622: 98/03/26: VHDL shareware editor?
Greg Quintana:
    5863: 97/03/20: FIFOs
    6708: 97/06/17: PCI interfaces
    7228: 97/08/16: CDMA corellator
Greg Sajdak:
    8817: 98/01/28: Re: ALtera Devices.
Greg Schmid:
    38564: 02/01/17: Re: ADPCM?
Greg Smith:
    5834: 97/03/19: Re: Complexity of standards
    8173: 97/11/25: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
    8171: 97/11/24: Re: What is the difference between CPLD and FPGA ?
    8172: 97/11/25: Re: what is metastability time of a flip_flop
Greg Steinke:
    50706: 02/12/17: Re: ACEX 1K Configuration Time
    50860: 02/12/20: Re: Programming ACEX1K from FlashEprom
    51338: 03/01/10: Re: In-Rush current in Stratix device
    51340: 03/01/10: Re: Stratix IOE "Input Pin to Input Register Delay"
    52566: 03/02/13: Re: Altera Stratix terminator technology
    52567: 03/02/13: Re: Altera Cyclone EP1C12 pins changed in Quartus 2.2 from 2.1
    53312: 03/03/10: Re: Does ByteBlasterMV support the Cyclone EP1C6 configured for 3.3V I/O?
    53437: 03/03/13: Re: Cyclone power up problem
    53470: 03/03/13: Re: Cyclone power up problem
    55150: 03/04/28: Re: Using Cyclone's PLL
    55367: 03/05/05: Re: Ibis for Cyclone?
    55368: 03/05/05: Re: Output switching time
    55719: 03/05/16: Re: Output switching time
    55815: 03/05/20: Re: Output switching time
    55816: 03/05/20: Re: Altera CPLDs
    56473: 03/06/05: Re: Stapl Player vs. SVF Player
    57286: 03/06/26: Re: Power sequencing on EP20K400E
    57287: 03/06/26: Re: How to get 27MHz from 10 MHz in FPGA???
    57691: 03/07/03: Re: ACEX (EP1K) Power-Up Current
    58354: 03/07/21: Re: Altera ByteBlaster Standalone Programming Utility
    59325: 03/08/14: Re: Multiple device configuration using local update over ethernet
    59404: 03/08/18: Re: Altera JTAG verification
    59456: 03/08/19: Re: Altera JTAG verification
    59507: 03/08/20: Re: IO tco timing differs between Altera Quartus II versions
    59714: 03/08/26: Re: quetions about configure altera fpga(apex20k) using ppa scheme
    59718: 03/08/26: Re: parallel port and cyclone?
    59719: 03/08/26: Re: Problem configuring Cyclone
    59824: 03/08/28: Re: Problem configuring Cyclone
    60290: 03/09/09: Re: question about configue apex20k with ppa scheme
    60326: 03/09/10: Online Troubleshooters
    64063: 03/12/15: Re: Programming Altera MAX 7000E
    64953: 04/01/16: Re: Altera Cyclone Programming device programming
    64955: 04/01/16: Re: Programming and debugging the Altera Cyclone family
    64964: 04/01/16: Re: Faster than a speeding bullet...
    65694: 04/02/04: Re: Power extimation?
    66124: 04/02/12: Re: Configuration Altera Decives using EPC16 in PPS mode
    66143: 04/02/12: Re: How many PCB layers ?
    66512: 04/02/20: Re: Configuration Altera Decives using EPC16 in PPS mode
    66515: 04/02/20: Re: Using 3.3V compliant FPGA for 5V PCI
    66650: 04/02/24: Re: Altera ACEX chip wide reset
    66708: 04/02/25: Re: Altera ACEX chip wide reset
    66765: 04/02/26: Re: JTAG Opcodes for Altera MAX7000S
    66853: 04/02/27: Re: JTAG Opcodes for Altera MAX7000S
    66855: 04/02/27: Re: Altera ACEX chip wide reset
    66942: 04/03/01: Re: Configuring Altera FLEX10KE using EPC2 device
    66943: 04/03/01: Re: Altera ACEX chip wide reset
    67108: 04/03/05: Re: Jitter in DLLs vs PLLs
    67111: 04/03/05: Re: TRST Pin in Altera FPGAs
    67268: 04/03/09: Re: HOW to Increase jitter in ALTERA PLL ?
    67282: 04/03/09: Re: copy protection on FPGA using embedded serial number
    67284: 04/03/09: Re: Altera ACEX chip wide reset
    67285: 04/03/09: Re: Using ALTPLL
    67288: 04/03/09: Re: HOW to Increase jitter in ALTERA PLL ?
    67615: 04/03/15: Re: Altera, Cyclone: pin not connected warning
    67976: 04/03/23: Re: Altera and PCI-X
    67978: 04/03/23: Re: Apparent Altera Cyclone JTAG problem
    69269: 04/05/03: Re: Connecting a crystal to a Cyclone or Max PLD
Greg Stenzoski:
    2503: 95/12/20: VLSI DESIGN AND TEST Short Course at Georgia Tech
    2783: 96/02/07: VLSI DESIGN AND TEST Short Course at Ga Tech
Greg Tate:
    1142: 95/05/04: Register Based VXI device interface
Greg Vanslyke:
    18364: 99/10/19: New to FPGA
Greg Waters:
    1690: 95/08/16: route Lattice ispLSI 1048C with -y pins_file?
Greg Watson:
    12953: 98/11/06: aLTERA 10KA Series PCI question
    109505: 06/09/27: Anyone had success with MIG, DDR2 and V2Pro?
    109553: 06/09/28: Re: Anyone had success with MIG, DDR2 and V2Pro?
<greg.polk@polkservices.net>:
    30709: 01/04/25: Accept credit cards online at only 9.1% service charge 8363
<greg@accupel.com.nospam>:
    110787: 06/10/23: Spartan 3 Configuration Questions
gregben:
    133778: 08/07/14: First CPLD project
Greger G.:
    54742: 03/04/17: Xilinx to process 8-bit paralell binary to ICM7212 for LED display
    55737: 03/05/18: easy design implementation ic's
Gregg C Levine:
    23632: 00/07/04: Re: Which notebook is for you?
    70549: 04/06/20: Is the Xilinix XC3020 atill supported?
    70555: 04/06/20: Re: Is the Xilinix XC3020 atill supported?
    71416: 04/07/18: Re: Xilinx 6.2i ISE WebPACK running under wine?
    76486: 04/12/04: Re: Help! What is this card?
    76506: 04/12/05: JTAG software from OpenWINCE project
Gregg Mack:
    366: 94/10/30: Re: Metastable Immune? (Was: High Bus Drive (24mA) FPGAs/CPLDs?)
<gregneff@my-deja.com>:
    17853: 99/09/14: Re: A mix is best
Gregor Glawitsch:
    3992: 96/08/30: Re: DES in Xilinx
    4856: 96/12/20: Re: Proper target for design
    6811: 97/06/30: Re: Smart Card Design and Interface. How?
    7692: 97/10/03: Re: FPGA multiprocessors
    8177: 97/11/25: Q: Xilinx foundation V1.3 optimizes out my WHOLE design !?!?
<gregorstellpflug@my-deja.com>:
    18352: 99/10/18: Re: Virtex Board
Gregory Burd:
    76990: 04/12/18: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
    77001: 04/12/19: Re: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
    77002: 04/12/19: Re: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
    77023: 04/12/20: Re: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
    77024: 04/12/20: Re: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
    77025: 04/12/20: Re: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
Gregory C. Read:
    8559: 98/01/08: Re: Synthesize large LUT
    12180: 98/10/02: Re: Orcad Capture error DSM0006 and DBO3203
    12187: 98/10/03: Re: Orcad Capture error DSM0006 and DBO3203
    14108: 99/01/13: Re: Orcad Express Plus vs Foundation Express
    25737: 00/09/18: Re: Freelance Designer Needed: Protel & FPGA
    34804: 01/09/08: Re: Actel FPGA glitches
    42057: 02/04/14: Re: FPGA config without boot PROM???
    46594: 02/09/04: Re: Actel Proto Boards
    46617: 02/09/04: Re: Actel Proto Boards
    46857: 02/09/10: Re: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
    48636: 02/10/22: Re: 6502 core available
    50156: 02/12/04: Re: ESD problems
    52326: 03/02/07: Contract Rates?
    53075: 03/03/03: Re: PCB board design software vs outsourcing?
    54037: 03/04/01: Re: Input Characteristics : HCMOS vs TTL
    56179: 03/05/29: Re: Antifuse and SRAM FPGA
    56237: 03/05/31: Re: Xilinx Spartan download with Parallel III cable
    59836: 03/08/29: Re: Moving Sum
    64368: 03/12/31: Re: 4-bit binary divider circuit PLEASE!!!!!!!
    66069: 04/02/12: Re: Sine Wave Generation
    66075: 04/02/12: Re: How many PCB layers ?
    68347: 04/04/01: Re: Actel tools (Designer and others) - command line driven compilation?
    68424: 04/04/04: Re: The Logic Behind License Renewal
    69606: 04/05/15: Re: Clueless newbie question -- what has changed to make moisture such an issue?
    72170: 04/08/10: Re: let me have logic design for traffic light
    72751: 04/08/31: Re: From good-old ISA bus cards to PCI bus
    72884: 04/09/07: Re: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
    72945: 04/09/08: Re: PCI Noise
    73553: 04/09/23: Re: 5V Tolerant?
    74227: 04/10/06: Re: ActGen to use or not to use?
    74485: 04/10/12: Re: Actel Fusefile Reverse Engineering
    75911: 04/11/19: Re: Suggestion for Xilinx parallel port cable replacement.
    77498: 05/01/08: Re: Showing schematic changes
    78357: 05/01/30: Re: Actel A54SX72A - FF with clear and preset? Necessary for triple redundant register
    81554: 05/03/27: Re: reset on startup
    86301: 05/06/24: Re: LVTTL Spec
    88440: 05/08/18: Re: Easy USB2.0 hi-speed device solutions ?
    93057: 05/12/13: Re: How can I surpress noise in an ADC board?
    100814: 06/04/18: Re: FPGA availability & distribution options.
    104836: 06/07/07: Re: debouncing a switch (in hardware)
    118046: 07/04/16: Re: License Key based on WLAN/Bluetooth MAC
    135042: 08/09/12: Re: errors in schematics
Gregory Estrade:
    138285: 09/02/12: Re: Logic Analyzer
    138292: 09/02/13: Re: Logic Analyzer
    138295: 09/02/13: Re: Logic Analyzer
    138330: 09/02/16: Re: Logic Analyzer
    139912: 09/04/19: Re: Atari VCS 2600 FPGA Cartridge
    139935: 09/04/20: Re: Atari VCS 2600 FPGA Cartridge
    145392: 10/02/08: Re: using an FPGA to emulate a vintage computer
Gregory M. Haskins:
    5840: 97/03/19: Lattice software
    6435: 97/05/23: RE: Reverse Engineering
Gregory Smith:
    5919: 97/03/26: Re: Safety Critical Apps -> Xilinx Checker.
    7701: 97/10/04: Re: Xilinx license idiocy
    7941: 97/11/01: Re: Division & Multiplication (unsigned/signed) - Need HELP
    7940: 97/11/01: Re: Polynomial division tool for LFSR/MISR simulation
    8049: 97/11/11: Re: Where can I find documents talking about constraining FPGA?
Gregory Titievsky:
    61822: 03/10/13: Clock doesn't seem to work on Xilinx CoolRunner XPLA3
Gregory Toomey:
    81131: 05/03/18: Re: How much current does an LED take?
<gregs@altera.com>:
    79664: 05/02/22: Re: Is Altera Cyclone a good choice ?
    84697: 05/05/24: Re: Altera Apex20KE PLL output jitter problem
    92740: 05/12/05: Re: Clock problem? Altera Stratix-II ES and MP
    97796: 06/02/27: Re: How to use Gigabit transciever
    118301: 07/04/23: Re: Altera MPM7064LC84 vs EPM7064LC84
gretzteam:
    77919: 05/01/20: Asic prototyping in Fpga - prototyping the gates.
    77935: 05/01/20: Re: Asic prototyping in Fpga - prototyping the gates.
    77976: 05/01/21: Re: Asic prototyping in Fpga - prototyping the gates.
    79823: 05/02/24: Fast 28x28 multiplier + adder in Virtex4
    79870: 05/02/25: Re: Fast 28x28 multiplier + adder in Virtex4
    79908: 05/02/25: Re: Fast 28x28 multiplier + adder in Virtex4
    80082: 05/03/01: Re: Fast 28x28 multiplier + adder in Virtex4
    84457: 05/05/19: Re: Which Simulators
    100481: 06/04/10: Register Map coding style
<gretzteam@hotmail.com>:
    92401: 05/11/29: first time managing a project
Grey Beard:
    95804: 06/01/26: SDRAM Controller
<greywolf82@hotmail.it>:
    119901: 07/05/29: Linux device driver for FPGA Xilinx Virtex-4
    119902: 07/05/29: Linux device driver for FPGA Xilinx Virtex-4
    119910: 07/05/29: Re: Linux device driver for FPGA Xilinx Virtex-4
Griffin:
    142221: 09/07/29: Implementing VHDL code in an embedded processor design and readout to
    142226: 09/07/29: Re: Implementing VHDL code in an embedded processor design and
    142251: 09/07/30: Re: Implementing VHDL code in an embedded processor design and
    142271: 09/07/31: Re: Implementing VHDL code in an embedded processor design and
    142310: 09/08/03: Re: Implementing VHDL code in an embedded processor design and
    144174: 09/11/17: Error:Place:645 on a non-clock pin.
    144215: 09/11/20: Re: Error:Place:645 on a non-clock pin.
    144221: 09/11/20: Re: Error:Place:645 on a non-clock pin.
    144255: 09/11/23: Re: Error:Place:645 on a non-clock pin.
    144641: 09/12/21: Configuring the ML402
    144663: 09/12/21: Re: Configuring the ML402
    144684: 09/12/22: Re: Configuring the ML402
    144687: 09/12/22: Re: Configuring the ML402
    144809: 10/01/05: Why are my pins being removed? LIT:243 and MapLib:701 warnings
    144870: 10/01/10: Solved! Why my pins were being optimized out. How do I get the
    144987: 10/01/18: Using a timer in EDK 11.
    146991: 10/04/08: Cannot download ELF; I-Side Memory Access Check Failed
    146993: 10/04/08: Re: Cannot download ELF; I-Side Memory Access Check Failed
    148050: 10/06/16: Expand TEMAC fifo?
    148064: 10/06/17: Re: Expand TEMAC fifo?
    148079: 10/06/18: Re: Expand TEMAC fifo?
    149503: 10/10/31: Timing error for EDK project using a DCM?
    149509: 10/11/01: Re: Timing error for EDK project using a DCM?
    149533: 10/11/02: Re: Timing error for EDK project using a DCM?
grigio:
    144810: 10/01/06: Re: ASM hardware language definition file for Altera/Xilinx
<grigsoft@gmail.com>:
    103710: 06/06/08: Re: Good free or paid merge software that edits two similar files?
GrIsH:
    136930: 08/12/14: i2c interface
    136955: 08/12/15: Re: i2c interface
    136956: 08/12/15: Re: i2c interface
    136960: 08/12/15: Re: i2c interface
    137349: 09/01/10: what is the difference between two process model & one process model
    137837: 09/01/31: how can we connect the two buses of different width
    138080: 09/02/05: How to divide clock frequency......
    138155: 09/02/08: offtnproblem during ise synthesis
    138179: 09/02/08: Re: How to divide clock frequency......
    138234: 09/02/10: problem in place and route
    138235: 09/02/10: Re: offtnproblem during ise synthesis
    138354: 09/02/17: Problem using external clock!!!!!
    141378: 09/06/22: problem with XPS and SDK!!
    143426: 09/10/11: problem while receiving negative integer in microblaze
    143473: 09/10/12: Re: problem while receiving negative integer in microblaze
    143485: 09/10/12: Re: problem while receiving negative integer in microblaze
    143532: 09/10/14: Re: problem while receiving negative integer in microblaze
    143757: 09/10/23: Re: problem while receiving negative integer in microblaze
    143778: 09/10/25: Re: problem while receiving negative integer in microblaze
    143780: 09/10/25: Re: problem while receiving negative integer in microblaze
    143782: 09/10/25: Re: problem while receiving negative integer in microblaze
Griva:
    65708: 04/02/05: Re: Comparison of the Co-verification tools for SoC/ASIC
    65709: 04/02/05: The fastest interface between FPGA's
    65713: 04/02/05: Re: The fastest interface between FPGA's
GrizzlySteve:
    146191: 10/03/07: Re: Looking for a USB JTAG cable
    152230: 11/07/25: Re: Issues with Soft-Cores
    152323: 11/08/08: Re: image storing into BRAM
    152330: 11/08/09: Re: image storing into BRAM
grky:
    130592: 08/03/27: need help.....how do i download an image onto a virtex 4 fpga
Grog:
    46076: 02/08/16: Xilinx iMPACT/Parallel Port programming in Win XP soloution?
    46395: 02/08/28: My SpartanII thinks it's a Virtex??
grohss:
    38408: 02/01/14: variable declare
Gromer:
    89088: 05/09/05: Nand Flash Emulator
grouchy:
    95452: 06/01/23: Re: need for a group FAQ?
Grubi:
    129914: 08/03/10: Virtex-4 VLX25 DCM problem
    129928: 08/03/10: Re: Virtex-4 VLX25 DCM problem
    129929: 08/03/10: Re: Virtex-4 VLX25 DCM problem
    129930: 08/03/10: Re: Virtex-4 VLX25 DCM problem
    129980: 08/03/12: Re: Virtex-4 VLX25 DCM problem
    130083: 08/03/14: Re: Virtex-4 VLX25 DCM problem
    130086: 08/03/14: Re: Virtex-4 VLX25 DCM problem
GrueblsAndi:
    41562: 02/04/01: Virtex-II Pro: Rocket I/O termination power supply
Grumps:
    26431: 00/10/16: Re: 5V compatible Virtex
    26441: 00/10/16: Re: 5V compatible Virtex
    26561: 00/10/20: Re: 5V compatible Virtex
    124777: 07/10/04: FFT core
    124797: 07/10/04: Re: FFT core
    124801: 07/10/04: Re: FFT core
    124887: 07/10/09: Re: FFT core
    129049: 08/02/13: State machine outputs and tri-state
    129054: 08/02/13: Re: State machine outputs and tri-state
    129085: 08/02/14: Re: State machine outputs and tri-state
    129086: 08/02/14: Re: Erratic Behavior of Virtex 4 FPGA
    129088: 08/02/14: Re: State machine outputs and tri-state
    129090: 08/02/14: Re: State machine outputs and tri-state
grunzasr:
    146441: 10/03/18: Re: Any Experiences with the GN4124 PCI Express - FPGA bridge?
grupa1:
    82156: 05/04/07: ADPCM IP core
grupy:
    90845: 05/10/22: Re: Simulation : EDK
gruve5112:
    143510: 09/10/13: PLB Master writing to DDR Ram
Grzegorz:
    21851: 00/04/04: JTAG programming
    21877: 00/04/05: Re: JTAG programming
    21904: 00/04/06: Re: JTAG programming
Grzegorz Apczynski:
    13574: 98/12/10: Re: Why doesn't Xilinx's simulator work?
    13866: 98/12/30: Re: Aldec integration
Grzegorz Kasprowicz:
    72755: 04/08/31: VirtexII Pro Evaluation Kit from Avnet
    73271: 04/09/17: Re: problem with ALtera CPLD
    73305: 04/09/18: Re: problem with ALtera CPLD
Grzegorz Labiak:
    15904: 99/04/20: Question about Statechart
Grzegorz Mazur:
    67632: 04/03/16: Re: Schematic Edition Tool : Suggestions
Grzegorz Plywacz:
    151837: 11/05/23: Problem with Xilinx 10.1 PowerPC simulator
Grégory HERMANT:
    43491: 02/05/22: xc2v-6000 FF1152 orcad symbol ???
gs:
    13219: 98/11/20: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
    13323: 98/11/25: Re: Synchronous SRAM design wanted
    13324: 98/11/25: Re: VHDL->boolean equation
    13325: 98/11/25: Re: daisy chain help!!!!
    13326: 98/11/25: Re: Which parts are fastest for 3-state enables?
    13462: 98/12/03: Re: Which parts are fastest for 3-state enables?
    13626: 98/12/14: Re: Documention AHDL?
GSB:
    13030: 98/11/12: Help with identifying possible programmable logic chip
    13092: 98/11/15: Re: Help with identifying possible programmable logic chip
    13546: 98/12/09: Thanks to wonderful support from this group
<gseegmiller@gmail.com>:
    120422: 07/06/06: No output while booting ML403 board
    120462: 07/06/07: Re: No output while booting ML403 board
    120836: 07/06/18: No serial output while booting a Xilinx ML403 board
    120885: 07/06/19: Re: No serial output while booting a Xilinx ML403 board
<gsinfo@gefen.com>:
    32805: 01/07/09: DVI to ADC Conversion Box 8968
GSM User:
    69736: 04/05/19: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
<gsosar@gmail.com>:
    114821: 07/01/24: ML403 board - VGA schematics - wrong pins
    114878: 07/01/25: Re: ML403 board - VGA schematics - wrong pins
    114883: 07/01/25: Re: ML403 board - VGA schematics - wrong pins
GT:
    81593: 05/03/28: What type of IO to use
    81612: 05/03/28: Re: What type of IO to use
<gt7522b@acmex.gatech.edu>:
    2125: 95/10/18: Re: Xilinx Configuration Memory Hacking
GTE news:
    11082: 98/07/17: Re: Floorplanning Intro?
gtwrek@pacbell.net:
    130197: 08/03/17: Re: Virtex-5 FX when ? (III)
    134584: 08/08/19: Re: why does inferred RAM cause synthesis times to explode?
<gtwrek@pacbell.net>:
    116827: 07/03/19: Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*
Gu Feng:
    8842: 98/02/01: can u give me some advice?
guards:
    139253: 09/03/24: chipscope pro 9.2i can't triger immediately !
Guenter:
    87720: 05/07/29: Re: XST and TCL support?
    87750: 05/07/30: Re: ISE webpack doesnt support Spartan xcs10, solution??
    89773: 05/09/26: Re: "Free" core and license
    90365: 05/10/11: Re: iVerilog / VVP output to GTKwave.
    108982: 06/09/19: Re: Hilbert Transform in verilog or VHDL -- it has got to be out there somewhere
    110477: 06/10/16: Re: OT: Internships?
    113889: 06/12/28: Re: What next next big thing coming for HDL?
    113895: 06/12/28: Re: What next next big thing coming for HDL?
    113996: 07/01/02: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
    114231: 07/01/08: Re: Build an FPGA programmer cable
    114800: 07/01/24: book recommendation for self study in digital logic design
    114802: 07/01/24: Re: Good hardware design code re-use strategies, reference book
    114888: 07/01/25: Re: book recommendation for self study in digital logic design
    115929: 07/02/26: Re: Xilinx Platform cable USB and impact on linux without windrvr
    116528: 07/03/12: Re: Estimating number of FPGAs needed for an application
    117201: 07/03/26: Re: Where is Open Source for FPGA development?
    117248: 07/03/27: Re: how to read a sequence of video
    120868: 07/06/19: Re: How to simulate testbenches using the ISE simulator in linux
    124405: 07/09/20: Re: Free downloadable PDF graph paper.
guenter:
    153327: 12/02/01: Difference between Xilinx isim and modelsim
    153328: 12/02/01: Re: =?ISO-8859-1?Q?Post=2Dsynth=E8se_simulation?=
Guenter Dannoritzer:
    69286: 04/05/04: Re: Ethernet & FPGA
    69826: 04/05/21: How to handle different proccessing speeds?
    69852: 04/05/22: Re: How to handle different proccessing speeds?
    70812: 04/06/29: Re: FPGA jobs in Germany
    72490: 04/08/20: Help, synthesis for Spartan XL; does FPGA Express licenses for ISE
    72518: 04/08/23: Re: Help, synthesis for Spartan XL; does FPGA Express licenses for
    72757: 04/08/31: Synthesize verilog code with Icarus for Spartan?
    73475: 04/09/22: Re: How feasible is a SoC project?
    74784: 04/10/19: Re: Xilinx Virtex II MAC & PHY. ( HELP)
    76289: 04/11/30: Config Spartan3 in serial slave mode
    76305: 04/11/30: Re: Config Spartan3 in serial slave mode
    82667: 05/04/16: ISE 7.1 GUI (slightly OT)
    122801: 07/08/07: Re: Digilent USB module linux
    124793: 07/10/04: Re: FFT core
    124889: 07/10/09: Re: FFT core
    124902: 07/10/10: Re: FFT core
    124903: 07/10/10: Re: Xcell Article on 1.2Gsamples/sec FFT
    126071: 07/11/14: Re: VCD Files Viewer?
    126075: 07/11/14: Re: FPGA for hobby use
    126191: 07/11/16: Re: TI DSP soft core in Xilinx?
    126942: 07/12/06: Re: student requiring assistance :)
    127711: 08/01/06: Re: How to connect a LED with a clock?
    131914: 08/05/07: Re: Getting started with VHDL and Verilog
    132155: 08/05/16: Re: Open source Core generators?
    132862: 08/06/09: Re: readmem[b|h]
    136163: 08/11/04: Re: 2D DCT algorithm
Guenter Strubinsky:
    11582: 98/08/25: Re: Porn spamming
    11583: 98/08/25: Re: Porn spamming
Guenter Wolpert:
    58931: 03/08/04: how to protect own IP in Xilinx ISE
    85911: 05/06/17: Re: Xlinix configuration: DONE pin too early?
Guenther Wenninger:
    157850: 15/04/20: Directly connect two XAUI ports inside FPGA
    157866: 15/04/28: Re: Registered signal synchronizer [was: Directly connect two XAUI
Guerre:
    44894: 02/07/04: 3.3 volt tolerance in Virtex-II Pro?
    45836: 02/08/07: Re: AES (rijndael) Ip core
guest:
    57537: 03/07/02: Regarding NRZ
    57629: 03/07/03: Re: Regarding NRZ
Guest:
    13277: 98/11/23: FPGA vs. CPLD
    57704: 03/07/03: information required
    57736: 03/07/04: Re: information required
Guest Internet User:
    25874: 00/09/23: Xilinx Student Edition 2.1i with "Digital Design:Principles and
    25911: 00/09/25: Re: Xilinx Student Edition 2.1i with "Digital Design:Principles and
guestuser1:
    136267: 08/11/07: Re: Altera Quartus II 8.1 (and Modelsim AE 6.3g)
    136268: 08/11/07: Re: Linux on Microblaze
    136269: 08/11/07: Synplicity/Synplify and Systemverilog support?
guhaoqi:
    71136: 04/07/09: comparison between FPGA and computer
    71173: 04/07/10: Re: A simple VHDL question
Guibert, Martin:
    27664: 00/12/01: xilinx NGDanno
    28997: 01/02/01: Virtex PCI Core problem
    29196: 01/02/09: Low skew lines in Virtex-E
    30095: 01/03/22: Help! DLL Feedback in Virtex-E
Guido:
    73700: 04/09/28: Re: How to design a programming parallel cable
    73537: 04/09/23: How to design a programming parallel cable
    73617: 04/09/26: Re: How to design a programming parallel cable
    94301: 06/01/09: Re: about the ftp.altera.com
    99689: 06/03/28: Bidirectional signals with Altera Signaltap
    100128: 06/04/04: Re: Bidirectional signals with Altera Signaltap
Guido Pohl:
    19014: 99/11/24: MACH445 - parallel port programming cable
    19015: 99/11/24: Re: MACH445 - parallel port programming cable
    21253: 00/03/14: Is there a chance to synthesize that?
    27944: 00/12/16: questions regarding external setup & hold time considerations
    32409: 01/06/26: BUFGs in an XC4000EX
    43957: 02/06/07: Re: FPGA destruction vs power management
Guillaume:
    40355: 02/03/05: FPGA exp with "timing constraint export"
Guillaume SZCZYGIEL:
    9832: 98/04/08: FLEX 10K : FPGA or CPLD
guille:
    64183: 03/12/19: predictable timing for xilinx cpld?
    64311: 03/12/27: Re: predictable timing for xilinx cpld?
    64328: 03/12/28: Re: predictable timing for xilinx cpld?
    64329: 03/12/28: Re: predictable timing for xilinx cpld?
    64336: 03/12/29: Re: predictable timing for xilinx cpld?
    64350: 03/12/29: Re: predictable timing for xilinx cpld?
    64356: 03/12/30: Re: predictable timing for xilinx cpld?
    64546: 04/01/07: Re: predictable timing for xilinx cpld?
    64582: 04/01/08: min propagation delay in xilinx cpld
    64708: 04/01/12: Re: min propagation delay in xilinx cpld
    64709: 04/01/12: Re: min propagation delay in xilinx cpld
    64758: 04/01/13: 'universal delay' term in Xilinx parts
    64846: 04/01/15: Gray encoding for FSM
    64914: 04/01/16: Re: Gray encoding for FSM
    64915: 04/01/16: Re: Gray encoding for FSM
    65170: 04/01/21: xilinx 70% tracking rule
    65213: 04/01/22: Re: xilinx 70% tracking rule
    66015: 04/02/11: NAND flash interface?
Guillermo:
    104677: 06/07/03: UCF File : LOC signal syntax
Guirico C.:
    130254: 08/03/18: Using TimeQuest Timing Analyzer
Guitar Man:
    9499: 98/03/18: Re: Ideas for an FPGA Project?
    9512: 98/03/19: Re: Ideas for an FPGA Project?
Guitarman:
    72908: 04/09/07: how to get the data from ADC
    72975: 04/09/09: Picoblaze VHDL Code Block diagram
    74309: 04/10/07: Re: XILINX SHIPS ONE MILLION SPARTAN-3 FPGAS
    74655: 04/10/15: How many Altera LE's to Xilinx Slices????
GuiWoo,KIM:
    11226: 98/07/28: [Q]ALTERA DEVICE - EPF10K10LC84-4 ??
Gunnar Alm:
    9221: 98/03/03: Xilinx XC5206 driving dedicated input pins
Gunnar Tufte:
    26879: 00/11/02: Re: Pwer supply for a XCV300. Recommendations please.
Gunter =?iso-8859-1?Q?F=F6ttinger?=:
    20047: 00/01/25: Combination of FPGA and DSP
Gunter Knittel:
    75579: 04/11/10: Overshoot/undershoot towards 2V4000
    75630: 04/11/11: Re: Overshoot/undershoot towards 2V4000
    75631: 04/11/11: Re: Overshoot/undershoot towards 2V4000
    75760: 04/11/14: Re: Overshoot/undershoot towards 2V4000
    75765: 04/11/14: Driving towards 2V4000 during Power up
    83854: 05/05/08: Fake Buffers in ECS
    84184: 05/05/13: Re: Fake Buffers in ECS
    84186: 05/05/13: Virtex-II Switch Matrix Performance
    84414: 05/05/18: Re: Virtex-II Switch Matrix Performance
    91855: 05/11/15: Research Position
    91869: 05/11/15: Re: Research Position
    91945: 05/11/17: Re: Suggestions on good books
    91998: 05/11/18: Re: Suggestions on good books
Gunther:
    39084: 02/01/31: WebPack 4.1 ISE Errors with Insight Demo files
Gunther Lehmann:
    469: 94/11/28: --- Libraries free of charge ---
Gunther Mannigel:
    87647: 05/07/27: Re: simulatable but not synthesizable (verifiable)
    92493: 05/11/30: Re: Unconnected Ports
Gunther May:
    35988: 01/10/25: GAL compiler
    36697: 01/11/16: Pinning in Lattice Design Expert
    36928: 01/11/26: Simple Logic State Analyser
    36962: 01/11/27: Re: Simple Logic State Analyser
    38702: 02/01/22: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
    38732: 02/01/23: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
    39579: 02/02/13: Problem with Lattice Design Expert Starter
    41861: 02/04/09: Freeware EDIF viewer
<guochenglv@gmail.com>:
    126995: 07/12/07: the FPGA gate way
Guosheng Wu:
    152459: 11/08/25: The smallest EDA tool
Gupreet S. Bhullar:
    2033: 95/10/04: Prohibit Local lines during routing ?
Gupta:
    71895: 04/08/03: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    71949: 04/08/04: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    71952: 04/08/04: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    71972: 04/08/04: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    72000: 04/08/05: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
<gupta.gaurav@gmail.com>:
    82807: 05/04/18: Tutorial on FPGAs
Gurpreet S. Bhullar:
    3511: 96/06/12: Wanted Info on faults in FPGAs
    3837: 96/08/08: Using Carry logic in XC4000...
    4412: 96/10/25: 4K Carry Logic & XAPP NOTE...
Guru:
    90455: 05/10/13: Xilinx EDK : mb-gcc linker errors with C++ features
    99630: 06/03/27: OPB IPIF Master Support
    99688: 06/03/28: Re: OPB monitor error
    99807: 06/03/29: Re: OPB monitor error
    99809: 06/03/29: Re: problem with IO in EDK 8.1
    100205: 06/04/05: Re: DMA with EDK
    100206: 06/04/05: Re: done pin didn't go high
    100311: 06/04/06: Re: problem with IO in EDK 8.1
    100325: 06/04/06: Re: Virtex-4 Gigabit Ethernet design
    100326: 06/04/06: OPB master
    100353: 06/04/07: Re: Someone need to port LwIP to ll_temac core/wrapper?
    100355: 06/04/07: Re: OPB master
    100358: 06/04/07: Re: OPB master
    100363: 06/04/07: Re: OPB master
    100548: 06/04/11: Re: spartan-3 starter kit board
    100837: 06/04/19: Re: FPGA + FTDI
    100922: 06/04/21: Re: Virtex-4 Gigabit Ethernet design
    101069: 06/04/25: Re: Virtex-4 Gigabit Ethernet design
    101566: 06/05/03: Re: OPB Clocking Question
    101879: 06/05/08: Re: Opteron HT coprocessors
    102468: 06/05/16: Re: Microblaze dcm_module problems
    102471: 06/05/16: Virtex4 FX12 dynamic clock divider
    102513: 06/05/17: Re: Virtex4 FX12 dynamic clock divider
    102517: 06/05/17: Re: Virtex4 FX12 dynamic clock divider
    102524: 06/05/17: Re: Virtex4 FX12 dynamic clock divider
    102700: 06/05/19: Re: Virtex4 FX12 dynamic clock divider
    102970: 06/05/24: Re: someone used FIFO along with the OPB-bus in FPGA ?
    103158: 06/05/26: Re: Xilinx IP wizard help
    103227: 06/05/29: Re: Xilinx IP wizard help
    103228: 06/05/29: Re: Peripheral connected to multiple OPB buses
    103577: 06/06/06: Re: Jtag Programmer
    103826: 06/06/12: Virtex4 DCM in DRP mode
    103844: 06/06/13: Re: Virtex4 DCM in DRP mode
    104601: 06/06/30: Re: Problem to extend Xilinx GSRD Design
    104602: 06/06/30: Re: EDK: Using DCR bus on ML310-based project
    104611: 06/07/01: Re: Problem to extend Xilinx GSRD Design
    104690: 06/07/04: Re: Problem to extend Xilinx GSRD Design
    104723: 06/07/05: Re: Xilinx ML403 hard mac (xapp443)
    104725: 06/07/05: Re: PPC and Chipscope?
    104769: 06/07/05: Re: PLB master without xilinx ipif
    104770: 06/07/05: Incorporating CoreGen files in EDK 8.1 peripheral
    104789: 06/07/06: Re: Incorporating CoreGen files in EDK 8.1 peripheral
    104858: 06/07/07: Virtex4 Mini-Module GBL Phy
    104873: 06/07/07: Re: Virtex4 Mini-Module GBL Phy
    105155: 06/07/14: Virtex4 Mini-Module Phy interrupt
    105551: 06/07/25: uClinux on Virtex-4 Mini-Module
    105566: 06/07/26: Re: uClinux on Virtex-4 Mini-Module
    105567: 06/07/26: Re: uClinux on Virtex-4 Mini-Module
    105592: 06/07/26: Re: uClinux on Virtex-4 Mini-Module
    105779: 06/07/31: S3E USB2.0 port
    105805: 06/08/01: Re: S3E USB2.0 port
    106065: 06/08/07: Re: Who is your favourite FPGA guru?
    106067: 06/08/07: Re: virtex ppclinux files
    106273: 06/08/10: EDK peripherals and CoreGen netlists
    106296: 06/08/10: Re: EDK peripherals and CoreGen netlists
    106485: 06/08/14: Re: OPB_IPIF, too many versions...
    106746: 06/08/18: Re: EDK vs. ISE for image processing
    106748: 06/08/18: Re: EDK vs. ISE for image processing
    106750: 06/08/18: Re: EDK vs. ISE for image processing
    106800: 06/08/19: Re: tcp/ip
    108106: 06/09/05: Re: DMA on Virtex-4 using PPC
    108107: 06/09/05: Re: EDK 7.1
    108633: 06/09/14: Re: Spartan3E availability
    108634: 06/09/14: Re: SoC Development Board
    108635: 06/09/14: Re: removing Ethernet_MAC kills mini-module project
    109982: 06/10/09: ISE/EDK computer selection
    110456: 06/10/16: Re: SPAM or Not - Re: Platform USB Cable schematic
    110783: 06/10/23: Re: Potential problem w/EDK's Microblaze and the Spartan-3E Starter Kit?
    110784: 06/10/23: Re: Potential problem w/EDK's Microblaze and the Spartan-3E Starter Kit?
    110823: 06/10/24: Re: Camera link specification
    110862: 06/10/24: Re: DDR SDRAM access with MPMC2, Databus Width
    110863: 06/10/24: S3ESK JTAG
    111106: 06/10/29: Re: A pre-emptive strike against blaming the chip
    111107: 06/10/29: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    111305: 06/11/01: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    111449: 06/11/03: Re: DDR_controller_EDK
    111803: 06/11/10: opb_ddr
    111979: 06/11/14: Re: MPMC2: MPMC2 with DDR2 SDRAM
    112920: 06/12/01: Re: Opencores DDR SDRAM controller
    113018: 06/12/05: Re: XEM3010
    113084: 06/12/06: Re: Xilinx MPMC2 "External Ports" question
    113186: 06/12/07: Re: Xilinx MPMC2 "External Ports" question
    113726: 06/12/20: Re: Spartan 3E Starter Kit Woes
    114033: 07/01/03: Re: OT. Re: Surface mount ic's
    114034: 07/01/03: PPC cache errata
    114035: 07/01/03: Re: ERROR:NgdBuild:604
    114073: 07/01/04: Re: PPC cache errata
    114099: 07/01/04: Re: PPC cache errata
    114129: 07/01/05: Re: ERROR:NgdBuild:604
    114436: 07/01/16: Re: 16-bit DDR memory controller in EDK
    118065: 07/04/17: Re: PLB Master
    118884: 07/05/05: Re: OPB Master Peripheral
    118953: 07/05/08: Re: lwIP RAW mode support for V4 temac
    118999: 07/05/09: Re: lwIP RAW mode support for V4 temac
    119066: 07/05/10: Re: lwIP RAW mode support for V4 temac
    119214: 07/05/15: Re: Xilinx EDK: Slow OPB write speeds
    119275: 07/05/16: Re: Xilinx EDK: Slow OPB write speeds
    119850: 07/05/28: Re: low speed communication
    119887: 07/05/29: Re: MPMC2 + flash bootloader problem
    119888: 07/05/29: Re: Looking for experiences with SUZAKU SZ010/SZ030
    119931: 07/05/29: Re: MPMC2 + flash bootloader problem
    119961: 07/05/30: Re: Has anyone used Sundance Boards?.
    119962: 07/05/30: Re: Looking for experiences with SUZAKU SZ010/SZ030
    120016: 07/05/31: Re: FIR Filter ON FPGA
    120917: 07/06/20: Re: Linux 2.6.20 on MicroBlaze now available
    121472: 07/07/05: Re: Add DMA support to a custom core?
    121580: 07/07/09: Re: Power PC Reference Design timing failed
    121581: 07/07/09: Re: Add DMA support to a custom core?
    122132: 07/07/19: DDR2 vs SDR on Spartan3
    122134: 07/07/19: SDRAM vs DDR2 on Spartan3E
    122140: 07/07/20: Re: DDR2 vs SDR on Spartan3
    122754: 07/08/06: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122797: 07/08/07: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122840: 07/08/08: Re: TEMAC Performance Issues with Virtex 4FX
    122880: 07/08/09: Re: SDR SDRAM controller for Xilinx Spartan-3E
    122881: 07/08/09: Re: Write of 64 from PowerPC to my IP conected to the PLB?
    123310: 07/08/23: Re: how to bidirectional signal in xilinx EDK tool ?
    123556: 07/08/30: Spartan3E and DDR termination
    123698: 07/09/02: Re: Spartan3E and DDR termination
    123987: 07/09/10: Re: high bandwitch ethernet communication
    124711: 07/10/01: Spartan3E DDR clock feedback
    125329: 07/10/22: Re: ISE or EDK?
    125419: 07/10/25: Re: MPMC2 NPI Help!
    125474: 07/10/26: Re: builing a SPI interface in vhdl
    125475: 07/10/26: Re: MPMC2 NPI Help!
    126277: 07/11/19: Re: New Laptop for work
    127286: 07/12/17: Debugging EDK DDR interface
    127839: 08/01/09: MPMC3, DDR 32Mx16, S3E1200, single bank, impossible?
    127883: 08/01/09: Re: MPMC3, DDR 32Mx16, S3E1200, single bank, impossible?
    127904: 08/01/10: Re: MPMC3, DDR 32Mx16, S3E1200, single bank, impossible?
    129194: 08/02/18: Re: Ballpark PLB frequency
    129223: 08/02/19: Re: Ballpark PLB frequency
    129224: 08/02/19: Re: Ballpark PLB frequency
    129825: 08/03/06: Re: EDK 9.2 MicroBlaze Tutorial and SDRAM TestApp_memory
    131979: 08/05/09: Re: AHB and APB master VHDL generator
    133451: 08/06/30: Re: EDK DMA peripherals?
    133574: 08/07/04: Re: OPB_CENTRAL_DMA
    133626: 08/07/07: Re: basic chipscope pro query
    133649: 08/07/08: Re: OPB_CENTRAL_DMA
    134490: 08/08/13: Re: Microblaze Projects
    144104: 09/11/11: 1.8V LVDS on spartan3A DSP
    144105: 09/11/11: Re: 1.8V LVDS on spartan3A DSP
    144125: 09/11/12: Re: 1.8V LVDS on spartan3A DSP
    144643: 09/12/21: Re: multiprocessor on spartan 3
    144645: 09/12/21: H.264 on Spartan3A DSP
Guru Prasad:
    101554: 06/05/02: detailed description on the archetecture of FPGA's/CPLD's
Gus Baldauf:
    64008: 03/12/11: Xilinx 6.1i Tools and Newer Redhat Linux OSes
    64123: 03/12/17: Re: Xilinx 6.1i Tools and Newer Redhat Linux OSes
    64128: 03/12/17: Re: Xilinx 6.1i Tools and Newer Redhat Linux OSes
    64129: 03/12/18: Re: Xilinx 6.1i Tools and Newer Redhat Linux OSes
    64143: 03/12/18: Re: Xilinx 6.1i Tools and Newer Redhat Linux OSes
Gush Bhumbra:
    1410: 95/06/18: Re: Understanding Lattice equations
Gustav Jindra:
    29392: 01/02/18: XILINX WebPACK
GUSTAVO D. BOTVINIKOFF:
    8617: 98/01/13: Altera and Xilinx
guy:
    38340: 02/01/11: Re: Picking an FPGA
    44413: 02/06/19: probs with...
    96910: 06/02/13: xilinx ise 8.1 mig 1.4 /1.5
    126896: 07/12/05: why do i see negative clock hold time
Guy:
    45414: 02/07/22: Re: anyone get email about www.cradle.com ???
    52421: 03/02/08: Win CE or CE.NET
    73826: 04/09/30: Re:ELABORATED DISCLOSURE and continued discussion : NV on-chip memory?
    73835: 04/09/30: Re: ELABORATED DISCLOSURE and continued discussion : NV on-chip memory?
    73838: 04/09/30: Re: ELABORATED DISCLOSURE and continued discussion : NV on-chip memory?
    73705: 04/09/28: Re: NV on-chip memory?
    73796: 04/09/29: Re: NV on-chip memory?
    73797: 04/09/29: Re: NV on-chip memory?
    73815: 04/09/29: DISCLOSURE : NV on-chip memory?
    73675: 04/09/27: NV on-chip memory?
Guy Eschemann:
    18525: 99/10/28: Re: Duty-cycle change in Virtex
    27252: 00/11/16: Re: 5v parallel cable with 2.5/3.3v spartan II?
    40320: 02/03/05: digital video PLL
    40343: 02/03/05: Re: digital video PLL
    50041: 02/11/29: SDRAM technology
    61501: 03/10/06: Should I worry about metastability
    61521: 03/10/06: Re: Should I worry about metastability
    61571: 03/10/07: Re: Should I worry about metastability
    62164: 03/10/21: Re: Should I worry about metastability
    66156: 04/02/13: Using DLL "locked" output as a global reset signal ?
    71303: 04/07/14: Re: extending a signal pulse
    71313: 04/07/14: extending a signal pulse
    71874: 04/08/03: Re: ChipScope Pro Loading Memory
    71937: 04/08/04: Re: Guidelines for Timing Closure on FPGAs
    72572: 04/08/25: Re: Xilinx version ROM with automatic increment
    116889: 07/03/20: Using xilkernel with C++
    117106: 07/03/23: Re: Using xilkernel with C++
    129592: 08/02/28: Re: Making changes to custom IP in EDK
    132274: 08/05/20: Re: Problem with Scheduler in Xilkernel.
    144025: 09/11/08: Sinewave generation
    144056: 09/11/09: Re: Sinewave generation
    144057: 09/11/09: Re: Sinewave generation
    144059: 09/11/09: Re: Sinewave generation
    145577: 10/02/14: How relevant is the Residue Number System (RNS)?
    147122: 10/04/14: Re: Read from the compact flash
    149034: 10/09/23: Tool for automatically generating Microblaze peripheral registers
    151881: 11/05/28: Re: Best syntheses
    152176: 11/07/15: Re: Area optimization (optimizing DSP48E usage)
    152177: 11/07/15: Re: RTL timing issue
    152183: 11/07/16: Re: RTL timing issue
    152720: 11/10/09: Re: MAXDELAY constraint
    155342: 13/06/24: FPGA Exchange
    155345: 13/06/24: Re: Pure HDL Xilinx Zynq Arm Instantiation
    155378: 13/06/25: Re: FPGA Exchange
    155389: 13/06/25: Re: FPGA Exchange
    157082: 14/09/26: Re: Functional safety guidelines
    157692: 15/01/30: Re: Send a pulse across clocks
    157693: 15/01/30: Re: Transfering image file to DDR RAM using EDK
    157973: 15/06/09: Re: PCIe card with FPGA and DAC
    158014: 15/07/03: What's the name of this circuit?
Guy G. Lemieux:
    10024: 98/04/22: Re: Could you help me save CLB's?
Guy Gerard Lemieux:
    743: 95/02/22: Re: PLA? PAL? PLD? GAL?
    812: 95/03/05: Re: area of RAM cells in FPGAs
    846: 95/03/12: Re: FPGA multi-chip modules ?
    929: 95/03/30: High-speed counters (was: AT&T FPGA #6 - Application Notes)
    2240: 95/11/08: FPD'96 Call for Papers
    7830: 97/10/20: Re: Importing FLEX10k into Cadence
    7845: 97/10/22: Altera MAXplus+II 8.1 and HP-UX
    8319: 97/12/08: Re: Q: MAX+ Plus II External connections
    8556: 98/01/08: Re: simple FPGA project for somebody...
    11449: 98/08/14: Re: Gray code counter in ABEL HDL?
    11540: 98/08/21: Re: half full flag in a xilinx async fifo?
    11541: 98/08/21: Re: half full flag in a xilinx async fifo?
    12586: 98/10/19: Re: gray code counter in a Xilinx fpga???
    14722: 99/02/12: Re: Supercomputer uses 280 Xilinx FPGAs
    14723: 99/02/12: Re: Parity and flex10k
Guy Laden:
    10539: 98/05/28: Compiling a HLL to FPGA
Guy Lemieux:
    10003: 98/04/22: Re: Compression for 10K20
    10004: 98/04/22: Re: Could you help me save CLB's?
    10005: 98/04/22: Re: Could you help me save CLB's?
    10066: 98/04/25: Re: Could you help me save CLB's?
    10293: 98/05/10: Re: speed and area
    87117: 05/07/15: FPGA2006 Call for Papers -- ACM/SIGDA International Symposium on FPGAs
    88047: 05/08/07: FPGA 2006 - Call for Papers - Now Accepting Submissions
    159434: 16/11/05: Re: Quad-Port BlockRAM in Virtex
    159435: 16/11/05: Re: Quad-Port BlockRAM in Virtex
Guy LEONHARD:
    2019: 95/10/03: Re: QUICKSIM & XBLOX HELP
    2115: 95/10/17: (no subject)
    2116: 95/10/17: (no subject)
Guy Macon:
    24609: 00/08/15: Re: Non-disclosures in job interviews
    24656: 00/08/16: Re: Non-disclosures in job interviews
    77744: 05/01/16: Re: What is the difference between ASIC and FPGA?.
    82241: 05/04/09: Re: Reverse engineering masked ROMs, PLAs
    85212: 05/06/06: Re: Sch & Layout Free Program
Guy R. Paquet:
    30111: 01/03/23: Boundary Scan tools - price comparison
Guy Schlacter:
    38497: 02/01/15: Re: Altera Compiling Error..WHY?????
    39181: 02/02/03: Re: APEX-II vs VIRTEX-II
    41029: 02/03/20: Re: how to deal with signal pass through two clock domain
    41031: 02/03/20: Re: Xilinx Virtex II in comparsion with Altera Apex 20KC
    41033: 02/03/20: Any Stratix impressions based on results?
    41548: 02/04/02: Re: Any Stratix impressions based on results?
    41549: 02/04/02: CAM info: Data Compression in FPGAs
    42938: 02/05/08: Re: Opinions on FPGA cores - best for a commercial project?
    45015: 02/07/10: anyone get email about www.cradle.com ???
    45054: 02/07/11: Re: Converting Altera Block Ram to Xilinx Block Ram
    45055: 02/07/11: Re: anyone get email about www.cradle.com ???
Guy-Armand:
    37509: 01/12/13: svf files in webpack 4.2
    37522: 01/12/13: Re: svf files in webpack 4.1
<Guy.Eschemann@gmail.com>:
    82866: 05/04/19: Re: source control and Xilinx ISE 6 and 7
<guy@mail.com>:
    18523: 99/10/28: You must read this! It's your chance.
Guy_FPGA:
    112890: 06/11/30: Xilinx XPS - OPB - EMC software halts. Someting fishy
    113318: 06/12/11: How to read data from intel strata flash using microblaze?
    113322: 06/12/11: Re: How to read data from intel strata flash using microblaze?
    113372: 06/12/12: Re: How to read data from intel strata flash using microblaze?
    113839: 06/12/24: Need Recommandation for DDR2 controller virtex4
    113842: 06/12/24: Re: Need Recommandation for DDR2 controller virtex4
    114791: 07/01/24: Re: Platform Cable USB & Windows 2003 Server
    114792: 07/01/24: Re: ethernet MAC and switch
    115429: 07/02/10: Xilinx Ethernet MAC - working with DMA (EDK)
    122500: 07/07/29: Re: ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm
    136521: 08/11/20: Altera DE3 - USB Bulk Transfer
    136576: 08/11/22: Re: Altera DE3 - USB Bulk Transfer
    137195: 09/01/01: Altera - Create sof file with software inside.
    137257: 09/01/06: Re: Altera - Create sof file with software inside.
    137263: 09/01/06: How to program altera on power up? or Can't recognize silicon ID for
    137273: 09/01/07: Re: How to program altera on power up? or Can't recognize silicon ID
    137321: 09/01/08: Read from CF - Stratix II
    137668: 09/01/27: NIOS is stuck at alt_tick after reset
    137845: 09/01/31: Re: NIOS is stuck at alt_tick after reset
    139149: 09/03/22: Cross talk in Altera
Guy_Sweden:
    110812: 06/10/23: How to check if ROM got inferred from synth reports
    115248: 07/02/04: SystemC hangs abruptly
<guybye@hotmail.com>:
    112442: 06/11/22: Xilinx EDK - using EMC with Intel Strata Flash - assistance needed
gvaglia:
    70284: 04/06/11: Xilinx Coregen
gvark:
    128230: 08/01/18: Fuzzy Fixed Point Calculating
    128306: 08/01/21: Re: Fuzzy Fixed Point Calculating
    128315: 08/01/22: Re: Fuzzy Fixed Point Calculating
gw:
    85877: 05/06/17: Xlinix configuration: DONE pin too early?
    85884: 05/06/17: Re: Xlinix configuration: DONE pin too early?
    85892: 05/06/17: Re: Xlinix configuration: DONE pin too early?
<gweinreb@gwinst.com>:
    21043: 00/03/04: Need help w/ Dual Port Ram
<gwise@ibm.net>:
    2511: 95/12/21: Lattice Products
GX:
    116173: 07/03/03: V.34 Modem IP core
    116380: 07/03/07: Re: V.34 Modem IP core
    116441: 07/03/08: Re: V.34 Modem IP core
<gyansorova@gmail.com>:
    159340: 16/10/13: Re: FPGA LABVIEW programming
    159818: 17/03/20: Re: FPGA LABVIEW programming
Gyles Harvey:
    24788: 00/08/18: Re: Instantiation of Virtex-E Block SelectRAMs
    24871: 00/08/21: Re: Non-disclosures in job interviews
    29495: 01/02/23: UCF mode for vim (Re: UCF mode for Emacs?)
gyoung.sna.com:
    2305: 95/11/18: Re: Industry Trends
gyp:
    39567: 02/02/13: Re: Altera's new family Stratix
    39604: 02/02/14: Re: Which PC for ALTERA development tools ?
Gyunseog Yang:
    34781: 01/09/07: Clock division in Xilinx Vertex-E.
    34798: 01/09/08: Re: Clock division in Xilinx Vertex-E.
    34831: 01/09/10: Re: Clock division in Xilinx Vertex-E.
    37446: 01/12/11: i want "RAMB4_S1_S16.VHD"
gzcgh:
¤GŞŮŞk§J:
    510: 94/12/15: Any Way to Download a XNF to FPGA?
Göran Bilski:
    109575: 06/09/29: Re: Interfacing second bram port to user logic?
    109956: 06/10/09: Re: Two instances of Microblaze ...
    109957: 06/10/09: Re: 75Mhz Spartan3e microblaze
    110114: 06/10/11: Re: Two instances of Microblaze ...
    111201: 06/10/31: Re: Question about importing modules to XPS.
    111565: 06/11/06: Re: To Xilinx guys out there - microblaze mapping problem
    111631: 06/11/07: Re: To Xilinx guys out there - microblaze mapping problem
    111641: 06/11/07: Re: To Xilinx guys out there - microblaze mapping problem
    111756: 06/11/09: Re: Microblaze + uClinux issues
    111757: 06/11/09: Re: Microblaze + uClinux issues
    112029: 06/11/15: Re: Microblaze store
    112093: 06/11/16: Re: Microblaze store
    112720: 06/11/28: Re: Mico32, how good is it?
    112779: 06/11/29: Re: Mico32, how good is it?
    112863: 06/11/30: Re: Prefetch buffer in microblaze
    113076: 06/12/06: Re: Spartan-3A launched
    113081: 06/12/06: Re: Spartan-3A launched
    113204: 06/12/08: Re: Microblaze LMB bus
    113311: 06/12/11: Re: How to develop custom opb devices for Microblaze?
    113371: 06/12/12: Re: How to develop custom opb devices for Microblaze?
    114267: 07/01/10: Re: Is the FSL a good approach for this...?
    115348: 07/02/08: Re: Multiple Micorblaze instantion problem solved, Facing debugging related problem.
    115394: 07/02/09: Re: FSL Questions
    115882: 07/02/23: Re: MicroBlaze and OPB block ram interface controller run at different frequency
    116911: 07/03/20: Re: softcore CPU tools
    117870: 07/04/12: Re: System Generator pcore I/O performance results
    118767: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
    119277: 07/05/16: Re: Xilinx EDK: Slow OPB write speeds
    119278: 07/05/16: Re: Lockup with Xilinx mch_opb_ddr
    119284: 07/05/16: Re: how to delay a signal in virtex FPGA
    119626: 07/05/24: Re: fit_timer: trouble connecting interrupt
    119656: 07/05/24: Re: 6502 and CPU licences in general
    119890: 07/05/29: Re: ML505 : beginners problems
    121585: 07/07/09: Re: Microblaze and software interrupts?
    121587: 07/07/09: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121955: 07/07/16: Re: Microblaze V4 / FSL2.0 - putfsl_interruptable() not working reliably
    122097: 07/07/19: Re: modelsim Warning "VIOLATION ON D WITH RESPECT TO CLK"
    122276: 07/07/25: Re: Connecting Bram LMB Controller to Microblaze
    122910: 07/08/10: Re: EDK speed issue
    123059: 07/08/15: Re: Multiplication Problem on Microblaze Software
    123095: 07/08/16: Re: Multiplication Problem on Microblaze Software
    123103: 07/08/16: Re: Multiplication Problem on Microblaze Software
    123107: 07/08/16: Re: Multiplication Problem on Microblaze Software
    123206: 07/08/20: Re: Multiplication Problem on Microblaze Software
    123244: 07/08/21: Re: Multiple MicroBlazes error
    123502: 07/08/29: Re: VHDL core to read/write to Bram_Block.
    123725: 07/09/03: Re: How to add additional FSL interface to customized IP?
    123755: 07/09/04: Re: FPGA CPU
    124045: 07/09/11: Re: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller
    124191: 07/09/14: Re: Problem with Microblaze max clocking
    124788: 07/10/04: Re: Count Leading Zero (CLZ) possible by MicroBlaze??
    125608: 07/10/30: Re: registers are not shown in waveform (xilinx microblaze)
    127172: 07/12/13: Re: Newbee Microblaze system BRAM utlization confusion
    128086: 08/01/15: Re: Debbuging a RISC processor on an FPGA
    128536: 08/01/30: Re: Can I connect PLB and OPB to mlcroblase v7 (use EDK 9.2 and Virtex 5) ?
    128633: 08/02/01: Re: question about fsl and microblaze
    128642: 08/02/01: Re: question about fsl and microblaze
    129688: 08/03/03: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction.
    129725: 08/03/04: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction.
    130066: 08/03/14: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction.
    130235: 08/03/18: Re: FSL or DMA w/ FIFO?
    131393: 08/04/21: Re: attached a 2nd peripheral to FSL bus. how to use it in software?
    131684: 08/04/29: Re: Could someone tell me NIOS II/MB performance on this benchmark?
    131685: 08/04/29: Re: Could someone tell me NIOS II/MB performance on this benchmark?
    131729: 08/04/30: Re: Could someone tell me NIOS II/MB performance on this benchmark?
    131859: 08/05/05: Re: EDK9.2i simulation problems.
    131881: 08/05/06: Re: EDK9.2i simulation problems.
    132226: 08/05/19: Re: difference between 8.2i and 9.2i with respect to Microblaze Core
    133975: 08/07/21: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    134014: 08/07/22: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    134072: 08/07/24: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    134092: 08/07/25: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    135441: 08/10/02: Re: floating point round off errors
    135510: 08/10/06: Re: Reading files from CF (microblaze 7 and plb)
    135511: 08/10/06: Re: Reading files from CF (microblaze 7 and plb)
Günther Jehle:
    117480: 07/04/02: Re: ISE on Fedora?
    119734: 07/05/25: Re: VGA signal through breadboard?
    121180: 07/06/27: Re: Bit error counter - how to make it faster


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