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Hi all,
I am trying to generate a vcd file from the model sim V6.0a. tried
the following command
vcd file test1.vcd
vcd add -ports /top_module/DUT/*
It is giving all the signals but bus signals are split into separate
bits. How can i genrate a vcd file in which bus signals are combined
(values in hex) rather than bits.
Also in the documentation of model sim i only found the way to gnerate
the vcd file from console. Is there any way to generate that from GUI.
Thanks in advance
Article: 96651
The VHDL code that I posted before is buggy. After the first signal
resolution, the resolved vector never becomes all '0'. The following
code solves it:
signal requests : std_logic_vector(m-1 downto 0);
signal resolved : std_logic_vector(m-1 downto 0);
signal some_request : std_logic;
process(i_Clk, i_Rst, first_level)
variable found : std_logic;
variable var_resolved : std_logic_vector(m-1 downto 0);
begin
if (i_Rst = '1') then
resolved <= (others=>'0');
var_resolved := (others=>'0');
some_request <= '0';
found := '0';
elsif (i_Clk'event and i_Clk = '1') then
found := '0';
var_resolved := (others=>'0');
for y in 0 to m-1 loop
if (requests(x) = '1' and found = '0') then
var_resolved <= ext(requests(y downto 0), m);
found := '1';
end if;
end loop;
some_request <= found;
resolved <= var_resolved;
end if;
end process;
It also adds a new wire, some_req, that is '1' when there is any wire
requesting the resource, and '0' when there isn't. That is useful when
you don't want to grant the resource inmediately, but controlled by a
state machine or any other decision-making procedure. It is tested and
it works after Place & Route in a Virtex-2 at 100 Mhz. The synthesizer
reports good operation over 200 Mhz, although I didn't try this.
Regards.
Jose.
Article: 96652Hey guys Thanks a lot. The inputs are basically a chipselect (SEL compared against ADD...where ADD is dip switches left alone and SEL comes from the PC) and a single signal that is the serial 32 bit word. I then feed that serial data into a register and then clock it out parallel to the LED1. There is no reset signal in the system so dont want to add one to the state machine just yet. I was assuming that by only taking the inputs during a rising edge of the clock, I AM sampling them syncronously, even though they might occur asynch. The CLK and the SEL signals are pretty much timed by the PC sending them so all I need to do is sample the SEL line during a rising CLK edge. I am not sure where in Quartus to setup the timing requirements and how to make it test that they are all met? Any help? "Andy Peters" <Bassman59a@yahoo.com> wrote in message news:1139357387.186650.274220@g43g2000cwa.googlegroups.com... > Matt Clement wrote: > >> here is the basic "program" >> >> LIBRARY IEEE; >> USE IEEE.STD_LOGIC_1164.ALL; >> >> ENTITY CLONE34 IS >> PORT >> (clk : IN BIT; >> SEL : IN BIT_VECTOR(7 DOWNTO 0); >> ADD : IN BIT_VECTOR(5 DOWNTO 0); >> DAT : INOUT BIT_VECTOR(1 DOWNTO 0); >> LED1 : OUT BIT_VECTOR(31 DOWNTO 0)); >> >> END CLONE34; >> >> ARCHITECTURE ONE OF CLONE34 IS >> TYPE STATE_TYPE IS >> (IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34); >> SIGNAL STATE: STATE_TYPE; >> >> BEGIN >> >> PROCESS (clk, ADD) >> VARIABLE DATA : BIT_VECTOR(35 DOWNTO 0); >> BEGIN >> >> IF (clk'EVENT AND clk = '1')THEN >> >> DAT(0)<='0'; >> CASE STATE IS >> WHEN IDLE => > > (snip) > > You might consider adding an asynchronous reset state to your state > machine. > > -a >Article: 96653
GNU Radio is a pain to install the first time, but once it's up it takes care of most of the nuissance/tedious stuff for you and you can focus directly on the signal processing. You can do signal processing in C code on the linux host or inside the cyclone fpga in vhdl (using free version of quartus). One advantage for you is, if you do something simple like BFSK or BPSK you could do a loop back system and implement the receiver too. Truth is all the interesting stuff is in the receiver anyway: carrier recovery, synchronization, equalization, etc. It's great for education tool. The board can stay with the school and each semester students can build on the previous groups work. Just my opinion. I spent most of my senior design (years ago) wire wrapping my board (an FM receiver on an ISA card (years before you could buy commercially)). I would have learned a lot more if I'd had the GNU radio tool. -Clark <zhangweidai@gmail.com> wrote in message news:1139379598.662192.273600@g44g2000cwa.googlegroups.com... > Clark, > > After you mentioned using GNU Radio, I looked it up and yes we are > going to do something similiar. We are building this demo board > ourselves as best we could as a senior design project. We dont know > enough about USRP to decide to jump into using it yet. > > -Peter >Article: 96654
Hi all, I am a Verilog user and I want to find some tools do assertion(like C's assert()). I found Open Verification Libiary(OVL) has been updated. And it is free for download( http://www.accellera.org/activities/ovl/ ). I hope to use it in the near future. Anyone has used it yet? Please give some comment. Thanks! Best regards, DavyArticle: 96655
The timing spec you want in the I2C bus specification is called tHD (data hold time after falling edge of SCL). Minimum spec is 0 ns (like your first picture) maximum depends on whether you are driving SCL or not. For a master just be sure to meet the setup time to the next rising edge of SCL. For a slave, you need to observe the maximum for the clock rate used, because you can only control the rising edge of SCL if you implement clock stretching. For 100 KHz devices, the max is 3.45 uS. for 400 KHz it is 900 nS. The best practice is usually to sense that the SCL line has fallen using feedback from the pin, and then allowing the data to change. Regards, Gabor hyankijitu@gmail.com wrote: > hi! > i am developing i2c master in FPGA. suppose ia m transmitting 1. > i have doubt whether data transition should be at mid edge of > scl when it is low or at the falling edge as in the below waveform. > > scl -------------- ---------------------- > | | > | > / here > | / or | > | > ------------------ > ---------------------------- > |------------------- > | here | > SDA ---------------------- > |------------------------------------Article: 96656
not used it but does anybody know if it is going to be ported to VHDL too? (like the old OVLs) Regards Nikolaos KavvadiasArticle: 96657
> I was assuming that by only taking the inputs during a rising edge of the > clock, I AM sampling them syncronously, even though they might occur asynch. the internal routing from the pad to your first flipflop is not constrained ... if you are unlucky you get different delays for different paths and they even change from one implementation to the next (making it work just sometimes) ... I have to admit that it's somewhat uncommon that this is a problem at only 5 MHz ... > The CLK and the SEL signals are pretty much timed by the PC sending them so > all I need to do is sample the SEL line during a rising CLK edge. That would be that first thing I would change ... > I am not sure where in Quartus to setup the timing requirements and how to > make it test that they are all met? Any help? in xilinx florplanner you can open the routed FPGA, click on a net and press the button "delay". This gives you some numbers to find out if you violate setup/hold ... (sorry - I just know for xilinx) If you specify a timing constraint the report should say which items matched and if they met the constraint ... somehow ... just insert the input FF - this is likely to solve the problem and you don't have to care about complicated constraints ;-) bye, MichaelArticle: 96658
Hi having MicroBlaze to boot uClinux to command prompt sure is nice also but seeing it running graphical tuxchess is even better ! afterwards it seems always so simple, here are the steps to do it: 1 make EDK 8.1 MicroBlaze system (W32 host) 2 TFT LCD ref from Ml300 ref design (needs tweaking in EDK to enable PLB bus for Spartan 3 architecture) 3 build uClinux (only step that requires linux machine or emulator!) 3 get CYGWIN 4 get GNU C source for MB from Xilinx 5 run build scritps to build the toolchain 6 get u-boot sources 7 add framebuffer support for u-boot (really simple!) 8 add MMC/SD card support to uboot (also simple) 9 build u-boot 10 add MMC driver to ucLinux, rebuild kernel 11 copy linux.bin, libc.a and some .h files from tree into W32 machine 12 setup Out of tree compile make file 13 get microwindows sources 14 setup custom makefiles for microwin 15 fix graphic driver for microwindos (maybe 20 lines of code changes!) 16 build microwindows drivers and nano-X server objects 17 build tuxchess 18 copy tuxchess into romfs\bin\ 19 copy chess images into some location on the romfs 20 run genromfs (all on W32 machine!) 21 copy /b linux.bin + ronmfs.img image.bin 22 copy image.bin onto SD card 23 insert SD card and reboot FPGA and here it goes.. .. preboot loader reads u-boot into SDRAM .. u-boot starts and loads image.bin .. uClinux prompt appears >tuxchess and voila you have the Chess game on the TFT LCD simple uhh ? - actually it is simple, after doing it once AnttiArticle: 96659
Thanks all. >From the datasheet of cyclone,it is compatible with pci-5v by diode and risistors. Can somebody help me to solve the first question?Article: 96660
HI, Leow Yuan Yeow wrote: > Hi, may I know whether there is any free program that is able to convert a > vhdl file to a .edf file? I am unable to find such options in the Xilinx ISE > Navigator. I have tried using the Xilinx ngc2edif convertor but when I tried > to generate a bit file from the edf file its says: > > ERROR:NgdBuild:766 - The EDIF netlist 'synthetic2.edf' was created by the > Xilinx > NGC2EDIF program and is not a valid input netlist. Note that this EDIF > netlist is intended for communicating timing information to third-party > synthesis tools. Specifically, no user modifications to the contents of > this > file will effect the final implementation of the design. > ERROR:NgdBuild:276 - edif2ngd exited with errors (return code 1). > ERROR:NgdBuild:28 - Top-level input design file "synthetic2.edf" cannot be > found > or created. Please make sure the source file exists and is of a > recognized > netlist format (e.g., ngo, ngc, edif, edn, or edf). > > Any help is appreciated! > YY > > Hmm is it possible to embedd VHDL constructs in EDIF really? Then who will do the syntheses? /michaelArticle: 96661
Hi *, I'm planning a device with a backup battery. In case of power failure, the FPGA (a Virtex4 in this case) should be shut down to save power, whereas other components on the board need to keep working. So, since the PWRDWN-pin doesn't do anything what I was planning to do is to simply turn off the regulators for Vccint and Vccaux as soon as the power fails. But I can't turn off Vcco, since it's used as a supply for other components as well (unless I use a separate regulator just for Vcco). Can I damage the FPGA if the IO-banks are powered but the core isn't? And what will happen to the I/Os once the core supply goes away, but Vcco stays? Will they just start floating? cu, SeanArticle: 96662
Thanks for all the advice. I have a Xilinx spartan 3 starter kit that i'd like to use to implement this, but not EDK. Any suggestions for a simple CPU to use on the FPGA? ThanksArticle: 96663
Antti wrote: > Hi > > having MicroBlaze to boot uClinux to command prompt sure is nice also > but seeing it running graphical tuxchess is even better ! > > afterwards it seems always so simple, here are the steps to do it: > > 1 make EDK 8.1 MicroBlaze system (W32 host) > 2 TFT LCD ref from Ml300 ref design > (needs tweaking in EDK to enable PLB bus for Spartan 3 architecture) > 3 build uClinux (only step that requires linux machine or emulator!) > 3 get CYGWIN > 4 get GNU C source for MB from Xilinx > 5 run build scritps to build the toolchain > 6 get u-boot sources > 7 add framebuffer support for u-boot (really simple!) > 8 add MMC/SD card support to uboot (also simple) > 9 build u-boot > 10 add MMC driver to ucLinux, rebuild kernel > 11 copy linux.bin, libc.a and some .h files from tree into W32 machine > 12 setup Out of tree compile make file > 13 get microwindows sources > 14 setup custom makefiles for microwin > 15 fix graphic driver for microwindos (maybe 20 lines of code changes!) > 16 build microwindows drivers and nano-X server objects > 17 build tuxchess > 18 copy tuxchess into romfs\bin\ > 19 copy chess images into some location on the romfs > 20 run genromfs (all on W32 machine!) > 21 copy /b linux.bin + ronmfs.img image.bin > 22 copy image.bin onto SD card > 23 insert SD card and reboot FPGA > > and here it goes.. > .. preboot loader reads u-boot into SDRAM > .. u-boot starts and loads image.bin > .. uClinux prompt appears > > >>tuxchess > > > and voila you have the Chess game on the TFT LCD > > simple uhh ? > > - actually it is simple, after doing it once No Smiley ? I might not call the above simple, but I would call it impressive. -jgArticle: 96664
Antti wrote: <snip> > and voila you have the Chess game on the TFT LCD Who won ? :) -jgArticle: 96665
al99999 wrote: > Thanks for all the advice. I have a Xilinx spartan 3 starter kit that > i'd like to use to implement this, but not EDK. Any suggestions for a > simple CPU to use on the FPGA? > > Thanks PicoBlaze should handle it if it's not too complex. You may run out of instruction space (the 8-bit PicoBlaze for Spartan 3 is limited to 1K instructions if memory serves me right). This does not require the EDK and is published as a reference design with source. Regards, GaborArticle: 96666
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:43ea393e$1@clear.net.nz... > Antti wrote: > <snip> >> and voila you have the Chess game on the TFT LCD > > Who won ? :) > -jg > ROTFL - the computer won!! with greate opening move: E2E4 !!! because I have no input device configured in microwindows so I cant respond... AnttiArticle: 96667
Sean, Nothing bad happens. The IO banks draw 2 to 8 mA from 3.3V while remaining tristate. The center banks are smaller and draw 2 mA, the larger banks all draw ~ 8mA each. Austin Sean Durkin wrote: > Hi *, > > I'm planning a device with a backup battery. In case of power failure, > the FPGA (a Virtex4 in this case) should be shut down to save power, > whereas other components on the board need to keep working. > > So, since the PWRDWN-pin doesn't do anything what I was planning to do > is to simply turn off the regulators for Vccint and Vccaux as soon as > the power fails. > But I can't turn off Vcco, since it's used as a supply for other > components as well (unless I use a separate regulator just for Vcco). > > Can I damage the FPGA if the IO-banks are powered but the core isn't? > And what will happen to the I/Os once the core supply goes away, but > Vcco stays? Will they just start floating? > > cu, > SeanArticle: 96668
Leow Yuan Yeow wrote:
> Hi, may I know whether there is any free program that is able to convert a
> vhdl file to a .edf file? I am unable to find such options in the Xilinx ISE
> Navigator. I have tried using the Xilinx ngc2edif convertor but when I tried
> to generate a bit file from the edf file its says:
I would try a vhdl to verilog conversion:
http://www.ocean-logic.com/downloads.htm
and then consider using Icarus Verilog to generate the edif:
http://www.icarus.com/eda/verilog/
Article: 96669Jerome wrote about USB: > However concerning the 5V tolerance, i'm not sure it is necessary > since the D+ & D- level swing stays in the 0V - 3.6 V range If I'm not mistaken, there's nothing that guarantees that the postive swing can't approach the positive supply rail.Article: 96670
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:43ea38ea$1@clear.net.nz... > Antti wrote: >> Hi >> >> having MicroBlaze to boot uClinux to command prompt sure is nice also >> but seeing it running graphical tuxchess is even better ! >> >> afterwards it seems always so simple, here are the steps to do it: >> >> 1 make EDK 8.1 MicroBlaze system (W32 host) >> 2 TFT LCD ref from Ml300 ref design >> (needs tweaking in EDK to enable PLB bus for Spartan 3 architecture) >> 3 build uClinux (only step that requires linux machine or emulator!) >> 3 get CYGWIN >> 4 get GNU C source for MB from Xilinx >> 5 run build scritps to build the toolchain >> 6 get u-boot sources >> 7 add framebuffer support for u-boot (really simple!) >> 8 add MMC/SD card support to uboot (also simple) >> 9 build u-boot >> 10 add MMC driver to ucLinux, rebuild kernel >> 11 copy linux.bin, libc.a and some .h files from tree into W32 machine >> 12 setup Out of tree compile make file >> 13 get microwindows sources >> 14 setup custom makefiles for microwin >> 15 fix graphic driver for microwindos (maybe 20 lines of code changes!) >> 16 build microwindows drivers and nano-X server objects >> 17 build tuxchess >> 18 copy tuxchess into romfs\bin\ >> 19 copy chess images into some location on the romfs >> 20 run genromfs (all on W32 machine!) >> 21 copy /b linux.bin + ronmfs.img image.bin >> 22 copy image.bin onto SD card >> 23 insert SD card and reboot FPGA >> >> and here it goes.. >> .. preboot loader reads u-boot into SDRAM >> .. u-boot starts and loads image.bin >> .. uClinux prompt appears >> >> >>>tuxchess >> >> >> and voila you have the Chess game on the TFT LCD >> >> simple uhh ? >> >> - actually it is simple, after doing it once > No Smiley ? > > I might not call the above simple, but I would call it impressive. > > -jg > > Hi Jim, here is the similey ;) well, as said after doing it once it all looks like real simple. but sure the way to the point when it all worked wasnt so simple at all. what I have been positivly been surprised is that a lot of C code actually works without change, as soon as you have the proper makefiles and libs and defines in place ;) this goes for uclinux, u-boot and userland apps, etc also CYGWIN is doing a great deal better now supporting C compilers on W32 xilinx GNU tools actually compiled out of box, I only had to adjust location of tcsh genroms also works also with symlinks making valid romfs image uclinux kernel build on w32 also works, but with some issues on one PC kernel was build ok but required some directory include tweakinga and removing most of userland, on another PC out of box uclinux build worked til core dump during busybox make having however no issues except during busybox build. anyway its quite close to get microblaze-uclinux fully built on w32 host. sure I still do the actual kernel builds on linux host still (real linux box, not emulator) been trying to setup CoLinux several times, always casued network issues, tried 0.6.3 from free downloads, did not work, then purchased Open Colinux tha is supposedly easy install version of CoLinux, but this easy install installed without asking a VNC server and made all my email and networking not working. I have been looking at CoLinux in order to make disk images with pre installed uClinux toolchain and sources, but, well lets see maybe I try again CoLinux (after seeing the commercial packaged version to fail real badly) what I was really amazed was the easiness of the adoption of the graphic drivers for microwindows I did take the empty donthing debug driver and inserted single line calls to the xilinx tft_l.h and that was it, it worked !!! in u-boot it was about as simple as well, but for some reason in uboot the graphic logo doesnt show at start even though graphics load and display is all working AnttiArticle: 96671
This issue seems to be fixed with the newer ISE version ( 8.1i ). Thank-you Aurelian Lazarut, for you support. Roldao Antonio Roldao Lopes wrote: > Greetings FPGA Group, > > I'm attempting to input an LVDS clock signal into a SoC design. This > development is based on a NuHorizons SP3 board with a Spartan-3 > (xc3s1500-fg676-4). Although it supports primitives for input > differential clock signals through the usage of, for example, the > IBUFGDS_LVDS_25 component, when I do instantiate such blocks, Bitgen > reports a couple of non-informative warnings and finally generates the > stream. However the result corrupts all the internal signals of the > SoC... > > The warnings only show up with the Spartan-3 family. All works fine, > and no warnings are displayed if using a Virtex family device. These > warnings as following pop-up during the bit-generation (using ISE > 7.1i): > > WARNING:Bitgen:74 - Unknown primitive "DRIVE_0MA" for site "IOB4". > WARNING:Bitgen:74 - Unknown primitive "DRIVE_0MA" for site "IOB5". > > Any help, hint, or even pointers to successful implementations of LVDS > clocks inputs on a Spartan 3, will be mostly appreciated. > > Thanks in Advance, > Antonio Roldao Lopes > > I've isolated the code that generates such warnings and produced a > simple test-bench, here it goes... > > -- LVDS BLACK BOX > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > library UNISIM; > use UNISIM.VComponents.all; > > entity LVDS_BOX is > port(nRESET : in std_logic; > CLK_T : in std_logic; > CLK_I : in std_logic; > CLK_O : out std_logic); > end LVDS_BOX; > > architecture Behavioral of LVDS_BOX is > > signal CLK : std_logic; > signal s : std_logic; > > begin > > U0: IBUFGDS_LVDS_25 port map (I=>CLK_T,IB=>CLK_I,O=>CLK); > > process(nRESET, CLK) > begin > if nRESET = '0' then > s <= '0'; > elsif rising_edge(CLK) then > s <= not s; > end if; > end process; > > CLK_O <= s; > > end Behavioral; > > > > -- TEST BENCH LVDS BLACK BOX > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > USE ieee.std_logic_unsigned.all; > USE ieee.numeric_std.ALL; > > ENTITY Tb_LVDS_BOX IS > END Tb_LVDS_BOX; > > ARCHITECTURE behavior OF Tb_LVDS_BOX IS > > COMPONENT LVDS_BOX > PORT( > nRESET : IN std_logic; > CLK_T : IN std_logic; > CLK_I : IN std_logic; > CLK_O : OUT std_logic > ); > END COMPONENT; > > --Inputs > SIGNAL nRESET : std_logic := '0'; > SIGNAL CLK_T : std_logic := '0'; > SIGNAL CLK_I : std_logic := '1'; > > --Outputs > SIGNAL CLK_O : std_logic; > > BEGIN > > -- Instantiate the Unit Under Test (UUT) > uut: LVDS_BOX PORT MAP(nRESET,CLK_T,CLK_I,CLK_O); > > -- Generate Differential Clock Signal > CLK_T <= not CLK_T after 100 ns; > CLK_I <= not CLK_I after 100 ns; > > tb : PROCESS > BEGIN > -- Reset System > nRESET <= '0'; > wait for 400 ns; > nRESET <= '1'; > > -- Stop Simlation, the ugly way! > wait for 1 us; > report "Done" severity Failure; > END PROCESS; > > END;Article: 96672
HI; Leow Yuan Yeow wrote: > Pardon me, but I don't understand your question, are you saying its > impossible? I was trying to make a edif file from my vhdl file, and > synthesize it with Xilinx together with another external edif file which > uses my vhdl component. I have tried to get Synplify and LeonardoSpectrum > evaluation version which reportedly can change vhdl to edif, but the trial > license is taking so long to arrive and I'm running out of time. Hmm, Am I missing something but from VHDL to EDIF is done with syntheses, then Xilinx can merge EDIFs to one for place and route using ngdbuild. Or what are you trying to do exactly, you have Xilinx webedition is that not good enough for what you are trying to do? cheers MichaelArticle: 96673
> > PicoBlaze should handle it if it's not too complex. You may run out > of instruction space (the 8-bit PicoBlaze for Spartan 3 is limited to > 1K instructions if memory serves me right). This does not require > the EDK and is published as a reference design with source. > Is there a C compiler for PicoBlaze?Article: 96674
I see my inputs and outputs, but no internal signals. > If you mean how to add signals to the simulation graphic, just open the > whole tree of the UUT on your Sim Hierarchy tab (on the left side, > beside Process View), choose the signal you need, drag and drop it > inside the simulation graphic and you're done. > Then re-run the simulation to see their behaviour. > Marco >
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