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Authors (R)

R A Felton:
    13286: 98/11/24: Report problems
R Allen:
    35670: 01/10/13: Re: Block RAMs
R Sefton:
    28166: 00/12/23: spartan-II power supply sequencing problem
    29811: 01/03/12: Re: Again Spartan II power
    29831: 01/03/13: Re: Again Spartan II power
R! Tafas Jr:
    104173: 06/06/20: Re: Google FPGA Designer beta release
R!SC:
    77282: 05/01/03: problem with edk
    77307: 05/01/04: LEON2 or microblaze
    77889: 05/01/19: jvm on microblaze
    82349: 05/04/11: xilinx virtex 4 download cable
    84917: 05/06/01: problem with edk 7.1
<r-m-w@web.de>:
    103236: 06/05/29: JTAG in-system programming of PROM devices
r. bansal:
    1512: 95/07/06: VHDL/FPGAs/PLDs help
R. Colin Johnson:
    6511: 97/05/29: Convener, where are you?
R. D. Davis:
    2515: 95/12/22: Re: [q][Reverse Engineering Protection]
R. Hofman:
    132407: 08/05/26: How to update a row and a column at the same clock cycle?
R. Lamberts:
    9413: 98/03/11: Announcing: Open Design Circuits
R. Mark Gogolewski:
    9203: 98/03/02: Re: The case for Linux and EDA
    9244: 98/03/04: Re: The case for Linux and EDA
    9255: 98/03/05: Re: The case for Linux and EDA
    9261: 98/03/05: Re: The case for Linux and EDA
    9288: 98/03/05: Re: The case for Linux and EDA
    17299: 99/07/19: Re: License sharing for synopsys/cadence/modeltech
    17306: 99/07/20: Re: License sharing for synopsys/cadence/modeltech
R. Scheuerer:
    7834: 97/10/21: Save your 49c402 microcode investment
R. T. Finch:
    22214: 00/05/02: new2fpga
    22476: 00/05/09: Xilinx Student Edition 1.5 License.dat
    22527: 00/05/11: Re: Xilinx Student Edition 1.5 License.dat
    22804: 00/05/25: Verilog assignment
    23009: 00/06/08: Re: Xilinx foundation Student Edition problem.
    23473: 00/06/26: Re: Different ?
    23501: 00/06/27: Re: Different ?
    23523: 00/06/28: Re: I cant stand it any more.
    24250: 00/08/01: clock quadrupling
R. T. Wurth:
    5223: 97/01/31: Re: Steven K. Knapp - no such article
    6546: 97/06/02: Re: New Reconfigurable Computing newsgroup?
<r.fridolin@gmx.de>:
    140493: 09/05/14: XILINX license model restricts longtime availability
<r.kinkead@gmail.com>:
    91908: 05/11/16: Lattice XP flash memory access.....
    91925: 05/11/16: Re: Lattice XP flash memory access.....
<(r.m.muench+ieee.org)>:
    5660: 97/03/05: Re: What kind of functions mostly implemented using FPGAs?
R.Sriram:
    36029: 01/10/26: Bi directional pin
    51015: 02/12/26: Interested in FPGA design
R.W. DeHoedt:
    5922: 97/03/26: Re: BIT SERIAL MULTIPLY
<ra_arce@yahoo.com>:
    79968: 05/02/27: Resource (FMAPs) use when using block RAMs
Raanan:
    13314: 98/11/25: Synchronous SRAM design wanted
<raarce@gmail.com>:
    103017: 06/05/24: Report for routing resource usage?
Raban:
    131312: 08/04/18: Has anyone dealt with Avnet? or NuHorizons when trying to purchase Xilinx stuff
<rabbiaqamar@yahoo.com>:
    129082: 08/02/13: i need ur help
    129083: 08/02/13: i need fpga board with 10 Gig interface and pcie interface
RAcoops:
    41830: 02/04/09: Xilinx Prototype Platforms
    41836: 02/04/09: Re: Xilinx Prototype Platforms
radarman:
    89514: 05/09/16: Looking for info on the V8/Arclite MicroRISC 8-bit core
    90050: 05/10/03: Re: for...generate loop with generics, constants (vhdl)
    96942: 06/02/13: Problem programming Altera flex 10k100 & EPC2
    96985: 06/02/14: Re: Problem programming Altera flex 10k100 & EPC2
    96989: 06/02/14: Re: is there a way to initialize signals to a value
    98637: 06/03/13: Coregen in ISE 8.1i webpack not working quite right
    98693: 06/03/14: Re: Coregen in ISE 8.1i webpack not working quite right
    99035: 06/03/19: Re: Support software for XC3042
    99234: 06/03/21: Re: Support software for XC3042
    99352: 06/03/23: Re: Going from CLK1X to CLK2X.. really safe?
    100067: 06/04/02: Re: Hierarchical FSM?
    100613: 06/04/13: Re: Spartan 3E Starter Kit is finally here!
    100791: 06/04/18: Re: PLD610
    100870: 06/04/19: Re: Multiple Independent Circuits on a Single FPGA
    100871: 06/04/19: =?iso-8859-1?q?Re:_ow_to_connect_FPGA_and_=B5C?=
    100872: 06/04/19: Re: C# and Spartan 3 Starter Kit
    100887: 06/04/20: Re: Multiple Independent Circuits on a Single FPGA
    100908: 06/04/20: Re: Reliability CPLD/FPGA vs Microcontroller
    101011: 06/04/24: Re: Reliability CPLD/FPGA vs Microcontroller
    101532: 06/05/02: Re: RESET pin on NIOS II processor
    101954: 06/05/08: Re: Spartan 3e starter kit & Multimedia
    101959: 06/05/08: Re: Xilinx 3s8000?
    101990: 06/05/09: Re: Spartan 3e starter kit & Multimedia
    102006: 06/05/09: Re: Xilinx 3s8000?
    102050: 06/05/09: Re: Xilinx 3s8000?
    102073: 06/05/10: Re: Xilinx 3s8000?
    102670: 06/05/18: Spartan 3e sample: pack power control with M(1)?
    102735: 06/05/19: Re: Spartan 3e sample: pack power control with M(1)?
    102782: 06/05/20: Re: Why do the electronics manufacturers have to spam me?
    102811: 06/05/21: Re: JTAG chaining of two different Xilinx Spartan 3E boards
    103125: 06/05/25: Altium Livedesign eval boards - can you add a configuration prom?
    103189: 06/05/27: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
    103436: 06/06/01: XIlinx 7.1i ISE problem with Spartan 3e design
    103443: 06/06/01: Re: XIlinx 7.1i ISE problem with Spartan 3e design
    103465: 06/06/02: Problem with Xilinx ISE 7.1i core generator
    103497: 06/06/04: Re: Problem with Xilinx ISE 7.1i core generator
    103653: 06/06/07: Re: Anyone with Xilinx SP305-board ?
    103766: 06/06/10: Re: Anyone with Xilinx SP305-board ?
    104370: 06/06/26: Re: newbie wants to do VHDL on an FPGA
    104604: 06/06/30: Re: How to control the uart
    104605: 06/06/30: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104617: 06/07/01: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104640: 06/07/03: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104742: 06/07/05: Re: "Large" memory array in VHDL
    105017: 06/07/11: Re: Development Boards -Your chance to suggest features
    105421: 06/07/22: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
    105466: 06/07/24: Re: Hardware book like "Code Complete"?
    105480: 06/07/24: Re: Hardware book like "Code Complete"?
    105728: 06/07/30: Re: "This design element is inferred rather than instantiated" (newbie)
    106004: 06/08/04: How to implement large ROM's from binary sources?
    106070: 06/08/07: Re: verilog versus vhdl
    106342: 06/08/11: Re: Dio5 interface with ps2 port
    106513: 06/08/14: Any interest in a v8 uRISC/Arclite clone?
    106576: 06/08/15: Re: Alternative for Mentor''s HDL Designer
    106688: 06/08/17: Re: Alternative for Mentor''s HDL Designer
    106807: 06/08/19: Re: Speed vs Area Optimisation
    106853: 06/08/21: Re: CPU design
    106901: 06/08/22: Re: CPU design
    106902: 06/08/22: Re: CPU design
    108164: 06/09/06: Re: Qestion about the ability of synthesis
    108301: 06/09/07: Re: Qestion about the ability of synthesis
    108306: 06/09/07: Re: Synchronous Clocks
    108309: 06/09/07: Re: Why No Process Shrink On Prior FPGA Devices ?
    108393: 06/09/10: Re: Can a FPGA work like a microprocessor ?
    108613: 06/09/13: Re: Spartan3E availability
    108637: 06/09/14: Re: uclinux on spartan-3e starter kit
    108918: 06/09/19: Re: USB programming cables
    109095: 06/09/20: Re: Old vs. New FPGAs
    109855: 06/10/06: Re: Spartan 3 Starter Kit I/O ports
    109951: 06/10/08: Re: Antifuse, lower cost?
    109979: 06/10/09: Re: Antifuse, lower cost?
    110012: 06/10/09: Re: Quartus II 6.0: System clock has been set back
    110089: 06/10/10: Altera Quartus II 5.1 SP2 fails on MIF/HEX reconfig
    110116: 06/10/11: Re: Quartus II 6.0: System clock has been set back
    110166: 06/10/11: Re: Quartus II 6.0: System clock has been set back
    110167: 06/10/11: Re: Antifuse, lower cost?
    110227: 06/10/12: Re: Altera Quartus II 5.1 SP2 fails on MIF/HEX reconfig
    111398: 06/11/02: Re: EDK software development
    111461: 06/11/03: Re: digilent spartan-3 board sram timing
    111493: 06/11/03: Re: reset
    112319: 06/11/20: Parallax Stratix Smartpack accessories?
    112342: 06/11/20: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    112373: 06/11/21: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    113001: 06/12/04: Can you configure an Altera Stratix without the nStatus line?
    113005: 06/12/04: Re: Can you configure an Altera Stratix without the nStatus line?
    113042: 06/12/05: Re: Can you configure an Altera Stratix without the nStatus line?
    113476: 06/12/14: Re: what are your current SoC design for ?
    113899: 06/12/28: Re: ChipScope - impact on design or not?
    113902: 06/12/28: Re: moving from xlinx 8.1 to 8.2 or better wait ?
    113937: 06/12/29: Re: ChipScope - impact on design or not?
    113942: 06/12/29: Re: ChipScope - impact on design or not?
    113944: 06/12/29: Re: moving from xlinx 8.1 to 8.2 or better wait ?
    114678: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
    115178: 07/02/01: EDK tri-state control
    116041: 07/02/28: Can write, can't read with OPB_SPI 1.00e
    116050: 07/02/28: Re: Can write, can't read with OPB_SPI 1.00e
    117273: 07/03/27: (Xilinx) OPB watchdog timer fails to release RESET
    117426: 07/03/30: Re: (Xilinx) OPB watchdog timer fails to release RESET
    117501: 07/04/02: Does the XC3S250E-VQ100 exist?
    117587: 07/04/04: Re: Does the XC3S250E-VQ100 exist?
    118783: 07/05/03: Re: Unused Pin setting on per-pin basis
    118793: 07/05/03: Re: Unused Pin setting on per-pin basis
    119010: 07/05/09: Re: ML405 LCD
    120700: 07/06/13: Re: custom peripheral registers
    120754: 07/06/15: Re: Stolen Spartan 3E-1600 Development Board
    121523: 07/07/06: Re: I need relocate my program outside bram...
    121718: 07/07/11: Flex 10k100 & EPC2 redux - forgot the special ingredient?
    126245: 07/11/17: Altera webpack for Linux?
    126306: 07/11/19: Re: Altera webpack for Linux?
    128118: 08/01/15: Re: Where has Xilnet gone?
    129319: 08/02/20: Interrupt Handler page missing in from software platform settings in
    130126: 08/03/15: Re: ISSI SRAM.
    130981: 08/04/07: Modify POF with new ESB (ROM) content?
    131063: 08/04/09: Re: Disable optimisation - Ring oscillator
    132151: 08/05/15: Re: xilinx spi core question (microblaze)
    136959: 08/12/15: Re: Terasic DE1 board commentary
    140530: 09/05/15: Cheap Ethernet PHY boards?
    140641: 09/05/20: Re: Cheap Ethernet PHY boards?
    140874: 09/05/27: Cyclone III == Spartan ?
    140950: 09/05/30: Re: Cyclone3 and AT45DB serial flash
    140958: 09/05/31: GMII pinning issue
    141213: 09/06/11: Re: XILINX WEB SERVER DEMO
    141319: 09/06/17: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
    141597: 09/06/29: Re: usefulness of Virtex-II devices
    144732: 09/12/29: Re: EPCS vs SPI Flash
    145003: 10/01/19: Re: working with ADC and DAC together
    146158: 10/03/06: Re: Actel is now the only FPGA vendor with hard-core processor in the
    146726: 10/03/26: PCB routing issues for sync SRAM
    146761: 10/03/27: Re: PCB routing issues for sync SRAM
    146803: 10/03/29: Re: PCB routing issues for sync SRAM
    146809: 10/03/29: Re: PCB routing issues for sync SRAM
    147417: 10/04/26: Re: Quartus II under Windows7?
    147738: 10/05/20: Re: I'd rather switch than fight!
    147816: 10/05/25: Re: Last Xilinx Webpack that was big-brother free?
    149123: 10/10/03: Re: External Circuit to FPGA.
    149284: 10/10/13: Re: Xilinx Artix 7 - When?
    152248: 11/07/27: Re: FPGA security, Actel down, now Xilinx too?
    152374: 11/08/16: Re: 5V FCT TO Cyclone II
    152398: 11/08/18: Re: Altera Flex10K support ?
Radboud Verberne:
    23158: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
<raderrl@my-deja.com>:
    17527: 99/08/06: Xilinx vs. Lucent vs. XX FPGA comparison
    19228: 99/12/07: tool command language (TCL)
Radha:
    135681: 08/10/12: Good reference for Static Timing Analysis
RADHIKA:
    29334: 01/02/14: Re: XILINX FPGA programming through JTAG
radhika:
    29305: 01/02/13: Configuration of FPGA using SPROM
    29308: 01/02/13: Configuration of FPGA using SPROM
    29339: 01/02/14: Re: Configuration of FPGA using SPROM
    29386: 01/02/17: Re: Configuration of FPGA using SPROM
    29387: 01/02/17: Re: Configuration of FPGA using SPROM
    29427: 01/02/20: Re: Configuration of FPGA using SPROM
Radioman:
    90837: 05/10/22: Re: MAC Architectures
RadioShox:
    109839: 06/10/06: Instantiating Altera M4K block without MegaWizard
Radosalw Gasiorek:
    17122: 99/07/01: 82XX INTEL
Radoslaw Gasiorek:
    20827: 00/02/23: IEC 1131-3 i NEED HELP
Radoslaw Mitura:
    44876: 02/07/03: Jtag extest
Rad Zoltn:
    35515: 01/10/09: VHDL code
    35849: 01/10/20: I search a free 8086 core...
Rafa:
    83550: 05/05/03: JTAG without parallel port
Rafael:
    134174: 08/07/28: code for slipway + abits
Rafael Antunes Nobrega:
    45692: 02/08/01: FPGA needed
Rafael Arce:
    80091: 05/03/01: Re: Resource (FMAPs) use when using block RAMs
Rafael Deliano:
    124353: 07/09/19: Re: FPGA history
    130268: 08/03/19: Re: A Challenge for serialized processor design and implementation
Rafael Gadea Girones:
    18472: 99/10/26: BlockRAM of VIRTEX
rafael plonka:
    35009: 01/09/17: Altera Quartus II: Ouput skew ;-(
    35391: 01/10/02: Implementation of Quartus Megafunctions in Mentor HDS???
    35854: 01/10/21: Re: Verilog vs. VHDL
    36362: 01/11/07: Re: FPGA BGA and decoupling
    36813: 01/11/21: Re: Altera & Actel prices
<rafaelcns@gmail.com>:
    90215: 05/10/06: matrix inversion in hardware
Rafal Jastrzebski:
    73794: 04/09/29: Re: what to do with the DCM locked signal?
Rafal Kielbik:
    15156: 99/03/10: LUT
rafayhasan:
    148607: 10/08/05: Verification of the SEU estimates
<rafeeqs@excite.com>:
    19080: 99/11/27: Re: Virtex: Getting flip-flops into the pads
Rafiki Kim Hofmans:
    3112: 96/04/04: addressing PCI-interface
    3201: 96/04/24: so little posts about PCI :(
    3239: 96/05/02: Mr. Holmes D.
    3295: 96/05/10: socket wanted for xilinx or other way to plug in
    3360: 96/05/20: Re: PCI fpga
    3420: 96/05/28: how to use memgen
    3783: 96/07/31: assigning LOC in XACT
    3857: 96/08/09: XACT:error301 with flow engine
    3876: 96/08/13: Re: XACT:error301 with flow engine
    3890: 96/08/15: XACT6.0:prosim and routed design
    3909: 96/08/18: Re: XACT6.0:prosim and routed design
    3964: 96/08/26: XC4010E en downloading bitstream
    4027: 96/09/04: Re: Xilinx Foundation w/64Mb RAM
    4055: 96/09/06: Re: PCI Bus Protocal & FPGA vendors
    4070: 96/09/07: Re: Help with XACT 6.0 ProSim Problem
    4331: 96/10/16: xc4000 and 2 clocks
Raghavendra:
    61211: 03/09/30: Re: Implementing Bidirectional pins
    65435: 04/01/29: what is back annotation
    65436: 04/01/29: Power extimation?
    69098: 04/04/27: Re: ASIC RTL and FPGA RTL
    75162: 04/10/27: Re: unstable fpga design
    74461: 04/10/11: DCM for generating higher frequencies.
    77159: 04/12/26: Doubt on DDR SDRAM read/write operation sequence.
    77405: 05/01/06: Refresh rate in DDR-SDRAM
Raghavendra G Jorapur:
    3605: 96/07/03: Re: LCA to Schematic
    3718: 96/07/21: Re: FPGA - RAM interfacing
    3793: 96/08/02: Re: assigning LOC in XACT
raghu:
    110843: 06/10/24: Please Help
    140424: 09/05/13: Connect two bidirectional pins in FPGA
Raghu:
    110632: 06/10/18: Learner
<raghunandan85@gmail.com>:
    131572: 08/04/25: PLB Master Example
    131679: 08/04/28: Re: PLB Master Example
    131846: 08/05/03: Re: PLB Master Example
    132389: 08/05/25: EDK 10.1 Map Error
    132432: 08/05/27: Re: EDK 10.1 Map Error
    132433: 08/05/27: Re: XILINX core generator question
    132473: 08/05/28: Re: EDK 10.1 Map Error
    132923: 08/06/10: Re: Cheating the FPGA clock speed
<raghurash@rediffmail.com>:
    87067: 05/07/14: Re: ise 7.1 Input clk is never used.
ragon:
    17718: 99/08/27: Short path check in Virtex M2.1i
Ragu:
    134219: 08/07/31: Re: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION
Rah:
    51227: 03/01/07: Spartan II:Bidirectional IO interfacing 5V CMOS ?
Rahul:
    52057: 03/01/29: Huffman Encoder and Decoder in verilog/ vhdl
rahul joshi:
    47333: 02/09/24: querries regarding cpld
Rahul Khanna:
    64113: 03/12/16: What is this ASMBL thing from Xilinx?
rahul_fpga:
    151873: 11/05/26: Instantiation of an EDF netlist within a Verilog top RTL
rahulkhikher:
    155215: 13/06/11: problem with the GTX wrapper in questa
RAI:
    126648: 07/11/28: Re: An error occured while using Dual Port Block Memory
Rai:
    141773: 09/07/08: Multipliers and CORDIC cores
    141798: 09/07/09: Re: Multipliers and CORDIC cores
    141800: 09/07/09: Re: Multipliers and CORDIC cores
    141806: 09/07/10: Re: Multipliers and CORDIC cores
    141842: 09/07/12: Re: Multipliers and CORDIC cores
Rain One:
    48838: 02/10/25: PCI burst reads w/ Spartan
Rainer Becker:
    7908: 97/10/29: Configuration of XC4000 FPGAs with JTAG
    27000: 00/11/07: Flex10KA RAM Inferencing with Synplify 5.1.5
    26999: 00/11/07: Flex10KA RAM Inferencing with Synplify 5.1.5a
Rainer Buchty:
    26883: 00/11/02: Re: OT: Xilinx T-Shirt
    57556: 03/07/02: Re: Xilinx ISE drops support for more parts
    57644: 03/07/03: Re: Xilinx ISE drops support for more parts
    66741: 04/02/26: Re: Free PCI-bridge in VHDL for Spartan-IIE
    67834: 04/03/20: Re: Why It Is not Recommended to Infer latches in VLSI Design...
    75757: 04/11/14: Re: Obsolete processors resurected in FPGAs
    75766: 04/11/14: Re: Obsolete processors resurected in FPGAs
    82692: 05/04/16: Re: Xilinx tools on Linux
    82694: 05/04/16: Re: salary ballpark please guys
    82873: 05/04/19: Re: salary ballpark please guys
    95018: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    97224: 06/02/19: Re: MontaVista Linux and Virtex-II & 4
    97234: 06/02/19: Re: MontaVista Linux and Virtex-II & 4
    98092: 06/03/04: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    101293: 06/04/28: Re: Opteron HT coprocessors
    104968: 06/07/11: Programming the Spartan-3E Starter Kit using Linux?
    105031: 06/07/12: Re: Programming the Spartan-3E Starter Kit using Linux?
    121728: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
    121997: 07/07/17: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    129731: 08/03/04: Re: my Spartan-4 wishlist
    139458: 09/03/30: Re: Toolchain for programming Mach211SP PLD.
    141659: 09/07/02: Re: FPGA as FM RADIO transmitter
    142465: 09/08/12: Re: Spartan-6 Boards - Your Wish List
    142472: 09/08/12: Re: Spartan-6 Boards - Your Wish List
    143047: 09/09/17: 82S153 Fuse Map / Disassembler
    143054: 09/09/17: Re: 82S153 Fuse Map / Disassembler
    143079: 09/09/18: Re: 82S153 Fuse Map / Disassembler
    143098: 09/09/20: Re: 82S153 Fuse Map / Disassembler
Rainer Dorsch:
    14867: 99/02/21: Re: Free circuit design
Rainer M. Malzbender:
    2173: 95/10/25: US-CO-Boulder Digital Designer (EE) Job Opening
    2999: 96/03/11: US-CO-Digital Hardware Designers Wanted
Rainer Malzbender:
    594: 95/01/14: FPGA tools that run on SGI ?
    1478: 95/06/27: OrCAD support for Xilinx 5200 series ??
    1766: 95/08/29: Re: Actel PCI App Note
    1927: 95/09/20: Re: Fast FPGA's?
Rainer Scharnow:
    3496: 96/06/11: Xtal Osc. at XC31xxA
    3510: 96/06/12: Re: Xtal Osc. at XC31xxA
    3554: 96/06/20: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
    3686: 96/07/15: Atmel EEPROMs 17C65: again
    3687: 96/07/15: Re: Atmel EEPROMs 17C65: again
    3689: 96/07/16: Re: Atmel EEPROMs 17C65: again
    3714: 96/07/19: IMPORTANT! ATMEL 17C65
    3767: 96/07/29: Re: Question about books for FPGA
    3804: 96/08/05: Re: Question about books for FPGA
    4107: 96/09/11: XChecker and WinNT or OS/2
Rainer Schmidt:
    52360: 03/02/07: Partial Reconfiguration - Virtex-E
    52370: 03/02/07: Re: Partial Reconfiguration - Virtex-E
    53798: 03/03/24: Difference between static and active partial reconfiguration of Xilinx
Rainer Storn:
    29983: 01/03/20: Book on FPGA-Design with Xilinx chips
    29984: 01/03/20: Packing density of Xilinx FPGAs
Rainier:
    101561: 06/05/03: How to open an ISE 8.1 project in ISE 7.1?
rAinStorms:
    34922: 01/09/14: Help!
    54368: 03/04/09: Re: Altera not supplying Leonardo any more
    54402: 03/04/10: Altera Serial Configuration - ST Serial Flash?
    54893: 03/04/22: Re: Complex FIR in FPGA
    54894: 03/04/22: Re: spartan2e vs cyclone
    54917: 03/04/22: Re: spartan2e vs cyclone
    64422: 04/01/04: Re: please help! state machine
    67301: 04/03/10: Anyone Had Spurious Reconguration Issues With Cyclone Devices?
    67314: 04/03/10: Re: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
    67527: 04/03/14: Re: Anyone Had Spurious Reconguration Issues With Cyclone Devices?
Raintech Consulting Limited:
    29982: 01/03/20: Jobs....?
Raivo Nael:
    65092: 04/01/20: Re: WTD: info on AMD palce22v10
    65258: 04/01/22: Re: WTD: info on AMD palce22v10
    65278: 04/01/23: Re: WTD: info on AMD palce22v10
    65438: 04/01/29: Is FPGA fully static?
    67343: 04/03/10: Re: licence for Xilinx 2.1i
raj:
    69116: 04/04/27: Xpower Static Current
    69283: 04/05/04: synthsizing multi-dimensional array XST
    69481: 04/05/11: VHDL-Verilog Co-Simulation
    69641: 04/05/16: load on a clock signal in FPGA
    70253: 04/06/10: Reading Back Configuration of Slice/LUT
    71661: 04/07/26: configuration SRAM cells in Xilinx/Altera FPGAs
    71693: 04/07/27: Re: configuration SRAM cells in Xilinx/Altera FPGAs
    71729: 04/07/28: Re: configuration SRAM cells in Xilinx/Altera FPGAs
    72617: 04/08/26: Re: Xilinx Command Prompt
    89073: 05/09/05: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
    133513: 08/07/01: real time FIR implementation in FPGA
    133519: 08/07/02: Re: real time FIR implementation in FPGA
    133539: 08/07/03: synthesis in xilinx
    133806: 08/07/16: unified protocol
    133817: 08/07/16: Re: unified protocol
    133839: 08/07/17: Re: unified protocol
    133895: 08/07/18: Re: unified protocol
    136587: 08/11/23: distributed dual port RAM with asynchronous read in ACTEL Smartgen
    137215: 09/01/03: time limited netlist generation
    137228: 09/01/04: Re: time limited netlist generation
Raj B Krishnamurthy:
    24159: 00/07/27: compact PCI Xilinx virtex FPGA card
Raj Kumar Nagarajan:
    51361: 03/01/11: Re: MicroBlaze MDK2.2 opb_timer
Raj Nagarajan:
    63718: 03/12/01: Re: debugging microblaze with xmd
Raj Patel:
    3728: 96/07/22: Xilinx XC6200 Information
raja:
    20039: 00/01/25: global clock distribution
    20090: 00/01/27: CARRY CHAIN CIRCUIT in ORCA 3T
    20175: 00/01/30: Re: Xilinx vs Altera
    20566: 00/02/15: Re: LUT & VHDL
    21249: 00/03/14: Re: Testbench for a modulator and a demodulator
Raja Neogi:
    2437: 95/12/05: final call for paper (ICSE'96)
rajan:
    65551: 04/02/02: Comparison of the Co-verification tools for SoC/ASIC
<rajashekar_798@yahoo.com>:
    94836: 06/01/18: xilmfs on flash
    94894: 06/01/18: Re: xilmfs on flash
    94912: 06/01/19: Re: xilmfs on flash
    94981: 06/01/19: Re: xilmfs on flash
Rajat Karol:
    43699: 02/05/29: Engineering Samples for free?
    43784: 02/06/02: Engineering Samples for free?
Rajeev:
    46633: 02/09/04: Viewing Xilinx netlist
    46670: 02/09/05: Re: Viewing Xilinx netlist
    46706: 02/09/06: Re: Viewing Xilinx netlist
    46708: 02/09/06: Re: Viewing Xilinx netlist
    46937: 02/09/12: Xilinx LogicCore Pipelined Divider Clock Cycles
    46938: 02/09/12: Xilinx LogicCore Pipelined Divider at 4 Clocks/Division
    46972: 02/09/13: Re: 2-D resistor array
    47157: 02/09/19: Re: GCLK pin used like an standard input
    47165: 02/09/19: Re: VHDL : Lookup Table
    47439: 02/09/25: Virtex2 Block Multiplier: Faster, Faster
    47465: 02/09/26: Re: Virtex2 Block Multiplier: Faster, Faster
    47483: 02/09/26: Re: Virtex2 Block Multiplier: Faster, Faster
    47817: 02/10/04: Re: Finding nets in hierarchy
    48379: 02/10/16: Standing on the shores of Stratix-land
    48582: 02/10/21: Re: Standing on the shores of Stratix-land
    48650: 02/10/22: Re: Transferring Design from XILINX --> ALTERA
    48855: 02/10/25: Re: Please recommend a FPGA chip!
    48857: 02/10/25: 3.3V Device Programmer Suggestions ?
    48971: 02/10/28: Re: 3.3V Device Programmer Suggestions ?
    49046: 02/10/30: Re: 3.3V Device Programmer Suggestions ?
    53921: 03/03/27: Tristate pins + Inputs => External Pullup ?
    54197: 03/04/04: Re: Xilinx Divider Core
    54200: 03/04/04: Re: Spartan vs. Cyclone for arithmetic functions
    54203: 03/04/04: Re: PCI specification
    54286: 03/04/07: Re: Tristate pins + Inputs => External Pullup ?
    54326: 03/04/08: Re: price of fpga chips
    54477: 03/04/11: Buying FPGAs from parts brokers
    54563: 03/04/14: Re: Buying FPGAs from parts brokers
    54566: 03/04/14: Re: 2.5V switching regulator for Spartan 2
    54714: 03/04/16: Re: 2.5V switching regulator for Spartan 2
    59387: 03/08/18: Altera JTAG verification
    59434: 03/08/19: Re: Altera JTAG verification
    59500: 03/08/20: Re: Altera JTAG verification
    67647: 04/03/16: Applying Timing Constraints in the face of Synthesis consolidation : Quartus
    67703: 04/03/17: Re: Applying Timing Constraints in the face of Synthesis consolidation : Quartus
    67704: 04/03/17: Re: Answering Machine RAM
    67749: 04/03/18: Re: clock rising edge alignment
    67814: 04/03/19: Altera DSP Builder
    67959: 04/03/23: Re: Apparent Altera Cyclone JTAG problem
    68095: 04/03/26: Re: study verilog or vhdl?
    68171: 04/03/28: Re: counter design
    68238: 04/03/30: Out Of My Depth: VHDL Use Clause warning : Altera DSPBuilder
    68246: 04/03/30: Re: FIFO Depth(Length) Calculation
    68282: 04/03/31: Re: Out Of My Depth: VHDL Use Clause warning : Altera DSPBuilder
    68446: 04/04/05: VHDL: Use of literal '1' on an input port ?
    68494: 04/04/06: Re: Quartus removes Tristate Buffer
    68495: 04/04/06: Re: VHDL: Use of literal '1' on an input port ?
    68641: 04/04/12: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    68648: 04/04/12: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    68716: 04/04/15: Re: Yet Another Altera Online Support Is USELESS Rant...
    68718: 04/04/15: Re: System Generator HDL co-simulatin problem
    68860: 04/04/20: Re: Trouble with rising edge signals in functional simulation
    68886: 04/04/21: Re: What does a "background check" mean? ...
    68887: 04/04/21: Re: Trouble with Altera DSP Builder Licensing while trying to use Signal Compiler...
    68933: 04/04/22: Re: calculate the number of logic gate in FPGA
    69322: 04/05/06: Re: costal loop question
    69438: 04/05/11: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
    69621: 04/05/15: Re: best fpga development board?
    69942: 04/05/25: Re: Driving fpga pin out over long cable
    70143: 04/06/04: Re: VHDL test bench in Quartus
    70210: 04/06/09: Re: comp.arch.fpga: reset strategy
    70363: 04/06/14: Re: RAM in Altera EABs and Xilinx Block Rams
    70373: 04/06/14: Stratix DSP Block: Choosing which FFs are enabled
    70422: 04/06/16: Re: Stratix DSP Block: Choosing which FFs are enabled
    70649: 04/06/22: Re: Initializing data in EAB ram
    70674: 04/06/23: Re: Trying to remember how to use Quartus
    70949: 04/07/02: Re: Does Xilinx have the worst web site on the planet?
    71019: 04/07/05: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
    71068: 04/07/07: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
    71138: 04/07/09: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
    71226: 04/07/12: Re: Same bitstream files give different behavior.
    71286: 04/07/13: Re: extending a signal pulse
    71773: 04/07/29: Re: FPGA vs CPLD
    71806: 04/07/30: Re: FPGA vs CPLD
    72967: 04/09/09: Re: vhdl error ?? - [code included]
    81186: 05/03/18: Re: Which HDL?
    81191: 05/03/18: Re: LVDS as general differential input ?
    81192: 05/03/18: Re: Spartan 3 to tempsensor interface
    81193: 05/03/18: Re: Using DSP Builder with Quartus
    81739: 05/03/30: Re: LVDS as general differential input ?
    108679: 06/09/14: ispDesignExpert available for download anywhere ?
    108692: 06/09/15: Re: ispDesignExpert available for download anywhere ?
    108733: 06/09/15: Re: ispDesignExpert available for download anywhere ?
    108965: 06/09/19: Re: VHDL oddity
    109986: 06/10/09: Re: a clueless bloke tells Xilinx to get a move on
    129570: 08/02/27: Using dma_sg_v2_01_a component with plb_ipif
    150112: 10/12/14: ISE 11.5 to ISE 12.3 migration problem
rajeev:
    104513: 06/06/28: NCO Clock driven Designs in FPGA
Rajeev Jayaraman:
    25351: 00/09/07: Re: Slow routing of PWR/GND (Virtex)
    35504: 01/10/08: Call For Papers - Special Issue on Programmable Logic (ACM Trans. on
    42430: 02/04/23: Re: Maximum Usage in a Virtex FPGA
    67879: 04/03/21: Re: Difficulties fitting a design into a Xinlinx Virtex-II XC2V6000 FPGA.
Rajeev Mishra:
    15745: 99/04/11: URGENT! Need VHDL code for ADPCM decompression on Xilinx FPGA
rajendra:
    70524: 04/06/18: Programming FPGA in Xilinx Virtex 2 pro board
    114269: 07/01/10: ise8.1 and 8.2 difference for SIM_CLKIN_CYCLE_JITTER parameter
Rajendra:
    104141: 06/06/19: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
rajendra k singh:
    72390: 04/08/17: linux on virtex 2 pro board
    72414: 04/08/18: Re: linux on virtex 2 pro board
rajesh:
    137126: 08/12/24: Generation of WR and RD signal for ASYNC FIFO
    137136: 08/12/27: Re: Generation of WR and RD signal for ASYNC FIFO
    137160: 08/12/29: Re: Generation of WR and RD signal for ASYNC FIFO
Rajesh Bawankule:
    29394: 01/02/19: Verilog FAQ : February 2001
    30358: 01/04/04: Verilog FAQ: April 2001
    31633: 01/06/01: Verilog FAQ: June 1, 2001
    32170: 01/06/17: Verilog FAQ : Jun 17, 2001
    32597: 01/07/01: FAQ: Verilog FAQ : July 1, 2001
    32658: 01/07/04: Third issue of Chip-Guru is ready: July 2001
    49400: 02/11/11: FAQ: Verilog FAQ : November 15, 2002
Rajesh Gandhi:
    142320: 09/08/04: AES encryption of bitstream - is my design secure?
    142324: 09/08/04: Re: AES encryption of bitstream - is my design secure?
    142325: 09/08/04: Re: AES encryption of bitstream - is my design secure?
    142326: 09/08/04: Re: AES encryption of bitstream - is my design secure?
    142328: 09/08/04: Re: AES encryption of bitstream - is my design secure?
    142334: 09/08/05: Re: AES encryption of bitstream - is my design secure?
    142342: 09/08/05: Re: AES encryption of bitstream - is my design secure?
    142354: 09/08/05: Re: AES encryption of bitstream - is my design secure?
    142369: 09/08/06: Re: AES encryption of bitstream - is my design secure?
    142370: 09/08/06: Re: AES encryption of bitstream - is my design secure?
    142453: 09/08/11: Re: AES encryption of bitstream - is my design secure?
    142454: 09/08/11: Re: AES encryption of bitstream - is my design secure?
Rajesh Kumar E.V:
    33631: 01/08/01: VIRTEX E FPGA Configuration through SelectMap
Rajesh Murugesan:
    67250: 04/03/09: How to use BUFGMUX in SPARTAN 2 device????
    67251: 04/03/09: Reg..How to use BUFGMUX in Spartan 2 family
    69392: 04/05/10: Can I use an internal reset signal in DLL?
    69680: 04/05/18: DLL - Change in input frequency (CLKIN)
    69922: 04/05/24: Re: DLL - Change in input frequency (CLKIN) ---help needed
    70061: 04/06/01: DLL- Change in input clock source --Suggestions plz
Rajesh Pathak:
    68976: 04/04/23: Verilog RTL of a Galois Field Multiplier
rajesh52:
    23182: 00/06/16: Verilog FAQ
<rajesh52@hotmail.com>:
    13774: 98/12/24: Version 8 of Verilog FAQ released
    14150: 99/01/15: Re: Verilog Book --- Me too!
    14569: 99/02/04: Re: Verilog ROM Models
    14757: 99/02/15: Verilog FAQ
    14769: 99/02/16: Verilog FAQ
    14974: 99/03/01: Verilog FAQ
    15225: 99/03/15: Verilog FAQ
    16100: 99/05/03: Verilog FAQ
    16660: 99/06/01: Verilog FAQ
    17295: 99/07/19: Verilog FAQ
    17483: 99/07/30: Verilog FAQ.
    17632: 99/08/16: Verilog FAQ
    17887: 99/09/15: verilog FAQ
    17996: 99/09/22: Re: FPGA Compiler II/FPGA Express User's Manual
    18330: 99/10/15: Verilog FAQ
    19141: 99/12/02: Re: HDL editor?
    19142: 99/12/02: Verilog FAQ
    19911: 00/01/17: Verilog FAQ
    20603: 00/02/16: Verilog FAQ
    22205: 00/05/01: Verilog FAQ
    25206: 00/08/30: Verilog FAQ
    28327: 01/01/07: FYI: chip-guru online chip design magazine
    28947: 01/01/30: Verilog FAQ : Jan 2001
<rajesh52@my-dejanews.com>:
    14089: 99/01/12: Re: programming language interface
    14322: 99/01/25: Re: Needed: PCI interface
<rajesh@comit.com>:
    6580: 97/06/04: Alternate Verilog FAQ : New release
    7870: 97/10/26: Verilog FAQ version 5 released
    8114: 97/11/18: Free verilog models , examples
    9889: 98/04/11: Verilog FAQ version released
    10108: 98/04/27: Alt. Verilog FAQ released.
    10312: 98/05/11: Re: available eda environments
    11303: 98/08/03: Verilog FAQ Version 7 published
    11304: 98/08/03: Verilog FAQ Version 7 published
<rajesh@NoSPAM-1606.comit.com>:
    8731: 98/01/22: Re: MAX+II software from Altera.
<rajeshobli@yahoo.co.in>:
    133447: 08/06/29: FIR filter with integer coefficients
Rajeshwary:
    62585: 03/11/02: Spartan II with Digilab board, IO communication
    62731: 03/11/05: ISE : Synthesis process hangs
rajiv:
    68896: 04/04/21: liberary component
    120215: 07/06/03: Synchronization of instruction with clock
    121546: 07/07/07: verilog code for read write in Bram block
    121557: 07/07/08: verilog code for read write in bram block
    121579: 07/07/09: Adding a bram block to a user defined bram controller
<rajivc53@gmail.com>:
    120705: 07/06/14: c code to initialize a peripheral
    121448: 07/07/04: read/write in bram block
Rajkumar:
    128415: 08/01/24: Re: How to choose an FPGA for High speed applications
    128580: 08/01/31: Re: I need a SDRAM controller
    135815: 08/10/16: Re: Xilinx SPI PROM programming via JTAG
Rajkumar Kadam:
    119442: 07/05/19: Re: How do I constraint multiple clock cycle in Altera?
<rajkumar@gdatech.com>:
    12137: 98/10/01: Re: Which FPGA tool is better
    22099: 00/04/22: Re: Interface with Altera's LPM_RAM_IO && Multiple cycle instruction with Synplify??
    25399: 00/09/09: Re: Mealy vs Moore FSM model
rajsinghdua:
    141401: 09/06/23: Interfacing microblaze with External RAM
raju:
    116139: 07/03/02: Re: Where can i get free CAN VHDL core
<raju.penum@gmail.com>:
    116071: 07/02/28: Where can i get free CAN VHDL core
raju_lingala:
    97305: 06/02/20: SDRAM Reading problem
Rajul Maheshwari:
    16841: 99/06/14: site for reconfigurable computing
RaKa:
    87129: 05/07/15: Re: Why cann't this block be synthesized in top level
    116211: 07/03/04: Ideas for Masters Project.
    126029: 07/11/13: Asynchronous FIFO Latency.
rakesh:
    90517: 05/10/15: Problem with Xilinx Impact under windowsXP
Rakesh Sharma:
    74008: 04/10/02: How to generate a signal on Xilinx Spartan II
    74901: 04/10/21: Xilinx translate error : Cannot find signal "clk"
Rakesh YC:
    71134: 04/07/09: configuration for a mixed mode VHDL-verilog lang
Ralf:
    43794: 02/06/03: Lattice Synario Service Pack
    84535: 05/05/20: ALTERA EPXA1 SDRAM BUG
Ralf =?iso-8859-1?Q?Oberl=E4nder?=:
    30239: 01/03/29: Encryption Bitstrems
    30706: 01/04/25: Failed to configure Spartan2
Ralf A. Eckhardt:
    28687: 01/01/21: xc95108 funny behaviour
    28691: 01/01/21: Re: xc95108 funny behaviour
    28717: 01/01/22: Re: xc95108 funny behaviour
    28730: 01/01/22: Re: xc95108 funny behaviour
    42527: 02/04/26: Re: XC9500XL problem
    48947: 02/10/28: Re: cpld I/O modes
Ralf Duschef:
    82529: 05/04/13: Re: "The ISE 7.1 Experience"
Ralf Hildebrandt:
    42963: 02/05/08: Re: State machine synthesis
    49439: 02/11/12: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
    51174: 03/01/05: Re: conversions and some assistance please
    55777: 03/05/19: Re: about simulation
    56847: 03/06/17: Re: An All Digital Phase Lock Loop
    57006: 03/06/20: Re: Quartus bug or wrong VHDL?
    57480: 03/07/01: Re: FPGA vs. DSP.
    59921: 03/09/01: Re: What does + synthesize to?
    65227: 04/01/22: Re: How can I have multiple drivers of one inout port?
    66550: 04/02/22: Re: Comparator and minimum value address
    66558: 04/02/22: Re: Comparator and minimum value address
    69695: 04/05/18: Re: std_logic_vector vs unsigned
    82964: 05/04/20: Re: Unconstrained ports for synthesis
    92761: 05/12/06: Re: Info on packing regular tree-like structures into rectangles?
    97973: 06/03/02: Re: Help wanted
    97982: 06/03/02: Re: Help wanted
    98681: 06/03/14: Re: VHDL
    98728: 06/03/15: Re: About Altera FPGA Board
    98787: 06/03/16: Re: About Altera FPGA Board
    98789: 06/03/16: Re: Urgent Help Needed!!!!!
    98870: 06/03/17: Re: About Altera FPGA Board
    98873: 06/03/17: Re: Urgent Help Needed!!!!!
    98969: 06/03/18: Re: Microblaze FSL peripheral problem
    98976: 06/03/18: Re: Urgent Help Needed!!!!!
    99001: 06/03/18: Re: About Altera FPGA Board
    99133: 06/03/20: Re: Urgent Help Needed!!!!!
    99359: 06/03/23: Re: XST takes unusually long
    99441: 06/03/24: Re: XST takes unusually long
    99611: 06/03/27: Re: Clock multiplication without using the Xilinx DCM's
    100250: 06/04/05: Re: Dual-edge synthesizable D flip-flop - any pitfalls?
    100414: 06/04/08: Re: Compiler to FPSLIC
    100484: 06/04/10: Re: How to handle the high fanout
    101437: 06/05/01: Re: Question about the ip I developed
    101710: 06/05/05: Re: RFID chip has battary in it or not
    101828: 06/05/07: Re: flashing a led
    102328: 06/05/15: Re: difference of variable and signal
    104216: 06/06/21: Re: xst can, but vcomp can't
    104282: 06/06/22: Re: xst can, but vcomp can't
    104316: 06/06/23: Re: xst can, but vcomp can't
    104317: 06/06/23: Re: stimulus for FPGA
    104340: 06/06/24: Re: stimulus for FPGA
    105090: 06/07/13: Re: how to implement multi-port memory
    105677: 06/07/28: Re: Verilog case statements
    105681: 06/07/28: Re: Verilog case statements
    105711: 06/07/29: Re: Verilog case statements
    105712: 06/07/29: Re: "This design element is inferred rather than instantiated" (newbie)
    105770: 06/07/31: Re: Verilog case statements
    105899: 06/08/02: Re: generating sine-like waveforms
    106011: 06/08/05: Re: How to implement large ROM's from binary sources?
    106080: 06/08/07: Re: verilog versus vhdl
    106356: 06/08/12: Re: Embedded clocks
    106357: 06/08/12: Re: ISE Webpack 8.1 adder wierdness
    106917: 06/08/22: Re: hex format 16 bit?
    107815: 06/09/01: Re: Higher voltages input, quick check....
    108274: 06/09/07: Re: how can I decrease the time cost when synthesis and implement
    108936: 06/09/19: Re: BUF component
    109294: 06/09/23: Re: please tell me how to learn testbench?
    110684: 06/10/19: Re: Meeting Timing Constraint
    111540: 06/11/05: Re: Integration of modules
    112755: 06/11/28: Re: pre-synthezis simulation in ModelSim for Actel
    112829: 06/11/29: Re: pre-synthezis simulation in ModelSim for Actel
    112832: 06/11/29: Re: FPGA workstation - should I wait for Window Vista?
    112833: 06/11/29: Re: FPGA application field
    112892: 06/11/30: Re: FPGA application field
    112950: 06/12/02: Re: FPGA application field
    113920: 06/12/29: Re: SPI slave problem
    114494: 07/01/17: Re: Process on both edges
    114568: 07/01/19: Re: Generation of Divided-by-3 clock
    115887: 07/02/23: Re: porting virtex2-pro into virtex4. Performance!!
    115888: 07/02/23: Re: 2x technique
    116287: 07/03/06: Re: VHDL and Latch
    116766: 07/03/17: Re: What official function should I call to genertate a sum of products
    117737: 07/04/09: Re: Clocking data into a shift register on positive AND negative
    118016: 07/04/16: Re: combinatorial vs sequential
    119027: 07/05/09: Re: 'EVENT (or rising_edge) static prefix requirement....
    120212: 07/06/03: Re: Microcontrollers have a better predictable time behaviour than
    122052: 07/07/18: Re: Latches
    122067: 07/07/18: Re: or1200 uses more than 100% of resources. how to reduce?
    122142: 07/07/20: Re: Counter ?
    123693: 07/09/02: Re: flip-flop enable
    128046: 08/01/14: Re: sine and cosine wave generation
    129313: 08/02/20: Re: From ASIC RTL to FPGA, what are the things I should take care
    144153: 09/11/14: Re: An incomplete Mux and Latch?
    144726: 09/12/29: Re: fsm coding question
    147689: 10/05/16: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
Ralf Koehler:
    6271: 97/05/07: universal PCI-Interface with FPGA?
Ralph:
    47597: 02/09/30: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
    93911: 06/01/03: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
    94143: 06/01/06: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
ralph:
    42402: 02/04/23: Re: Post-synthesis simulation
    94061: 06/01/05: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
    153737: 12/05/03: Re: FPGA communication with a PC (Windows)
Ralph Friedrich:
    27871: 00/12/13: Configuration : XC4000
    87335: 05/07/21: Re: General-purpose STAPL Composer?
Ralph Hartley:
    109491: 06/09/27: Re: An algorithm with Minimum vertex cover without considering its
Ralph Malph:
    64523: 04/01/06: Re: Spartan3 availability
    64637: 04/01/09: Re: Anybody know what the REAL story is? Jim figured it out.
    64649: 04/01/10: Re: Anybody know what the REAL story is? Jim figured it out.
    64670: 04/01/11: Re: Spartan-3 LC Development Kit from Insight (Memec)
    64680: 04/01/11: Re: Spartan-3 LC Development Kit from Insight (Memec)
    64681: 04/01/11: Re: Spartan3 prices again...
    64703: 04/01/11: Re: Altera Cyclone data is incomplete or messy
    64721: 04/01/12: Re: fpga database?
    64814: 04/01/14: Re: Altera Cyclone data is incomplete or messy
    64815: 04/01/14: Re: Open source ARM, Version 0.1
    64828: 04/01/14: Re: Altera Cyclone data is incomplete or messy
    64833: 04/01/14: Re: Altera Cyclone data is incomplete or messy
    64901: 04/01/15: Re: Spartan-IIE as an ASYNC RAM?
    64943: 04/01/16: Re: Spartan-IIE as an ASYNC RAM?
    65059: 04/01/19: Re: Deriving 36MHz from a 40MHz crystal using DCM?
    65060: 04/01/19: Re: Spartan3 prices again...
    65062: 04/01/19: Re: Which version of ISE Webpack has FPGA Editor on it?
    65063: 04/01/19: Re: WTD: info on AMD palce22v10
    65064: 04/01/19: Re: QUES: Where can I find Xilinx M1 tools
    65177: 04/01/21: Re: WTD: info on AMD palce22v10
    65222: 04/01/22: Re: WTD: info on AMD palce22v10
    65224: 04/01/22: Re: Soft failures (?) 9536XL
    65252: 04/01/22: Re: OT: liability insurance
    65253: 04/01/22: Re: xilinx 70% tracking rule
    65256: 04/01/22: Re: Why is router software not multi-threaded?
    65263: 04/01/22: Re: WTD: info on AMD palce22v10
    65311: 04/01/24: Re: WTD: info on AMD palce22v10
    65312: 04/01/24: Re: xilinx 70% tracking rule
    65406: 04/01/27: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
    65412: 04/01/27: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
Ralph Mason:
    20184: 00/01/30: Which FPGA to learn with?
    32169: 01/06/18: Verilog or VHDL?
    48595: 02/10/22: Newbie Questions - Jan Gray XSOC
    48614: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
    48642: 02/10/22: Webpac Simulation
    48680: 02/10/23: Re: Webpac Simulation
    48683: 02/10/23: Re: Webpac Simulation
    48685: 02/10/23: Re: Newbie Questions - Jan Gray XSOC
    48883: 02/10/26: #1's in verilog
    48921: 02/10/27: Couple of Questions
    49025: 02/10/30: Re: filters on fpgas
    49165: 02/11/04: Learner ? - Open Collector in Verilog
    49264: 02/11/07: Instruction sets to implement instruction sets
    49324: 02/11/09: Re: Instruction sets to implement instruction sets
    49423: 02/11/12: Re: CLB numbers for various ops?
    49658: 02/11/19: Some Basic Understanding - RTL
    50207: 02/12/05: Re: ISA bus VGA
    50370: 02/12/10: Tiny Forth Processors
    50421: 02/12/11: Re: Tiny Forth Processors
    50448: 02/12/11: Re: Tiny Forth Processors
    50960: 02/12/24: Re: Combinatorial clock source question
    51975: 03/01/28: Re: GNU C for custom processor
    52403: 03/02/08: XC9536XL - ISP
    52536: 03/02/13: Setting CPLD options (Webpac)
    52965: 03/02/27: xc9500 Low power mode
    52991: 03/02/28: Re: xc9500 Low power mode
    53272: 03/03/10: Re: Clocking a spartanIIE with a 5V signal?
    53602: 03/03/18: Re: new XC95xx global clock
    53610: 03/03/18: Re: new XC95xx global clock
    53820: 03/03/25: Re: Xilinx FPGAs available?
    54065: 03/04/02: Re: XC9572XL Macrocell power
    54073: 03/04/02: Re: XC9572XL Macrocell power
    54110: 03/04/03: Re: XC9572XL Macrocell power
    55108: 03/04/27: Re: Xilinx of Linux HOWTO has been updated
    55526: 03/05/12: Re: help on FPGA-programming tutorial for students
    55578: 03/05/13: Re: OK I am pissed off with Xilinx webpack.
    55695: 03/05/16: Re: smallest embedded cpu.
    55697: 03/05/16: Re: smallest embedded cpu.
    55714: 03/05/17: Re: smallest embedded cpu.
    55929: 03/05/24: Re: CLKDLL: Dividing
    55966: 03/05/25: Re: Newbie CPLD question
    55967: 03/05/25: Re: Why is there a large gulf between CPLD and FPGA?
    56036: 03/05/28: Re: 2 Questions about VHDL
    56058: 03/05/28: Re: FIFO Controller
    56090: 03/05/29: Re: FIFO Controller
    56163: 03/05/30: FPGA's an Flash
    56177: 03/05/30: Re: FPGA's an Flash
    56433: 03/06/05: Re: Xilinx Block RAM
    56747: 03/06/13: Re: How to Capture a VGA display EXTERNALLY
    57295: 03/06/27: Xlilin xc9572XL Default register values
    57302: 03/06/27: Re: Xlilin xc9572XL Default register values
    57378: 03/06/29: Re: Xlilin xc9572XL Default register values
    57403: 03/06/30: Re: Xlilin xc9572XL Default register values
    57441: 03/07/01: Re: Xlilin xc9572XL Default register values
    57402: 03/06/30: Re: Xlilin xc9572XL Default register values
    57582: 03/07/03: Re: Xlilin xc9572XL Default register values
    59154: 03/08/11: Re: FPGA for a Newcomer
    59161: 03/08/11: Re: Upgrading OS or WebPack
    60068: 03/09/05: Re: New to FPGA, seeking advice
    62439: 03/10/30: Re: Xilinx Spartan3: Price
    62694: 03/11/05: Re: FPGA Prototyping Board
    62878: 03/11/11: Re: Home grown CPU core legal?
Ralph Reinhold:
    6911: 97/07/08: Re: Generating Sine/Cosine digitally
Ralph Remme:
    3076: 96/03/27: Re: LOG/iC Installation Problem
    3312: 96/05/13: Re: Looking for free FPGA softw./Xilinx
Ralph Watson:
    1925: 95/09/20: Re: Anyone using Altera 8820A ?
    2464: 95/12/08: Re: Median filter
    3384: 96/05/23: Re: Fitting problems with Altera MAX9560
Ralph Weir:
    20882: 00/02/25: Re: MRP systems
    30109: 01/03/23: Re: Virtex Em on a board?
    30363: 01/04/04: Re: DSP Volume-control in FPGA
ralphie:
    110392: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
    110395: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
ralstef:
    115184: 07/02/01: DDR SDRAM controller for virtex 2 pro
Ram:
    60214: 03/09/08: FPGA: Interfacing external NVRAM
    60819: 03/09/23: PPC access to PROM using Virtex @ pro
    60923: 03/09/24: on the fly Reconfig
    68083: 04/03/25: Re: xilinx PPC map file
    78712: 05/02/06: problem with xilinx platform studio 6.2i
    78792: 05/02/07: Re: problem with xilinx platform studio 6.2i
    78849: 05/02/08: virtex4 distributed RAM
    78861: 05/02/09: Beginner: running EDK 6.3 in linux
    78897: 05/02/09: Re: Beginner: running EDK 6.3 in linux
    78902: 05/02/09: Re: virtex4 distributed RAM
    78903: 05/02/09: Re: virtex4 distributed RAM
    78906: 05/02/09: Re: virtex4 distributed RAM
    88947: 05/09/01: FS: Lot of 60 XCV1000 FPGAs
    88978: 05/09/01: Re: Lot of 60 XCV1000 FPGAs
    89287: 05/09/11: Which JTAG cable for Xilinx & Linux?
    89318: 05/09/12: ISE 7.1i & Linux / reg code question
    89321: 05/09/12: Microblaze & Memory DMA operation
    89348: 05/09/13: Re: ISE 7.1i & Linux / reg code question
    89349: 05/09/13: Re: Microblaze & Memory DMA operation
    89367: 05/09/13: Re: ISE 7.1i & Linux / reg code question
    89370: 05/09/13: Re: Microblaze & Memory DMA operation
    89555: 05/09/19: Re: Reading a PAL fusemap with a microscope
    89591: 05/09/20: ISE 7.1i & Linux / reg code question
    89870: 05/09/28: Re: a ISE installation problem on linux
    89871: 05/09/28: Pricing for V2-Pro / V4-FX ?
    89872: 05/09/28: Req to Xilinx: eCos port for Microblaze
    90004: 05/10/01: Re: Req to Xilinx: eCos port for Microblaze
    91402: 05/11/05: Re: FPGA : PCI-CORE
ram:
    8212: 97/11/29: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
    12651: 98/10/21: Re: Schematic entry?
    14454: 99/01/30: Re: No. of CLBs in Xilinx nearly 100% can't implement.
    60043: 03/09/04: Memory
    60094: 03/09/04: Re: Memory
    61052: 03/09/26: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
    61910: 03/10/14: Re: Universities that focus on IC design
    61912: 03/10/14: Partial Reconfiguration
    61916: 03/10/14: Partial/ Dynamic Reconfiguration Virtex 2 pro- does it have any help at all
    61918: 03/10/14: Re: Xilinx "Programming failed" message
    61932: 03/10/15: Re: newbie linker script question
    61986: 03/10/15: Re: Partial Reconfiguration
    62015: 03/10/16: Re: explain the vhdl code
    62016: 03/10/16: xilinx System ACE solution
    62099: 03/10/19: Re: To our future engineers, smart and otherwise...
    62216: 03/10/22: PPC boot
    62219: 03/10/22: EMC/SDRAM
    62451: 03/10/29: Questions that question????
    62555: 03/11/01: Re: data recorder examples?
    62981: 03/11/11: Re: How to visit the files in CF cards
    63208: 03/11/17: Re: How to visit the files in CF cards
    64437: 04/01/04: System Ace - Flash card formatting
    64838: 04/01/14: Re: Can i get a sample XSVF file?
    64840: 04/01/14: Re: Microblaze simulation
    65161: 04/01/21: EDK - Desinging system with C++
    65334: 04/01/24: Re: Spirit on Mars
    65995: 04/02/10: Building a NN using FPGA
    66060: 04/02/11: Re: Xilinx Platform Flash Prom
    66061: 04/02/11: Re: XC2V2000 + System Ace + Reconfig
    66522: 04/02/20: Re: Power supply for the Xilinx Virtex Pro FF1152 Proto Board
    66828: 04/02/26: Re: Done Pin Remains Low after JTAG Configuration of V2Pro
    66996: 04/03/02: V2pro + A/D + IrDA + RS232 board???
    66997: 04/03/02: Re: Xilinx iMPACT error: "Done did not go high"
    67489: 04/03/12: Re: System Ace: can not program Avnet V2P7 board
    67533: 04/03/13: Re: Virtex 2 P -> PPC write to block RAM
    67534: 04/03/13: Re: any body help me about xc4010e board
    67557: 04/03/14: Board with all modules
    67733: 04/03/17: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
    67734: 04/03/17: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
    67860: 04/03/21: Re: What's the flow V2P SysAce handles the software inside the ACE file
    68027: 04/03/24: Re: PULL-UPs on Xilinx-FPGA
    68034: 04/03/24: Re: PULL-UPs on Xilinx-FPGA
    68160: 04/03/28: Re: Help with Xilinx Ram16X1S example VHDL code
    68311: 04/03/31: Re: Virtex 2 PRO Eval/Development platforms
    68313: 04/03/31: newbie - TCP/IP
    68643: 04/04/12: system C - streams C
    68960: 04/04/22: Re: FPGA within demonstration
    68961: 04/04/22: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    68962: 04/04/22: Re: liberary component
    68963: 04/04/22: Re: documents
    69202: 04/04/29: Re: basic question, virtex 2 pro
    69207: 04/04/29: Is this a best approach- FPGA ANN
    69361: 04/05/07: OPB IPIF user logic
    70342: 04/06/13: Re: Xilinx .bit to .svf...
    71219: 04/07/12: Re: Need some help regarding dynamic reconfiguring of the pin connections
    72345: 04/08/16: Re: Using SDRAM on Xilinx AFX V2P board
    75473: 04/11/06: what's the scenario out there
    112350: 06/11/20: timing constraints
    112351: 06/11/20: timing constraints
    112482: 06/11/22: query
    112530: 06/11/24: types of FPGA
    112574: 06/11/24: query
    112575: 06/11/24: query
    112631: 06/11/26: query in constraining timing
    112638: 06/11/26: Re: query in constraining timing
    112639: 06/11/26: Re: query in constraining timing
    112643: 06/11/26: Re: query in constraining timing
    112653: 06/11/27: tips for P&R in FPGA(quartus)
    112869: 06/11/30: help
    112947: 06/12/01: Hi
    113014: 06/12/05: Re: Hi
    113071: 06/12/05: query in gate level simulationin quartus s/w 6.0
    113200: 06/12/07: query regarding capacitance of pins of cyclone device
    113466: 06/12/14: query
    113506: 06/12/14: Query
    113507: 06/12/14: Re: Query
    115242: 07/02/04: query in P&R of FPGA
    115243: 07/02/04: Re: query in P&R of FPGA
    116187: 07/03/03: regarding power and timing
    116315: 07/03/07: Re: A Very good VLSI Chip design website
    117710: 07/04/08: query
    121338: 07/07/02: cosimulation
    122474: 07/07/28: query in byte blaster/signal topic logic analyser
Ram Meenakshisundaram:
    17554: 99/08/10: Newbie - what are the limitations of the student edition
    17556: 99/08/10: Emulating a transputer on FPGA
    17565: 99/08/10: Re: Emulating a transputer on FPGA
    19868: 00/01/14: XACT where is it??
Ram Prabhakar:
    6595: 97/06/04: Re: Alternate Verilog FAQ : New release
Ramakrishnan:
    45753: 02/08/04: Controller for a Architecture
    45789: 02/08/05: Re: Controller for a Architecture
    45805: 02/08/06: Re: Controller for a Architecture
    45947: 02/08/12: Reconfiguration in Xilinx FPGA
    45958: 02/08/12: Re: Reconfiguration in Xilinx FPGA
    45981: 02/08/13: Re: Reconfiguration in Xilinx FPGA
    46091: 02/08/17: Re: Reconfiguration in Xilinx FPGA
    46104: 02/08/19: onboard reconfiguration of Xilinx FPGA
    46125: 02/08/19: Re: onboard reconfiguration of Xilinx FPGA
    46155: 02/08/20: Re: onboard reconfiguration of Xilinx FPGA
    46241: 02/08/22: Downloading bit streams in Xilinx
    46272: 02/08/23: Re: Downloading bit streams in Xilinx
    93156: 05/12/14: Xst Error
<ramakrishnan.vijayakumar@gmail.com>:
    111151: 06/10/30: Programming Virtex II Pro Eval Board
Raman Arora:
    38405: 02/01/14: Re: speech recognition - active noise cancellation
Raman Narayan:
    24007: 00/07/20: Re: 104 Page Collective DAC'00 Trip Report Up
Ramanathan:
    27772: 00/12/07: Test Bench
Ramanathan S:
    29687: 01/03/05: URGENT HELP REQ......
Rambutwa Gooberundi:
    9492: 98/03/18: Re: Xilinx XACT 6.01 crack
ramesh:
    95646: 06/01/24: porting linux on ml403
    96588: 06/02/07: Re: porting linux on ml403
    97031: 06/02/15: can i use gcc of EDK?
Ramesh:
    148802: 10/08/26: Re: Differences between Verilog versions
Ramesh C. Tekumalla:
    5468: 97/02/18: Re: Mealy/Moore state machines
Ramesh Narayanaswamy:
    2597: 96/01/10: Re: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
    7133: 97/08/04: Re: Simulating large VHDL design (FPGA backannotated)
<ramesh_z@my-deja.com>:
    22914: 00/06/02: view synthesis 7.0
    23086: 00/06/14: ASIC DESIGN
    23657: 00/07/04: silicon
Rami:
    26042: 00/10/01: Begineer
Rami Gideoni:
    7614: 97/09/28: Re: vme vs compact pci
    7615: 97/09/28: Re: vme vs compact pci
Raminder S Bajwa:
    982: 95/04/06: Re: Aptix (Field Programmable Interconnect) ??
    1048: 95/04/20: VMEbus interface using fpgas
Ramnath:
    35851: 01/10/20: Xilinx Libraries
    35852: 01/10/20: Fpga Synthesis Process
    35859: 01/10/21: FPGA based IPv6 router -- hi
    36522: 01/11/10: Reconfigrable Routers
    36868: 01/11/22: Re: Viewing generated VHDL
    36888: 01/11/23: Re: Fpga Synthesis Process
    37483: 01/12/12: Constraints Some basics
    37539: 01/12/13: Relation between net delay & Period
ramshankar:
    33233: 01/07/19: foundation series 2.1i
Ramtilak:
    71182: 04/07/11: Need some help regarding dynamic reconfiguring of the pin connections
    71514: 04/07/20: Area constraint on a sub-module
    72326: 04/08/14: Hardware/Software Communication in Virtex-2p
Ramy:
    24516: 00/08/11: Re: Xilinx chip not programming correctly
    24678: 00/08/16: Re: Xilinx chip not programming correctly
    24679: 00/08/16: Permanently programming FPGAs
ramy:
    24484: 00/08/10: Help with Xilinx
    79546: 05/02/20: does anyone have a c compiler for the picoblaze
    79547: 05/02/20: Re: Question about microblaze C complier
    79688: 05/02/23: Re: C compiler for Picoblaze
ran:
    77058: 04/12/21: MAP failes after inserting ILA and ICON cores to the design
    77093: 04/12/21: Re: MAP failes after inserting ILA and ICON cores to the design
    77111: 04/12/23: Re: MAP failes after inserting ILA and ICON cores to the design
    77442: 05/01/06: Re: MAP failes after inserting ILA and ICON cores to the design
rana:
    140947: 09/05/30: time constraining asynchronous fifo
    147996: 10/06/11: how to interface a ddr2 memory controller to a processor
    148001: 10/06/11: Re: how to interface a ddr2 memory controller to a processor
    148002: 10/06/11: Re: how to interface a ddr2 memory controller to a processor
ranbow:
    64051: 03/12/14: multiplier,CLK-insufficient RECOVERY time after async CLEAR
    64086: 03/12/15: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
    64115: 03/12/17: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
    64137: 03/12/18: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
Randal Kuramoto:
    37625: 01/12/17: Re: ISP by JTAG using a microcontroller
    45221: 02/07/16: Re: Spartan PROMs...
Randall Holman:
    45110: 02/07/12: PCMCIA host
Randall Logan:
    14043: 99/01/08: Anyone have an Altera LP6 interface card FS?
<randallchaas@sbcglobal.net>:
    129538: 08/02/27: Re: Viewing RTL schematic in Xilinx ISE
<randombit@my-deja.com>:
    19640: 00/01/05: Re: Design security
    19641: 00/01/05: Re: Design security
    19642: 00/01/05: Re: Design security
randomdude@gmail.com:
    82271: 05/04/10: A PCI FPGA card I found on ebay
    82276: 05/04/10: Re: A PCI FPGA card I found on ebay
    82288: 05/04/10: Re: A PCI FPGA card I found on ebay
    84364: 05/05/17: VHDL array question
    84376: 05/05/18: Re: VHDL array question
    84395: 05/05/18: Re: VHDL array question
<randomdude@gmail.com>:
    121032: 07/06/22: Reshipping spartan3 PCIE board to England
    121064: 07/06/24: Re: Reshipping spartan3 PCIE board to England
    122289: 07/07/25: Re: Beginners question
    122763: 07/08/06: Re: Need suggestion for my project
    134786: 08/08/31: FPGA on a DIMM module, performing encryption
    134788: 08/08/31: Re: FPGA on a DIMM module, performing encryption
    134798: 08/09/01: Re: FPGA on a DIMM module, performing encryption
    134802: 08/09/01: Re: FPGA on a DIMM module, performing encryption
    134824: 08/09/02: Re: FPGA on a DIMM module, performing encryption
<randraka@ids.net>:
    452: 94/11/21: RE: Looking for VHDL & VIEWLOGIC FPGA Experts/Consult
    568: 95/01/06: RE: Fpga programming
    579: 95/01/10: Lee Fadden, what is your address?
    595: 95/01/15: Re: ViewLogic simulation without master reset
    617: 95/01/19: Re: ViewLogic simulation without master reset
    629: 95/01/23: Re: ViewLogic simulation without master reset
    677: 95/02/03: re:Inefficiency(?)
    681: 95/02/05: Re: "on-fly" reprogrammable devices/research
    729: 95/02/18: Re: Can I implement a digital PLL in an FPGA??
    776: 95/02/28: Re: Can I implement a digital PLL in an FPGA??
    786: 95/03/02: Re: Can I implement a digital PLL in an FPGA??
    800: 95/03/03: RE: FPGA Custom Computing Machine
    836: 95/03/09: Re:FPGA bit serial multipliers, correction
    1095: 95/04/27: Re: Need help about conference chip
    1185: 95/05/12: Re: Overheating (was Re: Compression algo's for FPGA's)
    1310: 95/05/31: Re: Any company for conversion FPGA to ASIC?
    1535: 95/07/11: RE: Xilinx 5200 Software
    1646: 95/08/10: RE: Xilinx FPGAs ---> Xilinx EPLDs
    1689: 95/08/16: Re: Xilinx xc4013 routing problems ??
    1884: 95/09/15: Re: Fast FPGA's?
    1926: 95/09/20: Re: Fast FPGA's?
<randraka@my-dejanews.com>:
    13026: 98/11/12: Re: placement&routing problems
randy:
    138603: 09/03/01: timequest error
    138991: 09/03/18: PLL inclk error
Randy:
    32606: 01/07/02: Re: Converting character to integer in VHDL
Randy Bickford:
    8549: 98/01/07: seeking example for PWM using PLDs
Randy Bolling:
    704: 95/02/10: Asset
    38605: 02/01/18: Re: VirtexII ES configuration
    38606: 02/01/18: Re: I2C multiplexer
Randy Given:
    23973: 00/07/19: Experts-Exchange
Randy Nachtrieb:
    27800: 00/12/08: FS: ADVICE RTOS In Circuit Emulator
Randy Robinson:
    9989: 98/04/21: Re: Xilinx FPGAs: Usable Pins on XS Boards (Help)
    10330: 98/05/12: Re: How to use LogiBlox Components in FPGA Express?
    10385: 98/05/15: Re: "Inferred" I/O flip-flops in XC4000E
    10386: 98/05/15: Re: Xilinx FGA Express
    14508: 99/02/02: Re: Opinions requested : Minc/Synario alternatives
    14575: 99/02/04: Re: Synplify/Xilinx4085XLA question
    17507: 99/08/03: Re: Xilinx Virtex configuration in chunks
    113675: 06/12/19: Re: unexplainable Problem on Spartan 3
Randy Tietz:
    4799: 96/12/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
    9503: 98/03/19: Re: Looking for space qualified FPGAs/ASICs
Randy Yates:
    11739: 98/09/05: Re: professional autorouters
    14274: 99/01/22: Re: Can we get back to DSP again? Was Re: Who cares what DSP
    19632: 00/01/04: Re: synthesis opportunities
    66451: 04/02/19: Re: Dual-stack (Forth) processors
    66624: 04/02/24: Re: Dual-stack (Forth) processors
    87440: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software
    87465: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software
    87545: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software
    87601: 05/07/27: Re: Best Practices to Manage Complexity in Hardward/Software
    87668: 05/07/28: Re: Best Practices to Manage Complexity in Hardward/Software
    87708: 05/07/29: Re: Best Practices to Manage Complexity in Hardward/Software
    87739: 05/07/30: Re: Best Practices to Manage Complexity in Hardward/Software
    89463: 05/09/15: Re: Looking for a DIgital Systems book with JPEG example code
    132732: 08/06/05: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    132809: 08/06/07: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    132825: 08/06/07: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    132861: 08/06/09: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    135669: 08/10/11: Re: XMOS XC-1 kits are shipping
    141764: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
    146738: 10/03/26: Multipliers in CoolRunner Series?
    146739: 10/03/26: Re: Multipliers in CoolRunner Series?
    146747: 10/03/27: Re: Multipliers in CoolRunner Series?
    146754: 10/03/27: Re: Multipliers in CoolRunner Series?
    146755: 10/03/27: Re: Multipliers in CoolRunner Series?
    146759: 10/03/27: Re: Multipliers in CoolRunner Series?
    146766: 10/03/28: Maximum output rate
    146784: 10/03/28: Re: Maximum output rate
    146816: 10/03/29: Re: Maximum output rate
    148083: 10/06/19: Xilinx DCM Block Stability Issues
    148085: 10/06/19: Re: Xilinx DCM Block Stability Issues
    148092: 10/06/21: Re: Xilinx DCM Block Stability Issues
    148093: 10/06/21: Re: Xilinx DCM Block Stability Issues
    148095: 10/06/21: Re: Xilinx DCM Block Stability Issues
    148110: 10/06/21: Re: Xilinx BULLSHITIX-8, when?
    148809: 10/08/27: Re: Plotting sampled data in Matlab
    156205: 14/01/17: Re: Math is hard
    156241: 14/01/21: Re: Math is hard
<randy97>:
    6935: 97/07/10: http://www.love.com
randyddr:
    141786: 09/07/08: Virtex 4 and 5
randyjg:
    84968: 05/06/01: Re: how to use GCC compiler
RANGA REDDY:
    51031: 02/12/27: RAMDAC implementation in FPGA
    51071: 02/12/30: Re: RAMDAC implementation in FPGA
    51131: 03/01/02: Re: Latch inferring : Async OR Sync ?
    51369: 03/01/12: schematic to VHDL conversion???
    69979: 04/05/25: SDRAM
    69984: 04/05/26: SDRAM controller
    70292: 04/06/11: Re: SDRAM
<ranjeeta.patil@gmail.com>:
    81866: 05/04/02: EDK:Question regarding opb_uart
rao:
    105107: 06/07/13: issue on on using Xilinx PROMS in conjugation with System ACE;
    105818: 06/08/01: Re: Information requested on FPGAs and ARM evaluation boards
    114160: 07/01/05: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
    114169: 07/01/05: Re: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
    115797: 07/02/20: Re: Xilinx MIG DDR2 Documentation
    134994: 08/09/09: IDELAYCTRL Locking problem with ISE10.1i
    135014: 08/09/10: Re: IDELAYCTRL Locking problem with ISE10.1i
    135382: 08/09/29: Problem with mpmc(4.02.a) simulation -- DDR never initializes
    135387: 08/09/29: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
Raoul:
    57951: 03/07/10: XILINX COREGEN FFT CORE 2.0
raph:
    90863: 05/10/24: SoC Processor design at gate level for edu
    136913: 08/12/12: BUFGMUX placement
    136957: 08/12/15: Re: BUFGMUX placement
    137011: 08/12/18: Re: LEON3 processor
    137012: 08/12/18: Re: BUFGMUX placement
    150620: 11/01/28: Re: Xilinx news
raphael:
    100287: 06/04/06: ddr in virtex2
Raphael BELLEC:
    4737: 96/12/09: Fpga, Epld, cpld....
raphfrk:
    122279: 07/07/25: verilog parser question about `defines
    122582: 07/07/31: Re: verilog parser question about `defines
Raquette Eric:
    2024: 95/10/03: Re: FPGA for a 20k gates micro-controller.
raravan:
    17046: 99/06/27: Re: newbie -- What's the best way to get started?
<rarteaga@gmail.com>:
    84048: 05/05/11: Slice Virtex II = Equivalent gates ??
Ras Sim:
    35571: 01/10/10: I need free PCI-Core (vhdl)!!
Rascal:
    23456: 00/06/26: Xilinx XC5200 implementation with F2.1i
    23490: 00/06/27: Re: First time user Spartan problem
    23543: 00/06/29: Re: Xilinx XC5200 implementation with F2.1i
    26440: 00/10/16: Re: PROM 17512
    26491: 00/10/18: Re: source PROM 17512
    26973: 00/11/06: Re: Need help locking pins for Spartan XL
Rashid:
    105163: 06/07/16: An idea for a product (FPGA/ASIC based)
    105165: 06/07/16: Re: An idea for a product (FPGA/ASIC based)
Rashid Karimov:
    37989: 01/12/28: Re: Look for FPGA Starterkit
    38001: 01/12/29: Re: How to set block ram contents ?
<rashid.karimov@gmail.com>:
    104272: 06/06/22: Any eval SW comes with Spartan 3E Dev board from Xilinx/Digilent ?
<rashidk@home.net>:
    85152: 05/06/06: Re: Basics FPGA
rasic:
    111996: 06/11/14: sending data across a 32 bit bus
raso:
    104702: 06/07/04: ADPLL (50Hz to 2kHz)
    105521: 06/07/25: 2Khz clock signal from 50Hz main frequency with ADPLL
    105530: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105553: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105554: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105618: 06/07/27: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
Rasquinha:
    71304: 04/07/14: Quartus SOPC Builder doesnt Recgnize my .elf file
<rasti123@eunet.yu>:
    62942: 03/11/11: Re: Reverse engineering an EDIF file?
Rastislav Struharik:
    20143: 00/01/28: Spartan XL
    62889: 03/11/10: Reverse engineering an EDIF file?
<rastr@lan.novsu.ac.ru>:
    3412: 96/05/27: We can HELP ALTERA user for Remote_simulation projects E-mail:rastr@lan.novsu.ac.ru
rat:
    69373: 04/05/09: is it possible to design usb only with fpga?
    69524: 04/05/13: program flash memory through JTAG on FPGA
    70032: 04/05/28: how can I merge 66mhz pci clock to 33mhz clock?
    70773: 04/06/28: How to add clock delay in CPLD?
    70786: 04/06/28: Re: How to add clock delay in CPLD?
    70845: 04/06/30: a question in the pci interface design
    70882: 04/07/01: Re: a question in the pci interface design
ratemonotonic:
    124739: 07/10/02: Re: Basic VHDL Development kit
    124750: 07/10/03: Re: Basic VHDL Development kit
    125888: 07/11/08: P160 Communication Module 3
    125890: 07/11/08: Re: P160 Communication Module 3
    125935: 07/11/09: Re: P160 Communication Module 3
    126939: 07/12/06: Using FSL with Interrupts
    126975: 07/12/07: Re: Using FSL with Interrupts
    127129: 07/12/12: Newbee Microblaze system BRAM utlization confusion
    127184: 07/12/13: Re: Newbee Microblaze system BRAM utlization confusion
    127185: 07/12/13: Re: Newbee Microblaze system BRAM utlization confusion
    127186: 07/12/13: Re: Newbee Microblaze system BRAM utlization confusion
    127253: 07/12/15: Re: Newbee Microblaze system BRAM utlization confusion
    127639: 08/01/04: XPS MPMC
    127643: 08/01/04: Re: XPS MPMC
    127676: 08/01/05: MPMC On EDK
    127677: 08/01/05: Re: DDR SDRAM demo for Spartan-3E starter kit?
    127730: 08/01/06: Re: MPMC On EDK
    127756: 08/01/07: Re: MPMC On EDK
    127919: 08/01/10: XAPP924 Doesnt work
    127979: 08/01/11: opb_emc_v1_10_b
    128000: 08/01/12: Re: opb_emc_v1_10_b
    128003: 08/01/12: Re: opb_emc_v1_10_b
    128004: 08/01/12: Re: XAPP924 Doesnt work
    128034: 08/01/14: Where has Xilnet gone?
    128207: 08/01/18: Re: Where has Xilnet gone?
    128941: 08/02/11: FSL version compatability with Microblaze version
    131299: 08/04/18: New to FPGA : Timing Closure
    132181: 08/05/16: Resetting FPGA Without watch dog timer
    132227: 08/05/19: Re: Resetting FPGA Without watch dog timer
    132228: 08/05/19: Re: Resetting FPGA Without watch dog timer
    132252: 08/05/19: Re: Resetting FPGA Without watch dog timer
    132381: 08/05/24: Microblaze Cache and FSL problem
Rathna Rao:
    22089: 00/04/20: jobs
ratztafaz:
    130272: 08/03/19: ISE 10.0 finally with multi-threading and SV support ?
    130284: 08/03/19: Re: ISE 10.0 finally with multi-threading and SV support ?
    130514: 08/03/26: Re: ISE 10.0 finally with multi-threading and SV support ?
raul:
    89733: 05/09/23: Re: Modelsim XE, what's the latest version?
    89735: 05/09/23: Re: Modelsim XE, what's the latest version?
    90731: 05/10/19: Re: Best Async FIFO Implementation
    90757: 05/10/20: Re: Best Async FIFO Implementation
    90808: 05/10/21: Re: Best Async FIFO Implementation
    92976: 05/12/10: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
<rauletta@erebor.cudenver.edu>:
    8532: 98/01/05: ASIC 1998 CFP
    8825: 98/01/29: 1998 DAC University Booth (First Call for Participation)
RaulGonz:
    145468: 10/02/11: Actel FPGA corePWM IP
    145493: 10/02/11: Re: Actel FPGA corePWM IP
raulizahi@gmail.com:
    90852: 05/10/23: Re: Best Async FIFO Implementation
    91075: 05/10/28: Re: locking hdl to a particular fpga
<raullim7@hotmail.com>:
    125692: 07/11/01: can i use dual edge or two clocks?
    125700: 07/11/01: Re: can i use dual edge or two clocks?
    125732: 07/11/01: Re: can i use dual edge or two clocks?
    125736: 07/11/02: Re: can i use dual edge or two clocks?
    125784: 07/11/04: Global Variables
    125855: 07/11/06: Time Delay in FPGA
    125857: 07/11/07: FPGA Clock signal
    125924: 07/11/08: Re: FPGA Clock signal
    129450: 08/02/25: XEM3010
raven:
    119598: 07/05/23: Xilinx ML405 / VxWorks 6.3 Bootloader
raven1322:
    143373: 09/10/07: Re: Virtex 5 HDMI
Raven76:
    70199: 04/06/08: handel-c library file
    70269: 04/06/10: Xilinx Floorplanner
Ravi:
    74535: 04/10/13: Problem in Xilinx Rocket IO Simulation using HyperLynx SI tool
ravi:
    11470: 98/08/17: Job opportunities in Bay area for ASIC/ FPGA designers / Application Engg.
Ravi Bhat:
    21669: 00/03/28: Test: Please ignore...
    54815: 03/04/18: test
Ravi Bhormish:
    52269: 03/02/05: A forum for SystemC
Ravi Chandra Anantha:
    19016: 99/11/24: Re: Hierarchical Scan Insertion
Ravi Ramakrishnan:
    1838: 95/09/07: Re: verilog to fpga ?
    2428: 95/12/04: Re: Vendors For Verilog On The PC
Ravi Sankar K.:
    70450: 04/06/17: Synplify_pro
Ravi Singh:
    18179: 99/10/05: Board Designers required
ravihma:
    148211: 10/06/29: error in XPS
ravikumar:
    24910: 00/08/21: urgent help fr a beginer
Ravindra Divekar:
    2985: 96/03/08: x86 using FPGAs ..
    3012: 96/03/13: 8085A using FPGAs....
ravindra kalla:
    87759: 05/07/31: FPGA
    87808: 05/08/01: circular read address generator
    87900: 05/08/03: hi stefen
    88045: 05/08/07: circular buffer(its urgent)
    88195: 05/08/11: use of memory in verilog(uegent please)
    92009: 05/11/19: input in spartan kit(its urgent)
    92328: 05/11/27: hi
<ravipativishnu@yahoo.co.in>:
    116671: 07/03/15: doubt in verilog coding
    116679: 07/03/15: Re: doubt in verilog coding
    116684: 07/03/15: Re: doubt in verilog coding
    117112: 07/03/23: problem while using if or case statements
Raviraj Makwana:
    156538: 14/04/18: ERROR:HDLCompilers:27 - "ipcore_dir/Cordic_atan_synth.v" line 61
ravisguptaji:
    143005: 09/09/14: Everything in single clock cycle.
    143010: 09/09/14: Re: Everything in single clock cycle.
Ravishankar S:
    121117: 07/06/26: Trace capturing
    121119: 07/06/26: Amontec chameleon
    121166: 07/06/27: Re: Trace capturing
    121167: 07/06/27: Re: Amontec chameleon
    121261: 07/06/29: Re: Trace capturing
<raxpeter@gmail.com>:
    119997: 07/05/30: XS40 Download Cable
Ray:
    22469: 00/05/10: Re: Xilinx fpga board schematics?
    60283: 03/09/09: Power-on slope :Spartan IIE
    114058: 07/01/03: FPGA ROUTING
    114064: 07/01/03: Re: FPGA ROUTING
Ray Almond:
    17859: 99/09/14: Opinions Wanted
Ray Anderson:
    71675: 04/07/27: Re: New WinFilter Digital Filter design freeware tool release available.
Ray Andraka:
    1979: 95/09/27: Re: FPGA for a 20k gates micro-controller.
    2007: 95/10/01: Re: FFT in FPGAs ?
    2303: 95/11/18: Re: Industry Trends
    2331: 95/11/20: Re: [q][Reverse Engineering Protection]
    2468: 95/12/09: Re: CRC-32 implementation
    2490: 95/12/18: Re: Gated Clock Problem in Xilinx FPGA Implementation
    2491: 95/12/18: Re: WAnted: correlator!!!!!
    2492: 95/12/18: Re: WAnted: correlator!!!!!
    2829: 96/02/13: Re: Xilinx is NOT specified MINIMUM delay -- is it right??
    2908: 96/02/27: Re: Floating Point and Reconfigurable Architectures
    2964: 96/03/07: Re: [NEWBIE] FPGA Project?
    3087: 96/03/28: Re: Low-power FPGA or EPLD
    3129: 96/04/09: Re: Q: Multiplier & Subtractor in Xilinx 5204 FPGA ?
    3449: 96/06/01: Re: Xilinx and Viewlogic
    3568: 96/06/26: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
    3582: 96/07/01: Re: REQ:Old Picture of Bus
    3647: 96/07/08: Re: FPGA Companies
    3698: 96/07/17: Re: What about the XC6200 ?
    3699: 96/07/17: Re: What about the XC6200 ?
    3700: 96/07/17: Hardware sort?
    3819: 96/08/07: Re: Xilinx/FPGA Timing Problems
    3960: 96/08/24: Re: XC6200 FPGAs
    3978: 96/08/28: Re: USB Host Core for FPGA/Gate Array
    4012: 96/09/03: Re: FPGA vs. Custom design
    4064: 96/09/06: Re: FPGA design project
    4104: 96/09/10: Re: FPGA design project
    4139: 96/09/17: Re: How can I make my XILINX design faster?
    4193: 96/09/24: Re: manchester clock recovery
    4194: 96/09/24: Re: XilinX XC5200 address pointer based FIFO
    4202: 96/09/25: Re: 4800 baud serial input to xc4000
    4231: 96/10/02: Re: Viewlogic 4.1 (DOS) mouse alternatives?
    4252: 96/10/04: Re: Q on Xilinx/Viewsim macros
    4253: 96/10/04: Re: Reconfigurable hardware
    4310: 96/10/13: Re: Async with FPGA?
    4345: 96/10/18: Re: What are I/O's doing prior to configuration?
    4585: 96/11/18: Re: GEC Plessey, Toshiba, PlusLogic FPGAs?
    4689: 96/11/29: Re: Reconfigurable FPGAs in Networking
    4767: 96/12/12: Re: Anyone tried a FFT in a FPGA?
    4778: 96/12/13: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4789: 96/12/15: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4825: 96/12/18: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4836: 96/12/18: Re: Help: FPGA for fast digital signal processing
    4850: 96/12/19: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4851: 96/12/19: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5058: 97/01/17: Re: advice request
    5103: 97/01/23: Altera PCI experience anyone?
    5126: 97/01/24: Re: FPGA & division
    5212: 97/01/30: Re: What is the different between FPGA and CPLD?
    5228: 97/01/31: Re: Steven K. Knapp - no such article
    5230: 97/01/31: Re: What is the different between FPGA and CPLD?
    5231: 97/01/31: Re: Reconfigurable Logic Query
    5336: 97/02/07: Re: FPGA power dissipation
    5362: 97/02/10: Re: FPGAs with internal Tri-state busses ?
    5377: 97/02/11: Re: Random Number Generators with Xilinx FPGA xc4000 series
    5390: 97/02/12: Re: DES Challenge
    5392: 97/02/12: Re: bonding of XC4025
    5445: 97/02/16: Re: Mealy/Moore state machines
    5571: 97/02/25: Re: 2nd try: What kind of functions mostly implemented using FPGAs?
    5699: 97/03/07: Re: Xilinx config pins M0..M2
    5717: 97/03/10: Re: Xilinx FPGA & SIMMs
    5850: 97/03/20: Re: Is this really possible?
    5882: 97/03/22: Re: 8-bit divider in FPGA
    5744: 97/03/11: Re: ACTEL RAM BASED FPGAs
    6163: 97/04/20: Re: Exponential function architecture
    6199: 97/04/24: Re: prep benchmarks for FPGAs
    6220: 97/04/29: Re: Low power PLD?
    6319: 97/05/14: Re: Anyone using Actel software?
    6330: 97/05/15: Re: What's FPGA?
    6370: 97/05/19: Re: Fast comparator
    6600: 97/06/04: Re: New Reconfigurable Computing newsgroup?
    6770: 97/06/26: Re: Any designs to avoid in FPGAs
    6685: 97/06/13: Re: Don't Design With Altera Parts... Altera Obsolete Parts
    6686: 97/06/13: Re: Power consumption (Xilinx FPGA) questions
    6716: 97/06/18: Re: Help, FPGA Information
    6717: 97/06/18: Re: PC Keyboard Controller in a Xilinx...
    6786: 97/06/27: Re: Generating Sine/Cosine digitally
    6814: 97/06/30: Re: Smart Card Design and Interface. How?
    6916: 97/07/08: Re: Generating Sine/Cosine digitally
    6951: 97/07/14: Re: Generating Sine/Cosine digitally
    6895: 97/07/07: Re: Does FAQ for this group exist? (empty)
    7420: 97/09/08: Re: HELP: FIFO's on an FPGA
    7425: 97/09/09: Re: HELP: FIFO's on an FPGA
    7435: 97/09/10: Re: HELP: FIFO's on an FPGA
    7624: 97/09/29: Re: fifos design for fpga
    7715: 97/10/06: Re: bidirectional bus problem
    7744: 97/10/09: Re: bidirectional bus problem
    7797: 97/10/16: Re: I looked up Altera in an Italian dictionary.....
    7798: 97/10/16: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
    7814: 97/10/17: Re: Xilinx delay reports?
    7815: 97/10/17: [Reposted due to Enlow UCE cancel]: Re: Xilinx delay reports?
    7879: 97/10/26: Re: Xilinx Adder Trees in Viewlogic
    7924: 97/10/30: Re: Pin compatible
    7938: 97/11/01: Re: Complex Multiplier
    7990: 97/11/05: Re: Digital reverberator on FPGA
    8013: 97/11/07: Re: Digital reverberator on FPGA
    8020: 97/11/07: Re: Division using FPGAs
    8039: 97/11/10: Re: FPGA basics please ?
    8071: 97/11/14: Re: Looking for dynamically reprogrammable FPGA's
    8087: 97/11/16: Re: Oneshot for Atmel 6K series
    8117: 97/11/19: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
    8135: 97/11/20: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
    8152: 97/11/21: Re: Dr watson & M1
    8163: 97/11/23: Re: Need info on runtime configurable FPGAs
    8164: 97/11/23: Re: what is metastability time of a flip_flop
    8187: 97/11/25: Re: Q: Xilinx foundation V1.3 optimizes out my WHOLE design !?!?
    8412: 97/12/12: Re: combinational multipliers
    8588: 98/01/11: Re: Xilinx Stock
    8678: 98/01/19: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8691: 98/01/20: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8748: 98/01/23: Re: DSP vs FPGA
    8760: 98/01/23: Re: ALtera Devices.
    8839: 98/01/31: Re: VHDL vs schematics
    8840: 98/01/31: Re: How to design 3-staged pipelined multiplier in VHDL for Xilinx 4000XL
    8997: 98/02/12: Re: Walace tree???
    9170: 98/02/27: Re: Correlation implementation...
    9172: 98/02/27: Re: DES: beginner FPGA questions.
    9173: 98/02/27: Re: PLL design with Xilinx 4kseries
    9174: 98/02/27: Re: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
    9344: 98/03/06: Re: Correlation implementation...
    9210: 98/03/02: Re: Correlation implementation...
    9350: 98/03/06: Re: PLL design with Xilinx 4kseries
    9211: 98/03/02: Re: Correlation--Multichannel
    9345: 98/03/06: Re: Die Size Comparison of competing FPGAs
    9505: 98/03/19: Re: Looking for space qualified FPGAs/ASICs
    9549: 98/03/23: Re: Dual port
    9608: 98/03/25: Re: Partially reconfigurable FPGA
    9624: 98/03/26: Re: Dual port
    9646: 98/03/27: Re: Q: Random number generator
    9660: 98/03/28: Re: XactStep6 - The cure for a dongle
    9705: 98/03/31: Re: Floating point representation in FPGA
    9830: 98/04/08: Re: XactStep6 - The cure for a dongle
    9888: 98/04/11: Re: XactStep6 - The cure for a dongle
    9887: 98/04/11: Re: FLEX 10K : FPGA or CPLD
    9991: 98/04/21: Re: Could you help me save CLB's?
    10025: 98/04/22: Re: Arbiter help !!!
    10045: 98/04/23: Re: XC4000XL and Ground Bouncing
    10088: 98/04/26: Re: Make a delay in Xilinx FPGAs (more Details)?
    10242: 98/05/06: Re: Arbiter help !!!
    10211: 98/05/04: Re: DSP in an Altera or Xilinx?
    10230: 98/05/05: Re: DSP in an Altera or Xilinx?
    10231: 98/05/05: Re: Radix-4 CORDIC pipeline -- which chip?
    10267: 98/05/08: Re: Xilinx Routing Delay
    10456: 98/05/19: Re: Building signal delays inside an FPGA
    10457: 98/05/19: Re: Minimal ALU instruction set.
    10563: 98/05/29: Re: Xilinx 5200 - XACT 6.0.1 vs. M1.4
    10757: 98/06/16: Re: Wallace trees
    10867: 98/06/26: Re: High Speed Digital Designers...
    10868: 98/06/26: Re: synthesis and simulation
    10870: 98/06/26: Re: Xilinx Foundation simulator problem?
    10913: 98/06/30: Re: complete testing
    10959: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
    10960: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
    10961: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
    10962: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
    10963: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
    10964: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
    11016: 98/07/10: Re: is the code for XC4000E burned on it or in EEPROM ?
    11057: 98/07/15: Re: Shift Invarient Bit Transform
    11058: 98/07/15: Re: Shift Invarient Bit Transform
    11062: 98/07/16: Re: Shift Invarient Bit Transform
    11065: 98/07/16: Re: Floorplanning Intro?
    11072: 98/07/17: Re: Floorplanning Intro?
    11076: 98/07/17: Re: Shift Invarient Bit Transform
    11085: 98/07/17: Re: Floorplanning Intro?
    11087: 98/07/17: Re: Partial reprogramming
    11117: 98/07/20: Re: Xilinx Dynatext and NTFS ?
    11122: 98/07/20: Re: Need info -> implementing high-speed multipliers
    11123: 98/07/20: Re: Old Contace Information
    11124: 98/07/20: Re: Partial reprogramming
    11148: 98/07/21: Re: How to write a VHDL counter of up & down
    11170: 98/07/22: Re: How to write a VHDL counter of up & down
    11171: 98/07/22: Re: unknown speedgrade question
    11172: 98/07/22: Re: unknown speedgrade question
    11181: 98/07/22: Re: Schematic Symbol Generation
    11294: 98/08/02: Re: how much ? prices of Xilinx chips
    11319: 98/08/04: Re: [Q] motor control onto an FPGA
    11337: 98/08/05: Re: [Q] motor control onto an FPGA
    11338: 98/08/05: Re: fast 8x8-Multiplyer
    11411: 98/08/11: Re: Security
    11415: 98/08/11: Re: Combinatoric Divide-by-3 Algorithm
    11432: 98/08/12: Re: Newbie seeks cheap fun w/FPGAs
    11451: 98/08/14: Re: Combinatoric Divide-by-3 Algorithm
    11452: 98/08/14: Re: FFT-Speed
    11513: 98/08/20: Re: vector product minimization problem
    11522: 98/08/20: Re: Video 256 colors interface HELP!
    11525: 98/08/20: Re: half full flag in a xilinx async fifo?
    11587: 98/08/25: Re: FPGA vendors
    11588: 98/08/25: Re: half full flag in a xilinx async fifo?
    11604: 98/08/26: Re: How to design a PLL
    11638: 98/08/27: Re: half full flag in a xilinx async fifo?
    11673: 98/08/30: Re: CPLD/FPGA software
    11675: 98/08/31: Re: Video 256 colors interface HELP!
    11681: 98/08/31: Re: A Johnson counter
    11705: 98/09/02: Re: half full flag in a xilinx async fifo?
    11768: 98/09/08: Re: Altera 10K20 Register File Implementation??
    11792: 98/09/09: Re: 22V10 programming
    11813: 98/09/10: Re: Xilinx Spartan vs. 4K series
    11815: 98/09/10: Re: Need Permutation generator
    11826: 98/09/11: Multiplication hardware
    11914: 98/09/18: Re: sync or async SRAM?
    11915: 98/09/18: Re: measuring junction temperature
    11916: 98/09/18: Re: Design Security Question
    11917: 98/09/18: Re: ASIC -> FPGA async issues
    11929: 98/09/19: Re: sync or async SRAM?
    11996: 98/09/23: Re: sync or async SRAM?
    12005: 98/09/23: Re: Efficient max-function architecture?
    12037: 98/09/25: Re: Design Security Question
    12054: 98/09/25: Re: Efficient max-function architecture?
    12055: 98/09/25: Re: Efficient max-function architecture?
    12086: 98/09/28: Re: Faster 32_bit integer multiplier required !!
    12098: 98/09/28: Re: Fastest Add
    12116: 98/09/29: Re: Maxplus2 Timing Analyzer
    12135: 98/09/30: Re: Fastest Add
    12136: 98/09/30: Re: FIR Filter Design
    12150: 98/10/01: Re: FIR Filter Design
    12160: 98/10/01: Re: Fastest Add
    12224: 98/10/05: Re: FIR Filter Design
    12237: 98/10/06: Re: FIR Filter Design
    12267: 98/10/07: Re: FIR Filter Design
    12325: 98/10/08: Re: FIR Filter Design
    12226: 98/10/05: Re: RAM Implementation in Altera Flex10K100A
    12359: 98/10/09: Re: Xilinx may not support schematics for Virtex?????
    12361: 98/10/09: Re: Help Desperately Needed with Altera Microprocessor Design.
    12386: 98/10/10: Re: Help Desperately Needed with Altera Microprocessor Design.
    12394: 98/10/11: Re: FIR Filter Design
    12400: 98/10/11: Re: Xilinx may not support schematics for Virtex?????
    12402: 98/10/11: Re: FIR Filter Design
    12466: 98/10/12: Re: FOCUS FOCUS FOCUS (Xilinx not supporting viewlogic sim)
    12467: 98/10/12: Re: Digital Sine Generator
    12468: 98/10/12: Re: FPGA info..
    12587: 98/10/19: Re: Viewsim bashing 101
    12588: 98/10/19: Re: Schematic entry?
    12589: 98/10/19: Re: 100 MHz FPGA
    12590: 98/10/19: Re: optimized fpga
    12591: 98/10/19: Re: gray code counter in a Xilinx fpga???
    12593: 98/10/19: Re: FIR Filter Design
    12625: 98/10/20: Re: gray code counter in a Xilinx fpga???
    12657: 98/10/22: Re: Schematic entry?
    12658: 98/10/22: Re: Evaluation
    12673: 98/10/22: Re: Schematic entry?
    12687: 98/10/23: Re: gray code counter in a Xilinx fpga???
    12688: 98/10/23: Re: Fast multiplier, FPGA & ASIC
    12704: 98/10/23: Re: gray code counter in a Xilinx fpga???
    12705: 98/10/23: Re: 3.3V FPGAs on the ISA bus?????
    12706: 98/10/23: Re: DynaText **!?!?
    12707: 98/10/23: Re: Xilinx F1.5/FPGA Express wackiness (& Floorplanner)
    12709: 98/10/23: Re: Fast multiplier, FPGA & ASIC
    12733: 98/10/26: Re: FPGA Decouple Capacitor values
    12771: 98/10/29: Re: State machines in VHDL/Verilog
    12772: 98/10/29: Re: Q: Configure FPGA from an ISA bus?
    12773: 98/10/29: Re: !Recommendation wanted! Which CAD for shematic entry of Xilinx FPGA'based devices choose
    12778: 98/10/29: Re: FPGA Decouple Capacitor values
    12779: 98/10/29: Re: Schematic entry?
    12795: 98/10/29: Re: Q: Configure FPGA from an ISA bus?
    12796: 98/10/29: Re: Xilinx mode pins.
    12805: 98/10/30: Re: Digital Sine Generator
    12829: 98/10/30: Re: Xilinx mode pins.
    12992: 98/11/09: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
    12999: 98/11/10: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
    12989: 98/11/09: Re: Why doesn't Xilinx's simulator work?
    12990: 98/11/09: Re: placement&routing problems
    12991: 98/11/09: Re: design multipier?
    13016: 98/11/11: Re: FPGA VGA interface
    13053: 98/11/13: Re: VHDL project
    13054: 98/11/13: Re: placement&routing problems
    13057: 98/11/13: Re: Affordable boundary scan (JTAG) interconnect testing software any
    13128: 98/11/16: Re: Example of clock circuit needed !
    13130: 98/11/16: Re: newbie question about timing
    13159: 98/11/17: Re: Is there an alternative to Altera EPM5128 OTP?
    13165: 98/11/18: Re: Synthesizeablel fifo
    13181: 98/11/18: Re: XNF issue
    13182: 98/11/18: Re: Serial EPROMs
    13190: 98/11/18: Re: Synthesizeablel fifo
    13212: 98/11/20: Re: Synthesizeablel fifo
    13213: 98/11/20: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
    13214: 98/11/20: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
    13225: 98/11/20: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
    13240: 98/11/21: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
    13241: 98/11/21: Re: Synthesizeablel fifo
    13263: 98/11/22: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
    13266: 98/11/22: Re: Combining busses Xilinx
    13267: 98/11/22: Re: Synthesizeablel fifo
    13279: 98/11/23: Re: VHDL project
    13280: 98/11/23: Re: Combining busses Xilinx
    13281: 98/11/23: Re: Anyone use XChecker cable with 3.3V Xilinx parts?
    13282: 98/11/23: Re: Synthesizeablel fifo
    13300: 98/11/24: Re: Integer divide algorithms
    13315: 98/11/25: Re: Add-in board with FPGA Secondary Processor
    13688: 98/12/18: Re: Xilinx Foundation vs. Altera Max Plus II
    13367: 98/11/30: Re: PCB rules for Xilinx ICs
    13368: 98/11/30: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
    13492: 98/12/05: Re: A short digression...
    13499: 98/12/06: Re: A short digression...
    13510: 98/12/07: Re: A short digression...
    13583: 98/12/10: Re: A short digression...
    13601: 98/12/11: Re: HELP, Tool selection
    13449: 98/12/03: Re: Minimum clock freq reqd
    13447: 98/12/03: Re: Xilinx FPGA configuration problems... Help!
    13473: 98/12/04: Re: package/footprint/layout
    13517: 98/12/07: Re: New FPGA Brd: FPGA+PowerPC+Ethernet+TCP/IP
    13518: 98/12/07: Re: computer requirements for CAE systems
    13547: 98/12/08: Re: What are the 'rules' for assigning large buses to fpga's
    13602: 98/12/11: Re: Need basic info on FPGA!
    13610: 98/12/12: Re: XESS FPGA Board?
    13633: 98/12/15: Re: FAQ Address Please
    13634: 98/12/15: Re: Parallel Port Pass Through Specs?
    13713: 98/12/19: Re: Atmel's PLD
    13714: 98/12/19: Re: Async Fifo Core or Macro for Xilinx FPGA
    13719: 98/12/20: Re: Async Fifo Core or Macro for Xilinx FPGA
    13763: 98/12/22: Re: Xilinx - Viewlogic Virtex Support
    14080: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10
    14081: 99/01/11: Re: smallest DCT algorithm?
    13958: 99/01/05: Re: Bit-Serial Multiplier
    13965: 99/01/05: Re: FPGA development system
    13966: 99/01/05: Re: Dynamic reconfig
    14005: 99/01/06: Re: which FPGA to choose ?
    14008: 99/01/07: Re: fpga socket
    14012: 99/01/07: Re: fpga socket
    14021: 99/01/07: Re: fpga socket
    14110: 99/01/13: Re: 1-wire
    14135: 99/01/14: Re: DFF/Couter behavior with clock and control signals change
    14147: 99/01/15: Re: General FPGA introduction needed
    14202: 99/01/19: Re: Q:Hardware debugging with Xilinx M1.4
    14226: 99/01/21: Re: Can we get back to DSP again? Was Re: Who cares what DSP programmers think?
    14241: 99/01/21: Re: CORDIC (was: Best way to digitally synth. stable frequencies?)
    14245: 99/01/21: Re: CORDIC (was: Best way to digitally synth. stable frequencies?)
    14252: 99/01/21: Re: Q: Counting GHz pulses - ?
    14253: 99/01/21: Re: hdl vs. schematics - was <snip>
    14259: 99/01/22: Re: hdl vs. schematics - was <snip>
    14265: 99/01/22: Re: decoder Viterbi
    14317: 99/01/25: Re: PLL in FPGA
    14319: 99/01/25: Re: 8x8 (x8 -> 11) DCT Implementation Results?
    14340: 99/01/26: Re: FPGA architecture
    14349: 99/01/26: Re: Xilinx - Questions on clock & Async delays.
    14369: 99/01/27: Re: SWAP Home RF 4-FSK Demodulator
    14407: 99/01/28: Re: No. of CLBs in Xilinx nearly 100% can't implement.
    14436: 99/01/29: Re: Hazard
    14457: 99/01/30: Re: Q:Installing Xilinx F1.4 license server
    14596: 99/02/05: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
    14600: 99/02/05: Re: Hazard
    14617: 99/02/06: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
    14618: 99/02/06: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
    14696: 99/02/11: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
    14776: 99/02/16: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
    14620: 99/02/06: Re: routability of FPGA - is this an issue?
    14646: 99/02/08: Re: routability of FPGA - is this an issue?
    14699: 99/02/11: Re: Parity and flex10k
    14700: 99/02/11: Re: reconfiguring Logiblox ROM's
    14712: 99/02/12: Re: asyncronous finite state machines on FPGAs?
    14713: 99/02/12: Re: reconfiguring Logiblox ROM's
    14777: 99/02/16: Re: xnf de-compiler
    14791: 99/02/17: Re: Xilinx Spartan and pin-locking
    14844: 99/02/19: Re: P&R times for Altera10K200E and Virtex
    14931: 99/02/25: Re: High Fanout Signals
    14932: 99/02/25: Re: Xilinx Virtex
    14955: 99/02/26: Re: Virtex multiplication
    14956: 99/02/26: Re: JTAG HANG UP......
    14957: 99/02/27: Re: Virtex multiplication
    14971: 99/03/01: Re: JTAG HANG UP......
    15086: 99/03/05: Re: High Fanout Signals
    15112: 99/03/07: Re: Your view on this article?
    14977: 99/03/01: Re: graphic Lcd control core
    15001: 99/03/02: Re: Getting started in programmable logic
    15002: 99/03/02: Re: Student edition!
    15057: 99/03/04: Re: combining multiple xilinx designs into one
    15094: 99/03/05: Re: Getting started in programmable logic
    15147: 99/03/09: Re: Xilinx Foundation Timing
    15174: 99/03/10: Re: Current State of FPGA-based PCI Interfaces?
    15236: 99/03/15: Re: Want to learn about FPGA.
    15237: 99/03/15: Re: Clock multiplier
    15239: 99/03/15: Re: Possible problem with die shrink of xc4010
    15240: 99/03/15: Re: multiport register file--Altera Flex10k20 ?
    15281: 99/03/17: Re: help!
    15282: 99/03/17: Re: How can I improve an adder?
    15313: 99/03/18: Re: Xilinx Spartan configuration troubles
    15324: 99/03/18: Re: Xilinx Spartan configuration troubles
    15356: 99/03/19: Re: FPGA vendor comparison
    15357: 99/03/19: Re: Placement control in ALtera devices
    15358: 99/03/19: Re: Power Estimiation
    15375: 99/03/21: Re: FPGA vendor comparison
    15377: 99/03/21: Re: From VHDL to FPGA?
    15378: 99/03/21: Re: From VHDL to FPGA?
    15386: 99/03/21: Re: From VHDL to FPGA?
    15397: 99/03/22: Re: From VHDL to FPGA?
    15425: 99/03/23: Re: viterbi coder/decoder
    15459: 99/03/24: Re: Info about FPGA/PLD
    15460: 99/03/24: Re: Booth or Wallace Trees Multipliers
    15465: 99/03/25: keeping an Altera EAB register in synplicity
    15471: 99/03/25: Re: keeping an Altera EAB register in synplicity
    15472: 99/03/25: Re: Info about VHDL syntesis
    15473: 99/03/25: Re: keeping an Altera EAB register in synplicity
    15496: 99/03/26: Re: keeping an Altera EAB register in synplicity
    15504: 99/03/26: Re: keeping an Altera EAB register in synplicity
    15517: 99/03/28: Re: Free Xilinx Vendor Tools ... NOT :-(
    15518: 99/03/28: Re: Info about FPGA/PLD
    15549: 99/03/30: Re: From VHDL to FPGA?
    15586: 99/04/01: Re: Schematic Capture & FPGA synthesis
    15598: 99/04/02: Re: Schematic Capture & FPGA synthesis
    15606: 99/04/02: Re: Schematic Capture & FPGA synthesis
    15648: 99/04/06: Re: FPGAs with ECL-compatible I/Os
    15740: 99/04/11: Re: FPGAs with ECL-compatible I/Os
    15746: 99/04/12: Re: FPGAs with ECL-compatible I/Os
    15597: 99/04/02: Re: Does any one want to talk about Dynamic Configuration?
    15603: 99/04/02: Re: How to implement Matched Filter in FPGA?
    15604: 99/04/02: Re: How to implement Matched Filter in FPGA?
    15616: 99/04/02: Re: How to implement Matched Filter in FPGA?
    15621: 99/04/03: Re: XILINX CLB architecture
    15649: 99/04/06: Re: FIFO
    15652: 99/04/06: Re: newbie: FPGA suggestion
    15653: 99/04/06: Re: Levels of logic
    15656: 99/04/06: Re: How to implement Matched Filter in FPGA?
    15657: 99/04/06: Re: How to implement Matched Filter in FPGA?
    15676: 99/04/07: Re: Best FPGA for High Speed DSP Logic?
    15687: 99/04/08: Re: Best FPGA for High Speed DSP Logic?
    15688: 99/04/08: Re: FPGA testing board
    15699: 99/04/08: Re: Illegal States in 1 Hot State Machines
    15719: 99/04/09: Re: Levels of logic
    15723: 99/04/10: Re: Best FPGA for High Speed DSP Logic?
    15724: 99/04/10: Re: Levels of logic
    15814: 99/04/15: Re: craig
    15862: 99/04/17: Re: High speed reconfigurability
    15863: 99/04/17: Re: XC4000 LUT on the fly programming
    15864: 99/04/17: Re: High speed reconfigurability
    15874: 99/04/17: Re: XC4000 LUT on the fly programming
    15875: 99/04/17: Re: XC4000 LUT on the fly programming
    15876: 99/04/17: Re: High speed reconfigurability
    15901: 99/04/20: Re: texture mapping hardware
    15907: 99/04/20: Re: Virtex based PCI cards
    15911: 99/04/20: Re: Okay, a really dumb Xilinx FPGA question.
    15912: 99/04/20: Re: What's the best way to learn about fpga's?
    15947: 99/04/22: Re: High speed reconfigurability
    15970: 99/04/23: Re: on using EAB of FLEX10k
    15971: 99/04/23: Re: Xilinx Spartan experience?
    15972: 99/04/23: Re: Using Embedded RAM in Xilinx Virtex Chips
    15985: 99/04/25: Re: Using Embedded RAM in Xilinx Virtex Chips
    16010: 99/04/27: Re: Storage of 32Bit-Vectors
    16032: 99/04/28: Re: floating point converter
    16064: 99/04/30: Re: High speed PLL inside FPGA
    16065: 99/04/30: Re: Double Port ram for Altera EPF10K20
    16066: 99/04/30: Re: Xilinx Implementation error
    16067: 99/04/30: Re: Source code Ethernet, E1 Framer, HDLC Contr.
    16068: 99/04/30: Re: IRQ Controller
    16069: 99/04/30: Re: P I/O core
    16082: 99/04/30: Re: Double Port ram for Altera EPF10K20
    16083: 99/04/30: Re: Storage of 32Bit-Vectors
    16084: 99/04/30: Re: High speed PLL inside FPGA
    16457: 99/05/23: Re: Virtex based PCI cards
    16463: 99/05/24: Re: Virtex based PCI cards
    16108: 99/05/03: Re: Anyone use 27256 for config?
    16124: 99/05/05: Re: 10KE dual port RAM help ?
    16129: 99/05/05: Re: Reciprocator in VHDL
    16135: 99/05/05: Re: Anyone use 27256 for config?
    16150: 99/05/06: Re: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for Altera FPGA?
    16170: 99/05/07: Re: DSP in FPGA
    16171: 99/05/07: Re: BGA Prototyping ?
    16260: 99/05/12: Re: Synchronizer design?
    16261: 99/05/12: Re: Synchronizer design?
    16262: 99/05/12: Re: How synthesize tools concern with size of the design?
    16279: 99/05/13: Re: Reciprocator in VHDL
    16293: 99/05/13: Re: How synthesize tools concern with size of the design?
    16318: 99/05/15: Re: How synthesize tools concern with size of the design?
    16454: 99/05/23: Re: 4062XL problems and solutions
    16455: 99/05/23: Re: Case study: Viewlogic's IntelliFlow
    16456: 99/05/23: Re: Is schmitt trigger possible with Xilinx 9536?
    16458: 99/05/23: Re: Request FAQ
    16530: 99/05/26: Re: High Speed Reconfigurability
    16551: 99/05/27: Re: High Speed Reconfigurability
    16563: 99/05/28: Re: High speed with VHDL
    16565: 99/05/28: Re: virtex vs apex20k family comparison for DSP ?
    16578: 99/05/28: Re: High Speed Reconfigurability
    16579: 99/05/28: Re: RAM for external/internal use
    16580: 99/05/28: Re: Dynamically reconfigurable devices
    16591: 99/05/28: Re: RAM for external/internal use
    16592: 99/05/28: Re: Dynamically reconfigurable devices
    16623: 99/05/31: Re: Printing to picture files
    16624: 99/05/31: Re: Printing to picture files
    16684: 99/06/02: Re: Printing to picture files
    16690: 99/06/02: Re: Evolutionary computation
    16650: 99/06/01: Re: Fixed delay in FSM
    16668: 99/06/01: Re: FPGA Introduction is needed, right?
    16707: 99/06/03: Re: Initial Values, Xilinx Virtex
    16759: 99/06/07: Re: Initial Values, Xilinx Virtex
    16795: 99/06/08: Re: LINE DELAYS USING RAMS
    16802: 99/06/09: Re: LINE DELAYS USING RAMS
    16838: 99/06/12: Re: Digital filters in VHDL
    16876: 99/06/15: Re: newbie -- What's the best way to get started?
    16877: 99/06/15: Re: delay line in FPGA / ASIC with VHDL
    16878: 99/06/15: Re: Digital filters in VHDL/FPGA
    16910: 99/06/16: Re: FPGA board for ISA bus wanted
    16911: 99/06/16: Re: Recursive Structures under Aldec AVHDL3.3
    16913: 99/06/16: Re: Xilinx DP RAM SPO Output
    16914: 99/06/16: Re: aobut analog
    16915: 99/06/16: Re: vhdl and viewlogic problem
    16919: 99/06/16: Re: Recursive Structures under Aldec AVHDL3.3
    16953: 99/06/18: Re: vhdl and viewlogic problem
    16999: 99/06/22: Re: combining multiple xilinx designs into one
    17009: 99/06/23: Re: Purchase of Spartan chips on the internet
    17021: 99/06/25: www.reconfig.com
    17029: 99/06/25: Re: fast counter in 4013XL?
    17030: 99/06/25: Re: 100 Billion operations per sec.!
    17071: 99/06/29: Re: Read/Writes to memories/register files for PIC core
    17080: 99/06/29: Re: Read/Writes to memories/register files for PIC core
    17081: 99/06/29: Re: Read/Writes to memories/register files for PIC core
    17088: 99/06/29: Re: FGPA Servo Motor Controller
    17109: 99/06/30: Re: FPGAs v/s DSPs in Cell phones
    17110: 99/06/30: Re: uLaw and ALaw conversion in an FPGA
    17126: 99/07/01: Re: FW: Xilinx Acquisition of CoolRunners
    17190: 99/07/07: Re: 100 Billion operations per sec.!
    17119: 99/07/01: Re: Heat disspa
    17162: 99/07/06: Re: Xilink FPGA
    17169: 99/07/06: Re: Need informations (articles, on-line) about fast adders and multipliers
    17170: 99/07/06: Re: Floating point on fpga, Counters?
    17189: 99/07/07: Re: Floating point on fpga, Counters?
    17238: 99/07/13: Re: Dongle problems.
    17248: 99/07/14: Re: Dongle problems.
    17249: 99/07/14: Re: Dongle problems.
    17250: 99/07/14: Re: ISA PnP core
    17261: 99/07/15: Re: Dongle problems.
    17269: 99/07/15: Re: Dongle problems.
    17270: 99/07/15: Re: Dongle problems.
    17271: 99/07/15: Re: ISA PnP core
    17273: 99/07/15: Re: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
    17285: 99/07/17: Re: Digital modulator? Synthesisable Sin(x) funct.
    17287: 99/07/17: Re: fpga 10k50 and up prototype with a/d d/a
    17296: 99/07/19: Re: Frequency multiplier in XC4000
    17305: 99/07/19: Re: Xilinx/Synopsys License Problem
    17337: 99/07/21: Re: C language to programmable logic
    17341: 99/07/21: Re: fpga 10k50 and up prototype with a/d d/a
    17350: 99/07/22: Re: Solaris vs. NT
    17366: 99/07/22: Re: tiles-rus 8405
    17377: 99/07/23: Re: Designing a Virtex board
    17386: 99/07/23: Re: What does a SpartanXL look like prior to configuration?
    17387: 99/07/23: Re: CAN WE HAVE SIGNALS WITH MULTIPLE SOURCES IN VHDL?
    17393: 99/07/23: Re: Hardware FFT Design?
    17427: 99/07/27: Re: XACT vs. Workview office
    17428: 99/07/27: Re: NRZ Deserializing in Virtex
    17449: 99/07/28: Re: Digital modulator? Synthesisable Sin(x) funct.
    17456: 99/07/29: Re: Partial Reconfiguration?
    17466: 99/07/29: Re: Partial Reconfiguration?
    17472: 99/07/30: Re: Semi-deterministic behaviour in FPGA's
    17473: 99/07/30: Re: Semi-deterministic behaviour in FPGA's
    17487: 99/07/30: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
    17488: 99/07/31: Re: Digital modulator? Synthesisable Sin(x) funct.
    17493: 99/07/31: Re: Semi-deterministic behaviour in FPGA's
    17499: 99/08/02: Re: Semi-deterministic behaviour in FPGA's
    17506: 99/08/03: Re: Digital modulator? Synthesisable Sin(x) funct.
    17521: 99/08/05: Re: serial multiplier with LogiCore scaled 1/2 accumulator
    17528: 99/08/06: Re: serial multiplier with LogiCore scaled 1/2 accumulator
    17529: 99/08/06: Re: Xilinx vs. Lucent vs. XX FPGA comparison
    17530: 99/08/06: Re: carry logic for implementing wide logic functions
    17570: 99/08/10: Re: Emulating a transputer on FPGA
    17581: 99/08/11: Re: Emulating a transputer on FPGA
    17583: 99/08/11: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
    17591: 99/08/11: Re: Emulating a transputer on FPGA
    17595: 99/08/12: Re: Foundation F1.5i Floorplanner document - ?
    17729: 99/08/27: Re: Feasibility of 200 MHz, 12K design on FPGA
    17730: 99/08/27: Re: constrain into one XC4000 CLB
    17731: 99/08/27: Re: multiplier Virtex
    17732: 99/08/27: Re: microcontroller vs FPGA
    17733: 99/08/27: Re: looking for image processing hardware
    17741: 99/08/28: Re: PLL cascading in VIRTEX
    17770: 99/09/01: Re: Feasibility of 200 MHz, 12K design on FPGA
    17771: 99/09/01: Re: Dissolve hierarchy or not?
    17798: 99/09/05: Re: Newbie question: Reading FPGA programming?
    17846: 99/09/13: Re: differences between ALTERA-XILINX
    17847: 99/09/13: Re: Relative Location attribute
    17851: 99/09/13: Re: A mix is best
    17855: 99/09/14: Re: Virtex Interconnect
    17865: 99/09/14: Re: free/demo/low cost verilog synthesis tools available?
    17916: 99/09/16: Re: Xilinx development board > XVC400
    17943: 99/09/18: Re: speeding up place and route
    17944: 99/09/18: Re: Xilinx XC4005E
    17945: 99/09/18: Re: DSP in FPGA
    17946: 99/09/18: Re: Question about Alliance 2.1i
    17953: 99/09/19: Re: Loadable arithmetic in Virtex
    17954: 99/09/19: Re: Virtex global set/reset
    17960: 99/09/19: Re: Loadable arithmetic in Virtex
    17963: 99/09/19: Re: Loadable arithmetic in Virtex
    17965: 99/09/19: Re: Loadable arithmetic in Virtex
    17974: 99/09/20: Re: Programming Spartan XL
    17992: 99/09/21: Re: [Q] simple Queue implementation with external RAM
    18004: 99/09/22: Re: Virtex questions
    18028: 99/09/24: Re: Synopsys inside Foundation 2.1i does not infer fast-adder
    18073: 99/09/27: Re: New Xilinx Virtex-E is out!
    18091: 99/09/29: Re: Performance of reprogrammable FPGAs?
    18099: 99/09/29: Re: Verilog or VHSIC HDL ?
    18100: 99/09/29: Re: Need help programming Spartan FPGA with Atmel serial EEPROM
    18102: 99/09/29: Re: Fine grain vs. Coarse grain
    18113: 99/09/30: Re: Are all SRAM based FPGAs -Reconfigurable devices.
    18125: 99/10/01: Re: Slice (or CLB) count
    18135: 99/10/02: Re: Reconfigurable FPGAs-- A query on this..
    18136: 99/10/02: Re: Producing 60/40 clock in vhdl
    18137: 99/10/02: Re: Reconfigurable FPGAs-- A query on this..
    18138: 99/10/03: Re: Producing 60/40 clock in vhdl
    18139: 99/10/03: Re: Producing 60/40 clock in vhdl
    18140: 99/10/03: Re: Reconfigurable FPGAs-- A query on this..
    18145: 99/10/03: Re: ATM srambler
    18146: 99/10/03: Re: What are the Virtex REV connections?
    18150: 99/10/03: Re: Producing 60/40 clock in vhdl
    18158: 99/10/04: Re: ATM srambler
    18159: 99/10/04: Re: Clock multiplexing in Virtex
    18169: 99/10/04: Re: ABEL for CPLD Design
    18171: 99/10/04: Re: I need a Link
    18175: 99/10/05: Re: Multiplierless FIR filters in FPGAs
    18183: 99/10/05: Re: Producing 60/40 clock in vhdl
    18185: 99/10/05: Re: Multiplierless FIR filters in FPGAs
    18191: 99/10/06: Re: ATM srambler
    18210: 99/10/07: Re: Multiplierless FIR filters in FPGAs
    18221: 99/10/08: Re: RAM in xilinx FPGAs.
    18244: 99/10/08: Re: RAM in xilinx FPGAs.
    18301: 99/10/13: Re: Interconnecting LUTs on a Virtex
    18311: 99/10/13: Re: Xilinx FPGA Programmer
    18320: 99/10/14: Re: Virtex Board
    18321: 99/10/14: Re: Need info about a FAST adders. How built it? (0)
    18341: 99/10/16: Re: Interconnecting LUTs on a Virtex
    18342: 99/10/16: Re: VITERBI
    18343: 99/10/16: Re: VITERBI
    18362: 99/10/19: Re: Question on Jbits(Xilinx product) for Xc4000 series
    18388: 99/10/21: Re: Xilinx Orientation Question
    18392: 99/10/21: Re: Xilinx Orientation Question
    18412: 99/10/23: Re: VHDL carry chain RPMs
    18413: 99/10/23: Re: Xilinx Orientation Question
    18419: 99/10/23: Re: Seeking for FPGA/CPLD (Starter) kit
    18420: 99/10/23: Re: Static power consumption
    18423: 99/10/23: Re: floating point synthesis
    18431: 99/10/23: Re: floating point synthesis
    18513: 99/10/28: Re: Comparison between Altera and Xilinx
    18514: 99/10/28: Re: FPGA
    18515: 99/10/28: Re: schematics ==> www
    18516: 99/10/28: Re: schematics ==> www
    18526: 99/10/28: Re: Comparison between Altera and Xilinx
    18527: 99/10/28: Re: FPGA
    18533: 99/10/28: Re: schematics ==> www
    18547: 99/10/29: Re: StateCAD versus Viewdraw
    18551: 99/10/30: Re: Comparison between Altera and Xilinx
    18554: 99/10/30: Re: Comparison between Altera and Xilinx
    18561: 99/10/31: Re: Comparison between Altera and Xilinx
    18583: 99/11/01: Re: Comparison between Altera and Xilinx
    18585: 99/11/02: Re: XNF file formats ???
    18590: 99/11/02: Re: 16 bit counter in Abel
    18613: 99/11/03: Re: High Speed Enough!?
    18614: 99/11/03: Re: Xlinx FPGA
    18615: 99/11/03: Re: Why DSP in a FPGA?
    18622: 99/11/03: Re: Input metastability
    18623: 99/11/03: Re: Xlinx FPGA
    18643: 99/11/04: Re: High Speed Enough!?
    18644: 99/11/04: Re: Price of FPGA
    18650: 99/11/04: Re: Xilinx M2.1i SP2?
    18669: 99/11/05: Re: Xlinx FPGA
    18673: 99/11/06: Re: Why DSP in a FPGA?
    18684: 99/11/07: Re: ROM or SRAM !?
    18688: 99/11/07: Re: Input metastability
    18690: 99/11/07: Re: Downloading Xilinx FPGA with just .bit file???
    18696: 99/11/08: Re: ROM or SRAM !?
    18734: 99/11/10: Re: orcad synthesis for simplepld
    18743: 99/11/11: Re: fast programmable divider using xilinx xc4002xl
    18752: 99/11/11: Re: fast programmable divider using xilinx xc4002xl
    18753: 99/11/11: Re: Simulation of FPGA design. Please Help!
    18758: 99/11/12: Re: Pin locking problem in Altera fpga
    18833: 99/11/18: Re: How to use GSR-net in Virtex?
    18834: 99/11/18: Re: How to use multiple resets?
    18835: 99/11/18: Re: How many bits in an FPGA bitstream?
    18849: 99/11/18: Re: analog capabilities?
    18850: 99/11/18: Re: Not complett multipier LUT in FPGA
    18851: 99/11/18: Re: Need advice on interfacing SDRAM modules
    18864: 99/11/19: Re: How to use multiple resets?
    18865: 99/11/19: Re: How to use GSR-net in Virtex?
    18866: 99/11/19: Re: implementing TCP/IP on PLD
    18889: 99/11/19: Re: How to use GSR-net in Virtex?
    18918: 99/11/21: Re: Why not Lucent ORCA FGPAs?
    18944: 99/11/22: Re: Why not Lucent ORCA FGPAs?
    18959: 99/11/22: Re: VHDL vs. schematic entry
    18961: 99/11/22: Virtex mapper won't pack register with F5 combinatorial
    18965: 99/11/22: Re: VHDL vs. schematic entry
    18983: 99/11/23: Re: VHDL vs. schematic entry
    19000: 99/11/23: Re: VHDL vs. schematic entry
    19001: 99/11/23: Re: How to use GSR-net in Virtex?
    19002: 99/11/23: Re: Why not Lucent ORCA FGPAs?
    19003: 99/11/23: Re: How to use multiple resets?
    19094: 99/11/29: Re: LOC's RLOC's and Virtex
    19098: 99/11/29: Re: VHDL vs. schematic entry
    19102: 99/11/29: Re: FPGA vs DSP vs PENTIUM MMX
    19114: 99/11/29: Re: FPGA vs DSP vs PENTIUM MMX
    19115: 99/11/29: Re: VHDL vs. schematic entry
    19119: 99/11/30: Re: FPGA vs DSP vs PENTIUM MMX
    19124: 99/11/30: Re: FPGA vs DSP vs PENTIUM MMX
    19125: 99/11/30: Re: Xilinx FPGA Editor guessing games solved!
    19133: 99/12/01: Re: FPGA vs DSP vs PENTIUM MMX
    19134: 99/12/01: Re: Timing constraint not met
    19135: 99/12/01: Re: data serializer/decoder FPGA solution
    19169: 99/12/03: Re: Tristate bidirectional pads with Xilinx
    19174: 99/12/03: Re: Problems with routing Virtex device
    19176: 99/12/03: Re: Problems with routing Virtex device
    19180: 99/12/03: Re: Help with ROM in Xilinx Virtex
    19183: 99/12/03: Re: Solution: ROM in Xilinx Virtex
    19218: 99/12/06: Re: TIme Delay 1us-100ms
    19235: 99/12/07: Re: TIme Delay 1us-100ms
    19249: 99/12/08: Re: constraints between clock domains: can't advance
    19264: 99/12/09: Re: JTAG on PCI slot
    19266: 99/12/09: Re: Passing attributes from VHDL with FPGA Express for Xilinx
    19274: 99/12/09: Re: Is there two-read one-write asynchronous SRAM in FPGA?
    19307: 99/12/12: Re: Lattice ispLSI Security
    19335: 99/12/14: Re: Lattice ispLSI Security
    19378: 99/12/17: Re: Xilinx FPGA Editor...does it really work?
    19379: 99/12/17: Re: CIC Filters in FPGA
    19387: 99/12/17: Re: Speed grade
    19392: 99/12/18: Re: Dumb question springing from a discussion about chess on a chip...
    19395: 99/12/18: Re: Dumb question springing from a discussion about chess on a chip...
    19402: 99/12/19: Re: Speed grade
    19409: 99/12/20: Re: Necessary to 'synchronise' an asynchronous FSM reset?
    19410: 99/12/20: Re: Dumb question springing from a discussion about chess on a chip...
    19419: 99/12/20: Re: Speed grade
    19420: 99/12/20: Re: Dumb question springing from a discussion about chess on a chip...
    19429: 99/12/21: Re: fpga cost
    19433: 99/12/21: Re: Dumb question springing from a discussion about chess on a chip...
    19444: 99/12/21: Re: Speed grade
    19446: 99/12/21: Re: fpga cost
    19447: 99/12/21: Re: M1 timings
    19449: 99/12/21: Re: M1 timings
    19461: 99/12/22: Re: XC4000E
    19469: 99/12/23: Crossing clock domain boundaries[ was Speed grade]
    19476: 99/12/23: Re: Dumb question springing from a discussion about chess on a chip...
    19480: 99/12/24: Re: Dumb question springing from a discussion about chess on a chip...
    19481: 99/12/24: Re: viewlogic problem
    19588: 00/01/03: Re: Design security
    19589: 00/01/03: Re: Virtex Config Help
    19590: 00/01/03: Re: IRDY/TRDY Dedicated or Special Pin Name
    19591: 00/01/03: Re: FG and H function in Xilinx FPGA
    19600: 00/01/03: Re: Design security
    19633: 00/01/04: Re: fpga cost
    19634: 00/01/04: Re: STARTUP
    19643: 00/01/05: Re: Design security
    19655: 00/01/07: Re: Lucent Orca designs
    19662: 00/01/07: Re: Disable clockbuffer for only a single flip-flop
    19684: 00/01/08: Re: Disable clockbuffer for only a single flip-flop
    19686: 00/01/08: Re: Disable clockbuffer for only a single flip-flop
    19687: 00/01/08: Re: Virtex real time debugging
    19693: 00/01/08: Re: 100 MHz counters
    19699: 00/01/08: Re: Optimizing VHDL for Altera
    19700: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19702: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19701: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19703: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19704: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19705: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19706: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19707: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19708: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19709: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19710: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19711: 00/01/09: Re: Optimizing VHDL for Altera
    19721: 00/01/09: Re: How to upgrade Foundation 1.4 to build Spartan-XL code?
    19722: 00/01/09: Re: Optimizing VHDL for Altera
    19723: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
    19735: 00/01/10: Re: XC4000 Configuration Bitstream structure
    19736: 00/01/10: Re: Virtex Temperature Sensing diode pins DXP, DXN
    19743: 00/01/11: Re: Optimizing VHDL for Altera
    19744: 00/01/11: Re: THANX: Disable clockbuffer for only a single flip-flop
    19757: 00/01/11: Re: SDRAM controller ?
    19764: 00/01/11: Re: XC4000 Configuration Bitstream structure
    19775: 00/01/11: Re: 100 MHz counters
    19803: 00/01/12: Re: Xilinx Spartan2
    19804: 00/01/12: Re: 100 MHz counters
    19813: 00/01/13: Re: Reliability of programming SRAM FPGAs
    19825: 00/01/13: Re: Design security
    19826: 00/01/13: Re: fastest 32 bit RISC
    19848: 00/01/14: Re: fpga board
    19849: 00/01/14: Re: DDC Core for FPGA
    19862: 00/01/14: Re: fastest 32 bit RISC
    19878: 00/01/15: Re: XACT & XC4000E - Need help
    19888: 00/01/16: Re: Partly reprogrammable FPGAs
    19889: 00/01/16: Re: XACT & XC4000E - Need help
    19894: 00/01/16: Re: Random Number Generator
    19895: 00/01/16: Re: timing diagrams
    19899: 00/01/17: Re: Random Number Generator
    19908: 00/01/17: Re: Viterbi decoder in FPGA
    19909: 00/01/17: Re: Random Number Generator
    19922: 00/01/18: Re: Random Number Generator
    19933: 00/01/19: Re: Random Number Generator
    19937: 00/01/19: Re: Need advice on timing problem
    19944: 00/01/19: Re: looping FIFO?
    19952: 00/01/20: help: signal stuck at 'U' inside generate statement
    19969: 00/01/20: Re: Xilinx vs. other FPGAs manufactrers
    19978: 00/01/21: Re: odd behavior of Virtex RAM Block model
    19993: 00/01/21: Re: help: signal stuck at 'U' inside generate statement
    19994: 00/01/21: Re: help: signal stuck at 'U' inside generate statement
    20000: 00/01/22: Re: Transmeta CM & Conf. Comp?
    20028: 00/01/24: Re: How to access standard sdram ?
    20029: 00/01/24: Re: Polynomial calculation on FPGA ???
    20030: 00/01/24: Re: Xilinx vs. other FPGAs manufactrers
    20031: 00/01/24: Re: FPGA to manage serial DAQ?
    20078: 00/01/26: Re: EEPROM based FPGAs
    20080: 00/01/26: GSR in HDL on instantiated flip-flop primitives
    20089: 00/01/26: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    20108: 00/01/27: Re: GSR in HDL on instantiated flip-flop primitives
    20109: 00/01/27: Re: GSR in HDL on instantiated flip-flop primitives
    20110: 00/01/27: Re: What has happened to freecore.com ?
    20111: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    20112: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    20126: 00/01/28: Re: GSR in HDL on instantiated flip-flop primitives
    20128: 00/01/28: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    20149: 00/01/28: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    20167: 00/01/29: Re: ADC to DSP... FIFO?
    20174: 00/01/30: Re: Can Foundation import Viewlogic?
    20199: 00/01/31: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    20200: 00/01/31: Re: Which FPGA to learn with?
    20173: 00/01/30: Re: looping FIFO?
    20206: 00/01/31: Re: Virtex DLL inoperability
    20214: 00/02/01: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    20229: 00/02/01: Re: Xilinx Tools
    20230: 00/02/01: Re: Count 1's algorithm...
    20288: 00/02/04: Re: Count 1's algorithm...
    20289: 00/02/04: Re: Spartan 2 & Foundation
    20158: 00/01/29: Re: Spartan II availability and pricing
    20302: 00/02/04: Re: Spartan 2 & Foundation
    20321: 00/02/04: Xilinx "WebCD" gripes
    20322: 00/02/04: Re: Spartan 2 & Foundation
    20323: 00/02/04: Re: Conditional compilation in VHDL?
    20325: 00/02/05: Re: Conditional compilation in VHDL?
    20334: 00/02/05: Re: Xilinx "WebCD" gripes
    20354: 00/02/07: Re: Xilinx "WebCD" gripes
    20355: 00/02/07: Re: Xilinx "WebCD" gripes
    20384: 00/02/08: Re: ADC to DSP... FIFO?
    20411: 00/02/09: Re: Why does Virtex has no EPROM support like XC4000
    20520: 00/02/13: Re: launching a FPGA cores start-up
    20521: 00/02/13: Re: FPGA IP complexity
    20522: 00/02/13: Re: Xilinx Virtex Reset
    20523: 00/02/13: Re: A FPGA hickup
    20524: 00/02/13: Re: [NEED HELP] Carry Select Adder?
    20544: 00/02/14: Re: launching a FPGA cores start-up
    20545: 00/02/14: Re: LUT & VHDL
    20546: 00/02/14: Re: CIC Question
    20564: 00/02/14: Re: Xilinx Virtex Reset
    20568: 00/02/15: Re: Advice please
    20577: 00/02/15: Re: MULTIRATE DESIGN
    20579: 00/02/15: Re: launching a FPGA cores start-up
    20617: 00/02/16: Re: 100% slice utilization in Virtex FPGA
    20618: 00/02/16: Re: Virtex DLL inoperability
    20619: 00/02/16: Re: multiplier
    20638: 00/02/16: Re: CIC Question
    20658: 00/02/17: Re: Choosing the correct size FPGA
    20660: 00/02/17: Re: Request for Info
    20661: 00/02/17: Re: launching a FPGA cores start-up
    20671: 00/02/17: Re: CLAy 31 datasheet
    20687: 00/02/17: Re: Xilinx hold time problems...
    20688: 00/02/17: Re: multiplier
    20689: 00/02/17: Re: coregen-bug produces bad blockram > 16 bit
    20690: 00/02/17: Re: RECONFIGURABLE board for image processign
    20694: 00/02/18: Re: multiplier
    20695: 00/02/18: Re: Xilinx M2.1 Floorplanner Question
    20696: 00/02/18: Re: Using a programable logic device to search a huge number field
    20697: 00/02/18: Re: Using a programable logic device to search a huge number field
    20698: 00/02/18: Re: Suggested prototyping boards < $200
    20718: 00/02/18: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
    20728: 00/02/19: Re: BEHAVIOURAL VHDL
    20729: 00/02/19: Re: x18 FIFO's in Virtex
    20731: 00/02/19: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
    20735: 00/02/20: Distributed Arithmetic De-mystified
    20736: 00/02/20: Re: BEHAVIOURAL VHDL
    20738: 00/02/20: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
    20740: 00/02/20: Re: Spartan and timing analyzer: clock nets using non-dedicated
    20741: 00/02/20: Re: multiplier
    20742: 00/02/20: Re: Xilinx M2.1 Floorplanner Question
    20746: 00/02/20: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
    20747: 00/02/20: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
    20754: 00/02/20: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
    20755: 00/02/20: Re: Divider
    20761: 00/02/21: Re: Passing multi-cycle timing constrains from Synplify to M1
    20769: 00/02/21: Re: multiplier
    20770: 00/02/21: Re: Passing multi-cycle timing constrains from Synplify to M1
    20795: 00/02/22: Re: Distributed Arithmetic De-mystified
    20808: 00/02/23: Re: Xchecker schematic?
    20809: 00/02/23: Re: Bit Serial Arithmetic De-mystified
    20849: 00/02/24: Re: Bit Serial Arithmetic De-mystified
    20850: 00/02/24: Re: Xchecker schematic?
    20863: 00/02/24: Re: Design security
    20907: 00/02/26: Re: MRP systems
    20999: 00/03/02: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
    21040: 00/03/03: Re: BEHAVIOURAL VHDL
    20990: 00/03/02: Re: Xilinx Tools Vs Altera tools
    20991: 00/03/02: Re: AMS board design advice asked
    20965: 00/03/01: Re: AMS board simple questions
    20976: 00/03/01: Re: Xilinx Tools Vs Altera tools
    21009: 00/03/03: Re: Comment on Atmel AT40K ?
    21036: 00/03/03: Re: Comment on Atmel AT40K ?
    21037: 00/03/03: Re: SpartanXL route and place
    21039: 00/03/03: Re: SpartanXL route and place
    21042: 00/03/04: Re: EDA tools
    21046: 00/03/04: Re: Comment on Atmel AT40K ?
    21052: 00/03/04: Re: Comment on Atmel AT40K ?
    21057: 00/03/04: Re: Comment on Atmel AT40K ?
    21059: 00/03/05: Re: Xilinx Tools Question
    21061: 00/03/05: Re: Xilinx Tools Question
    21080: 00/03/06: Re: about multipliers
    21088: 00/03/06: Re: Comment on Atmel AT40K ?
    21109: 00/03/07: Re: SpartanXL route and place
    21110: 00/03/07: Re: SpartanXL route and place
    21113: 00/03/07: Re: SpartanXL route and place
    21146: 00/03/08: Re: SpartanXL route and place
    21169: 00/03/09: Re: SpartanXL route and place
    21171: 00/03/09: Re: ModelSim 2.1i ?
    21185: 00/03/09: Re: SpartanXL route and place
    21189: 00/03/09: Re: ModelSim 2.1i ?
    21203: 00/03/10: Re: SpartanXL route and place
    21204: 00/03/10: Re: FPGA board
    21205: 00/03/10: Re: SpartanXL route and place
    21213: 00/03/10: Re: SpartanXL route and place
    21214: 00/03/10: Re: SpartanXL route and place
    21216: 00/03/10: Re: ModelSim 2.1i ?
    21217: 00/03/10: Re: Spartan 2 Industrial temp range versions
    21233: 00/03/11: Re: Xilinx IP Protection
    21239: 00/03/12: Re: Xilinx Foundation Series and FSM designs
    21246: 00/03/13: Re: DSP with FPGA
    21250: 00/03/14: Re: DSP with FPGA
    21265: 00/03/14: Re: Virtex IOB T register
    21278: 00/03/15: Re: Atmel censors web access
    21279: 00/03/15: Re: Virtex IOB T register
    21280: 00/03/15: Re: Difference between FPGA, PLD, CPLD ?
    21322: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
    21378: 00/03/21: Re: How I can DLL function unsing VHDL in Virtex?
    21421: 00/03/22: Re: Virtex DLL inoperability
    21448: 00/03/22: Re: Virtex DLL inoperability
    21452: 00/03/22: Re: No- FPGA openness
    21462: 00/03/23: Re: FPGA openness
    21482: 00/03/23: Re: FPGA openness
    21493: 00/03/23: Re: FPGA openness
    21509: 00/03/23: Re: FPGA openness
    21527: 00/03/24: Re: No- FPGA openness
    21528: 00/03/24: Re: No- FPGA openness
    21529: 00/03/24: Re: FPGA openness
    21530: 00/03/24: Re: FPGA openness
    21567: 00/03/25: Re: FPGA openness
    21597: 00/03/26: Re: FPGA openness
    21598: 00/03/26: Re: FPGA openness
    21602: 00/03/26: Re: FPGA openness
    21626: 00/03/27: Re: FPGA openness
    21628: 00/03/27: Re: FPGA openness
    21637: 00/03/27: Re: FPGA & single point failure
    21647: 00/03/28: Re: FPGA & single point failure
    21665: 00/03/28: Re: Digital Filters - Help me!!
    21681: 00/03/29: Re: FPGA openness
    21688: 00/03/29: Re: VHDL at RTL level vs. floorplanning.
    21691: 00/03/29: Re: FPGA openness
    21702: 00/03/29: Re: FPGA openness
    21703: 00/03/29: Re: FPGA openness
    21704: 00/03/29: Re: FPGA openness
    21753: 00/03/30: Re: 10 gbit/s input
    21754: 00/03/30: Re: FPGA openness
    21755: 00/03/30: Re: FPGA openness
    21756: 00/03/30: Re: Global clock nets. Can I use it for signal other than clock.
    21757: 00/03/30: Re: Memory cores
    21758: 00/03/30: Re: What's so good about antifuse???
    21759: 00/03/30: Re: What's so good about antifuse???
    21768: 00/03/31: Re: FPGA openness
    21786: 00/03/31: Re: FPGA openness
    21787: 00/03/31: Re: ANTIFUSE AND XILINX
    21788: 00/03/31: Re: 82C54
    21627: 00/03/27: Re: FPGA openness
    21812: 00/04/01: Re: FPGA openness
    21892: 00/04/05: Re: Memory cores
    21907: 00/04/06: Re: Memory cores
    21875: 00/04/05: Re: MaxPlus9.5 License and Fitter problems
    21876: 00/04/05: Re: Clocks and BUFGP
    21888: 00/04/05: Re: MaxPlus9.5 License and Fitter problems
    21908: 00/04/06: Re: JTAG programming
    21909: 00/04/06: Re: Spartan on chip oscillator
    21910: 00/04/06: Re: Warnings during mapping
    21920: 00/04/07: Re: FPGA Openness/ Summary
    21933: 00/04/07: Re: multiprocessor support of IC design tools
    21946: 00/04/07: Re: multiprocessor support of IC design tools
    21955: 00/04/09: Re: multiprocessor support of IC design tools
    21962: 00/04/10: Re: multiprocessor support of IC design tools
    21974: 00/04/10: Re: Distributed Arithmetic
    21975: 00/04/10: Re: setup and hold time violation
    21980: 00/04/11: Re: Programator for xilinx
    22002: 00/04/11: Re: Is there any DSP and FPGA based board suitable to motor drive
    22003: 00/04/11: Re: Clock Dividers
    22009: 00/04/12: Re: Multiple Clock design, setup & hold time violation
    22049: 00/04/16: Re: FPGA/PLD design tools?
    22207: 00/05/01: Re: Why are there no "cheap" FPGAs?
    22233: 00/05/02: Re: Why are there no "cheap" FPGAs?
    22274: 00/05/04: Re: Why are there no "cheap" FPGAs?
    22275: 00/05/04: Re: How to Prevent theft of FPGA design
    22279: 00/05/04: Re: How to Prevent theft of FPGA design
    22327: 00/05/05: Re: How to Prevent theft of FPGA design
    22353: 00/05/05: Re: How to Prevent theft of FPGA design
    22354: 00/05/05: Re: How to Prevent theft of FPGA design
    22382: 00/05/07: Re: How to Prevent theft of FPGA design
    22502: 00/05/10: Re: ? economical SPROM programmer for Xilinx
    22734: 00/05/21: Re: Why are there no "cheap" FPGAs?
    22231: 00/05/02: Re: random integer
    22473: 00/05/10: Re: pipeline shiftreg in virtex
    22474: 00/05/10: Re: HELP - what to choose?
    22522: 00/05/11: Re: appropriate ASIC Prototyping Board
    22524: 00/05/11: Re: HELP - what to choose?
    22525: 00/05/11: Re: Error with Quartus for Altera APEX20K device: clock skew is greater
    22542: 00/05/11: Re: appropriate ASIC Prototyping Board
    22543: 00/05/11: Re: Info on using Reconfig feature of Virtex?
    22544: 00/05/11: Re: FPGA emulators?
    22560: 00/05/12: Re: Reccomend an ASIC emulation board
    22561: 00/05/12: Re: pipeline shiftreg in virtex
    22575: 00/05/12: Re: Do you know xilinx FPGAs well?
    22576: 00/05/12: Re: asic vs fpga
    22577: 00/05/12: Re: Xilinx Virtex SRL16
    22604: 00/05/13: Re: Do you know xilinx FPGAs well?
    22605: 00/05/13: Re: pipeline shiftreg in virtex
    22663: 00/05/17: Re: SMT 7 segment display ??
    22686: 00/05/17: Re: Spartan II availability and pricing
    22688: 00/05/18: Re: Spartan II availability and pricing
    22691: 00/05/18: Re: Spartan II availability and pricing
    22714: 00/05/19: Re: FPGA emultaion of a microprocessor
    22740: 00/05/21: Re: Help for a novice of Xilinx Foundation
    22750: 00/05/22: Re: US-IL-In desperate need of FPGA engineer
    22772: 00/05/23: Re: Xilinx Logic Cell counts and carry chains
    22777: 00/05/24: Re: Xilinx Logic Cell counts and carry chains
    22778: 00/05/24: Re: ISA interface on FPGA or CPLD
    22801: 00/05/25: Re: Xilinx Logic Cell counts and carry chains
    22802: 00/05/25: Re: Implementation in FPGA
    22803: 00/05/25: Re: 8087 in FPGA?
    22830: 00/05/25: Re: 8087 in FPGA?
    22844: 00/05/27: Re: 8087 in FPGA?
    22871: 00/05/29: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
    22881: 00/05/29: Re: Help with Coregen
    22907: 00/05/31: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
    22941: 00/06/05: Re: Help with Coregen
    22971: 00/06/06: Re: Help with Coregen
    22911: 00/06/01: Re: Microprocessors in FPGA
    22992: 00/06/08: Re: Xilinx Spartan; CLB's run out
    23007: 00/06/09: Re: TTL device Libraries
    23026: 00/06/09: Re: Simulation of VIRTEX BLOCKRAM
    23037: 00/06/10: Re: XILINX RAM Useless
    23048: 00/06/10: Re: XILINX RAM Useless
    23065: 00/06/12: Re: Altera vs Xilinx
    23070: 00/06/13: Re: Altera vs Xilinx
    23071: 00/06/13: Re: Altera vs Xilinx
    23109: 00/06/14: Re: for my students
    23186: 00/06/16: Re: Virtex ".FFX" contraint???
    23187: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog
    23188: 00/06/16: Re: Block level incremental synthesis (?)
    23189: 00/06/16: Re: SV: Xilinx config over parallel port ?
    23191: 00/06/16: Re: Hand soldering a PQ208 - It looks tough to do.
    23213: 00/06/17: Re: Virtex ".FFX" contraint???
    23214: 00/06/17: Re: Problem copying text from the Spartan II data sheet
    23217: 00/06/18: Re: Problem copying text from the Spartan II data sheet
    23224: 00/06/18: Re: Xilinx config over parallel port ?
    23236: 00/06/18: Re: Xilinx config over parallel port ?
    23271: 00/06/20: Re: Wanted: Xilinx VirtexE
    23355: 00/06/23: Re: dual processor PC for PPR - are they worth the extra cost?
    23450: 00/06/26: Re: How to speed it up?
    23108: 00/06/14: Re: FS: FpgaGuru.com DOMAIN
    23707: 00/07/06: Re: FFT/IFFT for FPGA
    23702: 00/07/05: Re: How to augment the output of a Xilinx lfsr in verilog??
    23705: 00/07/06: Re: Viewlogic schematic from Synplify edif output?
    23706: 00/07/06: Re: VHDL code for LFSR
    23708: 00/07/06: Re: BIST in FPGAs?
    23828: 00/07/12: Re: Xilinx buys LavaLogic
    23948: 00/07/17: Re: XC2018 development system xact5 or xact6 sale?
    24042: 00/07/24: Re: Routing Resources for Xilinx BlockRAM
    24044: 00/07/24: Re: Routing Resources for Xilinx BlockRAM
    24045: 00/07/24: Re: XC4000 select ram
    24046: 00/07/24: Re: IP CORE, 8250 core with 16byte fifo which only uses 100CLB's
    24047: 00/07/24: Re: Xilinx Logic Cell counts and carry chains
    24048: 00/07/24: Re: New Xilinx Student Edition
    24049: 00/07/24: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
    24053: 00/07/25: Re: 17 clocks in a Virtex
    24069: 00/07/26: Re: Routing Resources for Xilinx BlockRAM
    24070: 00/07/26: Re: Spartan II Pin
    24071: 00/07/26: Re: Silicon Valley Housing Nightmare?
    24072: 00/07/26: Re: Xilinx Logic Cell counts and carry chains
    24092: 00/07/26: Re: Variable shifting
    24110: 00/07/27: Re: Variable shifting
    24111: 00/07/27: Re: Variable shifting
    24112: 00/07/27: Re: Pad trireg in XLA FPGA
    24148: 00/07/27: Re: Variable shifting
    24150: 00/07/27: Re: Implementation
    24189: 00/07/29: Re: Variable shifting
    24193: 00/07/29: Re: LFSR as a divider
    24200: 00/07/29: Re: Variable shifting
    24208: 00/07/29: Re: Variable shifting
    24220: 00/07/30: Re: LFSR as a divider
    24221: 00/07/30: Re: Viewlogic Licensing
    24236: 00/07/31: Re: Viewlogic Licencing
    24237: 00/07/31: Re: Spartan-II / Virtex-E / DC linear regulators
    24261: 00/08/01: Re: Look-up tables in Altera
    24290: 00/08/02: Re: Viewlogic Licensing
    24260: 00/08/01: Re: Desperatly needing a SpartanII
    24277: 00/08/02: Re: Desperatly needing a SpartanII
    24278: 00/08/02: Re: Desperatly needing a SpartanII
    24279: 00/08/02: Re: FPGA selection
    24291: 00/08/02: Re: 32-input AND and 100-input OR - can I do it fast?
    24323: 00/08/04: Re: Who needs all those printed ac parameters?
    24349: 00/08/04: Re: FPGA selection
    24466: 00/08/10: Re: XST?
    24467: 00/08/10: Re: Can i see Gate-delay and Interconnection-delay of circuit on FPGA
    24479: 00/08/10: Re: some basic rules on FPGA design
    24537: 00/08/12: Re: Comparing Xilinx FPGAs
    24549: 00/08/13: Re: Virtex 2.5V part with 5V IO problems
    24564: 00/08/14: Re: state encoding in Synplify!!!
    24591: 00/08/14: Re: Help!!! Bit serial Baugh-Wooley multiplier
    24602: 00/08/15: Re: Help! Troubles using async FIFO cores in Virtex
    24658: 00/08/16: Re: Help!!! Bit serial Baugh-Wooley multiplier
    24659: 00/08/16: Re: fifo;s
    24697: 00/08/17: Re: Permanently programming FPGAs
    24729: 00/08/17: Re: Permanently programming FPGAs
    24743: 00/08/17: Re: Permanently programming FPGAs
    24745: 00/08/17: Re: Clock recovery in FPGA
    24763: 00/08/17: Re: state encoding in Synplify!!!
    24765: 00/08/17: Re: Clock recovery in FPGA
    24773: 00/08/18: Re: state encoding in Synplify!!!
    24805: 00/08/19: Re: Xilinx Xact & Alliance
    24806: 00/08/19: Virtex BEL constraints--do they really do anything?
    24812: 00/08/19: Re: Xilinx Student Edition Floorplanning
    24830: 00/08/20: Re: Further FPGA metastability questions
    24860: 00/08/21: Re: Metastability and antifuze
    24861: 00/08/21: Re: Further FPGA metastability questions
    24862: 00/08/21: Re: timing simulation vs functional one
    24866: 00/08/21: Re: Further FPGA metastability questions
    24867: 00/08/21: Re: Metastability measurement
    24887: 00/08/21: Looks like Xilinx is at it again!
    24897: 00/08/21: Re: Usage of ROC (Foundation 2.1i)
    24898: 00/08/21: Re: timing simulation vs functional one
    24899: 00/08/21: Re: Looks like Xilinx is at it again!
    24900: 00/08/21: Re: Looks like Xilinx is at it again!
    24905: 00/08/21: Re: Looks like Xilinx is at it again!
    24906: 00/08/22: Re: Verilog multiplier in Xilinx...
    24945: 00/08/23: Re: Looks like Xilinx is at it again!
    24975: 00/08/23: Re: create a RAM in a Virtex
    24977: 00/08/23: Re: timing simulation vs functional one
    25007: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
    25012: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
    25033: 00/08/24: Re: run time doubled with Xilinx 3.1i upgrade - Problem Fixed!!
    25038: 00/08/24: Re: largest fpga in the industry
    25045: 00/08/24: Re: largest fpga in the industry
    25050: 00/08/24: Re: largest fpga in the industry
    25054: 00/08/25: Re: create a RAM in a Virtex
    25072: 00/08/25: Re: help -- of RAMs, FFs, latches, inverted clocks, and other
    25073: 00/08/25: Re: DLL Properties on Xilinx Virtex/VirtexE
    25074: 00/08/25: Re: create a RAM in a Virtex
    25097: 00/08/25: Re: create a RAM in a Virtex
    25099: 00/08/25: Re: Large amout of Interconnect between FPGAs
    25100: 00/08/25: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
    25105: 00/08/25: Re: Is there any way to configure the Virtex BRAM outputs as direct,
    25129: 00/08/27: Re: Balls!
    25166: 00/08/29: Re: largest fpga in the industry
    25187: 00/08/30: Re: Spartan II vs. Virtex
    25270: 00/09/03: Re: Balls!
    25278: 00/09/04: Re: Balls!
    25254: 00/09/01: Re: Xilinx block Ram Verilog model
    25279: 00/09/04: Re: Slow routing of PWR/GND (Virtex)
    25288: 00/09/05: Re: XC4013 available
    25290: 00/09/05: Re: Slow routing of PWR/GND (Virtex)
    25291: 00/09/05: Re: Slow routing of PWR/GND (Virtex)
    25301: 00/09/05: Re: Slow routing of PWR/GND (Virtex)
    25307: 00/09/06: Re: Slow routing of PWR/GND (Virtex)
    25308: 00/09/06: Re: Model for 8101 - 8104
    25324: 00/09/06: Re: floorplanning
    25335: 00/09/06: Re: bga->dip?
    25353: 00/09/07: Re: floorplanning
    25364: 00/09/08: Re: XC3000A Configuration data
    25372: 00/09/08: Re: DCT implementation using FPGA
    25382: 00/09/09: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
    25468: 00/09/12: Re: Is this practical?
    25480: 00/09/12: Re: Is this practical?
    25481: 00/09/12: Re: computing difference between Gray values?
    25514: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
    25532: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
    25533: 00/09/13: Re: Is this practical?
    25534: 00/09/13: Re: Is this practical?
    25545: 00/09/13: Re: virtex shape
    25554: 00/09/13: Re: Is this practical?
    25625: 00/09/15: Re: FPGA Express Strikes Again!
    25627: 00/09/15: Re: Guide to useing Atmel FPGA (at40k)
    25708: 00/09/18: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
    25709: 00/09/18: Re: Clock skew in XILINX CPLD
    25711: 00/09/18: Re: Reassurance on Xilinx Sought
    25727: 00/09/18: Re: Clock skew in XILINX CPLD
    25743: 00/09/19: Re: Freelance Designer Needed: Protel & FPGA
    25760: 00/09/19: Re: PCB side of this
    25770: 00/09/20: Re: Adders in FPGA?
    25788: 00/09/20: Re: Complaint: Xilinx functional simulation libraries
    25802: 00/09/20: Re: Safe voltage regulator for Xilinx XC2S150 part?
    25803: 00/09/21: Re: Synthesiser comparisons (was: FPGA Express strikes again)
    25804: 00/09/21: Re: Complaint: Xilinx functional simulation libraries
    25834: 00/09/22: Re: Announce: Free HC11 CPU Core
    25855: 00/09/23: Re: Multi-Arch, Moderately High performance VHDL FPGA Code?
    25857: 00/09/23: Re: CORDIC COS/SIN with FPGA implementation
    25864: 00/09/23: Re: dp ram
    25870: 00/09/23: Re: Reassurance on Xilinx Sought
    25876: 00/09/24: Re: CORDIC COS/SIN with FPGA implementation
    26014: 00/09/30: Re: FPGA Express strikes again! Xilinx response
    26013: 00/09/30: Re: atmel verses altera
    26019: 00/10/01: Re: FPGA Express strikes again! Xilinx response
    26021: 00/10/01: Re: atmel verses altera
    26027: 00/10/01: Re: atmel verses altera
    26020: 00/10/01: Re: multi-input adders in virtex ?
    26026: 00/10/01: Re: multi-input adders in virtex ?
    26029: 00/10/01: Re: Xilinx XC2018 Design tools
    26039: 00/10/01: Re: multi-input adders in virtex ?
    26040: 00/10/01: Re: multi-input adders in virtex ?
    26058: 00/10/02: Re: multi-input adders in virtex ?
    26059: 00/10/02: Re: Multiplication
    26091: 00/10/03: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26092: 00/10/03: Re: Pwr/Gnd ( again)
    26114: 00/10/04: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26115: 00/10/04: Re: Pwr/Gnd ( again)
    26141: 00/10/05: Re: Pwr/Gnd ( again)
    26154: 00/10/05: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26170: 00/10/06: Re: Multiplication
    26253: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26254: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26269: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26297: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26433: 00/10/16: Re: clk'event
    26435: 00/10/16: Re: 5V compatible Virtex
    26437: 00/10/16: Re: const coeff multiplier w/ LUTs
    26438: 00/10/16: Re: Sinusoidal PWM on Xilinx FPGA
    26439: 00/10/16: Re: LUT to CLB assignment
    26447: 00/10/16: Re: 5V compatible Virtex
    26456: 00/10/16: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26457: 00/10/16: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26458: 00/10/16: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26459: 00/10/16: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26463: 00/10/17: Re: 5V compatible Virtex
    26474: 00/10/17: Re: VHDL vs Verilog
    26476: 00/10/17: Re: VHDL vs Verilog
    26481: 00/10/18: Re: VHDL vs Verilog
    26484: 00/10/18: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26498: 00/10/18: Re: Q: Xilinx unified libraries and synthesis
    26499: 00/10/18: Re: Virtex pull-up/down resistors question
    26507: 00/10/18: Re: Spartan II ?
    26511: 00/10/18: Re: Off subjuct, VHDL question
    26512: 00/10/18: Re: two complement multiplier
    26513: 00/10/18: Re: XILINX Download cable with USB
    26521: 00/10/19: Re: Off subjuct, VHDL question
    26525: 00/10/19: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26540: 00/10/19: Re: How safe is the algorithm implemented with FPGA?
    26541: 00/10/19: Re: DS2401 security from pirating an FPGA
    26550: 00/10/20: Re: Very Lucrative FPGA Jobs
    26563: 00/10/20: Re: DS2401 security from pirating an FPGA
    26571: 00/10/20: Re: "Number of logic levels" in xilinx PAR reports
    26590: 00/10/21: Re: xilinx floor planner issues
    26591: 00/10/21: Re: VHDL vs Verilog
    26592: 00/10/21: Re: Cheapy FPGA sw
    26614: 00/10/22: Re: Xilinx 4000 reset
    26615: 00/10/22: Re: xilinx floor planner issues
    26620: 00/10/23: Re: UCF Question
    26672: 00/10/24: Re: How safe is the algorithm implemented with FPGA?
    26706: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
    26732: 00/10/26: Re: How safe is the algorithm implemented with FPGA?
    26633: 00/10/23: Re: Typical toggle rates for power estimation ...
    26640: 00/10/23: Re: Typical toggle rates for power estimation ...
    26648: 00/10/23: Re: XILINX Download cable with USB
    26673: 00/10/24: Re: New PACT 50 GOP Reconfigurable Processor
    26674: 00/10/24: Re: Virtex Dual Port RAM simulation failure in Modelsim
    26677: 00/10/24: Re: How to reduce Tco?
    26690: 00/10/25: Re: Design theft story in EDN. New security ?
    26694: 00/10/25: Re: log2 function in VHDL
    26717: 00/10/25: Re: ROC (reset on configuration) on Virtex ?
    26731: 00/10/26: Re: Fpga vs. ASIC
    26739: 00/10/26: Re: High fan out CE signal.
    26740: 00/10/26: Re: what's meaning?
    26764: 00/10/27: Re: Using previous version as floorplan (2.1i vs 3.1i)
    26765: 00/10/27: Re: High fan out CE signal.
    26810: 00/10/30: Re: High fan out CE signal.
    26811: 00/10/30: Re: Long Island Verilog and VHDL people wanted!!
    26815: 00/10/31: Re: High fan out CE signal.
    26818: 00/10/31: Re: Long Island Verilog and VHDL people wanted!!
    26825: 00/10/31: Re: High fan out CE signal.
    26826: 00/10/31: Re: Using previous version as floorplan (2.1i vs 3.1i)
    26833: 00/10/31: Re: High fan out CE signal.
    26834: 00/10/31: Re: Alliance 3.2i
    26846: 00/11/01: Re: High fan out CE signal.
    26920: 00/11/03: Re: Alliance under Linux?
    26941: 00/11/04: Re: Group behaviour (was: Alliance under Linux)
    26969: 00/11/06: Re: High fan out CE signal.
    26903: 00/11/02: Re: Need a PCB speaker driven by XCV100
    26906: 00/11/03: Re: OT: Xilinx T-Shirt
    27005: 00/11/07: Re: Need help locking pins for Spartan XL
    27077: 00/11/09: Re: Non routable design
    27086: 00/11/10: Re: Non routable design
    27091: 00/11/10: Re: Non routable design
    27099: 00/11/10: Re: Pull-up
    27105: 00/11/10: Re: Virtex 32x1 RAM - Prevent usage
    27108: 00/11/11: Re: Non routable design
    27118: 00/11/11: Re: Number Format in DSP implementations
    27129: 00/11/12: Re: CRC, LFSR and scramblers
    27159: 00/11/13: Re: XC4000 maps better than Spartan2
    27175: 00/11/13: Re: XC4000 maps better than Spartan2
    27246: 00/11/16: Re: Problems wirh JTAG-Configuration of 18V512 and Spartan XCS40
    27247: 00/11/16: Re: Need help locking pins for Spartan XL
    27268: 00/11/16: Re: Can FPGA perform float point calculation?
    27274: 00/11/16: Re: Xilinx coregen problems
    27281: 00/11/17: Re: Xilinx coregen problems
    27305: 00/11/17: Re: Can FPGA perform float point calculation?
    27307: 00/11/17: Re: reset pulse ?
    27309: 00/11/17: Re: VHDL & Spartan: How to power-up a Register to '1' ?
    27324: 00/11/18: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
    27325: 00/11/18: Re: VHDL & Spartan: How to power-up a Register to '1' ?
    27326: 00/11/18: Re: reset pulse ?
    27355: 00/11/19: Re: Xilinx FPGA: SRAM based, but is it dependant upon SEEPROM?
    27358: 00/11/19: Re: Synthesis & Routing speed
    27366: 00/11/20: Re: Virtex circuit tricks -- add/mux in one LUT per bit
    27367: 00/11/20: Re: LUT and EDIF
    27384: 00/11/20: Re: Hardware suggestions for evolutionary experiments
    27538: 00/11/28: Re: Clock Skew : Does Xilinx know what they're doing?
    27612: 00/11/30: Re: Selfmade Cores or something similar (Xilinx)
    27644: 00/12/01: Re: Synplify Benchmarks
    27659: 00/12/01: Re: Synplify Benchmarks
    27660: 00/12/01: Re: Synplify Benchmarks
    27662: 00/12/01: Re: Synplify Benchmarks
    27721: 00/12/05: Re: Synplify Benchmarks
    27680: 00/12/02: Re: Synplify Benchmarks
    27663: 00/12/01: Re: DLLs driving DLLs in Virtex.
    27811: 00/12/09: Re: dual port ram for altera
    27848: 00/12/12: Re: dual port ram for altera
    27856: 00/12/12: Re: Synplify PRO 6.1 + Foundation 3.1i
    27962: 00/12/18: Re: ActiveHDL 4.1?
    27963: 00/12/18: Re: CSD OR DISTRIBUTED ARITHMETIC?
    27964: 00/12/18: Re: Verilog or VHDL
    27965: 00/12/18: Re: Setup violation
    27981: 00/12/18: Re: Setup violation
    28091: 00/12/20: Re: dual port ram for altera
    28092: 00/12/20: Re: 3V -> 5V clock signal level conversion
    28150: 00/12/23: Re: Question about programming xcv100
    28858: 01/01/26: Re: really fast counter in SpartanXL?
    28229: 01/01/03: Re: Question about programming xcv100
    28252: 01/01/03: Re: Fixing pins on Spartan II
    28265: 01/01/04: Re: XILINX SRL16E - FIFO
    28305: 01/01/05: Re: Fixing pins on Spartan II
    28306: 01/01/05: Re: XILINX SRL16E - FIFO
    28346: 01/01/08: Re: Spartan-II DLL Usage
    28347: 01/01/08: Re: FPGA for radar digital downconversion
    28372: 01/01/10: Re: VIRTEX : pad location
    28415: 01/01/11: Re: grey code counters
    28416: 01/01/11: Re: How to do simulation on Synopsys FPGA Express
    28453: 01/01/13: Re: Virtex counter speed
    28459: 01/01/13: Re: I wanna Model Sim cracked
    28493: 01/01/15: Re: Looking for prototyping board
    28494: 01/01/15: Re: fifo
    28495: 01/01/15: Re: Virtex-II officially launched
    28600: 01/01/18: Re: CMOS or TTL
    28601: 01/01/18: Re: FSM encoding
    28604: 01/01/18: Re: FAQ for this news group? (or What is an FPGA?)
    28629: 01/01/18: Re: FPGA for radar digital downconversion
    28664: 01/01/20: Re: spartanII chip availability
    28665: 01/01/20: Re: FPGAs with a partial reconfiguration
    28666: 01/01/20: Re: FSM encoding
    28667: 01/01/20: Re: FSM encoding
    28668: 01/01/20: Re: Best design for asyn. interface DSP <-> FPGA?
    28669: 01/01/20: Re: Synplicity newsgroup?
    28714: 01/01/22: Re: Virtex-II officially launched
    28738: 01/01/23: Re: Virtex-II officially launched
    28739: 01/01/23: Xilinx XCell is not on-line?
    28740: 01/01/23: Re: FPGAs with a partial reconfiguration
    28762: 01/01/23: Re: Xilinx XCell is not on-line?
    28763: 01/01/23: Re: Xilinx XCell is not on-line?
    28767: 01/01/24: Re: Virtex counter speed
    28768: 01/01/24: Re: multiplier architecture
    28781: 01/01/24: Re: Fixing pins on Spartan II
    28782: 01/01/24: Re: Verilog model of Xilinx macro in VHDL Testbench fails
    28783: 01/01/24: Re: Virtex-II officially launched
    28801: 01/01/24: Re: Virtex counter speed
    28805: 01/01/24: Re: Virtex counter speed
    28868: 01/01/26: Re: Advice on FPGA board.
    28869: 01/01/26: Re: mutiplier !!
    28870: 01/01/26: Re: CORDIC ALGORITHM
    28876: 01/01/26: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
    28885: 01/01/27: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
    28888: 01/01/27: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
    28892: 01/01/27: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
    28916: 01/01/29: Re: Is it a timing constraint problem?
    28925: 01/01/29: Re: Q: VIRTEX experience, multipliers
    28932: 01/01/30: Re: Is it a timing constraint problem?
    28963: 01/01/31: Re: CORDI C PROCESSOR!
    28964: 01/01/31: Re: Standard Deviation Moving Window
    28965: 01/01/31: Re: Xilinx fast carry counter question
    28974: 01/01/31: Re: Xilinx fast carry counter question
    28980: 01/02/01: Re: 64-bit counter @ 200 MHz on FPGA?
    29563: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
    29572: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
    29573: 01/02/27: Re: Virtex USB solution
    29574: 01/02/27: Re: Spartan II power
    29575: 01/02/27: Re: I want to learn sth about FPGA
    29577: 01/02/27: Re: DLL jitter "bake-off" vs. PLL
    29590: 01/02/27: Re: programmable coefficient fir filter?
    29630: 01/03/02: Re: What about speed-grade?
    29635: 01/03/02: Re: What about speed-grade?
    29653: 01/03/03: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29667: 01/03/04: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29679: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29722: 01/03/06: Re: Actel's FPGA : A54SX32A
    29762: 01/03/08: Re: Spartan II: POWERDOWN MODE WAS DELETED!!!
    29773: 01/03/08: Re: Problem with Xilinx 3.3-sp7
    29793: 01/03/10: Re: Metastability
    29808: 01/03/12: Re: Configuration devices
    29820: 01/03/12: Re: clock divider by 1.5
    29927: 01/03/18: Re: FFT in FPGAs
    29947: 01/03/19: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
    29951: 01/03/19: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
    29952: 01/03/19: Re: about placement and routing
    29971: 01/03/19: Re: TOA measurement
    29974: 01/03/20: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
    29975: 01/03/20: Re: TOA measurement
    29998: 01/03/20: Re: TOA measurement
    29999: 01/03/20: Re: TOA measurement
    30000: 01/03/20: Re: Book on FPGA-Design with Xilinx chips
    30001: 01/03/20: Re: Packing density of Xilinx FPGAs
    30004: 01/03/20: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
    30024: 01/03/21: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
    30037: 01/03/21: Re: Do I need to tie unused CPLD pins to GND?
    30051: 01/03/21: Re: TOA measurement
    30055: 01/03/22: Re: reduced precision floating point
    30064: 01/03/22: Re: reduced precision floating point
    30065: 01/03/22: Re: TOA measurement
    30066: 01/03/22: Re: Is the carry logic for Virtex included in PAR timing report/check?
    30067: 01/03/22: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
    30077: 01/03/22: Virtex Em on a board?
    30087: 01/03/22: Re: frequency measurement?
    30088: 01/03/23: Re: Virtex Em on a board?
    30137: 01/03/25: Re: Accumulator - Core in XC4K
    30138: 01/03/25: Re: How to find out where par placed things?
    30160: 01/03/26: Re: Asynchronus Mashine States
    30184: 01/03/27: Re: Asynchronus Mashine States
    30197: 01/03/27: Re: frequency measurement?
    30208: 01/03/28: Re: speech
    30234: 01/03/29: Re: Books for trade
    30303: 01/04/02: Re: pseudo random numbers
    30304: 01/04/02: Re: adding std_logic_vectors
    30315: 01/04/02: Re: pseudo random numbers
    30316: 01/04/02: Re: pseudo random numbers
    30327: 01/04/03: Re: pseudo random numbers
    30338: 01/04/03: Re: Timing Error
    30339: 01/04/03: Re: pseudo random numbers
    30348: 01/04/03: Re: pseudo random numbers
    30351: 01/04/04: Re: pseudo random numbers
    30353: 01/04/04: Re: Combined Multiplier-Divider in Virtex-E
    30367: 01/04/04: Re: salary info for FPGA/HardwareEng's
    30368: 01/04/04: Re: Combined Multiplier-Divider in Virtex-E
    30372: 01/04/04: Re: pseudo random numbers
    30379: 01/04/05: Re: QPSK phase rotator implementation in FPGA ?
    30390: 01/04/05: Re: How to specify Spartan2 GSR/GTS for Synthesis
    30391: 01/04/05: Re: URGENT: Using SpartanII DLL to multiply clock freq
    30427: 01/04/07: Re: pseudo random numbers
    30428: 01/04/07: Re: XCV1000BG560: onchip ram
    30461: 01/04/09: Re: MicroBlaze
    30503: 01/04/11: Re: How to specify Spartan2 GSR/GTS for Synthesis
    30509: 01/04/11: Re: Introductory Question - LSB to MSB Conversion.
    30650: 01/04/21: Re: Wanted: ISA bus implementation for Xilinx
    30671: 01/04/23: Re: looking for comment on implementation
    30672: 01/04/23: Re: looking for comment on implementation
    30673: 01/04/23: Re: looking for comment on implementation
    30674: 01/04/23: Re: looking for comment on implementation
    30676: 01/04/23: Re: CIC interpolate by 3 & filter
    30677: 01/04/23: Re: Frequency of FPGA
    30686: 01/04/24: Re: Something about the counter
    30695: 01/04/24: Re: CIC interpolate by 3 & filter
    30730: 01/04/26: Re: manufacturer's of FIR chips
    30765: 01/04/27: Re: Comparison of FPGA and DSP
    30921: 01/05/03: Re: Comparison of FPGA and DSP
    31081: 01/05/11: Re: Need Advice on what Xilinx Tools to purchase
    31279: 01/05/17: Re: Xilinx and Actel
    31303: 01/05/18: Re: Fine phase shift in Virtex2
    31370: 01/05/21: Re: free simulator
    31394: 01/05/21: Re: free simulator
    31413: 01/05/22: Re: Counter problem
    31419: 01/05/23: Re: Counter problem
    31444: 01/05/24: Re: frequency ramp
    31572: 01/05/30: Re: Help: RAM clear in one clock cycle
    31592: 01/05/31: Re: Help: RAM clear in one clock cycle
    31593: 01/05/31: Re: RLOC'in Virtex-II FDCs???
    31944: 01/06/08: Re: Virtex LUT4 problems in FPGA Express
    32013: 01/06/11: Re: [Xilinx] Spartan II Devices ..internal tristate busses ...
    32064: 01/06/12: Re: Virtex LUT4 problems in FPGA Express
    32065: 01/06/12: Re: Virtex LUT4 problems in FPGA Express
    32074: 01/06/12: Re: Virtex, Routing Error
    32075: 01/06/13: Re: Xilinx webpack annoyances (long and whiny)
    32154: 01/06/16: Re: Virtex II multiplier question
    32191: 01/06/19: Re: Timing results Xilinx Core Multiplier in FPGA Compiler 2
    32235: 01/06/20: Re: Pin locking in Maxplus2
    32251: 01/06/21: Re: Pin locking in Maxplus2
    32253: 01/06/21: Re: FFT limited size input
    32254: 01/06/21: Re: Xilinx Software free
    32263: 01/06/21: synplicity 6.2.4 'optimizing' instantiated designs
    32265: 01/06/21: Re: NT vs W2K (WAS Re: Pin locking in Maxplus2)
    32266: 01/06/21: Re: Pin locking in Maxplus2
    32275: 01/06/21: Re: synplicity 6.2.4 'optimizing' instantiated designs
    32276: 01/06/21: Re: FFT limited size input
    32285: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
    32286: 01/06/22: Re: LFSR Taps for 64 bit registers?
    32288: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
    32307: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
    32308: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
    32316: 01/06/22: Re: FFT limited size input
    32328: 01/06/23: Re: Unisim Library Question?
    32332: 01/06/23: Re: what tools run OK on windows 2000?
    32385: 01/06/25: Re: synplicity 6.2.4 'optimizing' instantiated designs
    32397: 01/06/25: Re: Register balancing in FPGA Express
    32398: 01/06/26: Re: IOB FF in Synplicity
    32399: 01/06/26: Re: Unisim Library Question?
    32400: 01/06/26: Re: black box instantiation in Spartan II Design
    32402: 01/06/26: Re: Xilinx logic usage
    32416: 01/06/26: Re: Alpha Particle
    32431: 01/06/26: Re: Xilinx System Generator Simulation Problem
    32460: 01/06/27: Re: Unisim Library Question?
    32462: 01/06/27: Re: Xilinx unified library
    32517: 01/06/28: Re: IOB FF in Synplicity
    32518: 01/06/28: Re: Xc4k parallel-parallel multiplier
    32543: 01/06/29: Re: Error to execute vcom.do in ModelSim XE5.3d
    32621: 01/07/03: Re: Asynchronous design in Virtex FPGA => sleepless nights
    32650: 01/07/04: Re: poor man's floating point...
    32651: 01/07/04: Re: Asynchronous design in Virtex FPGA => sleepless nights
    32652: 01/07/04: Re: Are these typical VirtexE timing values?
    32687: 01/07/05: Re: How to estimate the number of CLBs ?
    32709: 01/07/05: Re: How to estimate the number of CLBs ?
    32715: 01/07/05: Re: Arc Tangente and Square Root algorithms
    32716: 01/07/05: Re: AMS Wildstar Board
    32747: 01/07/06: Re: Floating Point SQRT
    32756: 01/07/07: Re: Problems with Virtex Block Ram Propagation Delay
    32771: 01/07/09: Re: Shift and Add Multiplier With Signed Numbers
    32772: 01/07/09: Re: Need some help using Synplify ... and also considering Xilinx
    32857: 01/07/10: Re: Online threshold limit counter
    32858: 01/07/10: Re: Simulation problems with BlockRAM's INIT values !
    32859: 01/07/10: Re: Adder/Subtracter Core???
    32860: 01/07/10: Re: How do I distribute cores?
    32879: 01/07/11: Re: How do I distribute cores?
    32880: 01/07/11: Re: Online threshold limit counter
    32882: 01/07/11: Re: Online threshold limit counter
    32883: 01/07/11: Re: Online threshold limit counter
    32884: 01/07/11: Re: Virtex2: Is it possible to place distributed DPRAM
    32897: 01/07/11: Re: Need to speed up VHDL accumulator on Xilinx
    32899: 01/07/11: Re: Virtex2: Is it possible to place distributed DPRAM
    32960: 01/07/13: Re: Shift and Add Multiplier With Signed Numbers
    32979: 01/07/13: Re: Design entry
    32980: 01/07/13: Re: How do I distribute cores?
    33023: 01/07/15: Re: Which Chip Family?
    33024: 01/07/15: Re: Shift and Add Multiplier With Signed Numbers
    33053: 01/07/16: Re: Fixing routing in a Virtex FPGA
    33055: 01/07/16: Re: Which Chip Family?
    33111: 01/07/17: Re: Working Design - Anyone
    33116: 01/07/17: Re: Which Chip Family?
    33146: 01/07/18: Re: FPGAs in Safety Involved Applications
    33149: 01/07/18: Re: Spartan2XC2S30 vs ACEXEP1K30
    33167: 01/07/18: Re: Xilinx WebPACK - ROM
    33169: 01/07/18: Re: Working Design - Anyone
    33176: 01/07/18: Re: Xilinx WebPACK - ROM
    33187: 01/07/19: Re: Spartan2XC2S30 vs ACEXEP1K30
    33207: 01/07/19: Re: Spartan2XC2S30 vs ACEXEP1K30
    33209: 01/07/19: Re: Taking 4MSB a problem in 2's complement?
    33263: 01/07/21: Re: regarding the constraints while writing VHDL code
    33264: 01/07/21: Re: Modulator Sizing Questions
    33265: 01/07/21: Re: Modulator Sizing Questions
    33279: 01/07/22: Re: Measuring power consumption
    33354: 01/07/24: Re: Soldering Ceramic BGA's
    33367: 01/07/24: Re: Register Chain
    33481: 01/07/27: Re: SRL16
    33525: 01/07/29: Re: Digital Mixer
    33526: 01/07/29: Re: SRL16
    33535: 01/07/29: Re: Jitter Added by FPGA counter
    33536: 01/07/29: Re: finite defect statistics
    33555: 01/07/30: Re: Modulator Sizing Questions
    33558: 01/07/30: Re: finite defect statistics
    33578: 01/07/31: Re: SRL16
    33579: 01/07/31: Re: Xilinx/Altera "behavioral" verilog
    33588: 01/07/31: Re: finite defect statistics
    33590: 01/07/31: Re: How to add carry optimizations
    33611: 01/07/31: Re: finite defect statistics
    33613: 01/07/31: Re: computer science Vs Computer Enginnering
    33619: 01/08/01: Re: finite defect statistics
    33620: 01/08/01: Re: Xilinx/Altera "behavioral" verilog
    33643: 01/08/01: Re: Xilinx/Altera "behavioral" verilog
    33644: 01/08/01: Re: computer science Vs Computer Enginnering
    33656: 01/08/01: Re: DLL useage
    33670: 01/08/02: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
    33711: 01/08/02: Re: finite defect statistics
    33712: 01/08/02: Re: Spartan II and asynchronous memory interface
    33727: 01/08/03: Re: Clock skew with Xilinx DLLs...
    33748: 01/08/03: Re: finite defect statistics
    33750: 01/08/03: Re: Spartan II and asynchronous memory interface
    33751: 01/08/03: Re: Clock skew with Xilinx DLLs...
    33765: 01/08/03: Re: Spartan II and asynchronous memory interface
    33766: 01/08/03: Re: Clock skew with Xilinx DLLs...
    33827: 01/08/06: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
    33828: 01/08/06: Re: Cordic NCO questions
    33829: 01/08/06: Re: how to give timing constraint in an hierarchy des
    33830: 01/08/06: Re: I needs a saturable adder.
    33831: 01/08/06: Re: May I connect two pins to the same net?
    33854: 01/08/06: Re: Choosing a verilog synthesis tool (Altera/Xilinx)
    33864: 01/08/07: Re: Polyphase and VHDL questions
    33865: 01/08/07: Re: I needs a saturable adder.
    33871: 01/08/07: Re: 200MHz, 28 bit counter in Spartan ii
    33874: 01/08/07: Re: What to do if a constrain is not met ???
    33878: 01/08/07: Re: Polyphase and VHDL questions
    33879: 01/08/07: Re: Cordic NCO questions
    33916: 01/08/08: Re: Wildcard and Foundation tools
    33931: 01/08/08: Re: LUT as Buffer?
    33938: 01/08/09: Re: Generate constants with a function
    33951: 01/08/09: Re: LUT as Buffer?
    33952: 01/08/09: Re: Cordic NCO questions
    33954: 01/08/09: Re: What to do if a constrain is not met ???
    33955: 01/08/09: Re: Problem with fft16 generated by Xilinx Core Gen 3.1i
    33957: 01/08/09: Re: Wildcard and Foundation tools
    33986: 01/08/09: Re: Generate constants with a function
    33987: 01/08/09: Re: multplier
    33997: 01/08/10: Re: Anyone using Xilinx System Generator yet???
    34533: 01/08/29: Re: new to fpga
    34537: 01/08/29: Re: Slowing PCI for FPGA
    34611: 01/08/30: Re: Big SR in Virtex-E
    34625: 01/08/31: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
    34639: 01/08/31: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
    34670: 01/09/03: Re: DSP in OTP
    34672: 01/09/03: Re: Virtex Architecture: Interconnect
    34678: 01/09/03: Re: Segmented interconnects
    34694: 01/09/04: Re: Open collector outputs
    34711: 01/09/04: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
    34743: 01/09/06: Re: Virtex II sizing rule of thumb
    34745: 01/09/06: Re: Virtex-2 engineering samples
    34763: 01/09/06: Re: Missing bits
    34766: 01/09/06: Re: Segmented interconnects
    34793: 01/09/08: Re: Actel FPGA glitches
    34795: 01/09/08: Re: Clock division in Xilinx Vertex-E.
    34796: 01/09/08: Re: Missing bits
    34797: 01/09/08: Re: Selection of a suitable FPGA board
    34799: 01/09/08: Re: Clock division in Xilinx Vertex-E.
    34805: 01/09/08: Re: SOS : A Question about synthesizng ROM
    34806: 01/09/08: Re: Missing bits
    34811: 01/09/08: Re: Xilinx dev. kit for Linux?
    34812: 01/09/09: Re: To mix frequency with a FPGA
    34816: 01/09/09: Re: Selection of a suitable FPGA board
    34829: 01/09/10: Re: Actel FPGA glitches
    34954: 01/09/15: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
    34987: 01/09/17: Re: QPSK modulator with no multipliers
    34989: 01/09/17: Re: Problems with Xilinx VirtexE (Newbie)
    34990: 01/09/17: Re: Block RAM initialization
    34991: 01/09/17: Re: Block RAM initialization
    34992: 01/09/17: Re: Carry Chain: Delay
    34993: 01/09/17: Re: INIT attribute of SRL16E
    34995: 01/09/17: Re: Virtex-2 availability
    34996: 01/09/17: Re: Altera survey
    35025: 01/09/18: Re: Virtex-2 variable DPS availability
    35026: 01/09/18: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
    35038: 01/09/18: Re: QPSK modulator with no multipliers
    35077: 01/09/20: Re: Synplicity logic replication
    35108: 01/09/21: Re: Synplicity logic replication
    35109: 01/09/21: Re: Increase routing delay in XILINX FPGA editor
    35120: 01/09/21: Re: problem with location constraints in Verilog
    35125: 01/09/22: Re: Virtex Clock Enable and Synplify
    35139: 01/09/23: Re: problem with location constraints in Verilog
    35140: 01/09/23: Re: how to simulate virtex components?
    35158: 01/09/24: Re: comp.arch.fpga : Unusual clock divider ckt
    35159: 01/09/24: Re: Synplicity logic replication
    35198: 01/09/25: Re: FPGA with embedded Memory
    35200: 01/09/25: Re: Virtex2 slice level instantiation in verilog question
    35205: 01/09/25: Re: Virtex2 slice level instantiation in verilog question
    35227: 01/09/26: Re: how to simulate virtex components?
    35263: 01/09/27: Re: Timing constraints...
    35276: 01/09/27: Re: Logical constraints of LUT
    35282: 01/09/27: Re: Logical constraints of LUT
    35286: 01/09/27: Re: System DSP Generator on Xilinx
    35297: 01/09/28: Re: Fastest way to become a Verilog samurai?
    35298: 01/09/28: Re: fir filter
    35299: 01/09/28: Re: verification problems please help
    35318: 01/09/28: Re: how to dublicate logic?
    35320: 01/09/28: Re: Active-HDL back annotated simulation and PC memory usage
    35321: 01/09/28: Re: Meta-stability
    35327: 01/09/29: Re: Forcing a LUT logic function (was Synplicity logic replication)
    35364: 01/10/01: Re: future Xilinx products wish list ...
    35365: 01/10/01: Re: Forcing a LUT logic function (was Synplicity logic replication)
    35374: 01/10/02: Re: barrel shifter in Xilinx Virtex-E
    35376: 01/10/02: Re: barrel shifter in Xilinx Virtex-E
    35397: 01/10/02: Re: Barrel Shifter
    35402: 01/10/03: Re: comp.arch.fpga : Unusual clock divider ckt
    35417: 01/10/04: Re: Barrel Shifter
    35429: 01/10/04: Re: comp.arch.fpga : Unusual clock divider ckt
    35430: 01/10/04: Re: multipliers in virtex-II
    35456: 01/10/05: Re: ROM based FSMs
    35459: 01/10/05: Re: Video processing
    35463: 01/10/06: Re: ROM based FSMs
    35469: 01/10/06: Re: ROM based FSMs
    35476: 01/10/07: Re: ROM based FSMs
    35480: 01/10/07: Re: ROM based FSMs
    35481: 01/10/07: Re: ROM based FSMs
    35484: 01/10/07: Re: ROM based FSMs
    35549: 01/10/10: Re: qpsk clock recovery
    35562: 01/10/10: Re: 155MHz to DLL in Spartan II
    35563: 01/10/10: Re: Virtex-2 maximum clock speed
    35593: 01/10/11: Re: FPGA reset
    35594: 01/10/11: Re: High level synthesis will never work well :)
    35605: 01/10/11: Re: High level synthesis will never work well :)
    35640: 01/10/12: Re: High level synthesis will never work well :)
    35641: 01/10/12: Re: I need free PCI-Core (vhdl)!!
    35642: 01/10/12: Re: PWM Signal in VHDL ?
    35643: 01/10/12: Re: Small FPGA proto boards
    35689: 01/10/13: Re: FPGA Asynchronous Design
    35703: 01/10/14: Re: FPGA Asynchronous Design
    35704: 01/10/14: Re: Instantiating Virtex II library macros.
    35734: 01/10/16: Re: System Gates
    35751: 01/10/16: Re: 1024 point non-complex FFT on a SPARTAN2
    35752: 01/10/16: Re: Instantiating Virtex II library macros.
    35869: 01/10/22: Re: Verilog vs. VHDL
    35911: 01/10/23: Re: Verilog vs. VHDL
    35912: 01/10/23: Re: Verilog vs. VHDL
    35924: 01/10/24: Re: RLOC under VHDL
    35973: 01/10/25: Re: Recommend a book
    35977: 01/10/25: Re: How to make an implementable big counter?
    35978: 01/10/25: Re: transferring data between related clocks
    35997: 01/10/25: Re: How to make an implementable big counter?
    35998: 01/10/25: Re: Cheap programming of XC2018?
    36010: 01/10/26: Re: DSP on FPGA Opinions Needed->Earn $100
    36028: 01/10/26: Re: How to make an implementable big counter?
    36033: 01/10/26: Re: S/PDIF interface for FPGA
    36051: 01/10/27: Re: How to make an implementable big counter?
    36056: 01/10/27: Re: fir filter
    36063: 01/10/27: Re: Digital image input for simulation on Altera FPGA
    36064: 01/10/27: Re: DSP on FPGA Opinions Needed->Those are good questions.
    36070: 01/10/27: Re: How to make an implementable big counter?
    36076: 01/10/28: Re: FIR >14 taps
    36077: 01/10/28: Re: How to make an implementable big counter?
    36161: 01/10/31: Re: Second Scenario: BRAM usage reduction in FIFO design
    36162: 01/10/31: Re: one SPROM for 2 XCS30XLs?
    36175: 01/11/01: Re: Leonardo bugs
    36210: 01/11/02: Re: Altera Local Routing
    36211: 01/11/02: Re: Registered as well as unregistered outputs?
    36213: 01/11/02: Re: XC6000
    36229: 01/11/02: Re: Altera Local Routing
    36230: 01/11/02: Re: Guided Design, Xilinx Virtex-E
    36262: 01/11/04: Re: spartan synthesis with synopsis
    36285: 01/11/05: Re: Implementing Filter
    36287: 01/11/05: Re: Registered as well as unregistered outputs?
    36306: 01/11/06: Re: Heatsink for Xilinx FF896 package?
    36307: 01/11/06: Re: Xilinx Floorplanner Effectiveness
    36311: 01/11/06: Re: count and divide Idea needed
    36312: 01/11/06: Re: spartan synthesis with synopsis
    36313: 01/11/06: Re: speed of adder in XC1000E-6
    36314: 01/11/06: Re: Can anyone guide me in selecting an FPGA?
    36329: 01/11/06: Re: Xilinx DLL clock question
    36330: 01/11/06: Re: speed of adder in XC1000E-6
    36331: 01/11/06: Re: RLOC for a block
    36334: 01/11/06: Re: placement for if (vhdl)
    36345: 01/11/07: Re: FPGA suppliers for hobbyists?
    36412: 01/11/08: Re: How dense are FPGA/CPLD's
    36413: 01/11/08: Re: count and divide Idea needed
    36416: 01/11/08: Re: Virtex2 gate-level simulation: SDF and timing errors
    36466: 01/11/09: Re: Log2(x) for vhdl?
    36486: 01/11/09: Re: RLOC on RAMB4_Sn_Sn
    36487: 01/11/09: Re: Xilinx unconnected logic
    36491: 01/11/09: Re: How to convert unsigned integer into std_logic_vector in VHDL
    36500: 01/11/09: Re: ideas
    36501: 01/11/09: Re: Implementation of filter with three set of coeffs
    36502: 01/11/09: Re: Implementation of filter with three set of coeffs
    36507: 01/11/10: Re: Log2(x) for vhdl?
    36539: 01/11/12: Re: Quadrature Encoder Sampling Time
    36597: 01/11/13: Re: ideas
    36643: 01/11/14: Re: Place your orders....
    36770: 01/11/19: Re: Synopsys+Xilinx vs Synplicity
    36771: 01/11/19: Re: DLL cycle-to-cycle jitter
    36779: 01/11/20: Re: Modelsim
    36803: 01/11/20: Re: Synplify use question
    36817: 01/11/21: Re: Bit-serial efficiency
    36895: 01/11/23: Re: fix LOC on LUT1
    36896: 01/11/23: Re: Fast Fourier Transformation - camera data
    36938: 01/11/26: Re: FFT with Distributed Arithmatic
    36941: 01/11/27: Re: Which vendor to choose
    37167: 01/12/02: Re: What do you like/dislike about place and route tools?
    37168: 01/12/02: Re: 128-bit scrambling and CRC computations
    37208: 01/12/04: Re: What do you like/dislike about place and route tools?
    37218: 01/12/04: Re: I need a Xilinx Spartan PCI Development Board
    37285: 01/12/06: Re: Where can I find the implemention of block float multiplier?
    37310: 01/12/06: Re: where is designed FPGA for apple II computer...?
    37316: 01/12/07: Re: Where can I find the implemention of block float multiplier?
    37320: 01/12/07: Re: where is designed FPGA for apple II computer...?
    37321: 01/12/07: Re: I need a Xilinx Spartan PCI Development Board
    37351: 01/12/07: Re: For Sale: Huge Xilinx FPGA lots
    37352: 01/12/07: Re: I need a Xilinx Spartan PCI Development Board
    37361: 01/12/08: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
    37370: 01/12/08: Re: I need a Xilinx Spartan PCI Development Board
    37371: 01/12/08: Re: Xilinx multiplier and block ram error
    37382: 01/12/09: Re: I need a Xilinx Spartan PCI Development Board
    37465: 01/12/11: Re: What do you like/dislike about place and route tools?
    37473: 01/12/12: Re: DCM error
    37475: 01/12/12: Re: how do i implement it?
    37477: 01/12/12: Re: Altera pin drivers
    37478: 01/12/12: Re: Altera pin drivers
    37479: 01/12/12: Re: Initialization of RAM
    37506: 01/12/13: Re: Initialization of RAM
    37508: 01/12/13: Re: Crosstalk on clocks
    37547: 01/12/14: Re: Dual-port ram templates
    37553: 01/12/14: Re: Fondation 4.1 and SpartanXL
    37556: 01/12/14: Re: Dual-port ram templates
    37564: 01/12/15: Re: Dual-port ram templates
    37662: 01/12/18: Re: is it OK?
    37664: 01/12/18: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
    37679: 01/12/19: Re: You take the low road and I'll ......
    37688: 01/12/19: Re: You take the low road and I'll ......
    37689: 01/12/19: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
    37695: 01/12/19: Re: Xilinx Foundation - Routing constraints/prohibit
    37740: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
    37741: 01/12/19: Re: You take the low road and I'll ......
    37765: 01/12/20: Re: Virtex 2 & Trace
    37766: 01/12/20: Re: Hardware FPGA questions
    37799: 01/12/20: Re: The speedest FPGA
    37805: 01/12/20: Re: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
    37817: 01/12/20: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
    37818: 01/12/20: Re: You take the low road and I'll ......
    37819: 01/12/20: Re: annoying problem and "simple and clever solution"
    37867: 01/12/22: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
    37881: 01/12/22: Re: Beginners question: several circuits in one chip
    37895: 01/12/23: Re: Default Should Be "Inputs and Outputs" For IOBs - please respond???
    37896: 01/12/23: Re: Kindergarten Stuff
    38015: 01/12/31: Re: Stupid Foundation Question (Hey Peter, some Kindergarden stuff for
    38023: 01/12/31: Re: CRC-32 48bit(width)
    38112: 02/01/06: Re: RNS
    38113: 02/01/06: Re: A Fast counter in VHDL?
    38194: 02/01/08: Re: 128 bit compare delay kill me!
    38203: 02/01/08: Re: ROM synthesis question
    38254: 02/01/10: Re: ROM synthesis question
    38255: 02/01/10: Re: distributed ram bits in XCVxxxx series
    38256: 02/01/10: Re: bufg instantiation in ISE 4.1
    38257: 02/01/10: Re: bufg instantiation in ISE 4.1
    38258: 02/01/10: Re: comp.arch.fpga : Problem with modelsim and ISE4.1
    38269: 02/01/10: Re: FPGA Synthesis and implementation
    38271: 02/01/10: Re: FPGA Synthesis and implementation
    38299: 02/01/11: Re: The speedest FPGA
    38300: 02/01/11: Re: multiply (*) 11000000000
    38301: 02/01/11: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
    38304: 02/01/11: Re: asic vs. fpga
    38328: 02/01/11: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
    38331: 02/01/11: Re: Picking an FPGA
    38332: 02/01/11: Re: APEX-II vs VIRTEX-II
    38335: 02/01/11: Re: How to constrain the inputs of a multi-level parity generator and
    38350: 02/01/12: Re: speech recognition - active noise cancellation
    38352: 02/01/12: Re: Picking an FPGA
    38353: 02/01/12: Re: Picking an FPGA
    38354: 02/01/12: Re: multiply (*) 11000000000
    38355: 02/01/12: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
    38372: 02/01/12: Re: speech recognition - active noise cancellation
    38391: 02/01/13: Re: Homebrew computers using FPGA?
    38392: 02/01/13: Re: speech recognition - active noise cancellation
    38475: 02/01/15: Re: Repost: Should clock skew be included for setup time analysis?
    38536: 02/01/16: Re: Signal processing using FPGAs
    38537: 02/01/16: Re: Repost: Should clock skew be included for setup time analysis?
    38538: 02/01/16: Re: Leonardo + Xilinx tools help
    38543: 02/01/17: Re: Repost: Should clock skew be included for setup time analysis?
    38567: 02/01/17: Re: Image Processing on FPGAs. Dose System Generator help??
    38598: 02/01/18: Re: Audio time delay circuit
    38624: 02/01/19: Re: Shift Register question
    38625: 02/01/19: Re: Audio time delay circuit
    38627: 02/01/19: Re: Audio time delay circuit
    38628: 02/01/19: Re: Simple shift register not working
    38629: 02/01/19: Re: Should clock skew be included for setup time analysis?
    38669: 02/01/21: Re: Signal processing using FPGAs
    38683: 02/01/22: Re: Signal processing using FPGAs
    38694: 02/01/22: Re: Q: can ROM content affect logic syn result
    38698: 02/01/22: Re: CRC-32 48bit(width)
    38706: 02/01/22: Re: analog input via serial connection
    38712: 02/01/23: Re: input source to feed 20 filters! how to decrease the load
    38721: 02/01/23: Re: Virtex-II Programming Highs and Lows
    38736: 02/01/23: Re: CRC-32 48bit(width)
    38737: 02/01/23: Re: Q: can ROM content affect logic syn result
    38738: 02/01/23: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
    38741: 02/01/23: Re: Internal tri state buffer..
    38764: 02/01/24: Re: Internal tri state buffer..
    38765: 02/01/24: Re: Dynamic Reconfiguration of single Xilinx FPGA
    38773: 02/01/24: Re: Dynamic Reconfiguration of single Xilinx FPGA
    38776: 02/01/24: Re: Synthsis Tools for Xilinx
    38781: 02/01/25: Re: Audio time delay circuit
    38785: 02/01/25: Re: Dynamic Reconfiguration of single Xilinx FPGA
    38816: 02/01/26: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
    38827: 02/01/26: Re: Mapping between Xlinx 4K and Spartan-II
    38828: 02/01/26: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
    38893: 02/01/28: Re: Simple shift register not working (update)
    38915: 02/01/28: Re: tri-state vs. Mux
    38918: 02/01/28: Re: Pin assignment on ACEX1K
    38919: 02/01/28: Re: Xilinx webpack
    38933: 02/01/28: Re: Books on DSP
    38935: 02/01/28: Re: Simple shift register not working (update)
    38947: 02/01/28: Re: Xilinx webpack
    38988: 02/01/29: Re: Books on DSP
    38992: 02/01/29: Re: dll error message in ModelSim XE/Starter 5.5b
    39030: 02/01/30: Re: The LUT puzzle, Iam on the way
    39033: 02/01/30: Re: Dont care simulation
    39035: 02/01/30: Re: Books on DSP
    39040: 02/01/30: Re: function synthesis.
    39047: 02/01/30: Re: 9 or 8 bits for image processing ?
    39051: 02/01/30: Re: Signal assignment mismatch with Aldec 5.1 problem
    39053: 02/01/30: Re: 9 or 8 bits for image processing ?
    39057: 02/01/30: Re: RLOCS with combinatorial logic
    39058: 02/01/30: Re: The LUT puzzle, Iam on the way
    39059: 02/01/30: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
    39089: 02/01/31: Re: The LUT puzzle, Iam on the way
    39090: 02/01/31: Re: Memory Question on Virtex
    39140: 02/02/01: Re: The LUT puzzle, Iam on the way
    39147: 02/02/01: Re: Linking IP
    39159: 02/02/02: Re: Linking IP
    39205: 02/02/04: Re: solutions manuals, and no they are not for school
    39206: 02/02/04: Re: ClkEnable vs gated clock
    39208: 02/02/04: Re: RAM question
    39209: 02/02/04: Re: Virtex-II and SDRAM Controller at 133MHz
    39220: 02/02/04: Re: RAM question
    39226: 02/02/04: Re: par and carry chains not allowing manual floorplanning
    39241: 02/02/05: Re: FPGA or Micro-controller in Lowpower designs?
    39248: 02/02/05: Re: FPGA or Micro-controller in Lowpower designs?
    39313: 02/02/06: Re: ClkEnable vs gated clock
    39315: 02/02/06: Re: Virtex 2 rect->pol conversion
    39326: 02/02/06: Re: Pseudorandom Bitstream
    39358: 02/02/07: Re: Virtex-II and SDRAM Controller at 133MHz
    39359: 02/02/07: Re: Pseudorandom Bitstream
    39360: 02/02/07: Re: CLKDLL x4 problem
    39362: 02/02/07: Re: MC6800 vhdl design
    39368: 02/02/07: Re: Pseudorandom Bitstream
    39369: 02/02/07: Re: Which PC for ALTERA development tools ?
    39370: 02/02/07: Re: Multiple clock domein synchronization.
    39386: 02/02/07: Re: Pseudorandom Bitstream
    39418: 02/02/08: Re: Xilinx DCM question anyone? (or Peter if he is there?)
    39420: 02/02/08: Re: CLKDLL x4 problem
    39421: 02/02/08: Re: Pseudorandom Bitstream
    39429: 02/02/08: Re: Xilinx ISE 3.3 upgrade to 4.1
    39430: 02/02/08: Re: Multiple clock domein synchronization.
    39457: 02/02/10: Re: Multiple clock domein synchronization.
    39459: 02/02/10: Re: Multiple clock domein synchronization.
    39460: 02/02/10: Re: par and carry chains not allowing manual floorplanning
    39463: 02/02/11: Re: par and carry chains not allowing manual floorplanning
    39479: 02/02/11: Re: Altera's new family Stratix
    39480: 02/02/11: Re: Multiple clock domein synchronization.
    39488: 02/02/11: Re: Altera's new family Stratix
    39489: 02/02/11: Re: I think it's a synthesis bug
    39491: 02/02/12: Re: Xilinx EDIF to BIT transation
    39493: 02/02/12: Re: par and carry chains not allowing manual floorplanning
    39497: 02/02/12: Re: Altera's new family Stratix
    39505: 02/02/12: Re: Pseudorandom Bitstream
    39507: 02/02/12: Re: Multiple clock domein synchronization.
    39508: 02/02/12: Re: Making Altera development quicker
    39531: 02/02/12: Re: Newbie SpartanII Block Ram question
    39532: 02/02/12: Re: Power estimation for Virtex-2 device
    39539: 02/02/12: Re: Spartan Program/Verify
    39541: 02/02/13: Re: Pseudorandom Bitstream
    39543: 02/02/13: Re: Making Altera development quicker
    39559: 02/02/13: Re: Suggestions on distributing a module...
    39560: 02/02/13: Re: RAM CORE settings for maximum speed
    39561: 02/02/13: Re: Pseudorandom Bitstream
    39562: 02/02/13: Re: par and carry chains not allowing manual floorplanning
    39564: 02/02/13: Re: Making Altera development quicker
    39565: 02/02/13: Re: Foundation 4.1 vs. ISE 4.1?
    39615: 02/02/14: Re: Spartan-II becomes Vertex.
    39616: 02/02/14: Re: RAM CORE settings for maximum speed
    39619: 02/02/14: Re: Power estimation for Virtex-2 device
    39620: 02/02/14: Re: Foundation 4.1 vs. ISE 4.1?
    39654: 02/02/15: Re: Spartan-II becomes Vertex.
    39656: 02/02/15: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
    39657: 02/02/15: Re: par and carry chains not allowing manual floorplanning
    39670: 02/02/15: Re: oscillation
    39675: 02/02/15: Re: Spartan-II becomes Vertex.
    39691: 02/02/16: Re: oscillation
    39696: 02/02/16: Re: FPGA choices and questions
    39801: 02/02/20: Re: Xilinx ISE 3.3 upgrade to 4.1
    39802: 02/02/20: Re: Xilinx IP Core multiplier performance
    39822: 02/02/20: Re: Virtex-II and SDRAM Controller at 133MHz
    39823: 02/02/20: Re: Pseudorandom Bitstream
    39824: 02/02/20: Re: Xilinx ISE 3.3 upgrade to 4.1
    39838: 02/02/21: Re: Do I need to install software in order to use Multilinx?
    39840: 02/02/21: Re: Xilinx IP Core multiplier performance
    39843: 02/02/21: Re: Do I need to install software in order to use Multilinx?
    39856: 02/02/21: Re: Do I need to install software in order to use Multilinx?
    39857: 02/02/21: Re: Virtex-E BRAM timing
    39858: 02/02/21: Re: CLKDLL x4 problem
    39859: 02/02/21: Re: SRL16E Initialization
    39879: 02/02/21: Re: Whether an FPGA & CPLD device has been spoiled.
    39880: 02/02/21: Re: FPGA: JTAG CABLE
    39881: 02/02/21: Re: Using a CoreGen component
    39882: 02/02/21: Re: Do I need to install software in order to use Multilinx?
    39917: 02/02/22: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
    39921: 02/02/22: Re: Coolrunner and ISP
    39953: 02/02/22: Re: QPRO questions
    40158: 02/03/01: Re: Comparison between two FPGAs- what is decisive factor?
    40159: 02/03/01: Re: Creation of FPGA tips and tricks forum - help required
    40161: 02/03/01: Re: Altera FPGAs
    40164: 02/03/01: Re: IIR. convolution
    40181: 02/03/01: Re: Clock multiplier/ADPLL in PLD
    40198: 02/03/01: Re: Clock multiplier/ADPLL in PLD
    40199: 02/03/01: Re: Rising and falling edge of a clk
    40228: 02/03/02: Re: What FPGA to use?
    40247: 02/03/03: Re: Rising and falling edge of a clk
    40273: 02/03/04: Re: Altera FPGAs
    40296: 02/03/05: Re: Altera FPGAs
    40300: 02/03/05: Re: Minimum Size and Logic Sharing
    40330: 02/03/05: Re: What FPGA to use?
    40339: 02/03/05: Re: exceeding 2GB limits in xilinx
    40341: 02/03/05: Re: Altera FPGAs
    40353: 02/03/05: Re: Altera FPGAs
    40389: 02/03/06: Re: FPGA or DSP
    40390: 02/03/06: Re: FPGA or DSP in a power supply?
    40391: 02/03/06: Re: exceeding 2GB limits in xilinx
    40393: 02/03/06: Re: Xilinx announces Virtex-II Pro is shipping
    40424: 02/03/07: Re: Rising and falling edge of a clk
    40446: 02/03/07: Re: FPGA or DSP in a power supply?
    40457: 02/03/07: Re: Rising and falling edge of a clk
    40483: 02/03/07: Re: Quartus II 2.0 fast fit option
    40512: 02/03/08: Re: FPGA or DSP in a power supply?
    40515: 02/03/08: Re: FPGA or DSP in a power supply?
    40529: 02/03/08: Re: exceeding 2GB limits in xilinx
    40540: 02/03/09: Re: BlockRam
    40545: 02/03/09: Re: BlockRam
    40546: 02/03/09: Re: exceeding 2GB limits in xilinx
    40622: 02/03/12: Re: Article in March Embedded Systems - "The Death of Hardware
    40652: 02/03/12: Re: exceeding 2GB limits in xilinx
    40653: 02/03/12: Re: floating pins
    40654: 02/03/12: Re: RTL/Gate-Level Simulation
    40677: 02/03/12: Re: Article in March Embedded Systems - "The Death of Hardware
    40683: 02/03/12: Re: Article in March Embedded Systems - "The Death of Hardware
    40688: 02/03/13: Re: How do I infer a carry-chain parity generator in XST?
    40689: 02/03/13: Re: Mystery two wire interface, or am I being dense?
    40744: 02/03/14: Re: where to start with constraining..
    40853: 02/03/16: Re: To Falk Brunner
    40856: 02/03/17: Re: Difference between Virtex-II(E) und Virtex-E
    40976: 02/03/19: Re: DDS in an FPGA
    40980: 02/03/19: Re: Xilinx : Altera pin compatibility
    41010: 02/03/19: Re: DDS in an FPGA
    41037: 02/03/20: Re: STARTUP_VIRTEX primitive
    41038: 02/03/20: Re: Any Stratix impressions based on results?
    41054: 02/03/20: Re: which is the fastest FPGA ?
    41094: 02/03/20: Re: questions from a newby
    41127: 02/03/21: Re: simulation issues
    41167: 02/03/22: Re: Maximum device usage for successful PAR
    41188: 02/03/22: Re: Altera Stratix compared to Xilinx Virtex
    41189: 02/03/22: Re: which is the fastest FPGA ?
    41234: 02/03/22: Re: Altera Stratix compared to Xilinx Virtex
    41238: 02/03/23: Re: GREAT availability on Coolrunner!!! (was: Poor availability problems
    41244: 02/03/23: Re: Altera Stratix compared to Xilinx Virtex
    41293: 02/03/25: Re: Maximum device usage for successful PAR
    41294: 02/03/25: Re: which is the fastest FPGA ?
    41295: 02/03/25: Re: Too many clocks
    41320: 02/03/26: Re: question on LFSR
    41324: 02/03/26: Re: question on LFSR
    41364: 02/03/26: Re: question on LFSR
    41382: 02/03/27: Re: question on LFSR
    41400: 02/03/27: Re: clock source
    41401: 02/03/27: Re: I2C Slave sampling edge
    41402: 02/03/27: Re: XPower & Power Estimator Spreadsheet
    41404: 02/03/27: Re: How can I add constrains?
    41413: 02/03/27: Re: XPower & Power Estimator Spreadsheet
    41431: 02/03/28: Re: I2C Slave sampling edge
    41451: 02/03/28: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
    41452: 02/03/28: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
    41458: 02/03/29: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
    41530: 02/04/01: Re: Laying out the design
    41543: 02/04/02: Re: Laying out the design
    41544: 02/04/02: Re: powerpc in virtex2pro
    41556: 02/04/02: Re: Laying out the design
    41578: 02/04/02: Re: Marquis of Queensbury Rules
    41587: 02/04/03: Re: Simulator for xilinx Cores?
    41629: 02/04/03: Re: ACEX maximal clock...
    41646: 02/04/04: Re: hand placement
    41647: 02/04/04: Re: Schematic Stuff
    41674: 02/04/05: Re: hand placement
    41678: 02/04/05: Re: powerpc in virtex2pro
    41680: 02/04/05: Re: Monostable multivibrator
    41682: 02/04/05: Re: hand placement
    41690: 02/04/05: Re: hand placement
    41691: 02/04/05: Re: hand placement
    41692: 02/04/05: Re: hand placement
    41693: 02/04/05: Re: Schematic Stuff
    41731: 02/04/06: Re: again this hand placement thing
    41732: 02/04/06: Re: Simulator for xilinx Cores?
    41733: 02/04/06: Re: hand placement
    41734: 02/04/06: Re: hand placement
    41843: 02/04/09: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
    41970: 02/04/12: Re: Built in multipliers in Virtex 2000E?
    41971: 02/04/12: Re: Attributes *and* generics!?
    41972: 02/04/12: Re: iMPACT FPGA detection error
    41976: 02/04/12: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
    41998: 02/04/12: Re: Attributes *and* generics!?
    42004: 02/04/12: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
    42024: 02/04/13: Re: Built in multipliers in Virtex 2000E?
    42025: 02/04/13: Re: Laying out the design
    42026: 02/04/13: Re: Marquis of Queensbury Rules
    42027: 02/04/13: Re: PCI Bridge Question
    42028: 02/04/13: Re: FPGA eval/dev boards with *serial* interface?
    42141: 02/04/16: Re: creating my own RPMs(?) or similar
    42181: 02/04/18: Re: FPGA Timing Problem
    42548: 02/04/27: Re: Floorplanning
    42549: 02/04/27: Re: SpartanII design considerations...
    42553: 02/04/27: Re: Using 74HCT245N between Spartan-II and ISA
    42554: 02/04/27: Re: Using 74HCT245N between Spartan-II and ISA
    42566: 02/04/27: Re: Xilinx Programmable World 2002 - Review
    42593: 02/04/28: Re: SpartanII design considerations...
    42596: 02/04/28: Re: Xilinx Easypath- Selling parts with known defects
    42907: 02/05/06: Re: 1000 I/O Pins -- What is cheapest FPGA?
    42909: 02/05/06: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
    42973: 02/05/08: Re: VHDL: FIFO
    43027: 02/05/09: Re: A special Thanks to :
    43028: 02/05/09: Re: "easter egg" in FPGA design?
    43037: 02/05/10: Re: "easter egg" in FPGA design?
    43102: 02/05/14: Re: Neverending ISA bus interface drama, Spartan-II
    43203: 02/05/16: Re: Virtex-E interconnection
    43267: 02/05/17: Re: RPMs
    43268: 02/05/17: Re: Need Help on FPGA and Spiking Neurons
    43270: 02/05/17: Re: What properties has FPGA?
    43271: 02/05/17: Re: virtex 2 block rams
    43296: 02/05/18: Re: Need Help on FPGA and Spiking Neurons
    43297: 02/05/18: Re: RPMs
    43316: 02/05/18: Re: button & 3 LED's
    43319: 02/05/18: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
    43336: 02/05/19: Re: RPMs
    43337: 02/05/19: Re: Reading GSR signal of Spartan-II
    43396: 02/05/21: Re: Rounding Accumulator
    43397: 02/05/21: Re: Difference between Altera and Xilinx.
    43398: 02/05/21: Re: button & 3 LED's
    43399: 02/05/21: Re: Reading GSR signal of Spartan-II
    43448: 02/05/21: Re: button & 3 LED's
    43494: 02/05/22: Time for a new computer. Suggestions?
    43495: 02/05/22: Re: 50Mhz driven - Overheat by Program?
    43507: 02/05/22: Re: Time for a new computer. Suggestions?
    43508: 02/05/22: Re: Aldec Active-HDL 5.1 + Xilinx ISE 4.1 - how to simulate ?
    43509: 02/05/22: Re: inverse engeneering on XC3020.
    43511: 02/05/22: Re: i need help getting started with fpgas
    43549: 02/05/23: Re: FPGA, VHDL : RAM initialization
    43550: 02/05/23: Re: Time for a new computer. Suggestions?
    43557: 02/05/24: Re: Time for a new computer. Suggestions?
    43573: 02/05/24: Re: Frequency synthesiser
    43574: 02/05/24: Re: FPGA and VHDL: question about RAM initialization
    43587: 02/05/24: Re: Time for a new computer. Suggestions?
    43634: 02/05/28: Re: Frequency synthesiser
    43635: 02/05/28: Re: P&R times
    43636: 02/05/28: Re: XACT - Xilinx design editor for a 2018 design desperately needed ...
    43637: 02/05/28: Re: avoiding resynthesis
    43639: 02/05/28: Re: SOPC for machine vision
    43745: 02/05/31: Re: Time for a new computer. Suggestions?
    43783: 02/06/03: Re: place and route simulation time
    43845: 02/06/04: Re: divide by 5
    43846: 02/06/04: Re: FPGA destruction possible?
    43847: 02/06/04: Re: FPGA destruction possible?
    43849: 02/06/04: Re: VirtexE DLL Output clock phase
    43867: 02/06/04: Re: Hard macro in FPGA, or how to cut a big project in smaller ones
    43868: 02/06/04: Re: VirtexE DLL Output clock phase
    43869: 02/06/04: Re: FPGA destruction possible?
    43870: 02/06/04: Re: FPGA destruction vs power management
    43871: 02/06/04: Re: Small FIFOs in Spartan
    43872: 02/06/04: Re: place and route simulation time
    43886: 02/06/05: Re: Interpreting coregen footprint output in terms of slices
    43903: 02/06/05: Re: Interpreting coregen footprint output in terms of slices
    43917: 02/06/06: Re: xc3042
    43918: 02/06/06: Re: Do I have metastability issues?
    43928: 02/06/06: Re: FPGA destruction vs power management
    43948: 02/06/07: Re: xc3042
    43970: 02/06/07: Re: Help - Xilinx SRL16 primitive gives 'X's in simulation
    43974: 02/06/07: Re: Doing Trig Functions in FPGA, EPLD
    43990: 02/06/08: Re: Doing Trig Functions in FPGA, EPLD
    43991: 02/06/08: Re: Xilinx ise software?
    43992: 02/06/08: Re: Do I have metastability issues?
    44010: 02/06/09: Re: Do I have metastability issues?
    44027: 02/06/10: Re: where did my MHz go!
    44040: 02/06/10: Re: programming xc3030 using atmel's ATDH2225 programmer cable
    44045: 02/06/10: Re: BUFGDLL again
    44058: 02/06/11: Re: programming xc3030 using atmel's ATDH2225 programmer cable
    44108: 02/06/12: Re: MAP problem with RLOC'ed macros
    44109: 02/06/12: Re: 20,000 gates?
    44110: 02/06/12: Re: synthesis query: Xilinx + Synplify
    44155: 02/06/12: Re: synthesis query: Xilinx + Synplify
    44159: 02/06/13: Re: Digital FM demodulator in FPGA-continue
    44160: 02/06/13: Re: Digital FM demodulator in FPGA-continue
    44161: 02/06/13: Re: Digital FM demodulator in FPGA-continue
    44163: 02/06/13: Re: 20,000 gates?
    44169: 02/06/13: Re: MAP problem with RLOC'ed macros
    44179: 02/06/13: Re: Digital FM demodulator in FPGA-continue
    44180: 02/06/13: Re: Digital FM demodulator in FPGA-continue
    44181: 02/06/13: Re: Digital FM demodulator in FPGA-continue
    44182: 02/06/13: Re: Digital FM demodulator in FPGA-continue
    44183: 02/06/13: Re: Xilinx primitives & ModelSim
    44202: 02/06/13: Re: MAP problem with RLOC'ed macros
    44217: 02/06/14: Re: MAP problem with RLOC'ed macros
    44218: 02/06/14: Re: MAP problem with RLOC'ed macros
    44231: 02/06/14: Re: Xilinx primitives & ModelSim
    44240: 02/06/14: Re: MAP problem with RLOC'ed macros
    44255: 02/06/14: Re: TTL library in Xilinx?
    44256: 02/06/14: Re: TTL library in Xilinx?
    44257: 02/06/14: Re: Xilinx newest version?
    44303: 02/06/17: Re: Xilinx System Generator FIR vs Core Generator FIR
    44314: 02/06/17: Re: Which Synthesis tool for XILINX
    44336: 02/06/18: Re: Which Synthesis tool for XILINX
    44362: 02/06/18: Re: Which Synthesis tool for XILINX
    44384: 02/06/19: Re: 5V tolerance
    44402: 02/06/19: Re: 5V tolerance
    44446: 02/06/20: Re: barrel shifter
    44458: 02/06/20: Re: 5V tolerance
    44459: 02/06/20: Re: How to get Unisims netlist?
    44471: 02/06/21: Re: 5V tolerance
    44472: 02/06/21: Re: hierarchy in Altera FPGAs
    44473: 02/06/21: Re: what's the use of BlockRAM
    44594: 02/06/24: Re: CIC filter
    44596: 02/06/24: Re: Clock enable & Synplify 7.1
    44604: 02/06/24: Re: CLK/2
    44622: 02/06/25: Re: Multiply by 8 with DLL in Spaertan-II.
    44650: 02/06/26: Re: Clock enable & Synplify 7.1
    44651: 02/06/26: Re: too hot fpga device
    44652: 02/06/26: Re: skew control between different signals ?
    44658: 02/06/26: Re: Multiply by 8 with DLL in Spaertan-II.
    44671: 02/06/26: Re: why not pipeline by default?
    44677: 02/06/26: Re: 5V tolerance
    44703: 02/06/27: Re: fast adders using HDL in Xilinx fpga
    44714: 02/06/27: Re: Generate loop and RLOC
    44718: 02/06/28: Re: Generate loop and RLOC
    44729: 02/06/28: Re: variable decimation filter with rational sampling factors
    44801: 02/07/01: Re: Can Coolrunner's be daisy chained?
    44811: 02/07/02: Re: Converting Altera Block Ram to Xilinx Block Ram
    44826: 02/07/02: Re: Power consumtion simulation for FPGA?
    44834: 02/07/02: Re: Virtex II - Assigning Pins before routing?
    44842: 02/07/02: Re: Power consumtion simulation for FPGA?
    44867: 02/07/03: Re: Converting to Altera Quartus
    44879: 02/07/03: Re: Power consumtion simulation for FPGA?
    44893: 02/07/04: Re: Maximum frequency in Virtex and Virtex-E Devices
    44902: 02/07/05: Re: Type conversion - adding integer to logic_vector
    44914: 02/07/05: Re: Type conversion - adding integer to logic_vector
    44917: 02/07/05: Re: Maximum frequency in Virtex and Virtex-E Devices
    44929: 02/07/06: Re: Converting to Altera Quartus
    44932: 02/07/06: Re: Converting to Altera Quartus
    44938: 02/07/07: Re: Converting to Altera Quartus
    44941: 02/07/07: Re: Newbie FPGA recommedation
    44984: 02/07/09: Re: Virtex reset signal internaly hold?
    44994: 02/07/09: Re: How can I preserve FFs in LeonardoSpectrum?
    45026: 02/07/10: Re: 32 bit multiplier (1 cycle)
    45039: 02/07/10: Re: DPLL
    45067: 02/07/11: Re: Dynamic Addition Subtraction
    45079: 02/07/11: Re: Need a non-pipelined signed integer divider
    45095: 02/07/12: Re: Deterministic Output?
    45118: 02/07/12: Re: Accurate Oscillator
    45131: 02/07/13: Re: Accurate Oscillator
    45140: 02/07/13: Re: Foundation 2.1i --- does it support vertexII?
    45150: 02/07/13: Re: Accurate Oscillator
    45173: 02/07/15: Re: Foundation 2.1i --- does it support vertexII?
    45174: 02/07/15: Re: What proportion of an FPGA's configuration data is used for routing?
    45188: 02/07/15: Re: How to add BUFG to an internal signal?
    45189: 02/07/15: Re: Foundation 2.1i --- does it support vertexII?
    45231: 02/07/17: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
    45242: 02/07/17: Re: 6 parallel inputs to Mux? How?
    45243: 02/07/17: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
    45244: 02/07/17: Re: problem porting sync write, async read RAM to Xilinx...
    45284: 02/07/18: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
    45293: 02/07/18: Re: Xilinx XC9500/XC9500XL versus XC5200 Questions
    45307: 02/07/18: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
    45341: 02/07/19: Re: black box components with parameters in Synplify
    45342: 02/07/19: Re: Theft protection of FPGA configuration data
    45349: 02/07/19: Re: Theft protection of FPGA configuration data
    45351: 02/07/19: Re: dsp v fpga
    45381: 02/07/21: Re: Spartan II JTAG connection with other devices
    45411: 02/07/22: Re: Cheap licenses..
    45413: 02/07/23: Re: black box components with parameters in Synplify
    45427: 02/07/23: Re: xilinx v ti
    45429: 02/07/23: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
    45430: 02/07/23: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
    45431: 02/07/23: Re: 16 X 16 multplier
    45432: 02/07/23: Re: Translate the design from FPGA to Custom IC
    45439: 02/07/23: Re: spiral / waterfall /watersluice : Which are your methods?
    45440: 02/07/23: RLOC Origin problems in ISE4.2sp3?
    45464: 02/07/24: Re: How's the FPGA design job market near you??
    45465: 02/07/24: Re: RLOC Origin problems in ISE4.2sp3?
    45472: 02/07/24: Re: delay pipes in verilog for spartan IIe?
    45520: 02/07/25: Re: How to implement efficient wide word comparator?
    45521: 02/07/25: Re: delay pipes in verilog for spartan IIe?
    45530: 02/07/25: Re: hold time
    45543: 02/07/26: Re: RLOC Origin problems in ISE4.2sp3?
    45544: 02/07/26: Re: logic elements v/s logic cells
    45565: 02/07/26: Re: ALU in VHDL and a bunch of questions
    45567: 02/07/27: Re: FPGA expert needed
    45583: 02/07/27: Re: ALU in VHDL and a bunch of questions
    45593: 02/07/28: Re: ALU in VHDL and a bunch of questions
    45607: 02/07/29: Re: Complex FIR low pass filters
    45608: 02/07/29: Re: Bit serial arithmetic Vs Digit serial Arithmetic
    45609: 02/07/29: Re: ALU in VHDL and a bunch of questions
    45619: 02/07/29: Re: secure FPGA
    45626: 02/07/30: Re: ALU in VHDL and a bunch of questions
    45627: 02/07/30: Re: logic elements v/s logic cells
    45628: 02/07/30: Re: secure FPGA
    45639: 02/07/30: Re: physical attacks (& secure FPGA) - some more questions
    45650: 02/07/30: Re: Maximum FIR coefficient widths on FPGA
    45653: 02/07/30: Re: Pipelined Multiplier Implemented in Slices in Virtex II
    45675: 02/07/31: Re: FPGA performance matrix..
    45686: 02/08/01: Re: Pipelined Multiplier Implemented in Slices in Virtex II
    45758: 02/08/05: Re: Safe design speed
    45778: 02/08/05: Re: Soundchip?
    45786: 02/08/05: Re: Soundchip?
    45788: 02/08/06: Re: clock timing
    45800: 02/08/06: Re: Pipelined Multiplier Implemented in Slices in Virtex II
    45803: 02/08/06: Re: lots of shift registers
    45806: 02/08/06: Re: Xilinx hiring practises
    45902: 02/08/09: Re: ... milk for free, Opencores?
    45904: 02/08/09: Re: Division
    45917: 02/08/10: Re: unloading a fast ADC
    45927: 02/08/11: Re: unloading a fast ADC
    45932: 02/08/12: Re: articles about FPGA based DSP design
    45956: 02/08/12: Re: Symplify Hacking/munging question...
    45966: 02/08/13: Re: Division
    45967: 02/08/13: Re: Symplify Hacking/munging question...
    45968: 02/08/13: Re: Xilinx IBUFGDS with both inputs grounded ?
    46000: 02/08/13: Re: Symplify Hacking/munging question...
    46002: 02/08/13: Re: Divider in Xilinx System Generator
    46003: 02/08/13: Re: Xilinx XST inferred Block-RAM Initialization
    46004: 02/08/13: Re: unloading a fast ADC
    46019: 02/08/14: Re: routing long line ressources
    46027: 02/08/15: Re: Xilinx tools: which one? Esp. schematic
    46046: 02/08/15: Re: Xilinx tools: which one? Esp. schematic
    46082: 02/08/16: Re: Divider in Xilinx System Generator
    46090: 02/08/17: Re: V2PRO PowerPC floating point
    46106: 02/08/19: Re: V2PRO PowerPC floating point
    46122: 02/08/20: Re: BRAM simulation model error?
    46123: 02/08/20: Re: Xilinx tools: which one? Esp. schematic
    46124: 02/08/20: Re: Polyphase filtering...
    46145: 02/08/20: Re: Xilinx FPGA start-up
    46158: 02/08/20: Re: BRAM simulation model error?
    46164: 02/08/20: Re: How to include Xilinx library for both ModelSim and Synplify?
    46173: 02/08/21: Re: BRAM simulation model error?
    46182: 02/08/21: Re: BRAM simulation model error?
    46206: 02/08/21: Re: Xilinx tools: which one? Esp. schematic
    46207: 02/08/21: Re: Logic Analyzers with an Altera Board
    46208: 02/08/21: Re: How to include Xilinx library for both ModelSim and Synplify?
    46209: 02/08/21: Re: How to include Xilinx library for both ModelSim and Synplify?
    46212: 02/08/21: Re: Is this asynchronous design safe ?
    46220: 02/08/22: Re: How to include Xilinx library for both ModelSim and Synplify?
    46221: 02/08/22: Re: Xilinx tools: which one? Esp. schematic
    46235: 02/08/22: Re: How to include Xilinx library for both ModelSim and Synplify?
    46274: 02/08/23: Re: How to include Xilinx library for both ModelSim and Synplify?
    46297: 02/08/25: Re: upgrade S/W -> timing worse
    46306: 02/08/25: Re: upgrade S/W -> timing worse
    46307: 02/08/25: Re: I2C BUS
    46308: 02/08/25: Re: Floorplanning 101
    46314: 02/08/26: Re: Virtex2 and Virtex-E speed performance
    46330: 02/08/26: Re: writeing a synthesized vhdl code for "shifter "
    46331: 02/08/26: Re: Can I directly connect XTAL to SpartanXL ?
    46350: 02/08/27: Re: need cheap and dirty time delay for spartan2e
    46371: 02/08/27: Re: FPGA speed level
    46389: 02/08/28: Re: Any FSM optimizer?
    46390: 02/08/28: Re: Stratix Experience
    46400: 02/08/28: Re: My SpartanII thinks it's a Virtex??
    46578: 02/09/04: Re: V2 Pipelined Embedded Mulitplier PAR issues
    46624: 02/09/04: Re: Virtex-2 BRAM
    46626: 02/09/04: Re: why the need for HIGH speed design?
    46630: 02/09/04: Re: xilinx contact with regard to qpro
    46641: 02/09/05: Re: Webpack 4.2 Schematic
    46744: 02/09/06: Re: why the need for HIGH speed design?
    46762: 02/09/07: Re: Fault tolerant FPGA design
    46778: 02/09/09: Re: Fault tolerant FPGA design
    46779: 02/09/09: Re: Fault tolerant FPGA design
    47031: 02/09/15: Re: scan insertion is easily feasible
    47041: 02/09/16: Re: 1.8V regulator needed for Spartan IIE
    47042: 02/09/16: Re: why the need for HIGH speed design?
    47044: 02/09/16: Re: Measuring FPGA performance eg max clock speed
    47045: 02/09/16: Re: ieee.math_real for presynthesis table calculation in vhdl
    47073: 02/09/16: Re: 1.8V regulator needed for Spartan IIE
    47074: 02/09/16: Re: ieee.math_real for presynthesis table calculation in vhdl
    47086: 02/09/17: Re: 1.8V regulator needed for Spartan IIE
    47143: 02/09/18: Re: Feasibility of 100 tap adaptive FIR design on FPGA
    47144: 02/09/18: Re: linear-log converter required
    47145: 02/09/18: Re: Multiple divide by 10
    47149: 02/09/19: Re: C\C++ to VHDL Converter
    47186: 02/09/20: Re: Multiple divide by 10
    47187: 02/09/20: Re: Overheat with XCV-600E
    47202: 02/09/20: Re: XCV600 Version and Firmware
    47207: 02/09/20: Re: Multiple divide by 10
    47208: 02/09/20: Re: Multiple divide by 10
    47209: 02/09/20: Re: Feasibility of 100 tap adaptive FIR design on FPGA
    47211: 02/09/20: Re: GCLK pin used like an standard input
    47212: 02/09/20: Re: ieee.math_real for presynthesis table calculation in vhdl
    47245: 02/09/21: RPM zippering redux
    47250: 02/09/21: Re: Can a fpga replace external inverters in a crystal osc ?
    47261: 02/09/21: Re: RPM zippering redux
    47280: 02/09/22: Re: VHDL : Lookup Table
    47281: 02/09/22: Re: Can a fpga replace external inverters in a crystal osc ?
    47282: 02/09/22: Re: Spartan II JTAG reconfiguration bug - workaround
    47303: 02/09/23: Re: Xilinx RAM16x1D, Write fails in functional Simulation
    47328: 02/09/23: Re: writing across a column in an SDRAM
    47398: 02/09/25: Re: Multiple divide by 10
    47419: 02/09/25: Re: Multiple divide by 10
    47426: 02/09/25: Re: FPGA fail when Electrostatic discharge Occurs
    47444: 02/09/25: Re: ESD Undressing Story
    47445: 02/09/25: Re: writing across a column in an SDRAM
    47446: 02/09/25: Re: Virtex2 Block Multiplier: Faster, Faster
    47447: 02/09/25: Re: Virtex2 Block Multiplier: Faster, Faster
    47467: 02/09/26: Re: Dual Port RAM
    47468: 02/09/26: Re: Can a fpga replace external inverters in a crystal osc ?
    47504: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
    47518: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
    47539: 02/09/28: Re: Block Ram maximum speed
    47548: 02/09/28: Re: Block Ram maximum speed
    47605: 02/09/30: Re: FFT in FPGA?
    47606: 02/09/30: Re: design multiplier
    47611: 02/10/01: Re: design multiplier
    47640: 02/10/01: Re: FFT in FPGA?
    47641: 02/10/01: Re: Configuration:Startup
    47665: 02/10/01: Re: question on ISE 5.1 and SMP machines...
    47666: 02/10/01: Re: DFT , Design For Test HELPPPPP
    47671: 02/10/02: Re: Rounting of non-global IO pad to a GCLKIOB site.
    47679: 02/10/02: Re: C\C++ to VHDL Converter
    47722: 02/10/02: Re: Moving average filter
    47723: 02/10/02: Re: C\C++ to VHDL Converter
    47726: 02/10/02: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
    47728: 02/10/02: Re: Help for Altera's FPGAs' pinout
    47745: 02/10/03: Re: C\C++ to VHDL Converter
    47746: 02/10/03: Re: Large Multiplexer
    47750: 02/10/03: Re: Large Multiplexer
    47775: 02/10/03: Re: A MAC design question
    47807: 02/10/04: Re: Low power design
    47808: 02/10/04: Re: Configuration:Startup
    47809: 02/10/04: Re: C\C++ to VHDL Converter
    47833: 02/10/04: Re: TCP/IP in FPGA
    47843: 02/10/05: Re: Low power design
    47878: 02/10/07: Re: Low power design
    47879: 02/10/07: Re: C\C++ to VHDL Converter
    47924: 02/10/07: Re: implementation of adaptive FIR with many input channels?
    47928: 02/10/07: Re: USB2 in FPGA?
    48006: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
    48012: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
    48019: 02/10/09: Re: USB2 in FPGA?
    48032: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48036: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48037: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48053: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48055: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48069: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48070: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48071: 02/10/10: Re: how do initialised signals really get set in Xilinx slices?
    48092: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
    48093: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
    48118: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
    48130: 02/10/11: Re: how do initialised signals really get set in Xilinx slices?
    48135: 02/10/11: Re: Active HDL
    48153: 02/10/12: Re: Why can Xilinx sw be as good as Altera's sw?
    48159: 02/10/12: Re: Why can Xilinx sw be as good as Altera's sw?
    48160: 02/10/12: Re: Sync Reset without clocks
    48169: 02/10/12: Re: Why can Xilinx sw be as good as Altera's sw?
    48173: 02/10/12: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as
    48174: 02/10/12: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as
    48198: 02/10/14: Re: hardmacro problem
    48214: 02/10/14: Re: hardmacro problem
    48215: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
    48240: 02/10/14: Re: Upgrading...
    48242: 02/10/14: Re: comp.arch.fpga : Power consumption Benchmark
    48244: 02/10/14: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as
    48261: 02/10/15: Re: how to generate LUT for DA?
    48263: 02/10/15: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as
    48264: 02/10/15: Re: Why can Xilinx sw be as good as Altera's sw?
    48307: 02/10/15: Re: Xilinx microblaze vs. picoblaze
    48314: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48315: 02/10/16: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as
    48326: 02/10/16: Re: Upgrading...
    48349: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48350: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48372: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48373: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48374: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48375: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48376: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48377: 02/10/16: Re: Why can Xilinx sw be as good as Altera's sw?
    48381: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48386: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48400: 02/10/17: Re: Hobbyist FPGA
    48406: 02/10/17: Re: Xilinx microblaze vs. picoblaze
    48425: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48447: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48448: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48473: 02/10/18: Re: Xilinx microblaze vs. picoblaze
    48490: 02/10/18: Re: log calculation
    48512: 02/10/18: Re: Floorplanner RPM. How to use it?
    48516: 02/10/18: Re: Floorplanner RPM. How to use it?
    48525: 02/10/19: Re: Number of Fpga posts vs dsp..
    48527: 02/10/19: Re: Floorplanner RPM. How to use it?
    48577: 02/10/21: Re: Floorplanner RPM. How to use it?
    48578: 02/10/21: Re: Floorplanner RPM. How to use it?
    48579: 02/10/21: Re: Floorplanner RPM. How to use it?
    48608: 02/10/21: Re: Newbie Questions - Jan Gray XSOC
    48613: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
    48645: 02/10/22: Re: Floorplanner RPM. How to use it?
    48646: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
    48648: 02/10/22: Re: High Performance FPGA's - Xilinx and ??????
    48661: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
    48697: 02/10/23: Re: Newbie Questions - Jan Gray XSOC
    48703: 02/10/23: Re: LCD driver implement with FPGA
    48762: 02/10/24: Re: clock divider
    48770: 02/10/24: Re: FPGA XC4005E
    48791: 02/10/24: Re: Silly Virtex 2 Pro question...
    48808: 02/10/24: Re: Silly Virtex 2 Pro question...
    48813: 02/10/24: Re: Silly Virtex 2 Pro question...
    48816: 02/10/24: Re: Pin locking Virtex 2 FPGA
    48817: 02/10/24: Re: Pin locking Virtex 2 FPGA
    48853: 02/10/25: Re: Pin locking Virtex 2 FPGA
    48854: 02/10/25: Re: Please recommend a FPGA chip!
    48872: 02/10/25: Re: Just some newbie ISE questions...
    48962: 02/10/28: Re: for what do you use fpga's
    48963: 02/10/28: Re: Phased clocks...
    48980: 02/10/28: Re: filters on fpgas
    48981: 02/10/28: Re: Phased clocks...
    49020: 02/10/30: Re: Information--conference paper
    49052: 02/10/30: Re: GlobalReset hogging routing resources
    49092: 02/10/31: Re: BLOCK RAM : FIFO implementation
    49133: 02/11/01: Re: FDRE inference in Synplify
    49203: 02/11/05: Re: C\C++ to VHDL Converter
    49222: 02/11/05: Re: C\C++ to VHDL Converter
    49398: 02/11/11: Re: new to fpga, what language is better to start with
    49415: 02/11/12: Re: HDL vs RTL
    49477: 02/11/13: Re: Feedback from a 200 MHz Virtex2 design
    49478: 02/11/13: Re: HDL vs RTL
    49479: 02/11/13: Re: multi-channel filters - how many channels?
    49487: 02/11/13: Re: Registering inputs or outputs of modules
    49512: 02/11/14: Re: How much to build this? xvga to ntsc uhf broadcaster
    49513: 02/11/14: Re: Anyone has VHDL code for decimator and interpolater?
    49515: 02/11/14: Re: C\C++ to VHDL Converter
    49516: 02/11/14: Re: multi-channel filters - how many channels?
    49517: 02/11/14: Re: LUT Consumption in Virtex-2
    49518: 02/11/14: Re: Registering inputs or outputs of modules
    49523: 02/11/14: Re: LU-decomposition
    49524: 02/11/14: Re: Feedback from a 200 MHz Virtex2 design
    49525: 02/11/14: Re: Question about algorithm implementing in FPGA
    49553: 02/11/14: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
    49593: 02/11/16: Re: Global clock routing
    49628: 02/11/18: Re: Metastability in FPGAs
    49629: 02/11/18: Re: Anyone has VHDL code for decimator and interpolater?
    49672: 02/11/19: Re: Metastability in FPGAs
    49674: 02/11/19: Re: clock difference between DLL input and output?
    49695: 02/11/19: Re: Metastability in FPGAs
    49709: 02/11/19: Re: Metastability in FPGAs
    49710: 02/11/19: Re: FPGA to implement Bluetooth baseband
    49711: 02/11/19: Re: how to use carry chain in Virtexe
    49715: 02/11/19: Re: C\C++ to VHDL Converter
    49716: 02/11/19: Re: C\C++ to VHDL Converter
    49727: 02/11/20: Re: how to use carry chain in Virtexe
    49762: 02/11/20: Re: Webpack and Virtex Pro?
    49773: 02/11/21: Re: Global clock routing
    49781: 02/11/21: Re: C\C++ to VHDL Converter
    49782: 02/11/21: Re: programmable oscillator for Virtex-E (XCV2000E)
    49783: 02/11/21: Re: XCS-05-3PC84 and XCS10-3PC84 Question
    49784: 02/11/21: Re: how to use carry chain in Virtexe
    49796: 02/11/21: Re: Global clock routing
    49814: 02/11/21: Re: Global clock routing
    49816: 02/11/21: Re: C\C++ to VHDL Converter
    49835: 02/11/22: Re: Metastability in FPGAs
    49843: 02/11/22: Re: Global clock routing
    49850: 02/11/22: Re: XCS-05-3PC84 and XCS10-3PC84 Question
    49851: 02/11/22: Re: LUT Consumption in Virtex-2
    49852: 02/11/22: Re: how to use carry chain in Virtexe
    49856: 02/11/22: Re: hardware image processing - log computation
    49864: 02/11/22: Re: Conversion functions
    49877: 02/11/23: Re: C\C++ to VHDL Converter
    49921: 02/11/25: Re: XCS-05-3PC84 and XCS10-3PC84 Question
    49958: 02/11/26: Re: Fast Digital Synthesis Generator
    49998: 02/11/27: Re: count based Frequency generator
    49999: 02/11/27: Re: question about PCB traces for FPGA board... ?
    50000: 02/11/27: Re: question about PCB traces for FPGA board... ?
    50069: 02/11/30: Re: Spartan-II 2S200 PCI Board
    50074: 02/11/30: Re: Asynchronous FIFOs using Handel-C?
    50086: 02/12/01: Re: ModelSim XE vcom 5.6a #ERROR: cannot read output
    50087: 02/12/01: Re: question about programmable oscillator ?
    50188: 02/12/04: Re: clock difference between DLL input and output?
    50209: 02/12/05: Re: clock difference between DLL input and output?
    50224: 02/12/05: Re: clock difference between DLL input and output?
    50235: 02/12/06: Re: meaning of system gates vs. logic gates?
    50269: 02/12/07: Re: Clocking in a Spartan IIE
    50271: 02/12/07: Re: Clocking in a Spartan IIE
    50295: 02/12/08: Re: memory in VHDL
    50308: 02/12/08: Re: Virtex archtecture question
    50323: 02/12/09: Re: Pierce Crystal Oscillator in Cypress 37128 CPLD
    50349: 02/12/09: Re: clock recovery suggestions
    50367: 02/12/10: Re: How to assign pins in VHDL?
    50374: 02/12/10: Re: How to assign pins in VHDL?
    50375: 02/12/10: Re: How to assign pins in VHDL?
    50377: 02/12/10: Re: FPGA/PCI on low budget
    50406: 02/12/10: Re: Clocking in a Spartan IIE
    50408: 02/12/10: Re: How to assign pins in VHDL?
    50409: 02/12/10: Re: FPGA/PCI on low budget
    50410: 02/12/10: Re: Xilinx ISE 5.1 Wait for statement unsupported??
    50433: 02/12/10: Re: Clocking in a Spartan IIE
    50438: 02/12/10: Re: ISA bus VGA
    50439: 02/12/10: Re: Xilinx ISE 5.1 Wait for statement unsupported??
    50440: 02/12/10: Re: FPGA/PCI on low budget
    50456: 02/12/11: Re: hardware image processing - log computation
    50473: 02/12/11: Re: hardware image processing - log computation
    50491: 02/12/11: Re: hardware image processing - log computation
    50504: 02/12/11: Re: FPGA/PCI on low budget
    50527: 02/12/12: Re: FPGA startup events
    50556: 02/12/12: Re: what makes an implementation a patent?
    50625: 02/12/14: Re: SpartanII Internal Clock ?
    50703: 02/12/18: Re: How to asynchronously reset a flip-flop?
    50704: 02/12/18: Re: Video timing generator on a Flex 20K / Acex 1K.
    50726: 02/12/18: Re: FPGA instead of HDMP-1022/24
    50745: 02/12/18: Re: Display "real" waves in simulation?
    50754: 02/12/18: Re: How to asynchronously reset a flip-flop?
    50756: 02/12/18: Re: Matrics Memory controller
    50764: 02/12/19: Re: Display "real" waves in simulation?
    50765: 02/12/19: Re: hardware image processing - log computation
    50781: 02/12/19: Re: Is there any generic BIST architectures for Xilinx FPGAs for
    50782: 02/12/19: Re: 16-bit LFSR
    50794: 02/12/19: Re: Multi cycle Paths..
    50808: 02/12/20: Re: Hi xilinx
    50832: 02/12/20: Re: stupid rookie timing question
    50847: 02/12/20: Re: FPGA Supercomputing opportunity
    50848: 02/12/20: Re: How to handle Fautly Interconnection in Virtex ?
    50849: 02/12/20: Re: Hi xilinx
    50850: 02/12/20: Re: Async RAM on an FPGA board
    50855: 02/12/20: Re: FPGA Supercomputing opportunity
    50876: 02/12/21: Re: FPGA Supercomputing opportunity
    50885: 02/12/21: Re: stupid rookie timing question
    50886: 02/12/21: Re: Async RAM on an FPGA board
    50888: 02/12/21: Re: stupid rookie timing question
    50920: 02/12/23: Re: serdes
    51218: 03/01/07: Re: Constraining a purely combinatorial logic path
    51290: 03/01/10: Re: Xilinx 5.1i Map question
    51391: 03/01/12: Re: SChematic design approach compared to VHDL entry approach
    51433: 03/01/13: Re: Simulate Virtex Primitive using ModelSim
    51453: 03/01/14: Re: Simulate Virtex Primitive using ModelSim
    51474: 03/01/14: Re: Virtex, Virtex II and Virtex II Pro
    51503: 03/01/15: Re: Open FPGA please!
    51524: 03/01/15: Re: Open FPGA please!
    51525: 03/01/15: Re: Short FIFO in Verilog / Spartan IIE
    51532: 03/01/15: Re: Open FPGA please!
    51533: 03/01/15: Re: Short FIFO in Verilog / Spartan IIE
    51553: 03/01/16: Re: Schematic design approach compared to VHDL entry approach
    51562: 03/01/16: Re: 200K gates FPGA for GPU
    51593: 03/01/17: Re: Schematic design approach compared to VHDL entry approach
    51598: 03/01/17: Re: Xilinx Constraint Problem
    51610: 03/01/17: Re: Schematic design approach compared to VHDL entry approach
    51634: 03/01/17: Re: quality of software tools in general
    51656: 03/01/18: Re: quality of software tools in general
    51658: 03/01/18: Re: Schematic design approach compared to VHDL entry approach
    51679: 03/01/19: Re: quality of software tools in general
    51680: 03/01/19: Re: quality of software tools in general
    51699: 03/01/20: Re: Schematic design approach compared to VHDL entry approach
    51735: 03/01/20: Re: frequency matching of ring oscillators
    51741: 03/01/21: Re: XST vs Synplify observations
    51743: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
    51764: 03/01/21: Re: Virtex II embedded multipliers
    51765: 03/01/21: Re: Tristate vs. MUX
    51782: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
    51804: 03/01/22: Re: VHDL or Verilog?
    51805: 03/01/22: Re: quality of software tools in general
    51820: 03/01/22: Re: Virtex II: noise on Vcco causing loss of DCM lock
    51898: 03/01/24: Re: What's the difference between LUT and RAM?
    51911: 03/01/25: Re: Why so many pins?
    51912: 03/01/25: Re: What's the difference between LUT and RAM?
    51952: 03/01/27: Re: Extending a Virtex-II block RAM?
    51960: 03/01/27: Re: Carry Logic propagation delay
    51961: 03/01/27: Re: What's the difference between LUT and RAM?
    51972: 03/01/28: Re: Carry Logic propagation delay
    51973: 03/01/28: Re: VHDL or Verilog?
    51986: 03/01/28: Re: 1024bit Adder
    51990: 03/01/28: Re: Installing 2 versions of Xilinx software in the same machine
    52001: 03/01/28: Re: What's the difference between LUT and RAM?
    52013: 03/01/28: Re: Random number generator
    52044: 03/01/29: Re: Xilinx memory size
    52110: 03/01/31: Re: Random number generator (OT)
    52111: 03/01/31: Re: STATE PROBLEM!
    52140: 03/02/03: Re: SChematic design approach compared to VHDL entry approach
    52153: 03/02/03: Re: Xilinx SwitchBox Structure
    52154: 03/02/03: Re: one hot encoding
    52163: 03/02/03: Re: Modules in a large design
    52164: 03/02/03: Re: which microprocessor core?
    52209: 03/02/04: Re: Modules in a large design
    52219: 03/02/04: Re: xilinx virtex II floorplanning
    52220: 03/02/04: Re: component instantiation in Xilinx
    52227: 03/02/04: Re: Clock Enables
    52229: 03/02/05: Re: low pass FIR filter in FPGA
    52230: 03/02/05: Re: xilinx virtex II floorplanning
    52258: 03/02/05: Re: DSP design in fpga - general guidelines please.
    52277: 03/02/05: Re: Switching synthesis tools
    52302: 03/02/06: Re: Help needed
    52309: 03/02/06: Re: Help needed
    52317: 03/02/06: Re: Help needed
    52319: 03/02/06: Re: Clock Enables
    52367: 03/02/07: Re: Partial Reconfiguration - Virtex-E
    52368: 03/02/07: Re: Carry Save Adder
    52397: 03/02/08: Re: FFT Size and speed
    52398: 03/02/08: Re: FFT Size and speed
    52399: 03/02/08: Re: Xilinx ISE 4.2i killing Windows 2000?
    52400: 03/02/08: Re: Annapolis Microsystems Wildcard
    52437: 03/02/10: Re: Xilinx ISE 4.2i killing Windows 2000?
    52469: 03/02/11: Re: Fast BlockRAM updates
    52494: 03/02/11: Re: JBits
    52515: 03/02/12: Re: Fast BlockRAM updates
    52516: 03/02/12: Re: Fast BlockRAM updates
    52517: 03/02/12: Re: Newbie Starting Places + Books?
    52525: 03/02/12: Re: Distributed RAM/ROM
    52528: 03/02/12: Re: difficulty in designing butterfly processor
    52545: 03/02/13: Re: Newbie Starting Places + Books?
    52551: 03/02/13: Re: Causing Modelsim to break using VHDL code
    52747: 03/02/20: Re: Generating a sin wave with vhdl
    52748: 03/02/20: Re: Xilinx Filter
    52786: 03/02/21: Re: Generating a sin wave with vhdl
    53049: 03/03/01: Atmel and Hotworks boards for sale
    53051: 03/03/01: Re: Atmel and Hotworks boards for sale
    53081: 03/03/03: Re: FPGA demo board schematic
    53100: 03/03/04: Re: VHDL & FPGA Design tools
    53102: 03/03/04: Re: Connect USB device to Spartan 2e FPGA
    53166: 03/03/05: Re: VHDL & FPGA Design tools
    53204: 03/03/06: Re: filter coefficients from sig. proc. toolbox to xilinx
    53205: 03/03/06: Re: Partial reconfiguration
    53218: 03/03/06: Re: Annapolis Microsystems Wildcard
    53220: 03/03/07: VCC XC6216 Hotworks board for sale
    53292: 03/03/10: Re: Multipliers Architectures use on FPGA COREGEN
    53293: 03/03/10: Re: Motion Control IP Cores , anyone do them ?
    53304: 03/03/10: Re: Minimum Real-state K-multiplier/divider
    53313: 03/03/10: Re: Altera Clock
    53315: 03/03/10: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
    53325: 03/03/11: Re: Are there any FPGA magazines/journals?
    53359: 03/03/11: Re: Can you recommend a text on...?
    53434: 03/03/13: Re: The structure of the multiplier
    53435: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
    53459: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
    53477: 03/03/14: Re: Path delay and timer question
    53479: 03/03/14: Re: Using divided clock
    53482: 03/03/14: Re: Adding delay to a signal?
    53500: 03/03/14: Re: ROM containing complex numbers
    53501: 03/03/14: Re: Adding delay to a signal?
    53502: 03/03/14: Re: Adding delay to a signal?
    53548: 03/03/16: Re: Adding delay to a signal?
    53584: 03/03/17: Re: Help understanding 7408 and gate chip
    53616: 03/03/18: Re: more footprints...
    53633: 03/03/18: Re: Modelsim - FPGA - Simulink integration
    53659: 03/03/19: Re: IFDs in Xilinx Foundation 4.1i
    53678: 03/03/19: Re: Using FPGAs as coprocessors in a PC
    53679: 03/03/19: Re: Bit patching of Xilinx VIRTEX-II devicex?
    53754: 03/03/21: Re: FPGA FFT Questions
    53762: 03/03/21: Re: source code for crc
    53769: 03/03/22: Re: FPGA FFT Questions
    53779: 03/03/22: Re: how do implement the algorithm in verilog?
    53780: 03/03/22: Re: FPGA FFT Questions
    53840: 03/03/25: Re: Permanent Local Damage to FPGA
    53868: 03/03/26: Re: Permanent Local Damage to FPGA
    53869: 03/03/26: Re: xst removes useful signals
    53954: 03/03/28: Re: CLKDLL synthesized with synplify pro
    53976: 03/03/29: Re: Spartan vs. Cyclone for arithmetic functions
    54057: 03/04/01: Re: Spartan vs. Cyclone for arithmetic functions
    54091: 03/04/02: Re: Matrix multiply in FPGA
    54092: 03/04/02: Re: FFT 256pt on Spartan
    54115: 03/04/02: Re: Matrix multiply in FPGA
    54166: 03/04/03: Re: What is DA and SLR16?
    54167: 03/04/03: Re: What is DA and SLR16?
    54204: 03/04/04: Re: FFT 256pt on Spartan
    54213: 03/04/04: Re: What is DA and SLR16?
    54269: 03/04/06: Re: Should I bother with Xilinx Foundation 1.5 vs 2.1?
    54535: 03/04/13: Re: An Improvement for the Booth multiplier
    54595: 03/04/14: Re: An Improvement for the Booth multiplier
    54604: 03/04/14: Re: Xilinx has released SpartanIII
    54619: 03/04/15: Re: request for simple UART
    54620: 03/04/15: Re: fpga fault tolerence.
    54621: 03/04/15: Re: Clock Doubled domain
    54647: 03/04/15: Re: Xilinx core generator: core speed?
    54648: 03/04/15: Re: request for simple UART
    54676: 03/04/15: Re: request for simple UART
    54677: 03/04/15: Re: Xilinx core generator: core speed?
    54678: 03/04/15: Re: fpga fault tolerence.
    54709: 03/04/16: Re: Xilinx has released SpartanIII
    54710: 03/04/16: Re: Basic components with Core generator?
    54711: 03/04/16: Re: Hardware acceleration for raytracing purposes
    54892: 03/04/21: Re: Clock Doubled domain
    54903: 03/04/22: Re: spartan2e vs cyclone
    54909: 03/04/22: Re: Boycott All Xilinx products untill they correct all ISE
    54910: 03/04/22: Re: Complex FIR in FPGA
    54940: 03/04/22: Re: Boycott All Xilinx products untill they correct all ISE software
    54969: 03/04/23: Re: Problem : Simulating SRL16 with webpack 5.2 and modelsim 5.6e
    54985: 03/04/23: Re: Problem : Simulating SRL16 with webpack 5.2 and modelsim 5.6estarter
    54986: 03/04/23: Re: Challenge: (n mod 3) in hardware???
    55036: 03/04/25: Re: Large adder placement / synthesis
    55073: 03/04/25: Re: Large adder placement / synthesis
    55074: 03/04/25: Re: Large adder placement / synthesis
    55076: 03/04/25: Re: Dynamic Reconfigurable FPGAs
    55090: 03/04/26: Re: Advice on FPGA IIR Filter
    55091: 03/04/26: Re: Dynamic Reconfigurable FPGAs
    55176: 03/04/29: Re: Xilinx XAct
    55177: 03/04/29: Re: DSP/FPGA board
    55180: 03/04/29: Re: RF transmitters/receivers with Xilinx Xtreme DSP Kit
    55243: 03/05/01: Re: Boycott All Xilinx products untill they correct all ISE software
    55246: 03/05/01: Re: DSP/FPGA board
    55247: 03/05/01: Re: Schmitt Trigger an a Virtex
    55277: 03/05/02: Re: I want a 800 k gates FPGA in 40 pin DIL
    55278: 03/05/02: Re: Boycott All Xilinx products untill they correct all ISE software
    55290: 03/05/02: Re: Boycott All Xilinx products untill they correct all ISE software
    55298: 03/05/02: Re: I want a 800 k gates FPGA in 40 pin DIL
    55299: 03/05/02: Re: Thermal Data for Logic Devices
    55353: 03/05/05: Re: Thermal Data for Logic Devices
    55395: 03/05/06: Re: xilinx area measure?
    55400: 03/05/06: Re: Thermal Data for Logic Devices
    55403: 03/05/06: Re: I want a 800 k gates FPGA in 40 pin DIL
    55404: 03/05/06: Re: I want a 800 k gates FPGA in 40 pin DIL
    55420: 03/05/07: Re: I want a 800 k gates FPGA in 40 pin DIL
    55421: 03/05/07: Re: OT: looking for I/Q mixers/modulators for TX and RX
    55433: 03/05/08: Re: I want a 800 k gates FPGA in 40 pin DIL
    55456: 03/05/08: Re: I want a 800 k gates FPGA in 40 pin DIL
    55458: 03/05/09: Re: accurate power measurements
    55541: 03/05/12: Re: Register in FPGA
    55543: 03/05/12: Re: where to buy 1 virtex-e fg680
    55560: 03/05/12: Re: OK I am pissed off with Xilinx webpack.
    55566: 03/05/12: Re: How do I know of Xilinx connectivity restrictions?
    55617: 03/05/14: Re: OK I am pissed off with Xilinx webpack.
    55618: 03/05/14: Re: how to calculate the gate count required for a FPGA design
    55624: 03/05/14: Re: "Primitives" in XST?
    55641: 03/05/14: Re: how to calculate the gate count required for a FPGA design
    55663: 03/05/15: Re: how to calculate the gate count required for a FPGA design
    55665: 03/05/15: Re: how to calculate the gate count required for a FPGA design
    55702: 03/05/16: Re: VitalGlitch
    55789: 03/05/20: Re: a (PC) workstation for FPGA development
    55803: 03/05/20: Re: a (PC) workstation for FPGA development
    55804: 03/05/20: Re: what are DCMs in FPGA
    55820: 03/05/20: Re: a (PC) workstation for FPGA development
    55830: 03/05/21: Re: a (PC) workstation for FPGA development
    55845: 03/05/21: Re: a (PC) workstation for FPGA development
    55853: 03/05/21: Re: FPGA design: firmware or hardware?
    55871: 03/05/22: Re: FPGA design: firmware or hardware?
    55885: 03/05/22: Re: a (PC) workstation for FPGA development
    55897: 03/05/23: Re: a (PC) workstation for FPGA development
    55898: 03/05/23: Re: FPGA design: firmware or hardware?
    55916: 03/05/23: Re: FPGA design: firmware or hardware?
    55920: 03/05/23: Re: FPGA design: firmware or hardware?
    55992: 03/05/26: Re: fir distributed arithmetic
    56081: 03/05/28: Re: FIFO Controller
    56217: 03/05/31: Re: FIFO Controller
    56218: 03/05/31: Re: FIFO Controller
    56255: 03/06/01: Re: power consumption in CMOS..
    56258: 03/06/01: Re: Need help with Xilinx ISE
    56276: 03/06/02: Re: Need help with Xilinx ISE
    56300: 03/06/02: Re: Xilinx : BEL constraint vs. ModelSim
    56450: 03/06/05: Re: Multipliers - Ram ratio
    56462: 03/06/05: Re: Multipliers - Ram ratio
    56832: 03/06/16: Re: spartan 2e dll locking
    56920: 03/06/18: Re: Controlling FPGA speed with VCCINT
    57222: 03/06/25: Re: Interfacing IDE
    57223: 03/06/25: Re: Multirate system in fpga
    57864: 03/07/08: Re: scaling fixed point fft
    57961: 03/07/10: Re: cascaded DLL's in VirtexE, routing problems
    58008: 03/07/11: Re: DDS theory of operation
    58009: 03/07/11: Re: Seminar: Digital Signal Processing, Programmable Device
    58010: 03/07/11: Re: Fixed point signed multiplication algorithm
    58085: 03/07/14: Re: Combinational logic and gate delays - Help
    58086: 03/07/14: Re: An All Digital Phase Lock Loop
    58096: 03/07/14: Re: An All Digital Phase Lock Loop
    58173: 03/07/16: Re: An All Digital Phase Lock Loop
    58187: 03/07/16: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
    58189: 03/07/16: Re: Xilinx --> WARNING:DesignRules:372
    58190: 03/07/16: Re: Cyclone vs Spartan-3
    58191: 03/07/16: Re: device selection for game system
    58248: 03/07/17: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
    58249: 03/07/17: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
    58282: 03/07/18: Re: How fast coregen FIR?
    58285: 03/07/18: Re: An All Digital Phase Lock Loop
    58369: 03/07/21: Re: device selection for game system
    58409: 03/07/22: Re: FPGA Editor
    58410: 03/07/22: Re: FPGA Editor
    58411: 03/07/22: Re: asynchronous FIFO
    58446: 03/07/23: Re: FPGA Editor
    58453: 03/07/23: Re: Use ICAp iwth a soft IP core to decompress!!!!
    58504: 03/07/24: Re: FPGA Editor
    58505: 03/07/24: Re: FPGA Editor
    58506: 03/07/24: Re: FPGA Editor
    58633: 03/07/29: Re: how to design hardware for 2's complement parallel multiplier(at
    58750: 03/07/31: Re: Question: String matching with CAM?
    59413: 03/08/18: Re: custom memory array implementaion
    59416: 03/08/18: Re: Old Xilinx FPGAs
    59517: 03/08/20: Re: Xilinx FPGA pin locking/assignment
    59588: 03/08/22: Re: DA FIR filter vs. MAC FIR filter
    59589: 03/08/22: Re: ise 5.2 timing summary
    59590: 03/08/22: Re: Async logic in FPGAs
    59662: 03/08/25: Re: Thinking out loud about metastability
    59665: 03/08/25: Re: Which Adder?
    59675: 03/08/25: Re: Enhancing PAR with FPGA floorplanners
    59676: 03/08/25: Re: Thinking out loud about metastability
    59677: 03/08/25: Re: TIG Constraint
    59678: 03/08/25: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
    59679: 03/08/25: Re: two questions
    59770: 03/08/28: Re: How to listen to music through an FPGA pin?
    59781: 03/08/28: Re: Thinking out loud about metastability
    59797: 03/08/28: Re: Moving Sum
    59801: 03/08/28: Re: How to listen to music through an FPGA pin?
    59963: 03/09/02: Re: Compact FIR filters with multiplier blocks?
    59969: 03/09/02: Re: HDL Designer from Mentor
    59972: 03/09/02: Re: FPGA/DSP Expert - business partner for innovative FFT
    59976: 03/09/03: Re: Thinking out loud about metastability
    59997: 03/09/03: Re: Compact FIR filters with multiplier blocks?
    60028: 03/09/03: Re: Thinking out loud about metastability
    60069: 03/09/04: Re: Moving Sum
    60075: 03/09/04: Re: New to FPGA, seeking advice
    60128: 03/09/05: Re: New to FPGA, seeking advice
    60129: 03/09/05: Re: Moving Sum
    60175: 03/09/06: Re: Schematic simulation and then FPGA programming?
    60513: 03/09/15: Re: FPGA start?
    60514: 03/09/15: Re: fft size in fpga
    60517: 03/09/15: Re: DDC design
    60518: 03/09/15: Re: Original (5V) Xilinx Spartan ?
    60625: 03/09/17: Re: Xilinx
    60631: 03/09/17: Re: Xilinx
    60654: 03/09/18: Re: Using LUTs for array of coefficients
    60655: 03/09/18: Re: divide by on spartan3?
    60702: 03/09/19: Re: Xilinx
    60704: 03/09/19: Re: Xilinx
    60706: 03/09/19: Re: Crystal Input to FPGA
    60708: 03/09/19: Re: AWGN in VHDL
    60718: 03/09/19: Re: Some question about using FPGA
    60719: 03/09/19: Re: hardware image processing - log computation
    60720: 03/09/19: Re: pipelined divider
    60721: 03/09/19: Re: Transistor count
    60722: 03/09/19: Re: fft size in fpga
    60733: 03/09/20: Re: divide by on spartan3?
    61158: 03/09/29: Re: OT: spam poll
    61159: 03/09/29: Re: OT: spam poll
    61164: 03/09/29: Re: Embedded/Microcontroller FPGA and Software Defined Radio
    61165: 03/09/29: Re: pipelined divider
    61323: 03/10/01: Re: Xilinx
    61324: 03/10/01: Re: Xilinx
    61325: 03/10/01: Re: Xilinx
    61326: 03/10/01: Re: Using LUTs for array of coefficients
    61335: 03/10/01: Re: Good VHDL/Verilog editor?
    61336: 03/10/01: Re: Counting ones
    61564: 03/10/06: Re: RLOC specification
    61581: 03/10/07: Re: Interesting article about FPGAs
    61595: 03/10/07: Re: More RPM / RLOC fun
    61596: 03/10/07: Re: ise 5.2 sp 3 for spartan 3
    61597: 03/10/07: Re: BF957C Application
    61598: 03/10/07: Re: Xilinx courses
    61599: 03/10/07: Re: Xilinx courses
    61605: 03/10/07: Re: More RPM / RLOC fun
    61606: 03/10/07: Re: Should I worry about metastability
    61607: 03/10/07: Re: Should I worry about metastability
    61608: 03/10/07: Re: Should I worry about metastability
    61609: 03/10/07: Re: Timing from 1x to 2x and back
    61621: 03/10/07: Re: More RPM / RLOC fun
    61623: 03/10/07: Re: Xilinx DCMs, DDR, CLK0, and CLK180
    61628: 03/10/08: Re: Digesting runs of ones or zeros "well"
    61629: 03/10/08: Re: Digesting runs of ones or zeros "well"
    61630: 03/10/08: Re: Digesting runs of ones or zeros "well"
    61657: 03/10/08: Re: Instantiating LUTs and INIT strings [was Re: Digesting runs of ones
    61682: 03/10/08: Re: Digesting runs of ones or zeros "well"
    61683: 03/10/08: Re: Should I worry about metastability
    61684: 03/10/08: Re: More RPM / RLOC fun
    61691: 03/10/09: Re: Visualizing VHDL
    61692: 03/10/09: Re: Floorplanning, Routing, FPGA Editor
    61706: 03/10/09: Re: More RPM / RLOC fun
    61733: 03/10/09: Re: Floorplanning, Routing, FPGA Editor
    61734: 03/10/09: Re: Xilinx dedicated multiers vs multipliers in slice fabric
    61735: 03/10/09: Re: Where is the logic?
    61741: 03/10/09: Re: Where is the logic?
    61742: 03/10/09: Re: Where is the logic?
    61754: 03/10/10: Re: Digesting runs of ones or zeros "well"
    61756: 03/10/10: Re: Inferring an accumulator using Verilog on Xilinx Spartan 2e
    61768: 03/10/10: Re: Floorplanning, Routing, FPGA Editor
    61791: 03/10/10: Re: Digesting runs of ones or zeros "well"
    61913: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61915: 03/10/15: Re: How to program an XC5210
    61929: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61954: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61955: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61982: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61983: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    62005: 03/10/16: Re: Ph.inisheD.
    62027: 03/10/16: Re: Electronic Dice ( 3 die ) In VHDL
    62112: 03/10/19: Re: ISE5.2 to ISE6.1
    62135: 03/10/20: Re: Xilinx Slice and Altera ...?
    62137: 03/10/20: Re: Should I worry about metastability
    63525: 03/11/24: Re: any FPGA design for video frame memory control?
    63957: 03/12/10: Re: Skew between the output of a DCM ?
    63958: 03/12/10: Re: 400 Mb/s ADC
    63960: 03/12/10: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
    64006: 03/12/11: Re: Skew between the output of a DCM ?
    64170: 03/12/18: Re: FIR Filter cores for Virtex-][
    64194: 03/12/19: Re: FIR Filter cores for Virtex-][
    64250: 03/12/22: Re: FIR Filter cores for Virtex-][
    64253: 03/12/22: Re: WHAT APPLICATION WE CAN IMPLEMENT ON VERTEX II PRO
    64254: 03/12/22: Re: Spartan3 availability
    64279: 03/12/23: Re: Spartan3 availability
    64286: 03/12/24: Re: Spartan3 availability
    64307: 03/12/26: Re: Spartan3 availability
    64349: 03/12/29: Re: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
    64482: 04/01/05: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
    64536: 04/01/07: Re: Is the P&R processing time proportional to the FPGA gate count or
    64537: 04/01/07: Re: Questions about guard bits in CORDIC algorithm
    64573: 04/01/07: Re: Virtex and Spartan
    64806: 04/01/14: Re: Synthesis in VHDL vs. Verilog
    64967: 04/01/16: Re: Why won't Xilinx document their code??
    64968: 04/01/16: Re: Port mapping a Verilog component in a VHDL design
    64990: 04/01/18: Re: How to generate a CSA tree?
    64991: 04/01/18: Re: How to generate a CSA tree?
    65061: 04/01/19: Re: par problems with modular design for partial reconfiguration
    65077: 04/01/19: Re: par problems with modular design for partial reconfiguration
    65121: 04/01/20: Re: SDRAM Controller timing problem
    65176: 04/01/21: Re: OT: liability insurance
    65178: 04/01/21: Re: Hardware to test (FPGA-based) prototype?
    65189: 04/01/21: Re: OT: liability insurance
    65190: 04/01/21: Re: WTD: info on AMD palce22v10
    65232: 04/01/22: Re: OT: liability insurance
    65233: 04/01/22: Re: WTD: info on AMD palce22v10
    65254: 04/01/22: Re: OT: liability insurance
    65299: 04/01/23: Re: Synthesizing pipelined multipliers in Synplify Pro
    65300: 04/01/23: Re: is this a good idea
    65305: 04/01/23: Re: Xilinx LVDS_25_DT termination issues????
    65306: 04/01/23: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
    65310: 04/01/23: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
    65329: 04/01/24: Re: xilinx 70% tracking rule
    65362: 04/01/26: Re: How to do with guard bits practically?
    65371: 04/01/26: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
    65372: 04/01/26: Re: Tristate buffer
    65373: 04/01/26: Re: How to do with guard bits practically?
    65375: 04/01/26: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
    65379: 04/01/26: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
    65448: 04/01/29: Re: building macros for Virtex-II with FPGA editor...
    65466: 04/01/29: Re: Is FPGA fully static?
    65468: 04/01/29: Re: Where to get FPGA devices for testing?
    65496: 04/01/30: Re: Good/Affordable Stater kits
    65576: 04/02/02: Re: Is it possible that a Virtex II device performs below its spec?
    65577: 04/02/02: Re: Where to get FPGA devices for testing?
    65601: 04/02/03: Re: using IIR in DDC
    65624: 04/02/03: Re: Xilinx Spartan3 Timing Problems - Whats about the chips
    65634: 04/02/03: Re: Is it possible that a Virtex II device performs below its spec?
    65638: 04/02/03: Re: Stratix II NIOS sizes ?
    65721: 04/02/05: Re: The fastest interface between FPGA's
    65723: 04/02/05: Re: Fast Fourier Transform
    65745: 04/02/05: Re: A small clock synchronization challenge with Virtex E
    66038: 04/02/11: Re: Pricing, 101
    66040: 04/02/11: Re: attribute +generate statement
    66059: 04/02/12: Re: Sine Wave Generation
    66088: 04/02/12: Re: Sine Wave Generation
    66113: 04/02/12: Re: is this enable structure ok for synthesis/high speed?
    66185: 04/02/13: Re: Pricing, 101
    66188: 04/02/13: Re: Sensible starter FPGA board
    66220: 04/02/15: Re: DCM Jitter?
    66365: 04/02/18: Re: GSR in Spartan3 ?
    66400: 04/02/18: Re: Can FPGA bootstrap itself?
    66401: 04/02/18: Re: regarding synchronization
    66402: 04/02/18: Re: GSR in Spartan3 ?
    66473: 04/02/19: Re: Dual-stack (Forth) processors
    66505: 04/02/20: Re: GZIP algorithm in FPGA
    66506: 04/02/20: Re: altera, xilinx susceptible to power transients?
    66507: 04/02/20: Re: Array Divider
    66513: 04/02/20: Re: multiple clocking in FPGA
    66580: 04/02/23: Re: altera, xilinx susceptible to power transients?
    66589: 04/02/23: Re: Spartan 3 - avaliable in small quantities?
    66601: 04/02/23: Re: Spartan 3 - avaliable in small quantities?
    66699: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
    66794: 04/02/26: Re: altera, xilinx susceptible to power transients?
    66814: 04/02/26: Re: Suggestions: Eval/Demo Board.
    66817: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
    66818: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
    66891: 04/02/28: Re: Polyphase filter
    66910: 04/02/29: Re: difference btw H/W & S/W implementations !!
    67002: 04/03/03: Re: Design never finish routing?
    67033: 04/03/03: Re: XST ff merging - how do I "preserve" flip flops
    67073: 04/03/04: Re: Global reset question?
    67079: 04/03/04: Re: Global reset question?
    67106: 04/03/05: Re: Global reset question?
    67199: 04/03/08: Re: Can anyone advise me on how to reduce the compilation time for our
    67215: 04/03/08: Re: Release asynchrounous resets synchronously
    67262: 04/03/09: Re: HOW to Increase jitter in ALTERA PLL ?
    67263: 04/03/09: Re: sorting need help as soon as possible
    67266: 04/03/09: Re: Release asynchrounous resets synchronously
    67278: 04/03/09: Re: sorting need help as soon as possible
    67281: 04/03/09: Re: Release asynchrounous resets synchronously
    67302: 04/03/09: Re: Release asynchrounous resets synchronously
    67434: 04/03/11: Re: what exactly means fanout ?
    67437: 04/03/11: Re: CORDIC vs. LUT
    67438: 04/03/11: Re: Release asynchrounous resets synchronously
    67447: 04/03/11: Re: Answering Machine RAM
    67660: 04/03/16: Re: Answering Machine RAM
    67695: 04/03/17: Re: newbie question about fpga internals
    67696: 04/03/17: Re: Schematic Edition Tool : Suggestions
    67707: 04/03/17: Re: newbie question about fpga internals
    67708: 04/03/17: Re: Answering Machine RAM
    67803: 04/03/19: Re: Xilinx ISE 6.2 and Virtex-II
    67948: 04/03/23: Re: How many times can I burn an FPGA?
    67962: 04/03/23: Re: How many times can I burn an FPGA?
    67974: 04/03/23: Re: Bus width between registers in IIR
    68000: 04/03/24: Re: Bus width between registers in IIR
    68051: 04/03/25: Re: Bus width between registers in IIR
    68111: 04/03/26: Re: Generating Xilinx cores.
    68118: 04/03/26: Re: Spartan RAMB4 Timing
    68126: 04/03/26: Re: Spartan RAMB4 Timing
    68227: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
    68233: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
    68248: 04/03/31: Re: Real-time Image Process on FPGA
    68276: 04/03/31: Re: Is there any Sync separator IP(Intellectual property) exists?
    68278: 04/03/31: Re: Real-time Image Process on FPGA
    68280: 04/03/31: Re: rs232 interface on nios
    68281: 04/03/31: Re: speed vs. temperature
    68304: 04/04/01: Re: Replace PPC in V2P with FPGA fabric!
    68323: 04/04/01: Re: Replace PPC in V2P with FPGA fabric!
    68462: 04/04/05: Re: Designing MUX with tri sate bus in xilinx virtex II FPGA
    68467: 04/04/05: Re: Real-time Image Process on FPGA
    68468: 04/04/05: Re: Logic required for multiplication
    68485: 04/04/06: Re: Designing MUX with tri sate bus in xilinx virtex II FPGA
    68497: 04/04/06: Re: Fast Carry Chains in Xilinx SpartanII FPGA's
    68554: 04/04/07: Re: how to get XST to infer 8:1 mux or just hard code it?
    68571: 04/04/08: Re: how to get XST to infer 8:1 mux or just hard code it?
    68595: 04/04/08: Re: how to get XST to infer 8:1 mux or just hard code it?
    68596: 04/04/08: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    68722: 04/04/15: Re: what is a better approach to synthezise synchronous reset on FPGA?
    68724: 04/04/15: Re: Apples to Apples? Stratix II <> Virtex-II Pro
    68807: 04/04/19: Re: vhdl example for use of external SRAM as a dual ported RAM?
    68827: 04/04/19: Re: Image-reject IF downmixing
    69046: 04/04/26: Re: Inferring Dynamic shift registers in XST
    69069: 04/04/26: Re: Stretch Inc
    69084: 04/04/26: Re: Inferring Dynamic shift registers in XST
    69085: 04/04/26: Re: Inferring Dynamic shift registers in XST
    69164: 04/04/28: Re: Image-reject IF downmixing
    69165: 04/04/28: Re: Inferring Dynamic shift registers in XST
    69302: 04/05/05: Re: XST, Virtex2-Pro, odd PAR counter timing failure
    69332: 04/05/06: Re: Wire crossing in a large partially reconfigurable design.
    69372: 04/05/08: Re: Muxes : 64X1
    69436: 04/05/11: Re: FPGA wanted
    69472: 04/05/11: Re: FPGA wanted
    69473: 04/05/11: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") -
    69553: 04/05/13: Re: V2p block ram clock -> Q delay help
    69561: 04/05/13: Re: V2p block ram clock -> Q delay help
    69576: 04/05/14: Re: Quartus II Web Edition
    69593: 04/05/14: Re: Simple way to generate random netlists of ALU cells
    69672: 04/05/17: Re: Simple way to generate random netlists of ALU cells
    69715: 04/05/18: Re: How to select an FPGA size (beginner)
    69726: 04/05/18: Re: Webpack 6.1, ISEexamples, and CoreGen
    69727: 04/05/18: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
    69743: 04/05/19: Re: How to select an FPGA size (beginner)
    69744: 04/05/19: Re: Webpack 6.1, ISEexamples, and CoreGen
    69787: 04/05/19: Re: How to select an FPGA size (beginner)
    69788: 04/05/19: Re: Nios II Going Live...
    69790: 04/05/20: Re: How to select an FPGA size (beginner)
    69872: 04/05/22: Re: OT: Electronics learner kit?
    70072: 04/06/01: Re: VHDL warning " Feedback mux " from synplify pro ...thx
    70091: 04/06/02: Re: FPGA + A/D converter
    70099: 04/06/02: Re: 5 V inputs to 3.3 V CPLD
    70120: 04/06/03: Re: tri-state in altera
    70135: 04/06/04: Re: tri-state in altera and xilinx
    70136: 04/06/04: Re: tri-state in altera and xilinx
    70141: 04/06/04: Re: tri-state in altera and xilinx
    70142: 04/06/04: Re: tri-state in altera and xilinx
    70193: 04/06/08: Re: slice # change from .syr to map report
    70287: 04/06/11: Re: Xilinx: infering dual port ROM in VHDL
    70355: 04/06/14: Re: SDRAM
    70602: 04/06/21: Re: Is there a verilog version of PicoBlaze?
    70638: 04/06/22: Re: VIRTEX v Spartan 3
    70648: 04/06/22: Re: Family Photo Album
    70701: 04/06/23: Re: Exponential Function
    70724: 04/06/24: Re: RAM in Altera EABs and Xilinx Block Rams
    71289: 04/07/13: Re: FIR filter running out of FPGA memory in stratix ep1s60
    71329: 04/07/14: Re: new Lattice FPGAs vs Cyclone and SpartanIII
    71330: 04/07/14: Re: FPGAs starting with incorrect bitstream !?
    71372: 04/07/15: Re: FPGA with fully asynchronous RAM
    71392: 04/07/16: Would Tom buy from Nu Horizons?
    71393: 04/07/16: Re: Multi-phase Motor Controller?
    71597: 04/07/23: Re: Xilinx registers resetr value
    73962: 04/10/01: Re: Removing set/reset logic for shift register (HDL ADVISOR )
    73964: 04/10/01: Re: Xilinx SRL16 test
    72997: 04/09/09: Re: Completed my first Virtex4 design
    73494: 04/09/22: Re: Ring Oscillator Redux
    74941: 04/10/21: Re: Async reset
    74942: 04/10/21: Re: ModelSim is ungraceful with my stupidity...
    74973: 04/10/22: Re: Altera Cubic Cyclonium
    75019: 04/10/24: Re: Altera Cubic Cyclonium
    75097: 04/10/26: Re: Low-power FPGAs?
    75305: 04/11/01: Re: "frying" FPGAs
    74089: 04/10/03: Re: Hardware Log and EXP
    74090: 04/10/03: Re: Hardware Log and EXP
    74092: 04/10/03: Re: How to generate a signal on Xilinx Spartan II
    74093: 04/10/03: Re: Removing set/reset logic for shift register (HDL ADVISOR )
    74118: 04/10/04: Re: XC2V1000 Block RAM size
    74188: 04/10/05: Re: Sine function implementation in FPGA??
    74189: 04/10/05: Re: Xilinx Multiple Clock Domains
    74237: 04/10/06: Re: I need help for Xilinx Demo Board (XC40xx-PC84
    74268: 04/10/06: Re: Removing set/reset logic for shift register (HDL ADVISOR )
    74272: 04/10/06: Re: Interfacing an 1GS ADC
    74276: 04/10/06: Re: Removing set/reset logic for shift register (HDL ADVISOR )
    74407: 04/10/10: Re: Interfacing an 1GS ADC
    74408: 04/10/10: Re: Sine function implementation in FPGA
    74409: 04/10/10: Re: Xilinx Multiple Clock Domains
    74421: 04/10/11: Re: CORDIC NCO Frequency resolution?
    74506: 04/10/12: Re: CORDIC NCO Frequency resolution?
    74755: 04/10/18: Re: How many Altera LE's to Xilinx Slices????
    74756: 04/10/18: Re: Virtex 4 released today
    74758: 04/10/18: Re: Virtex 4 released today
    74761: 04/10/18: Re: Unwanted shift in multiplier
    74768: 04/10/18: Re: How many Altera LE's to Xilinx Slices????
    75640: 04/11/11: Re: Xilinx Tshirts in football package.....
    75785: 04/11/15: Re: Digital LP filter in multiplier free FPGA
    75786: 04/11/15: Re: digital analog conversion
    76076: 04/11/23: Re: Favourite Design Entry Optomisation Method?
    76131: 04/11/25: Re: how to evaluate the needed number of gate?
    76348: 04/11/30: Re: 99% Utilisation !
    76359: 04/11/30: Re: CIC - Hogenauer glitch
    76360: 04/11/30: Re: Adder Tree Placement
    76423: 04/12/01: Re: CIC - Hogenauer glitch
    76424: 04/12/01: Re: 99% Utilisation !
    76426: 04/12/01: Re: EDIF -> Map & Place -> EDIF ?
    76590: 04/12/06: Re: Searching for rad tolerant, non-volatile (once programmable) FPGA
    76680: 04/12/08: Re: making an fpga hot
    76737: 04/12/09: Re: Adder Tree Placement
    76741: 04/12/09: Re: how to speed up my accumulator ??
    76742: 04/12/09: Re: how to speed up my accumulator ??
    76884: 04/12/15: Re: XILINX slice structure detaild description
    76885: 04/12/15: Re: algorithm: square operation
    76926: 04/12/15: Re: Inferring SRLs with INIT value
    76960: 04/12/17: Re: Inferring SRLs with INIT value
    76961: 04/12/17: Re: Digital clock synthesis
    76963: 04/12/17: Re: Digital clock synthesis
    77180: 04/12/28: Re: MAP failes after inserting ILA and ICON cores to the design
    77181: 04/12/28: Re: CIC filter implementation using FPGA
    77182: 04/12/28: Re: recommendations for a FIFO..
    77219: 04/12/30: Re: Multipliers implementation (xilinx)
    77439: 05/01/06: Re: xilinx as video processor?
    77553: 05/01/10: Re: a general question
    78172: 05/01/25: Re: dsp, arithmetic scaling questions, advice
    78173: 05/01/25: Re: Creating a pyramid of shift registers
    78989: 05/02/10: Variable phase shift on Spartan3 DCMs. Does it work?
    78997: 05/02/10: Re: Variable phase shift on Spartan3 DCMs. Does it work?
    79215: 05/02/15: Re: Fast counting in Spartan 3
    79334: 05/02/17: Re: clock split approach for 270MHz design in Spartan2E
    79365: 05/02/17: Re: FPGA Hardware/Cell Diagnostics
    80286: 05/03/03: Re: Need suggestion abt FFs without RST for pipelined datapath.
    80788: 05/03/11: Re: FIR Filter On FPGA
    80790: 05/03/11: Re: low speed FIR filter in FPGA
    80793: 05/03/11: Re: Xilinx ISE7.1
    80826: 05/03/11: Re: To estimate the maximum frequency?
    80992: 05/03/15: Re: Which HDL?
    81109: 05/03/17: Re: Bit-Rounding Algorithm
    81152: 05/03/18: Re: Performance evaluation of Distributed Arithmetic architectures
    81153: 05/03/18: Re: Performance evaluation of Distributed Arithmetic architectures
    81156: 05/03/18: Re: Performance evaluation of Distributed Arithmetic architectures
    81175: 05/03/18: Re: Newbie: Slow FPGAs
    81325: 05/03/21: Re: FIR choice
    81400: 05/03/22: Re: FIR choice
    81607: 05/03/28: Re: Block RAM in Xilinx Spartan 3
    81741: 05/03/30: Re: exp(-x) function
    81923: 05/04/04: Re: Xilinx tools, bugs all around?
    81927: 05/04/04: Re: fpga async design help me
    81931: 05/04/04: Re: Achieving required speed in Virtex-II Pro FPGA
    81933: 05/04/04: Re: Achieving required speed in Virtex-II Pro FPGA
    81934: 05/04/04: Re: Achieving required speed in Virtex-II Pro FPGA
    81943: 05/04/04: Re: exp(-x) function
    81989: 05/04/05: Re: Searching for Vision Concavity Algorithm
    81991: 05/04/05: Re: Stupid question
    82015: 05/04/05: Re: Reverse engineering ASIC into FPGA
    82064: 05/04/06: Re: Xilinx XPower - Accuracy Information
    82065: 05/04/06: Re: Stupid question
    82173: 05/04/07: Re: Reverse engineering ASIC into FPGA
    82341: 05/04/11: Re: DC component removal in FPGA
    82546: 05/04/13: Re: Neural Networks in FPGA
    82606: 05/04/14: Re: Fitting functionality in an XC2VP30 FPGA.
    83033: 05/04/21: Re: VHDL or Verilog
    83034: 05/04/21: Re: Unconstrained ports for synthesis
    83038: 05/04/21: Re: Spartan 3E slower that Spartan 3?
    83041: 05/04/21: Re: source control and Xilinx ISE 6 and 7
    83293: 05/04/27: Re: Rom Inference
    83295: 05/04/27: Re: CAM for FPGA ...
    83327: 05/04/27: Re: Virtex slow clock multiply options?
    83329: 05/04/27: Re: XC4k parts obsolete ?
    83342: 05/04/27: Re: XC4k parts obsolete ?
    83376: 05/04/28: Re: Virtex slow clock multiply options?
    83547: 05/05/02: Re: Map Error: "RLOC not supported for simple gates"
    83725: 05/05/05: Re: Xilinx V4 Power Calculations
    83733: 05/05/05: Re: Multiply Accumulate FPGA/DSP
    83738: 05/05/05: Re: Multiply Accumulate FPGA/DSP
    83776: 05/05/06: Re: Using capacitor to slow the rise time.
    84193: 05/05/13: Re: "Mine is bigger than yours..."
    84196: 05/05/14: Re: newbie question
    84197: 05/05/14: Re: true dual port memory v/s simple dual port memory
    84209: 05/05/14: Re: floorplanning
    84396: 05/05/18: Re: Which Simulators
    84469: 05/05/19: Re: VHDL array question
    84471: 05/05/19: Re: CORDIC bit-serial vs. bit-parallel
    84472: 05/05/19: Re: About back annotated simulations...
    84532: 05/05/20: Re: About back annotated simulations...
    84710: 05/05/25: Re: Bresenham Algorithms
    84711: 05/05/25: Re: more and more and more issues with Xilinx tools
    84713: 05/05/25: Re: Looking for core that does a vector product
    84785: 05/05/27: Re: Bresenham Algorithms
    85082: 05/06/03: Re: Share one BRAM block between user logic and microblaze (Spartan3)
    85086: 05/06/03: Re: not clear about doing power estimation using xpower
    85088: 05/06/03: Re: keypad scanner
    85166: 05/06/06: Re: FPGA : MAC FIR doubt--HELP ME PLEASE
    85463: 05/06/09: Re: faster Spartan III adder
    85464: 05/06/09: Re: How to convert Matlab to HDL?
    85465: 05/06/09: Re: not clear about doing power estimation using xpower
    85472: 05/06/09: Re: CORDIC bit-serial vs. bit-parallel
    85521: 05/06/10: Re: faster Spartan III adder
    85523: 05/06/10: Re: faster Spartan III adder
    85527: 05/06/10: computer upgrade time.
    85570: 05/06/10: Re: computer upgrade time.
    85654: 05/06/13: Re: Selecting FPGA synthesis, place and route and simulation tools
    85720: 05/06/14: Re: Selecting FPGA synthesis, place and route and simulation tools
    85772: 05/06/15: Re: computer upgrade time.
    85821: 05/06/16: Re: LUT, how to?
    86186: 05/06/22: Re: Automagic Circuit Pipelining
    86190: 05/06/22: Re: FPGA Filter Design
    86191: 05/06/22: Re: ISE 7.1 Service Pack 2 - Ready yet?
    86200: 05/06/22: Re: Xilinx MacFir5.0 - Block Ram requirenments
    86202: 05/06/22: Re: ISE 7.1 Service Pack 2 - Ready yet?
    86261: 05/06/23: Re: ISE 7.1 Service Pack 2 - Ready yet?
    86343: 05/06/25: Re: FPGA :FFT Core in Xilinx
    86421: 05/06/27: Re: FPGA Filter Design
    86473: 05/06/28: Re: V4 and NBTI question, again..
    86542: 05/06/29: Re: V4 and NBTI question, again..
    86860: 05/07/07: Re: Bit serial, book, other info???
    86862: 05/07/07: Re: Direct audio output from FPGA pins
    86865: 05/07/07: Re: XST: setting top-level generics
    86866: 05/07/07: Re: fastest FPGA speed grade?
    86880: 05/07/08: Re: Ray Andraka when will your book be on store???
    86980: 05/07/11: Re: Unrolled Pipeline Implementation
    87207: 05/07/19: Re: EHLO, board designers
    87234: 05/07/19: Re: Ones Count 64 bit on Xilinx in VHDL
    87275: 05/07/20: Re: Design is too large for the device! xc3s400
    87276: 05/07/20: Re: All of the design is being optimized away and logic removed
    87277: 05/07/20: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87280: 05/07/20: Re: Design is too large for the device! xc3s400
    87287: 05/07/20: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87288: 05/07/20: Re: Ones Count 64 bit on Xilinx in VHDL
    87289: 05/07/20: Re: Design is too large for the device! xc3s400
    87290: 05/07/20: Re: Design is too large for the device! xc3s400
    87315: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87318: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87332: 05/07/21: Re: Design is too large for the device! xc3s400
    87333: 05/07/21: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87351: 05/07/21: Re: Optimizing out a divide on altera cyclone fpga
    87424: 05/07/23: Re: Fastest way to compute floating point log and exp
    87476: 05/07/25: Re: Fastest way to compute floating point log and exp
    87810: 05/08/01: Re: Distributed Arithmetic Architecture - LUT Contents
    87811: 05/08/01: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
    88245: 05/08/12: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
    88501: 05/08/19: Re: Best FPGA for floating point performance
    88861: 05/08/30: Re: 36x36 signed multiplier?
    88934: 05/08/31: Re: Low Power RTL Design
    88982: 05/09/01: Re: Lot of 60 XCV1000 FPGAs
    88983: 05/09/01: Re: "Perform Timing-Driven Packing and Placement" error?
    89022: 05/09/02: Re: Creating higher bit multipliers from low bit.
    89703: 05/09/22: Re: Hints for efficient 32 bit multiplier
    90009: 05/10/01: Re: Prob in Synthesizing and Simulating large Mux
    90111: 05/10/04: Re: EasyPath, demystified
    90279: 05/10/07: Re: Virtex4 shift register layout: Horizontal or vertical?
    90280: 05/10/07: Re: Avoiding meta stability?
    90347: 05/10/10: 64 bit processor for FPGA workstation?
    90394: 05/10/11: Re: Floating point multiplication on Spartan3 device
    90395: 05/10/11: Re: Power on reset generation in FPGA
    90399: 05/10/11: Re: 64 bit processor for FPGA workstation?
    90400: 05/10/11: Re: Best FPGA for floating point performance
    90428: 05/10/12: Re: Avoiding meta stability?
    90451: 05/10/13: Re: how to implement 8x8 circular shifter on FPGA
    90452: 05/10/13: Re: computer upgrade time.
    90459: 05/10/13: Re: Storing a file onto FPGA
    90500: 05/10/14: Re: Storing a file onto FPGA
    90514: 05/10/15: Re: Storing a file onto FPGA
    90608: 05/10/17: Re: Storing a file onto FPGA
    90667: 05/10/18: Re: Storing a file onto FPGA (the last word)
    90735: 05/10/19: Re: which is Low power FPGA?
    90780: 05/10/20: Re: RPM reference for xilinx
    90882: 05/10/24: Re: RS232 Uart for Virtex-II Pro
    90884: 05/10/24: Re: RPM reference for xilinx
    90937: 05/10/25: Re: OSD implementation in FPGA
    90988: 05/10/26: Re: state machine with 2 clock's
    90989: 05/10/26: Re: SDRAM in EDK
    91223: 05/11/01: Re: ISE 8.1, EDK 8.1 any pre-release info available?
    91224: 05/11/01: Re: Sigma-Delta A/D
    91350: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91435: 05/11/06: Re: Anybody understand this ISE 7.1 error, and what to do about it???
    91437: 05/11/06: Re: Anybody understand this ISE 7.1 error, and what to do about it???
    91439: 05/11/06: Re: Anybody understand this ISE 7.1 error, and what to do about it???
    91456: 05/11/07: Re: Anybody understand this ISE 7.1 error, and what to do about it???
    91477: 05/11/07: Re: Xilinx Package/Logic Options
    91492: 05/11/07: Re: VHDL algorithm/code for implementing QAM on FPGA
    91493: 05/11/07: Re: Why Spartan-3e is the best
    91528: 05/11/08: Re: BRAMs readback
    91584: 05/11/09: Re: Forcing carry-ripple adder ?
    91586: 05/11/09: Re: how to implement Fast Fourier Transform on virtex pro
    91689: 05/11/10: Re: Is this even true???
    91708: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
    91713: 05/11/10: Re: SDRAM controller.
    91889: 05/11/15: Re: downloading with XMD ?
    92046: 05/11/21: Re: FFT on an FPGA
    92125: 05/11/22: Re: data encryption standard
    92360: 05/11/28: Re: Stupid reset question
    92361: 05/11/28: Re: Memory in VHDL
    92433: 05/11/29: Re: Slow FIFO using external SRAM
    92434: 05/11/29: Re: Stupid reset question
    92550: 05/12/01: Re: Virtex 4 FIFO16 blocks - Corruption ?
    92564: 05/12/01: Re: Virtex 4 FIFO16 blocks - Corruption ?
    92574: 05/12/01: Re: Virtex 4 FIFO16 blocks - Corruption ?
    92575: 05/12/01: Re: Virtex 4 FIFO16 blocks - Corruption ?
    92584: 05/12/01: Re: Virtex 4 FIFO16 blocks - Corruption ?
    92642: 05/12/02: Re: Virtex 4 FIFO16 blocks - Corruption ?
    92718: 05/12/05: Re: Virtex-4 DSP48 placement restrictions?
    92766: 05/12/06: Re: ISE 8.1 release delayed?
    92767: 05/12/06: Re: Virtex-4 DSP48 placement restrictions?
    92768: 05/12/06: Re: Virtex 4 FIFO16 blocks - Corruption ?
    92848: 05/12/07: Re: I2C controller chipset to interface with FPGA
    92886: 05/12/08: Re: Virtex 4 not meeting timing constraints
    92901: 05/12/08: Re: Simulating Post-Synthesis Model on Xilinx FPGA
    92903: 05/12/08: Re: Simulating Post-Synthesis Model on Xilinx FPGA
    92961: 05/12/09: Re: Adding "super-LUTs" to FPGA, good idea ?
    92966: 05/12/10: Re: Adding "super-LUTs" to FPGA, good idea ?
    92981: 05/12/10: Re: No, not FIFOs again...
    93007: 05/12/11: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA,
    93045: 05/12/12: Re: Xilinx for PDP
    93071: 05/12/13: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
    93073: 05/12/13: Re: who can help me? i want to know the bitsream format of Virtex-II
    93074: 05/12/13: Re: xilinx constraint
    93098: 05/12/13: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
    93100: 05/12/13: Re: 3/2 with virtex 300
    93109: 05/12/13: Re: who can help me? i want to know the bitsream format of Virtex-II
    93142: 05/12/14: Re: 3/2 with virtex 300
    93144: 05/12/14: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
    93150: 05/12/14: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
    93151: 05/12/14: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
    93314: 05/12/19: Re: Virtex 4 not meeting timing constraints
    93361: 05/12/20: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar
    93412: 05/12/21: Re: More beginner's verilog questions
    93436: 05/12/21: Re: Place and Route Algorithms: where's the fat?
    93437: 05/12/21: Re: More beginner's verilog questions
    93439: 05/12/21: Re: lpc922
    93466: 05/12/22: Re: More beginner's verilog questions
    93470: 05/12/22: Re: Place and Route Algorithms: where's the fat?
    93472: 05/12/22: Re: Place and Route Algorithms: where's the fat?
    93642: 05/12/27: Re: Xilinx Stepping Methodology
    93912: 06/01/03: Re: Start up condition of flip flops in FPGA?
    93922: 06/01/03: Re: Clock generation
    93983: 06/01/04: Re: Remapping from Virtex-II to Virtex-4
    94190: 06/01/06: Re: Schematic Entry, Xilinx or Altera?
    94049: 06/01/05: Re: Schematic Entry, Xilinx or Altera?
    94043: 06/01/04: Re: CORDIC for digital downconversion
    94322: 06/01/09: Re: CORDIC for digital downconversion
    94042: 06/01/04: Re: CORDIC for digital downconversion
    94210: 06/01/07: Re: Asynch. signal
    94348: 06/01/10: Re: Asynch. signal
    94366: 06/01/10: Re: Asynch. signal
    94350: 06/01/10: Re: How to keep the design from Synplify or XST optimizing
    94235: 06/01/08: "failed to create empty document"
    94240: 06/01/08: Re: "failed to create empty document"
    94270: 06/01/09: Re: "failed to create empty document"
    94299: 06/01/09: Re: "failed to create empty document"
    94320: 06/01/09: Re: "failed to create empty document"
    94325: 06/01/09: Re: "failed to create empty document"
    94332: 06/01/10: Re: "failed to create empty document"
    94380: 06/01/10: Re: "failed to create empty document"
    94293: 06/01/09: Re: Easier initializing of blockram (spartan3)
    94435: 06/01/11: Re: Back to Power?
    94439: 06/01/11: Re: DCI power variations
    94479: 06/01/12: Re: DSP soft processors
    94641: 06/01/15: Re: FPGA Journal Article
    94708: 06/01/16: Re: FPGA Journal Article
    94627: 06/01/14: Re: bandpass filter design for ACTEL FPGA
    94568: 06/01/13: Re: Xilinx Virtex-4 BRAM-16 Simulation
    94626: 06/01/14: Re: Xilinx Virtex-4 BRAM-16 Simulation
    94625: 06/01/14: Caution, Rant follows
    95285: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95435: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95004: 06/01/20: Re: Sorting large amounts of floats
    95154: 06/01/21: Re: working with XDL
    95209: 06/01/21: Re: Creating Multiple Configuration PROM File
    95251: 06/01/21: Re: Creating Multiple Configuration PROM File
    95583: 06/01/24: Re: Irrelevant, stupid, racist, and worse.
    95329: 06/01/22: Re: Virtual Pin in Xilinx ISE
    95481: 06/01/23: Re: Xilinx padding LC numbers, how do you really feel about it?
    95582: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    95607: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    95613: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    95689: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
    95714: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
    95738: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
    95439: 06/01/23: PE licensure: was Shooting Ourselves in the Foot
    95441: 06/01/23: Re: RPM.
    95477: 06/01/23: PE licunsure: was Shooting Ourselves in the Foot
    95682: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
    95762: 06/01/25: Re: So what happened to JHDLBits?
    95873: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source
    95919: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source
    96252: 06/02/01: Re: Parallel Cable IV does not work with parallel to usb cable
    96356: 06/02/02: Re: Die Area
    96366: 06/02/02: Re: Die Area
    96259: 06/02/01: Re: BPSK modulation on Xilinx FPGA
    96311: 06/02/01: Re: BPSK modulation on Xilinx FPGA
    96254: 06/02/01: Re: BPSK modulation on Xilinx FPGA
    96324: 06/02/02: Re: BPSK modulation on Xilinx FPGA
    96816: 06/02/10: Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?
    96843: 06/02/11: Re: Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?
    96853: 06/02/11: Re: using FPGA in control field
    96854: 06/02/11: Re: Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?
    96982: 06/02/14: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
    97172: 06/02/17: Re: What is 1QN and 2QN in Xilinx CORDIC ?
    97372: 06/02/21: Re: Is FPGA code called firmware?
    97404: 06/02/21: Re: Relative placement constraints in Xilinx ISE w/ Verilog
    97447: 06/02/22: Re: Ray Andraka's Book?
    97659: 06/02/25: Re: V4 FIFO16 and SRAM
    97732: 06/02/26: Re: V4 FIFO16 and SRAM
    97841: 06/02/28: Re: V4 FIFO16 and SRAM
    97998: 06/03/02: Re: Combinatorial Division?
    98876: 06/03/17: Re: Where are FPGA heading?
    98877: 06/03/17: Re: Where are FPGA heading?
    98985: 06/03/18: Re: Disk/LCD defect tolerant models for FPGA sales
    99014: 06/03/18: Re: Disk/LCD defect tolerant models for FPGA sales
    99071: 06/03/19: Re: FPGA FIR advice
    99073: 06/03/19: Re: is conv_integer(unsigned(value)) synthesizable
    99154: 06/03/20: Re: FPGA FIR advice
    99156: 06/03/20: Re: Disk/LCD defect tolerant models for FPGA sales
    99166: 06/03/20: Re: Disk/LCD defect tolerant models for FPGA sales
    99187: 06/03/21: Re: Virtex 4 deconfiguring itself ...
    99228: 06/03/21: Re: Disk/LCD defect tolerant models for FPGA sales
    99232: 06/03/21: Tisdale?
    99237: 06/03/21: Re: Support software for XC3042
    99238: 06/03/21: Re: BRAM for virtex-4
    99300: 06/03/22: Re: Going from CLK1X to CLK2X.. really safe?
    99388: 06/03/23: Re: Going from CLK1X to CLK2X.. really safe?
    99392: 06/03/23: Re: Number of taps for a FIR
    99408: 06/03/23: Re: Xilinx hi-speed interconnect/routing question
    99412: 06/03/23: Re: Data Muxing on Spartan3 using the embedded carry chain
    99458: 06/03/24: Re: Number of taps for a FIR
    99460: 06/03/24: Re: Xilinx hi-speed interconnect/routing question
    99462: 06/03/24: Re: Xilinx hi-speed interconnect/routing question
    99467: 06/03/24: Re: Number of taps for a FIR
    99550: 06/03/26: Re: Xilinx hi-speed interconnect/routing question
    99617: 06/03/27: Re: Altera web site inaccessible
    100304: 06/04/06: Re: Xilinx Schematic Entry
    100340: 06/04/06: Re: Bizarre behaviour by Quartus?
    100369: 06/04/07: Re: Accessing compact flash?????????
    100370: 06/04/07: Re: C H S in a Compact flash
    100398: 06/04/07: Re: who know what is the problem
    100410: 06/04/08: Re: Accessing compact flash?????????
    100453: 06/04/09: Re: Accessing compact flash?????????
    100567: 06/04/12: Re: To use adder and multiplier of DSP48 in V4
    100596: 06/04/12: Re: Print FAT table in a compact flash ??????????
    100825: 06/04/18: Re: driving high speed ADC using an FPGA
    100940: 06/04/21: Re: Video circle generator
    101111: 06/04/25: Re: Opinions on Viva
    101164: 06/04/26: Re: expanding multipliers, problem
    101551: 06/05/02: Re: 50-th Anniversary of the CORDIC Algorithm
    101552: 06/05/02: Re: Book Software for XC3190A?
    101553: 06/05/02: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101698: 06/05/04: Re: RFID chip has battary in it or not
    101699: 06/05/04: Re: Book Software for XC3190A?
    102183: 06/05/11: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
    102184: 06/05/11: Re: [Newbie] 64-point complex FFT with 32 bit floating-point representation
    102243: 06/05/12: Re: 64-point complex FFT with 32 bit floating-point representation
    102244: 06/05/12: Re: How to check IOB register packing?
    102303: 06/05/14: Re: Floating point reality check
    102447: 06/05/16: Re: Floating point reality check
    102934: 06/05/23: Re: Multiple Independent Circuits on a Single FPGA
    103009: 06/05/24: Re: I2C on Xilinx V4
    103039: 06/05/24: Re: Virtex 5 announced
    103040: 06/05/24: Re: Virtex 5 announced and sampling
    103129: 06/05/25: Re: DSP48E, What are the internal implementations used?
    103131: 06/05/25: Re: Virtex 5 announced
    103132: 06/05/25: Re: Xilinx/Synplicity LUT Placement
    103133: 06/05/25: Re: DSP48E, What are the internal implementations used?
    103136: 06/05/25: Re: Floating point reality check
    103167: 06/05/26: Re: Xilinx/Synplicity LUT Placement
    103505: 06/06/04: Re: VHDL code For Floating point adder and Multiplier
    103874: 06/06/13: Re: How to get lowest price for a ModelSim license?
    104011: 06/06/16: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    104547: 06/06/29: Re: NCO Clock driven Designs in FPGA
    104548: 06/06/29: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
    104549: 06/06/29: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
    104759: 06/07/05: Re: "Large" memory array in VHDL
    104760: 06/07/05: Re: Can I use all 18bits of a BlockRAM?
    104761: 06/07/05: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
    104762: 06/07/05: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
    104763: 06/07/05: Re: Chaos in FF metastability
    104945: 06/07/10: Re: The FFs with synchronous reset perform worse?
    105305: 06/07/19: Re: Sorting algorithm for FPGA availlable?
    105442: 06/07/22: Re: IIR FPGA 'crosspost'
    105648: 06/07/27: Re: OT (2nd try): do you get paid for your travel time?
    105651: 06/07/27: Re: Guided MAP/PAR in ISE
    105656: 06/07/27: Re: Guided MAP/PAR in ISE
    105825: 06/08/01: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
    105857: 06/08/01: Re: Programmable pulse generator
    105885: 06/08/02: Re: Programmable pulse generator
    105961: 06/08/03: Re: generating sine-like waveforms
    106226: 06/08/09: Re: DSP core, use of real type signals (Altera Stratix)
    106698: 06/08/17: Re: FFT on an FPGA
    106754: 06/08/18: Re: FFT on an FPGA
    106757: 06/08/18: Re: FFT on an FPGA
    106805: 06/08/19: Re: FFT on an FPGA
    106806: 06/08/19: Re: FFT on an FPGA
    106914: 06/08/22: Re: CPU design
    106921: 06/08/22: Re: Xilinx .002ns timing error
    106985: 06/08/23: Re: Xilinx Floorplanner
    106993: 06/08/23: Re: Timing
    107112: 06/08/24: Re: Xilinx Floorplanner
    107126: 06/08/24: Re: fastest FPGA
    107199: 06/08/25: Re: fastest FPGA
    107203: 06/08/25: Re: fastest FPGA
    107620: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
    107621: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
    107635: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
    107667: 06/08/30: Re: FFT on an FPGA
    107932: 06/09/02: Re: Performance Appraisals
    107968: 06/09/03: Re: FIR Implementation with System Generator 8.2
    107970: 06/09/03: Re: Xilinx VSK (Video Starter Kit)
    107971: 06/09/03: Re: wiring resource utilization?
    108067: 06/09/04: Re: Please help me with (insert task here)
    108093: 06/09/05: Re: fastest FPGA
    108172: 06/09/06: Re: fastest FPGA
    108173: 06/09/06: Re: fastest FPGA
    108219: 06/09/06: Re: fastest FPGA
    108220: 06/09/06: Re: Qestion about the ability of synthesis
    108238: 06/09/06: Re: fastest FPGA
    108242: 06/09/06: Re: how can I decrease the time cost when synthesis and implement
    108250: 06/09/06: Re: fastest FPGA
    108266: 06/09/07: Re: fastest FPGA
    108268: 06/09/07: Re: how can I decrease the time cost when synthesis and implement
    108474: 06/09/11: Re: Functional and Post-Synthesis Simulation
    108475: 06/09/11: Re: FPGA timing
    108476: 06/09/11: Re: xilinx bram instantation template in vhdl?
    108533: 06/09/12: Re: fastest FPGA
    108573: 06/09/13: Re: fastest FPGA
    108576: 06/09/13: Re: Xilinx Platform Studio, build up System: "block-RAM components
    108577: 06/09/13: Re: FPGA timing
    108578: 06/09/13: Re: Xilinx Platform Studio, build up System: "block-RAM components
    108587: 06/09/13: Re: FPGA timing
    108617: 06/09/13: Re: Prefered ieee libraries?
    108618: 06/09/13: Re: resets on synplicity inferred RAMs
    108638: 06/09/14: Re: downloading bitstream on FPGA
    108639: 06/09/14: Re: Prefered ieee libraries?
    108666: 06/09/14: Re: Spartan3: Multiplier Madness
    108921: 06/09/19: Re: resets on synplicity inferred RAMs
    108922: 06/09/19: Re: xilinx fir ipcore
    108923: 06/09/19: Re: Xilinx xapp802.pdf mistake?
    108975: 06/09/19: Re: Buffering the critical path.
    108976: 06/09/19: Re: Spartan3: Multiplier Madness
    109099: 06/09/20: Re: Xilinx PowerPC slower than FPGA Design?
    109172: 06/09/21: Re: DCM and domain crossing
    109380: 06/09/25: Re: Hilbert Transform in verilog or VHDL -- it has got to be out
    109429: 06/09/26: Re: Hilbert Transform in verilog or VHDL -- it has got to be out
    109500: 06/09/27: Re: Driving a 30 bit wide LVTTL bus at 160MHz
    109531: 06/09/27: Re: PUBLISHABLE PAPER RELATED TO FPGA!
    109546: 06/09/28: Re: PUBLISHABLE PAPER RELATED TO FPGA!
    109558: 06/09/28: Re: bit vs std_logic
    109672: 06/10/02: Re: Looking for HDL code for sin( a ) and x ** y Functions
    109673: 06/10/02: Re: Looking for HDL code for sin( a ) and x ** y Functions
    109706: 06/10/03: Re: logarithm look-up table
    109809: 06/10/05: Re: a clueless bloke tells Xilinx to get a move on
    109823: 06/10/05: Re: a clueless bloke tells Xilinx to get a move on
    109824: 06/10/05: Re: a clueless bloke tells Xilinx to get a move on
    109856: 06/10/06: Re: Design of a programmable delay line
    110035: 06/10/09: Re: An implementation of a clean reset signal
    110036: 06/10/09: Re: An implementation of a clean reset signal
    110056: 06/10/10: Re: longest webcase record
    110551: 06/10/17: Re: Newbie : Please give me an idea about programming an FPGA
    110563: 06/10/18: Re: Xilinx ISE UCF question
    110589: 06/10/18: Re: from LUT contents to boolean equation
    110612: 06/10/18: Re: FIR filter fpga help
    110613: 06/10/18: Re: 64 bit division compensate NCO
    110694: 06/10/19: Re: 64 bit division compensate NCO
    110695: 06/10/19: Re: FIR filter generic
    110734: 06/10/20: Re: FIR filter generic
    110946: 06/10/25: Re: OT: FPGA soft-core humor
    110955: 06/10/25: Re: FIR filter generic
    111141: 06/10/30: Re: Jumps in FPGA implemented integrator
    111164: 06/10/30: Re: Taking forever to synthesise (XILINX ISE 8.1i)
    111278: 06/10/31: Re: Dual Port RAM
    111282: 06/10/31: Re: filter design for low-pass
    111283: 06/10/31: Re: filter design for low-pass
    111329: 06/11/01: Re: Spectre of Metastability Update
    111351: 06/11/01: Re: De-serializer using Xilinx DCM
    111429: 06/11/02: Re: Spectre of Metastability Update
    111469: 06/11/03: Re: Spectre of Metastability Update
    111535: 06/11/04: Re: Scientific Computing on FPGA
    111582: 06/11/06: Re: reset
    111592: 06/11/06: Re: Global Clocks in Xilinx Virtex-4
    111595: 06/11/06: Re: Interface standards (was Re: Dual Port RAM)
    111597: 06/11/06: Re: reset
    111614: 06/11/06: Re: Global Clocks in Xilinx Virtex-4
    111619: 06/11/06: Re: Global Clocks in Xilinx Virtex-4
    111646: 06/11/07: Re: Scientific Computing on FPGA
    111647: 06/11/07: Re: Interface standards (was Re: Dual Port RAM)
    111691: 06/11/08: Re: Interface standards (was Re: Dual Port RAM)
    111698: 06/11/08: Re: floating point arithemetic on fpga
    111804: 06/11/10: Re: floating point arithemetic on fpga
    111805: 06/11/10: Re: Xilinx Partition for EDIF Flow (synthesis synplify)
    111875: 06/11/12: Re: Power-on reset
    111876: 06/11/12: Re: Xilinx Partition for EDIF Flow (synthesis synplify)
    111898: 06/11/12: Re: Power-on reset
    112022: 06/11/14: Re: Influence of temperature and manufacturing to propagation delay
    112050: 06/11/15: Re: xupv2p
    112056: 06/11/15: Re: xupv2p
    112066: 06/11/15: Re: Xilinx 2 DCMs with delay on lock
    112207: 06/11/17: Re: combinatorical divide by 2 in FPGA
    112299: 06/11/19: Re: board - T562.jpg
    112301: 06/11/19: Re: IDELAY Calibration - Virtex 4
    112335: 06/11/20: Re: Simple questions on IDELAYCTRL
    112345: 06/11/20: Re: 8080 FSGA model in an FPGA
    112346: 06/11/20: Re: board - T562.jpg
    112407: 06/11/21: Re: board - T562.jpg
    112410: 06/11/21: Re: board - T562.jpg
    112417: 06/11/21: Re: board - T562.jpg
    112689: 06/11/27: Re: CORDIC FM Demodulation
    112851: 06/11/29: Old XCell journals gone?
    112908: 06/11/30: Re: Old XCell journals gone?
    112964: 06/12/02: Re: LUT input order
    113038: 06/12/05: Re: RLOC weirdness
    113090: 06/12/06: Re: RLOC weirdness
    113183: 06/12/07: Re: Recursive component instantiation
    113184: 06/12/07: Re: RTL Hardware design issue: Count Leading Zeros CLZ
    113194: 06/12/07: Re: Recursive component instantiation
    113218: 06/12/08: Re: RTL Hardware design issue: Count Leading Zeros CLZ
    113227: 06/12/08: Re: RTL Hardware design issue: Count Leading Zeros CLZ
    113236: 06/12/08: Re: Barrel shifter in Virtex4?
    113298: 06/12/10: Re: Some questions about FFT implementation
    113300: 06/12/10: Re: Writing output signals to text file (VHDL)?
    113325: 06/12/11: Re: Some questions about FFT implementation
    113383: 06/12/12: Re: . What is the sign-and-magnitude of the following 4's complement
    113535: 06/12/15: Re: FPGA : Async FIFO, Programmable full
    113542: 06/12/15: Re: FPGA : Async FIFO, Programmable full
    113758: 06/12/20: Re: Spartan 3E Starter Kit Woes
    113760: 06/12/20: Re: Spartan 3E Starter Kit Woes
    113764: 06/12/20: Re: Spartan 3E Starter Kit Woes
    113765: 06/12/20: Re: Manually creating a LUT in VHDL
    113767: 06/12/20: Re: A nice CIC-Filter, but I can't find the result in the bitsequence!?
    114208: 07/01/07: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
    114209: 07/01/07: Re: [XST 8.2.3] DSP48 inference multiply/add
    114242: 07/01/08: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
    114459: 07/01/16: Re: interesting article FPGA routing field programmable nanowire
    114582: 07/01/19: Re: "Gate" = ???
    114586: 07/01/19: Re: FPGA implementation of UHF transmitter in airborne applications
    114858: 07/01/25: Re: On-chip randomness (V4FX)
    114977: 07/01/28: Re: Datapath design problem?
    114979: 07/01/28: Re: Minimal design for xilinx?
    115098: 07/01/30: Re: Minimal design for xilinx?
    115182: 07/02/01: Re: DDR FPGA Design
    115223: 07/02/03: Re: circle generation algorithm
    115388: 07/02/08: Re: Forcing a LUT to not be optimized
    115605: 07/02/14: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
    115610: 07/02/14: Re: Typical clock frequencies of FPGA designs
    115647: 07/02/15: Re: Digital AM/FM Receiver
    115919: 07/02/25: Re: Making a 32KB BRAM block, virtex-4
    116004: 07/02/27: Re: Making a 32KB BRAM block, virtex-4
    116010: 07/02/27: Re: Making a 32KB BRAM block, virtex-4
    116058: 07/02/28: Re: Spartan-3AN
    116168: 07/03/02: Re: What is the running frequency for a typical FPGA application
    116506: 07/03/11: Re: Heritage Data books!
    116538: 07/03/12: Re: RLOC not working correctly in ISE 8.2 and 9.1?
    116548: 07/03/12: Re: Estimating number of FPGAs needed for an application
    116565: 07/03/12: Re: Heatsink on FPGA?
    116753: 07/03/16: Re: Clearing fpga internal memory...
    116829: 07/03/19: Re: Use of both positive reference and negative reference of the
    116834: 07/03/19: Re: Clearing fpga internal memory...
    116873: 07/03/20: Re: Xilinx ISE support for dual/quad core CPUs?
    117418: 07/03/30: Re: Complex Baseband
    117430: 07/03/30: Re: shift register with distributed ram
    117520: 07/04/03: Re: Complex Baseband
    117552: 07/04/03: Re: shift register with distributed ram
    117553: 07/04/03: Re: ModelSim VHDL Pragmas
    117554: 07/04/03: Re: ModelSim VHDL Pragmas
    117555: 07/04/03: Re: ModelSim VHDL Pragmas
    117600: 07/04/04: Re: Digital Receiver chip suggestion
    117601: 07/04/04: Re: Digital AM/FM Receiver - Systemic Question
    117603: 07/04/04: Re: high number of multipliers / low cost
    117605: 07/04/04: Re: high number of multipliers / low cost
    117606: 07/04/04: Re: high number of multipliers / low cost
    117629: 07/04/05: Re: Digital Receiver chip suggestion
    117931: 07/04/13: Re: Which are the best books about CORDIC algorithms and applications
    117932: 07/04/13: Re: Which are the best books about CORDIC algorithms and applications
    117933: 07/04/13: Re: Which are the best books about CORDIC algorithms and applications
    117935: 07/04/13: Re: has anyone used mathstar field programmable object arrays?
    118944: 07/05/07: Re: Xilinx software quality - how low can it go ?!
    118964: 07/05/08: Re: Xilinx software quality - how low can it go ?!
    118972: 07/05/08: Re: Xilinx software quality - how low can it go ?!
    119617: 07/05/23: Re: clock wide pulse transfer b/w clock domains
    119618: 07/05/23: Re: how 33-bit BRAM?
    119944: 07/05/29: Re: How to calculate IFFT based on FFT result?
    120285: 07/06/04: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer
    121176: 07/06/27: Re: corgen cic = terrible efficiency?
    121178: 07/06/27: Re: corgen cic = terrible efficiency?
    121184: 07/06/27: Re: corgen cic = terrible efficiency?
    121191: 07/06/27: Re: corgen cic = terrible efficiency?
    122660: 07/08/02: Re: Corgen Adder Vs DSP48 Adder in Virtex4
    122661: 07/08/02: Re: Aldec ActiveHDL vs. ModelSim
    122696: 07/08/03: Re: Altera or Xilinx
    122702: 07/08/03: Re: How to choose FPGA for a huge computation?
    123256: 07/08/21: Re: Xilinx / ISE multi-cycle path constraint pitfall
    123277: 07/08/22: Re: Power Reduction Strategy
    123289: 07/08/22: Re: Power Reduction Strategy
    124417: 07/09/20: Re: Is it possible to perform gate level simulation on a design without
    124529: 07/09/25: Re: Guess: what is the largest number of state machines in a current
    124566: 07/09/26: Re: Inferring wide adders comprising multiple DSP48s
    124569: 07/09/26: Re: Logic minimization software with LUT6 support?
    124573: 07/09/26: Re: Logic minimization software with LUT6 support?
    124575: 07/09/26: Re: Logic minimization software with LUT6 support?
    124621: 07/09/28: Re: Never buy Altera!!!!
    124622: 07/09/28: Re: Bug in Synplify?
    124678: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124679: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124766: 07/10/03: Re: Basic VHDL Development kit
    124798: 07/10/04: Re: FFT core
    124799: 07/10/04: Re: Optimized bitcounting on FPGA
    124916: 07/10/10: Re: Xcell Article on 1.2Gsamples/sec FFT
    124918: 07/10/10: Re: Xcell Article on 1.2Gsamples/sec FFT
    125010: 07/10/15: Re: FFT core
    125027: 07/10/15: Re: FPGA quiz: what can be wrong
    125209: 07/10/17: Re: Reason for LUT1_L buffer insertion in Synplify EDIFs?
    125407: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
    125408: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
    125454: 07/10/25: Re: builing a SPI interface in vhdl
    125497: 07/10/26: Re: FPGA vs ASIC
    125642: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
    125673: 07/10/31: Re: FPGA vs ASIC
    125747: 07/11/02: Re: FPGA vs ASIC
    125804: 07/11/05: Re: Audio Output from Spartan 3 Starter Kit
    126016: 07/11/12: Re: newbie to 16v8
    126095: 07/11/14: Re: FPGA for hobby use
    126142: 07/11/15: Re: FPGA for hobby use
    126143: 07/11/15: Re: newbie to 16v8
    126194: 07/11/16: Re: Block-ram FIFO in Xilinx
    126195: 07/11/16: Re: FPGA for hobby use
    126196: 07/11/16: Re: FPGA for hobby use
    126212: 07/11/16: Re: FPGA for hobby use
    126916: 07/12/05: Re: Mixed language design
    126957: 07/12/06: Re: What's the difference for VHDL code between simulation and synthesis?
    126984: 07/12/07: Re: What's the difference for VHDL code between simulation and synthesis?
    127043: 07/12/10: Re: What's the difference for VHDL code between simulation and synthesis?
    128803: 08/02/06: Re: 1-Wire and Dallas DS1WM in Spartan
    128805: 08/02/06: Re: FPGA's as DSP's
    128808: 08/02/06: Re: function/process to generate sine and cosine wave
    128812: 08/02/07: Re: About 10-bit pixel datum from CMOS image sensor
    128813: 08/02/07: Re: function/process to generate sine and cosine wave
    128857: 08/02/07: Re: beleive
    129277: 08/02/19: Re: Efficient division algorithm?
    129308: 08/02/20: Re: Efficient division algorithm?
    129309: 08/02/20: Re: ModelSim versus Active-HDL....redux
    129311: 08/02/20: Re: ModelSim versus Active-HDL....redux
    129323: 08/02/20: Re: Is a FPGA the solution ?
    129324: 08/02/20: Re: When are FPGAs the right choice?
    129325: 08/02/20: Re: Random Number Generation in VHDL
    129326: 08/02/20: Re: Random Number Generation in VHDL
    129353: 08/02/21: Re: Random Number Generation in VHDL
    129364: 08/02/21: Re: Software Defined Radio auf Xilinx Virtex 4
    129365: 08/02/21: Re: Random Number Generation in VHDL
    129722: 08/03/03: Re: Random Number Generation in VHDL
    130988: 08/04/07: Re: A Challenge for serialized processor design and implementation
    131042: 08/04/08: Re: 32 bit multiplier
    131936: 08/05/07: Re: Chirp generator / CORDIC algo ?
    132149: 08/05/15: Re: Functional Simulation of Virtex-4 Block Memory
    132528: 08/05/29: Re: (won't even attempt to try again .. .. ..)
    132550: 08/05/30: Re: (won't even attempt to try again .. .. ..)
    132551: 08/05/30: Re: (won't even attempt to try again .. .. ..)
    132585: 08/06/02: Re: (won't even attempt to try again .. .. ..)
    135043: 08/09/11: Re: need fast FPGA suggestions
    135044: 08/09/11: Re: need fast FPGA suggestions
Ray Bowden:
    6681: 97/06/13: Re: Don't Design With Altera Parts... Altera Obsolete Parts
Ray Cheung:
    58567: 03/07/26: Re: Multi Cycle path and False paths
Ray D.:
    124003: 07/09/10: Re: VHDL Synthesis Error
    133831: 08/07/16: Xilinx Spartan-3E Microblaze Program Execution
    133904: 08/07/18: Additional Hardware Module with Xilinx MicroBlaze Processor
    133996: 08/07/21: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    134060: 08/07/23: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    134061: 08/07/23: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    134086: 08/07/24: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    134169: 08/07/28: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    134193: 08/07/30: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
    134305: 08/08/05: Microblaze to LCD module via FSL bus
Ray Dennison:
    489: 94/12/02: Re: XC3090 PERFROMANCE...
Ray Ehrisman:
    7597: 97/09/25: Re: Global Reset w/ VHDL & Xilinx
    10270: 98/05/08: Re: Xilinx Routing Delay
Ray Frost:
    54295: 03/04/07: Re: help with DLL problem in Spartan2E
    54317: 03/04/08: Re: help with DLL problem in Spartan2E
    54366: 03/04/09: Re: OK, where does an FPGA newbie start?
    54367: 03/04/09: Re: Power Supply for Spartan II FPGA
Ray Heasman:
    4016: 96/09/03: Re: query: C to FPGA?
    4132: 96/09/17: Re: ? C to FPGA
    4151: 96/09/19: Are there any FPGA Starter Kits?
Ray Liang:
    46236: 02/08/22: Re: onboard reconfiguration of Xilinx FPGA
Ray Morales:
    40254: 02/03/03: max3000a odd behavior -- is the bug in my vhdl code? help!
    40271: 02/03/04: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
    40285: 02/03/04: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
Ray Saarela:
    2001: 95/09/30: FlexLogic download cable/schematics for one ?
    2054: 95/10/06: Sockects for AMD MACH-445 anywhere ?
    2128: 95/10/18: Re: Programming AMD Mach Parts
<ray.delvecchio@gmail.com>:
    123995: 07/09/10: VHDL Synthesis Error
ray.frost:
    38703: 02/01/22: vhdl code example required - x186 uC bus interfacing
<ray@desinformation.de>:
    114441: 07/01/16: Re: Digital Filter and external PLL (VCO)
    116452: 07/03/09: Re: Xilinx Spartan DCM jitter spectrum
    117189: 07/03/26: Delta Sigma A/D's integrated in FPGA's
    125671: 07/10/31: Re: Ping Jim: The PFD is dead!
<raybakk@yahoo.no>:
    87784: 05/08/01: GNU Linker (MicroBlaze) / debugging problem
    91246: 05/11/02: ChipScope on ML401 kit
    91247: 05/11/02: Re: ChipScope on ML401 kit
Rayees:
    136185: 08/11/04: Help Me Plz
    136211: 08/11/06: How SPI Flash UserData is Accessed?
rayjune:
    88504: 05/08/20: Could you tell me some other good forums or website related?
Raymond:
    92281: 05/11/25: EDK from ISE
    93328: 05/12/19: ISE project with a Microblaze submodule: timing constrains warning
    93381: 05/12/21: exception (0xe06d7363) when creating a MicroBlaze from the ISE environment
    96257: 06/02/01: Maximum system frequency on FPGA/CPLD
    97962: 06/03/02: I want to use UltraEdit as a text editor for ISE
    98839: 06/03/16: replacement of opb_mdm core for ML401 kit: opb_mdm_v2_01_a
    99309: 06/03/22: Problem with LwIP and MicroBlaze
    99343: 06/03/23: Re: Problem with LwIP and MicroBlaze
    99588: 06/03/27: Re: Problem with LwIP and MicroBlaze
    102064: 06/05/10: Unable to debug MicroBlaze in SDK (Eclipse) and the Software debugger
    102840: 06/05/22: Unknown Processor Version (8)
    102908: 06/05/23: Re: Unknown Processor Version (8)
    102909: 06/05/23: OPB Timer MicroBlaze
    102910: 06/05/23: Re: Unknown Processor Version (8)
    102918: 06/05/23: Re: OPB Timer MicroBlaze
    106689: 06/08/17: FFT on an FPGA
    106711: 06/08/17: Re: FFT on an FPGA
    106713: 06/08/17: Re: FFT on an FPGA
    106798: 06/08/19: Warningmessage in ISE
    106811: 06/08/20: Re: Warningmessage in ISE
    106824: 06/08/20: Re: Warningmessage in ISE
    106844: 06/08/20: Re: Warningmessage in ISE
Raymond Bakken:
    85499: 05/06/10: Building a MicroBlaze from scratch, unable to run.
    85508: 05/06/10: A lot of trouble when trying to debug c code on MicroBlaze
    85643: 05/06/13: trouble trying to debug c code on MicroBlaze
Raymond Chiu:
    11738: 98/09/05: 22V10 programming
    11745: 98/09/06: Re: 22V10 programming
    11777: 98/09/08: Re: 22V10 programming
    11778: 98/09/08: Re: 22V10 programming
Raymond Chow:
    29144: 01/02/07: Xilinx vs Altera
Raymond E. Rogers:
    7273: 97/08/20: Re: FPGA prototyping board
    8462: 97/12/17: Re: FPGA Prototyping on the ISA Bus
Raymond Gaita:
    3950: 96/08/24: Re: Interesting Xilinx XACT observation.
    3951: 96/08/24: Re: Striphex Utility
    4114: 96/09/12: Re: PCI Bus Protocal & FPGA vendors
    4120: 96/09/13: Re: PCI Bus Protocal & FPGA vendors
    48740: 02/10/23: Re: LCD driver implement with FPGA
Raymond K. Petry:
    2543: 95/12/30: Re: [q][Reverse Engineering Protection]
Raymond Wiker:
    152347: 11/08/11: Re: Xilinx Coregen, command not found java error
Raymund Hofmann:
    77370: 05/01/05: Re: Using LM317S adjustable linear regulator for Spartan 3?
    90256: 05/10/07: Re: Question about metastability that's been on my mind for a while
    90286: 05/10/08: Re: Question about metastability that's been on my mind for a while
    90295: 05/10/09: Re: Question about metastability that's been on my mind for a while
    91108: 05/10/29: Spartan3 DFS & DLL Behaviour
    92005: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
    92469: 05/11/30: Re: Why Spartan-3e is the best
    92617: 05/12/02: Re: Spartan3E availability update
    96568: 06/02/06: Re: FPGA growth vs. ASIC growth
    96569: 06/02/06: Re: FPGA growth vs. ASIC growth
    96719: 06/02/09: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
    146029: 10/03/04: Re: Modelsim PE vs. Aldec Active-HDL (PE)
    146087: 10/03/05: Re: Tabula. (FPGA start up)
    146120: 10/03/05: Re: Display Control Application Using Spartan FPGA
    146318: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
    146352: 10/03/13: Re: Tier Logic introduces the world's first 3D FPGA
    149954: 10/12/03: Re: Opinions on Lattice ECP3
    149971: 10/12/04: Re: : The Danger of When Programmable Logic Meets the Consumer Market
raymund hofmann:
    51407: 03/01/13: Re: filter coefficient multiplication in vhdl
    54034: 03/03/31: Re: Xilinx announces 90nm sampling today!
    56390: 03/06/04: Re: DES-encrypt, Spartan3, was Re: FPGA's an Flash
    56440: 03/06/05: Re: DES-encrypt, Spartan3, was Re: FPGA's an Flash
    67405: 04/03/11: Quartus II 3.0 sp1 web, verilog input, memories optimized away ?
<rayzengyan@gmail.com>:
    139980: 09/04/21: Re: source for Spartan 3E chips
RAZ Semiconductors:
    10747: 98/06/15: Do You need any components
    10765: 98/06/17: Re: Do You need any components
razzy:
    153478: 12/03/07: Re: Virtex 6 System Monitor sensor readings in ChipScope gives weird
<razzy2@gmail.com>:
    127411: 07/12/21: Re: sampling error between 2 clocks
rbal:
    114471: 07/01/17: running applications from external memory
    114560: 07/01/19: Re: running applications from external memory
<rbblasco@gmail.com>:
    116527: 07/03/12: Estimating number of FPGAs needed for an application
<rbmm756@gmail.com>:
    120855: 07/06/19: How do i add my IP to EDK?
RBowoo:
    25020: 00/08/24: CHANGE $6 INTO $3500
<rbrooks1@my-dejanews.com>:
    12609: 98/10/20: FS: CAD & SW DEV
rburns1@ticnet.com:
    16011: 99/04/27: MII/RMII and UTOPIA/UTOPIA2 in FPGAs
RBW:
RC:
    52353: 03/02/07: Multicontext FPGA
rc0:
    155208: 13/06/07: Mentor Graphics Precision RTL + LatticeECP3 Versa
    155209: 13/06/07: Mentor Graphics Precision RTL + LatticeECP3 Versa
<rc0clx@gmail.com>:
    155275: 13/06/21: Equivalent .tdf file in Aldec Active-HDL?
rcarlson:
    77286: 05/01/03: Re: Recover FPGA Verilog or VHDL source from .SOF file
Rcat1204:
    27469: 00/11/23: work from home
<rcgipson@ix.netcom.com>:
    5771: 97/03/13: pld 74hc195 equiv
RCI111:
    4462: 96/11/01: FPGA Demonstration Board
RCIngham:
    106696: 06/08/17: Re: FFT on an FPGA
    113480: 06/12/14: Re: FPGA : Async FIFO, Programmable full
    113481: 06/12/14: Re: How does FPGA tools infer FIFO
    113482: 06/12/14: Re: Can I see the detail timing parameter by Quartus II tools?
    113518: 06/12/15: Re: FPGA : LIFO
    113519: 06/12/15: Re: Writing output signals to text file (VHDL)?
    113520: 06/12/15: Re: Resource estimation
    121384: 07/07/03: Re: Multiplier in Xilinx
    121596: 07/07/09: Re: Error message in ModelSIM PE
    121789: 07/07/13: Re: highly-parallel highspeed connection between two FPGA boards
    121967: 07/07/16: Re: 1ms delay in V5 FPGA
    122092: 07/07/19: Re: BD
    122095: 07/07/19: Re: or1200 uses more than 100% of resources. how to reduce?
    122139: 07/07/20: Re: Can multiple Ferrite Beads be used to connect ...?
    123061: 07/08/15: Re: Multiplication Problem on Microblaze Software
    123063: 07/08/15: Re: DDR/DDR2 controller - core
    123065: 07/08/15: Re: ChipHit: ASIC, FPGA, EDA Search Engine
    123266: 07/08/22: Re: Globally Asynchronous in FPGA
    123344: 07/08/24: Re: Annoying
    123345: 07/08/24: Re: Speed test between FPGA and DSP or PC.
    124265: 07/09/17: Re: overloading ' operators in VHDL
    124297: 07/09/18: Re: Tristate bus on spartan FPGA
    125117: 07/10/16: Re: FPGA to FPGA Bus
    125375: 07/10/24: Re: Addresses of subsystems
    125417: 07/10/25: Re: builing a SPI interface in vhdl
    125615: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
    125618: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
    125667: 07/10/31: Re: Updating my bookshelf
    125737: 07/11/02: Re: Another way to handle floating inputs.
    125788: 07/11/05: Re: Global Variables
    125789: 07/11/05: Re: Another way to handle floating inputs.
    125895: 07/11/08: Re: Maximum current drive according to datasheet ?!
    126288: 07/11/19: Re: VHDL language is out of date! Why? I will explain.
    126418: 07/11/21: Re: VHDL language is out of date! Why? I will explain.
    126614: 07/11/28: Re: What tools do you use ? Why ?
    126727: 07/11/30: Re: Global Reset using Global Buffer
    126728: 07/11/30: Re: Pipelining of FPGA code
    126814: 07/12/03: Re: lossless compression in hardware: what to do in case of uncompressibility?
    126874: 07/12/05: Re: clock cycle per Instructions
    126935: 07/12/06: Re: converting verilog to vhdl
    126963: 07/12/07: Re: converting verilog to vhdl
    127080: 07/12/11: Re: sobel in vhdl
    127113: 07/12/12: Re: Initializing Micron DDR2 Memory
    127315: 07/12/18: Re: multidimensional arrays in VHDL?
    127324: 07/12/18: Re: multidimensional arrays in VHDL?
    127352: 07/12/19: Re: sampling error between 2 clocks
    127398: 07/12/20: Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
    127399: 07/12/20: Re: What is
    128162: 08/01/17: Re: effect of xray on fpga electronic circuits
    128228: 08/01/18: Re: Using PECL inputs and PLL's in ProASIC Plus.
    128554: 08/01/30: Re: question on record types
    128604: 08/01/31: Re: FPGA in Telecommunications
    128605: 08/01/31: Re: Design security for pre-Virtex2 parts ?
    128694: 08/02/04: Re: Scaling data
    128745: 08/02/05: Re: Sythesisable subset of VHDL
    128975: 08/02/12: Re: ModelSim versus Active-HDL....redux
    128976: 08/02/12: Re: Unsigned to signed vector.
    129052: 08/02/13: Re: State machine outputs and tri-state
    129093: 08/02/14: Re: Is a FPGA the solution ?
    129103: 08/02/14: Re: signal generation in VHDL on FPGA.... Check my code please
    129374: 08/02/22: Re: Random Number Generation in VHDL
    129493: 08/02/26: Re: Synthesis of functions in Quartus
    129586: 08/02/28: Re: DSP newbie
    131107: 08/04/11: Re: why to trigger a NMI error after just receiving 35 pakcets?
    131196: 08/04/15: Re: Which to learn: Verilog vs. VHDL?
    131252: 08/04/17: Re: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?
    131466: 08/04/22: Re: Newbie: Testbench question
    131790: 08/05/02: Re: asic gate count
    132760: 08/06/06: Re: Compare and update in same clock cycle synthesis problem
    132897: 08/06/10: Re: FSM running with unstable clock
    132989: 08/06/12: Re: where is the IP address assigned to the fpga in Trimode Ethernet MAC Core???
    133008: 08/06/13: Re: HELP: a Funny asynchronous input design
    133099: 08/06/18: Re: Cadence offers to buy Mentor Graphics for $1.45B
    133100: 08/06/18: Re: Fixed point number hardware implementation
    133274: 08/06/23: Re: FPGA based database searching
    133773: 08/07/14: Re: Why cant XST sythesis this piece of code
    133816: 08/07/16: Re: unified protocol
    133845: 08/07/17: Re: unified protocol
    133990: 08/07/21: Re: audio serial port i2s
    134077: 08/07/24: Re: SD Card Controller
    134093: 08/07/25: Re: SD Card Controller
    134149: 08/07/28: Re: SD Card Controller
    134302: 08/08/05: Re: vhdl or verilog code for 64 point ifft
    134316: 08/08/06: Re: Altera sues Zilog - signs of desperation from Programmable Vendor ?
    134689: 08/08/26: Re: Verification methods importance
    134793: 08/09/01: Re: How many mux input on a Xilinx V4 are pratical
    134945: 08/09/08: Re: Signed multiplication
    135002: 08/09/10: Re: Can Soft microprocessor replace DSP's
    135098: 08/09/16: Re: Xilinx FFT core configured in natural order
    135156: 08/09/18: Re: security system password by voice recognition commands
    135395: 08/09/30: Re: if data moves faster faster than the Clock....
    135517: 08/10/06: Re: Barrel Shifter: Newbie's Attempt
    135518: 08/10/06: Re: A question about the use of FPGA
    136054: 08/10/29: Re: I need a good reference for VHDL
    137308: 09/01/08: Re: Which revision control do fpga designers use (2009)
    137367: 09/01/12: Re: what is the difference between two process model & one process model
    137380: 09/01/13: Re: PCIe endpoint instantiation - beginner
    137398: 09/01/14: Re: effect of channel capacity on hamming code
    138074: 09/02/05: Re: dual processor PC for PPR - are they worth the extra cost?
    138075: 09/02/05: Re: Core interface protocol
    138282: 09/02/12: Re: Implementing reset / enable in FPGA question
    139322: 09/03/26: Re: Fm digital baseband demodulation
    139846: 09/04/16: Re: reset & analog circuits
    141210: 09/06/11: Re: opencores shut down?
    143856: 09/10/30: Re: Best way to model a large external ROM in a simulation? (XST simulator)
    144388: 09/12/03: Re: This works, this does not... why?
    144831: 10/01/07: Re: ASM hardware language definition file for Altera/Xilinx
    144835: 10/01/07: Re: ADC problem on spartan3E
    144840: 10/01/07: Re: ASM hardware language definition file for Altera/Xilinx
    144919: 10/01/15: Re: SystemVerilog Verification Example using Quartus and ModelSim
    145134: 10/01/29: Re: E1 clock problem with Spartan3e...
    145206: 10/02/01: Re: Single Port Rom created by Core Generator configurable by generic values!!!!
    145234: 10/02/02: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for ?RS232 communication?
    145272: 10/02/04: Re: Board layout for FPGA
    145430: 10/02/09: Re: Board layout for FPGA
    145479: 10/02/11: Re: Multple architectures in ISE top level module?
    145589: 10/02/15: Re: To get higher clock frequencies at output using propagation delays.
    145649: 10/02/17: Re: what is incorrect about my usage of array with port entity?
    145697: 10/02/19: Re: System design in FPGA
    145749: 10/02/22: Re: FPGA platform??
    145827: 10/02/25: Re: EDK spi ip core
    145828: 10/02/25: Re: Altera data sheets.
    147059: 10/04/12: How to find latches in Xilinx ISE 10.1
    147062: 10/04/12: Re: How to find latches in Xilinx ISE 10.1
    147073: 10/04/13: Re: How to find latches in Xilinx ISE 10.1
    147077: 10/04/13: Re: How to find latches in Xilinx ISE 10.1
    147100: 10/04/14: Re: Implementing bidirectional bus inside the FPGA
    147101: 10/04/14: Re: Read from the compact flash
    147105: 10/04/14: Re: Implementing bidirectional bus inside the FPGA
    147425: 10/04/27: Re: Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface
    147804: 10/05/25: Re: MIG v3.0 inputs signal
    148044: 10/06/16: Re: Decoupling for Altera Cyclone II 2C8
    148240: 10/07/01: Re: Xilinx BULLSHITIX-8, when?
    148698: 10/08/18: Re: VDHL initializing
    148742: 10/08/19: Re: FPGA PCI BOARD .. Few Questions
    148786: 10/08/24: Re: Xilinx Xcell Journal Issue 72 Now available
    148790: 10/08/24: Re: Text compression Huffman Encoder and Decoder
    148837: 10/09/01: Re: Want to get into FPGA
    148841: 10/09/02: Re: parsing script arguments in QuestaSim/ModelSim
    148970: 10/09/16: Re: FPGA speech recongintion system
    149176: 10/10/06: Re: Starting a career with FPGAs
    149206: 10/10/07: Re: help with bad synchronous description error
    149252: 10/10/12: Re: JTAG stops working!
    149290: 10/10/14: Re: change with sums and shifts
    149378: 10/10/20: Re: Designing for Xilinx Spartan in 2010?
    149482: 10/10/29: Re: encrypted bitstream
    149760: 10/11/23: Re: Synthesis/place and route with Solid-State Drives
    149778: 10/11/24: Re: minimum clock period of a combinational circuit
    149994: 10/12/06: Re: FSM single process...BIG question
    150042: 10/12/07: Re: Interconnection of multiple cores
    150043: 10/12/07: Re: Concurrent Logic Timing
    150053: 10/12/08: Re: Concurrent Logic Timing
    150156: 10/12/21: Re: using a cordic on EDK
    150246: 11/01/05: Re: Dual port Ram
    150347: 11/01/11: Re: FPGA to PHY/MAC chip
    150348: 11/01/11: Re: Error in Clock Divider!
    150350: 11/01/11: Re: deconvolution
    150547: 11/01/26: Re: ISE 12.4
    150552: 11/01/26: Re: FPGA changes behaviour when the resource's usage percentage changes
    150554: 11/01/26: Re: FPGA changes behaviour when the resource's usage percentage changes
    150558: 11/01/26: Re: FPGA changes behaviour when the resource's usage percentage changes
    150660: 11/02/01: Xilinx Acquires AutoESL
    150672: 11/02/02: Re: PCI Express Transfer
    150682: 11/02/03: Re: Dynamic Voltage switching for FPGA IO
    150757: 11/02/09: Re: FPGA changes behaviour when the resource's usage percentage changes
    150764: 11/02/09: Re: Trivia: Where are you on the HDL Map?
    150822: 11/02/15: Re: why an FSM is not a counter?!
    150843: 11/02/16: Re: Regarding passing a control signal from fast to slow cloak domain
    150908: 11/02/21: Re: Mathematical definition of an FPGA
    150952: 11/02/24: Re: Simulating mutiplication of 'X' with '0'
    150953: 11/02/24: Re: timing issues at high speed
    150954: 11/02/24: Re: How to build a VHDL package in order to use it in other projects.
    150956: 11/02/24: Re: XST returning error code on success?
    151024: 11/03/01: Re: encryption in FPGA
    151047: 11/03/02: Re: encryption in FPGA
    151049: 11/03/02: Re: iir filter
    151131: 11/03/09: Re: Anti-benchmarking clauses
    151132: 11/03/09: Re: Pull up/down resistors on Spartan-3E configuration inputs
    151137: 11/03/10: Re: pcb&bitstream
    151177: 11/03/14: Re: pcb&bitstream
    151220: 11/03/16: Re: ping pong buffer overflow issue
    151334: 11/03/24: Re: SRL as a synchroniser
    151382: 11/03/31: Re: EDK - program behavior
    151532: 11/04/18: Re: [MODELSIM] How to add signals to wave which is a child of the module being tested?
    151533: 11/04/18: Re: same RTL on two same boards giving different behaviour
    151555: 11/04/19: Re: How to add signals to wave which is a child of the module being tested?
    151567: 11/04/20: Re: Help with Assinc counter
    151577: 11/04/21: Re: Help with Assinc counter
    151623: 11/04/27: Re: about slices in xilinx
    151669: 11/05/04: Re: Svar: Is fixed point (ieee_proposed.fixed_pkg_c) supported by XST for Xilinx DS 12.4
    151682: 11/05/05: Re: ise 10.1 (Linux) contraints problem
    151721: 11/05/10: Re: fpga
    151912: 11/06/03: Re: FFT using logic gates only
    151914: 11/06/03: Re: verilog task and vhdl
    151930: 11/06/08: Re: FFT using logic gates only
    151932: 11/06/08: Re: multiplication in indexation
    151958: 11/06/15: Re: What is the advantage of source-syncronization (in SDRAMs)?
    151959: 11/06/15: Re: Area Optimization
    151965: 11/06/15: Re: Determine latency of GTX links vs Aurora+LVDS
    151966: 11/06/15: Re: What is the advantage of source-syncronization (in SDRAMs)?
    152024: 11/06/23: Re: P&R based on the post-map simulation model?
    152046: 11/06/27: Re: digitization of sensor array
    152049: 11/06/28: Re: XST 13.1 explodes with generic of enum type with only one member
    152103: 11/07/07: Re: Verilog Custom Core To Read and Write From RAM
    152140: 11/07/13: Re: FSL Problem:Data Return and Use
    152141: 11/07/13: Re: Looking for a FPGA board
    152151: 11/07/14: Re: FSL Problem:Data Return and Use
    152246: 11/07/27: VHDL horror in Xcell 76
    152247: 11/07/27: Re: VHDL horror in Xcell 76
    152273: 11/08/01: Re: Pipeline stages of the Multiplier core (ISE Coregen)
    152274: 11/08/01: Re: die's in different packages
    152282: 11/08/03: Re: VHDL horror in Xcell 76
    152305: 11/08/05: Re: image storing into BRAM
    152553: 11/09/14: Re: FPGA acceleration v.s. GPU acceleration
    152574: 11/09/15: Re: CONSTRAINTS
    152680: 11/09/27: Re: Implementation Issue
    152711: 11/10/05: Re: Testbench
    152715: 11/10/06: Re: VHDL connection problem
    152716: 11/10/06: Re: Xilinx EDK: XPS netlist combination error
    152731: 11/10/13: Re: Spartan changes in glitch sensitivity
    152744: 11/10/17: Re: Spartan changes in glitch sensitivity
    152747: 11/10/18: Re: Doulos training courses at Xilinx
    152767: 11/10/20: Re: Peter Alfke has passed away
    152810: 11/10/25: Re: Reference books on microprocessor design with VHDL
    152825: 11/10/26: Re: newable need help
    153049: 11/11/23: Re: RTOS with support for TCP/IP sockets on Spartan 3E
    153102: 11/11/30: Re: Classic Disk Drive simulation and binary file IO.
    153126: 11/12/08: Re: DDR2 read interface
    153140: 11/12/12: Re: Need Clocked 1.5+Ghz LVDS buffer. Or bright ideas!
    153141: 11/12/12: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
    153167: 11/12/22: Re: Equivalence between
    153188: 12/01/05: Re: Beginner question on FIFO in
    153277: 12/01/24: Re: Semi-OT: Good Tcl Book
    153308: 12/01/30: Re: Design Notation VHDL or Verilog?
    153318: 12/01/31: Re: =?ISO-8859-1?Q?Post-synth=E8se_simulation?=
    153355: 12/02/06: Re: Xilinx Artix-7 availability
    153428: 12/02/23: Re: What is a PLD/FPGA with serial or Ethernet port logic or block built in
    153430: 12/02/23: Re: What is a PLD/FPGA with serial or Ethernet port logic or block built in
    153448: 12/02/27: Re: Strassen algorithm in vhdl
    153476: 12/03/07: Re: FPGA Area
    153550: 12/03/27: Re: FPGA communication with a PC (Windows)
    153767: 12/05/16: Re: FDE vs latch?
    153779: 12/05/17: Re: Xilinx ISE Multiple Drivers Error
    153803: 12/05/24: Re: Logic Glitches in Spartan-3?
    153814: 12/05/25: Re: Logic Glitches in Spartan-3?
    153819: 12/05/28: Re: Read output from external chip using microblaze
    153893: 12/06/25: Re: What are differences between IBUF and IBUFDS inferred and implemented for differential input signals?
    153898: 12/06/26: Re: Read output from external chip using microblaze
    154037: 12/07/18: Re: use differential I/O simultaneously
    154924: 13/02/15: ModelSim version numbers
    155135: 13/04/25: Re: Modelsim ought to be cheaper
    155152: 13/05/09: Any experience of Equivalence Checking tools?
    155162: 13/05/15: Linting tool setup
    155164: 13/05/16: Re: Linting tool setup
    155169: 13/05/22: Re: Linting tool setup
    155170: 13/05/22: Re: XILINX Artix-7 DDR2-RAM-Controller
    155179: 13/05/23: Re: Die size of BRAM/DSP48 in CLBs
    155218: 13/06/12: Re: problem with the GTX wrapper in questa
    155356: 13/06/24: Re: FPGA Exchange
    155429: 13/06/27: Re: FPGA Exchange
    155433: 13/06/28: Re: FPGA Exchange
    155434: 13/06/28: Re: New soft processor core paper publisher?
    155551: 13/07/18: Metastability mitigation and I/O registers
    155568: 13/07/22: Re: Metastability mitigation and I/O registers
    155577: 13/07/23: Re: Metastability mitigation and I/O registers
    155643: 13/07/31: Re: serial protocol specs and verification
    155658: 13/08/01: Re: serial protocol specs and verification
    155659: 13/08/01: Re: seperate high speed rules for HDL?
    155675: 13/08/02: Re: serial protocol specs and verification
    155688: 13/08/05: Re: serial protocol specs and verification
    155696: 13/08/08: Re: [cross-post] vlib, vmap, vcom, how it all works...
    155699: 13/08/09: Re: [cross-post] vlib, vmap, vcom, how it all works...
    155708: 13/08/12: Re: [cross-post] vlib, vmap, vcom, how it all works...
    155710: 13/08/13: Re: [HELP]problem with asynchronous fifo ip
    155712: 13/08/13: Re: [HELP]problem with asynchronous fifo ip
    155714: 13/08/14: Re: [HELP]problem with asynchronous fifo ip
RCSTWKS:
    6831: 97/07/01: Fast Turbo-Fault Simulator
    7182: 97/08/11: *Fast Fault Simulation*
    7811: 97/10/17: Fast Fault Simulation
RCU:
    47564: 02/09/29: Getting started
    47582: 02/09/29: Re: Getting started
    47657: 02/10/01: Re: Getting started
rcumplido:
    80273: 05/03/03: re:References for FPGA implementation of OS-CFAR
<rdeux@team-usa.com>:
    2035: 95/10/04: Consultant Needed
RDR:
    28814: 01/01/25: XC7272 vers XC9272.
    28849: 01/01/26: Re: XC7272 vers XC9272.
rduar002:
    148120: 10/06/22: SDRAM capacity using Petalinux
Re:
    50048: 02/11/29: R: SDRAM technology
Re Pas:
    58244: 03/07/17: Novice question...FPGA driver type
<reachranbir@gmail.com>:
    80067: 05/03/01: SoC positions in Bangalore
    80410: 05/03/04: Re: SoC positions in Bangalore
    80411: 05/03/04: Planning to Build Complex Wireless SoC...Anybody interested??
    80412: 05/03/04: Re: SoC positions in Bangalore
reactgary:
    75428: 04/11/05: Question abut ISE
Readon:
    125891: 07/11/08: FIFO interface design
    125918: 07/11/09: Re: FIFO interface design
    125958: 07/11/10: Re: FIFO interface design
Real SoPC New-Be:
    141041: 09/06/03: Xilinx ISE doesn't recognize a signal added in Xilinx Platform Studio
    141054: 09/06/03: Re: Xilinx ISE doesn't recognize a signal added in Xilinx Platform
Reala:
    45018: 02/07/10: 32 bit multiplier (1 cycle)
    45021: 02/07/10: Re: 32 bit multiplier (1 cycle)
    45045: 02/07/11: Re: 32 bit multiplier (1 cycle)
    45089: 02/07/12: How to develop a MCU?
    45230: 02/07/17: I would like to know how to develop a MCU.
    45281: 02/07/18: Re: I would like to know how to develop a MCU.
    45282: 02/07/18: Re: I would like to know how to develop a MCU.
    45416: 02/07/23: Translate the design from FPGA to Custom IC
    45419: 02/07/23: 16 X 16 multplier
    45423: 02/07/23: Re: Translate the design from FPGA to Custom IC
    45455: 02/07/24: Re: Translate the design from FPGA to Custom IC
    45505: 02/07/25: Re: Translate the design from FPGA to Custom IC
    45515: 02/07/25: Re: Translate the design from FPGA to Custom IC
    45766: 02/08/05: modelsim XE starter
    45790: 02/08/06: IC design Tools
    45884: 02/08/09: I would like to find some resource for IC layout
    45935: 02/08/12: Synthesis Verilog to ASIC
    45969: 02/08/13: Re: Synthesis Verilog to ASIC
    46006: 02/08/14: Re: Synthesis Verilog to ASIC
    46028: 02/08/15: Re: Synthesis Verilog to ASIC
    46127: 02/08/20: INOUT port
    46128: 02/08/20: debug for internal node
    46216: 02/08/22: Re: INOUT port
    46217: 02/08/22: Re: INOUT port
    46593: 02/09/04: Any resource about MCU and DSP
    46602: 02/09/04: Question for Verilog
    47177: 02/09/20: IC layout
    47456: 02/09/26: Re: IC layout
    48701: 02/10/23: LCD driver implement with FPGA
    48711: 02/10/23: Re: LCD driver implement with FPGA
    48766: 02/10/24: Re: LCD driver implement with FPGA
RealInfo:
    131499: 08/04/23: FPGA comeback
    131502: 08/04/23: Re: FPGA comeback
    131695: 08/04/29: Re: FPGA comeback
    133045: 08/06/16: WARP
    133057: 08/06/17: Re: WARP
    133071: 08/06/17: Re: WARP
    133090: 08/06/18: Xilinx Webpack
    137054: 08/12/21: FPGA for Contoll
    137058: 08/12/21: Re: FPGA for Contoll
    137143: 08/12/28: FPGA > ASIC
    137149: 08/12/28: Re: FPGA > ASIC
    137156: 08/12/29: DIP PACKAGE ?
    148834: 10/09/01: Want to get into FPGA
    149948: 10/12/03: FPGA BOARD QUESTION
<realmoney@pobox.com>:
    8880: 98/02/05: Make US$30,000 With 1 Phone Call!!!
realo:
    59910: 03/09/01: Re: Different types of ASICs?
realwood:
    145046: 10/01/22: offset constrain report confusion
    145068: 10/01/24: Re: offset constrain report confusion
    145085: 10/01/26: Re: offset constrain report confusion
    145199: 10/02/01: Re: offset constrain report confusion
rebai chiheb:
    30881: 01/05/02: failed to configure virtex
Rebecca:
    116289: 07/03/06: Routing problem of DCM
    116338: 07/03/07: Re: Routing problem of DCM
    116343: 07/03/07: Re: Routing problem of DCM
    116364: 07/03/07: Re: Routing problem of DCM
    116480: 07/03/09: Re: Routing problem of DCM
    116699: 07/03/15: ChipScope problem: "Waiting for core to be armed".
    116700: 07/03/15: Re: ChipScope problem: "Waiting for core to be armed".
    116701: 07/03/15: Re: ChipScope problem: "Waiting for core to be armed".
    116707: 07/03/15: Re: ChipScope problem: "Waiting for core to be armed".
    116784: 07/03/18: Re: ChipScope problem: "Waiting for core to be armed".
    118207: 07/04/19: Question about reset signal for several DCMs in EDK design.
    118249: 07/04/20: Re: Question about reset signal for several DCMs in EDK design.
    118262: 07/04/20: Question about intalling EDK9.1i
    118356: 07/04/24: EDK Simulation library compilation wizard can't find modelsim
    118357: 07/04/24: The simulation library compilation wizard of EDK can't find modelsim
    118431: 07/04/26: Re: EDK Simulation library compilation wizard can't find modelsim
    118432: 07/04/26: Re: The simulation library compilation wizard of EDK can't find modelsim
    118437: 07/04/26: Re: The simulation library compilation wizard of EDK can't find modelsim
    118443: 07/04/26: Question about the simulation library in EDK
    118445: 07/04/26: Question about the simulation library in EDK
    118447: 07/04/26: Question about the simulation library in EDK
    118476: 07/04/27: Re: Question about the simulation library in EDK
    118492: 07/04/27: Re: Question about the simulation library in EDK
    125451: 07/10/25: Question about the clocks power in XPower.
    127260: 07/12/16: =?ISO-8859-1?Q?Why_the_core_dynamic_power_isn't_0_when_the_toggle?=
    127275: 07/12/16: Re: Why the core dynamic power isn't 0 when the toggle rate is 0
    127276: 07/12/16: Re: Why the core dynamic power isn't 0 when the toggle rate is 0
    127295: 07/12/17: Re: Why the core dynamic power isn't 0 when the toggle rate is 0
    140911: 09/05/29: Question about SERR of Xilinx PCIE core.
Rebecca Selkregg:
recoder:
    127425: 07/12/23: video capturing+ filter + vga output
    128158: 08/01/17: effect of xray on fpga electronic circuits
    132148: 08/05/15: Open source Core generators?
    140267: 09/05/07: board with 2 gigabit ethernet connectors?
    141168: 09/06/10: IF board for fpga?
    141453: 09/06/24: 720 Mhz IF Processing
    141464: 09/06/25: Re: 720 Mhz IF Processing
    141476: 09/06/25: Re: 720 Mhz IF Processing
    141510: 09/06/26: Re: 720 Mhz IF Processing
recover back up:
    82927: 05/04/19: Recover back up
Recruit Express:
    26552: 00/10/20: Off subject-FPGA DESIGNERS for new PDA start up in San Jose
    26641: 00/10/23: Off subject-WIRELESS H/W S/W - pre IPO - San Jose
    27051: 00/11/08: Off subject-WIRELESS H/W S/W - pre IPO - San Jose
    27280: 00/11/17: Off subject-WIRELESS H/W S/W - pre IPO - San Jose
    27641: 00/12/01: Off subject-WIRELESS H/W S/W - pre IPO - San Jose
Recruit FPGA engineer:
    154141: 12/08/20: recruit FPGA design engineer in Scotland
<recruiterm2@my-deja.com>:
    21223: 00/03/10: Digital Design Engineer Job
Red Sleepy:
    15: 94/07/28: Re: FPGA based processors ?
Reda Roushdy El-Masry:
    8081: 97/11/16: I need Help
redbelly:
    108028: 06/09/04: Re: Please help me with (insert task here)
<redbens@my-deja.com>:
    21968: 00/04/10: setup and hold time violation
Reddy:
    78766: 05/02/07: comp.arch.fpga : Generate libraries and BSP`s
REDDY PRASAD REDDY:
    151020: 11/02/28: encryption in FPGA
redpumice:
    140147: 09/04/30: Re: FPGA simulator for face recognition
RedskullDC:
    101793: 06/05/07: Re: Spartan 3e starter kit & Multimedia
    114655: 07/01/22: Re: digilent nexys vga glitches
    114715: 07/01/23: Re: digilent nexys vga glitches
    115769: 07/02/20: Re: Nexys from Digilent... aka, binge hacking
    115849: 07/02/22: Re: Cyclone II "altsyncram" timing constraints?
    121080: 07/06/25: Re: Control Panel application for Altera Cyclone II Starter Kit, help?
    121255: 07/06/29: Re: vista 64 bits
    123735: 07/09/03: Re: Low-level FPGA programming?
    124749: 07/10/03: Re: Basic VHDL Development kit
    127519: 08/01/01: Re: Sparkfun FPGA board ?
    136001: 08/10/27: Re: Any more news on an Windows x64-compatible WebPack?
    136002: 08/10/27: Re: S3E starter kit: LCD interface questions
    136212: 08/11/07: Re: Help Me Plz
    137379: 09/01/13: Re: Digilent Nexys 2 Issue
redstripe:
    97850: 06/02/28: FPGA communication, I2C and DAC
Reetinder P. S. Sidhu:
    6805: 97/06/29: EDIF for Xilinx tools
    6983: 97/07/18: FPGA design tools
    7043: 97/07/26: FPGA die photograph
    7872: 97/10/26: Parallel-Serial Convertors for XC6200
    7979: 97/11/05: Division using FPGAs
    11131: 98/07/20: XC6200 Behavioral Synthesis?
    11176: 98/07/22: Re: FFT in Xilinx FPGA
    11442: 98/08/13: XC6200 Inspector
    28270: 01/01/04: Nondeterministic FSMs in hardware?
    28317: 01/01/05: Update on nondeterministic FSMs in hardware
<referringto@googlemail.com>:
    130371: 08/03/21: Re: Designing CPU
    130383: 08/03/21: Re: Designing CPU
    130415: 08/03/22: Re: A Challenge for serialized processor design and implementation
    130435: 08/03/24: Re: A Challenge for serialized processor design and implementation
    130856: 08/04/03: Re: A Challenge for serialized processor design and implementation
    130857: 08/04/03: Re: A Challenge for serialized processor design and implementation
    130873: 08/04/03: Re: A Challenge for serialized processor design and implementation
Reg Edwards:
    23164: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
    95025: 06/01/20: Re: OT:Shooting Ourselves in the Foot
regal:
    27415: 00/11/21: Help :asynchronous Reset has no effect
    27441: 00/11/22: Re: Help :asynchronous Reset has no effect
<reganireland@gmail.com>:
    136612: 08/11/25: Deserializing Camerlink on Spartan XC3s400
    136623: 08/11/26: Re: Deserializing Camerlink on Spartan XC3s400
    136683: 08/11/30: Re: Deserializing Camerlink on Spartan XC3s400
    136716: 08/12/02: CameraLink Deserilization and Module Constraint Files
    136748: 08/12/03: Re: CameraLink Deserilization and Module Constraint Files
    136783: 08/12/04: XAPP485 Equivalent for Spartan 3
    137300: 09/01/07: Digilent Nexys 2 Issue
    137301: 09/01/07: Re: Digilent Nexys 2 Issue
    137415: 09/01/14: Re: Digilent Nexys 2 Issue
    137470: 09/01/18: Time to de-assert RAM for changing CLK
    137481: 09/01/19: Re: Time to de-assert RAM for changing CLK
    137484: 09/01/19: Camlink Deserialization XAPP485 Clocks
    137805: 09/01/29: DCM_SP locking
    137886: 09/02/01: Cameralink Big Help Needed
    137887: 09/02/01: Re: Cameralink Big Help Needed
    137941: 09/02/02: Re: Cameralink Big Help Needed
    138056: 09/02/04: Re: help in VHDL procedure programming
    138181: 09/02/08: ISIM and SDF Files
    138289: 09/02/12: MicroBlaze Programming
    138426: 09/02/22: Re: ERROR:Map:11 - serdes_4b_1to7_wrapper symbol "rx0" - more than
    138429: 09/02/22: Combining FPGA design with Microblaze
    138455: 09/02/23: Re: Combining FPGA design with Microblaze
    138985: 09/03/17: uB and external CPU communications
Regina Steurer-Hall:
    4515: 96/11/08: Altera contract in Orange County
ReginaHT:
    14840: 99/02/19: US-CA jobs/ASIC-SCSI engineer
Regis:
    152922: 11/11/01: Re: Fundamental DSP/speech processing patent for sale
    152943: 11/11/03: Re: Fundamental DSP/speech processing patent for sale
    152971: 11/11/07: Re: Fundamental DSP/speech processing patent for sale
    152993: 11/11/08: Re: Fundamental DSP/speech processing patent for sale
    152995: 11/11/09: Re: Fundamental DSP/speech processing patent for sale
Regis Caillet:
    25154: 00/08/29: Re: Vacancy at European Space Agency
regis robart:
    3752: 96/07/25: MACH AMD Serie Programing
Rego:
    157167: 14/10/23: Altera 100-pins chip
    157169: 14/10/23: Re: Altera 100-pins chip
regomodo:
    147884: 10/05/29: Re: Programming Digilent Nexys 2 from Linux
Rehan:
    84945: 05/06/01: Xilinx -- iMPACT -- Parallel Port [JTAG Cable] Cable connect
    84989: 05/06/02: re:Xilinx -- iMPACT -- Parallel Port [JTAG Cable] Cable connect
Rehman:
    128586: 08/01/31: Actel Fusion FPGA
    128626: 08/01/31: Re: Actel Fusion FPGA
    128778: 08/02/06: Re: Actel Fusion FPGA
    129154: 08/02/15: Re: signal generation in VHDL on FPGA.... Check my code please
Reid Porter:
    10152: 98/04/29: Hotworks G1 step clock
Reid Wender:
    12560: 98/10/16: Xilinx Virtex Experiences
reidek@gmail.com:
    92842: 05/12/07: Re: Embedded ppc405 w/o RAM?
    92845: 05/12/07: Re: Embedded ppc405 w/o RAM?
<reidek@gmail.com>:
    92832: 05/12/07: Embedded ppc405 w/o RAM?
Reiner Abl:
    61143: 03/09/29: Xilinx configuration
    61205: 03/09/30: Re: Xilinx configuration
    64021: 03/12/12: Microblaze interrupts
    64096: 03/12/16: Re: .elf to .bin file for microblaze
Reiner Hartenstein:
    6411: 97/05/22: Re: Scientific American article on FPGAs
    6537: 97/06/01: Re: Any designs to avoid in FPGAs
    6538: 97/06/01: Re: New Reconfigurable Computing newsgroup?
    14729: 99/02/13: Re: Supercomputer uses 280 Xilinx FPGAs
    22029: 00/04/14: Re: Java to HDL compiler, Free Beta
    22030: 00/04/14: Re: US - Engineering Opportunities in NH,MA,NJ,NY,CA
    22176: 00/04/28: which Conference Calendars on the web .... (FPL 2000)
    21958: 00/04/10: FPL 2000 -- Call for Exhibitors
    33516: 01/07/28: FPL 2001 - keynotes -- tutorials
    33562: 01/07/30: multi-context FPGA
Reiner Huober:
    18665: 99/11/05: Re: Analog FPGA ?!
    93238: 05/12/16: Re: Simulating CRC32 according to IEEE Std. 802.3
<reiner@hartenstein.de>:
    97352: 06/02/21: Re: Is FPGA code called firmware?
    111578: 06/11/06: Re: Scientific Computing on FPGA
    126489: 07/11/24: Re: VHDL language is out of date! Why? I will explain.
Reinhard:
    153862: 12/06/10: Reading out LUTM content
Reinhard Kopka:
    7538: 97/09/19: Re: Atmel 17256 serial config EEPROMs
    7539: 97/09/19: Altera FPGA - asynch serial
    7912: 97/10/29: Re: Internal tri-state emulation.
    8009: 97/11/07: Re: Digital reverberator on FPGA
Reinhold Schmidt:
    80507: 05/03/07: Re: Asynchronous processor !?!
Reinier:
    82517: 05/04/13: Flowcharts and diagrams
    82608: 05/04/14: Re: Flowcharts and diagrams
Reinoud:
    16820: 99/06/11: Re: Place & Route Xilinx F1.5 Student ed.
    16842: 99/06/14: Re: Place & Route Xilinx F1.5 Student ed.
    26814: 00/10/31: Re: How safe is the algorithm implemented with FPGA?
    28659: 01/01/20: Re: Virtex-II officially launched
    28719: 01/01/22: Re: VirtexII and high speed counter
    28878: 01/01/26: Re: 6845
    29439: 01/02/21: Xilinx tools: RLOC hierarchy with HDL design?
    29474: 01/02/22: Re: fpga from linux/hc11
    29556: 01/02/26: Linux Xilinx Programmer
    29570: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
    29571: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
    29586: 01/02/27: Re: Samll quantities ordering
    29837: 01/03/13: Low volume users (was: Re: VirtexE LVPECL I/O Ports? experience?)
    33971: 01/08/09: Announcing MPGA: an open source meta-FPGA
    34105: 01/08/14: A parallel port - low voltage signal interface (for new FPGAs)
    34243: 01/08/17: Re: hardware damage to a Virtex or Spartan-II?
    34289: 01/08/19: Re: hardware damage to a Virtex or Spartan-II?
    34765: 01/09/06: MPGA (open source meta-FPGA) mailing lists, forums
    35257: 01/09/27: Re: Virtex II current consumption
    36411: 01/11/08: Re: FPGA Wish list
    37050: 01/11/29: Re: Is there a full open-source synthesis path for any FPGA?
    37334: 01/12/07: Re: XC6200
<rekha.arun@gmail.com>:
    115338: 07/02/07: Re: Altera ByteBlaster and SignalTap on Fedora Core
rem:
    91827: 05/11/14: 64/65-octet encapsulation IP cores?
Remco:
    89371: 05/09/13: FIFO design using Virtex-II block ram..
    89406: 05/09/14: Re: FIFO design using Virtex-II block ram..
    89416: 05/09/14: Re: FIFO design using Virtex-II block ram..
Remco Poelstra:
    39080: 02/01/31: Xilinx XC3020-70
    39095: 02/01/31: Re: Xilinx XC3020-70
    40229: 02/03/02: What FPGA to use?
    40314: 02/03/05: Re: What FPGA to use?
Remek Lipinski:
    8633: 98/01/15: Using Xiling schematic library macro from VHDL
remi-seglie:
    34809: 01/09/08: Re: Orcad Symbol
Remis Norvilis:
    64671: 04/01/11: Re: Spartan-3 LC Development Kit from Insight (Memec)
    66141: 04/02/12: Verilog and VHDL mix
    67862: 04/03/21: Re: Spartan-3 DSL-KIT
    69082: 04/04/26: Re: Is Xilinx Parallel Cable III OK For Memec V2Pro / Xilinx EDK?
    69083: 04/04/26: Re: UART with FIFO -> CPLD / FPGA / ?
    90227: 05/10/06: Xilinx WebPack and command line
    90253: 05/10/07: Re: Xilinx WebPack and command line
    96856: 06/02/11: Re: SDRAM Controller
    98565: 06/03/12: Xilinx DDR SDRAM Controller
    107479: 06/08/29: Re: Spartan-4 ?
    107480: 06/08/29: Re: Spartan-4 ?
    116903: 07/03/20: Re: a project work
remis norvilis:
    64665: 04/01/10: Spartan-3 LC Development Kit from Insight (Memec)
<RemisN@gmail.com>:
    116953: 07/03/21: Re: softcore CPU tools
    117039: 07/03/22: Re: softcore CPU tools
    117052: 07/03/22: Re: softcore CPU tools
remoterecon:
    76610: 04/12/07: Xilinx's website
    76612: 04/12/07: Re: Xilinx's website
    77369: 05/01/05: Re: Whither common courtesy ?
<remove_spam_rprager@frequentis.com>:
    60499: 03/09/15: Quartus internal synthesis more verbose?
    62267: 03/10/23: Re: Several Quartus II 3.0 questions
<REMOVEldavis@spacey.net>:
    16224: 99/05/10: Re: BGA Prototyping ?
<Remy.thomas.38@gmail.com>:
    129584: 08/02/27: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a
<remy@provide.net>:
    11726: 98/09/04: Xilinx CLPD
Ren:
    42709: 02/05/01: Newbie--Where to start learning?
    42814: 02/05/03: Re: Newbie--Where to start learning?
Renaud Pacalet:
    17443: 99/07/28: Re: Problem with Max+PlusII / Flex10k
    24121: 00/07/27: Re: Which one is good coding style?
    24123: 00/07/27: Re: Which one is good coding style?
    29342: 01/02/15: Re: double precision floating point arithmetic
    31598: 01/05/31: Re: IEEE VHDL library support in HDL compilers
    33941: 01/08/09: Re: Generate constants with a function
    42369: 02/04/22: Re: Simulating Unisim
    43118: 02/05/14: Re: State machine synthesis
    45556: 02/07/26: Re: ALU in VHDL and a bunch of questions
renaux:
    34905: 01/09/13: Re: Block RAM initialization
    34906: 01/09/13: Re: convert
    34907: 01/09/13: Re: SOS : A Question about synthesizng ROM
    35082: 01/09/20: Re: C designs wanted
    35178: 01/09/25: ROM initialisation on Xilinx Virtex design
    35189: 01/09/25: Re: fir filter
    35334: 01/09/29: Re: fir filter
    35685: 01/10/13: Re: PWM Signal in VHDL ?
RENE:
    60754: 03/09/21: 1024 POINTS FFT V2.0 Xilinx Core
Rene:
    12010: 98/09/24: Re: easier testing for PCI cards??
    153691: 12/04/24: Re: Data Transfer from PC to FPGA through USB
Rene Bakker:
    4326: 96/10/16: Re: Xilinx xchecker.exe and Windows NT
    4334: 96/10/17: Re: Update on Atmel AT17C128 Problem
    4619: 96/11/21: Re: ViewLogic PRO series under win95
Rene Becker:
    13145: 98/11/17: Re: Synthesizeablel fifo
    13668: 98/12/17: Re: Problem with clock IOB placement
    16179: 99/05/07: Re: PCI slave in FPGA?
    16180: 99/05/07: Re: PCI slave in FPGA?
Rene Doesburg:
    36323: 01/11/06: External clock for Altera UP1 Board
Rene Kellenbach:
    10649: 98/06/09: How about Lattice ispLSI?
    10657: 98/06/09: Re: How about Lattice ispLSI?
    10675: 98/06/10: Re: How about Lattice ispLSI?
    10676: 98/06/10: Re: How about Lattice ispLSI?
    10686: 98/06/10: Re: How about Lattice ispLSI?
    10700: 98/06/11: Re: How about Lattice ispLSI?
    10701: 98/06/11: Re: How about Lattice ispLSI?
    10703: 98/06/11: Re: How about Lattice ispLSI?
    10705: 98/06/11: Re: How about Lattice ispLSI?
    10741: 98/06/15: Re: How about Lattice ispLSI?
Rene Tschaggelar:
    35432: 01/10/04: Re: Linux tools
    35654: 01/10/12: Re: High level synthesis will never work well :)
    35656: 01/10/12: Re: Reassemble a BGA560 device
    35804: 01/10/18: Re: Career advice in fpga/asic design
    35946: 01/10/24: Re: High-speed Logic, Military/Space Grade
    35966: 01/10/25: Re: How to make an implementable big counter?
    36267: 01/11/04: Re: How dense are FPGA/CPLD's
    36365: 01/11/07: Re: How dense are FPGA/CPLD's
    36675: 01/11/15: Re: High Speed PWM?
    36677: 01/11/15: Re: interleaver delay question
    38044: 02/01/02: Re: asic vs. fpga
    40183: 02/03/01: Re: Altera FPGAs
    41368: 02/03/26: Re: ByteblasterMV EPM7064S voltage problem
    41612: 02/04/03: Re: Signals pollution.
    41765: 02/04/07: Re: 32 bit accumulator/comparator PWM?
    43609: 02/05/27: Re: How can I create an encrypted netlist for Altera?
    45133: 02/07/13: Re: Accurate Oscillator
    46551: 02/09/03: Re: C/C++ to Verilog/VHDL ?!
    46669: 02/09/05: Re: why the need for HIGH speed design?
    47014: 02/09/14: Re: Clcok divison : Rational clock divider
    47167: 02/09/19: Re: Apex unused pins voluntarily assigned by Quartus?
    47312: 02/09/23: Re: fpga eval kits
    47414: 02/09/25: Re: fpga comparisons???
    47415: 02/09/25: Re: PCB Design for Altera FPGA
    47903: 02/10/07: Re: lpm library for altera devices...
    47944: 02/10/08: pll jitter
    47964: 02/10/08: Re: Why can Xilinx sw be as good as Altera's sw?
    48157: 02/10/12: programming the FPGA by a microcontroller
    48193: 02/10/13: Re: programming the FPGA by a microcontroller
    48487: 02/10/18: Re: How to read files in a CompactFlash?
    48530: 02/10/19: Re: Number of Fpga posts vs dsp..
    48675: 02/10/22: Re: Altera FPGA and EPLD Download ByteBlaster
    48913: 02/10/27: Re: for what do you use fpga's
    48955: 02/10/28: Re: Porting from Xilinx to Altera?
    48987: 02/10/28: Re: Porting from Xilinx to Altera?
    49013: 02/10/29: Re: Porting from Xilinx to Altera?
    49033: 02/10/30: Re: Porting from Xilinx to Altera?
    49634: 02/11/18: Re: max3000
    49859: 02/11/22: BGA footprints
    49866: 02/11/22: Re: BGA footprints
    49934: 02/11/26: Re: count based Frequency generator
    49959: 02/11/26: Re: Fast Digital Synthesis Generator
    50327: 02/12/09: Re: FPGA/PCI on low budget
    50358: 02/12/09: ByteblasterMV on Quartus2
    50362: 02/12/09: Re: ByteblasterMV on Quartus2
    50692: 02/12/17: Re: ACEX 1K Configuration Time
    50734: 02/12/18: embedded programming of an ACEX1k30
    50775: 02/12/19: Re: 16-bit LFSR
    50777: 02/12/19: Re: embedded programming of an ACEX1k30
    50887: 02/12/21: Re: embedded programming of an ACEX1k30
    50895: 02/12/22: Re: CPLD ISP cables (newbie question)
    50922: 02/12/23: Re: How to generate a clock signal for CPLD?
    50923: 02/12/23: Re: serdes
    50941: 02/12/23: Re: How to generate a clock signal for CPLD?
    50975: 02/12/24: Re: embedded programming of an ACEX1k30
    50976: 02/12/24: Re: FPGA accelerated FPGA/ASIC tools
    50996: 02/12/25: Re: Altera Quartus or MAX Plus?
    51002: 02/12/26: Re: Altera Quartus or MAX Plus?
    51025: 02/12/26: Re: Altera Quartus or MAX Plus?
    51062: 02/12/29: Re: Future of VLSI in developing countries
    51164: 03/01/04: Re: Dynamic Reconfiguration
    51186: 03/01/06: Re: help for MAXPLUS2!
    51229: 03/01/07: Bug in Quartus2 Web 2.2
    51240: 03/01/08: Re: Bug in Quartus2 Web 2.2
    51252: 03/01/08: Re: Bug in Quartus2 Web 2.2
    51265: 03/01/09: Re: Bug in Quartus2 Web 2.2
    51271: 03/01/09: Re: In-Rush current in Stratix device
    51302: 03/01/10: Re: Student development board
    51372: 03/01/12: Re: In-Rush current in Stratix device
    51376: 03/01/12: Re: Bug in Quartus2 Web 2.2
    51378: 03/01/12: Re: Open FPGA please!
    51509: 03/01/15: Re: SChematic design approach compared to VHDL entry approach
    51575: 03/01/16: Re: Multiple FPGA-boards integration issues
    51606: 03/01/17: Re: Multiple FPGA-boards integration issues
    51933: 03/01/26: Re: New to FPGA world...need guidline/help
    51976: 03/01/28: Switching clock ( Altera ACEX )
    52131: 03/02/02: Re: FPGA Overclocking
    52203: 03/02/04: Re: Difference between : CPLD , FPGA , ASICS
    52796: 03/02/22: Re: Timing diagram input
    52951: 03/02/26: Re: Programming Altera EPC1 with ByteBlaster
    53018: 03/02/28: Re: PCB board design software vs outsourcing?
    53025: 03/02/28: Re: PCB board design software vs outsourcing?
    53031: 03/02/28: Re: FPGA programming question.
    53042: 03/03/01: Re: FPGA programming question.
    53045: 03/03/01: Re: Design consideration of high datarate wireless system
    53054: 03/03/01: Re: FIR Filter from Xilinx
    53058: 03/03/02: Re: How to select the chip before using FPGA?
    53071: 03/03/03: Re: How to select the chip before using FPGA?
    53115: 03/03/04: Re: rudimentary way to program CPLD
    53491: 03/03/14: Re: Adding delay to a signal?
    53492: 03/03/14: Re: Adding delay to a signal?
    53493: 03/03/14: Re: Buying memory for FPGA...
    53658: 03/03/19: Quartus2 : assigning I/O pins
    54471: 03/04/11: Re: Dynamic Reconfigurable FPGAs
    54571: 03/04/14: Re: request for simple UART
    54572: 03/04/14: Re: Hardware acceleration for raytracing purposes
    54573: 03/04/14: Re: So... I have some ready solutions about raytracing processor.
    54635: 03/04/15: Re: request for simple UART
    54643: 03/04/15: Re: where are the big power savings to be had?
    54649: 03/04/15: Re: request for simple UART
    54651: 03/04/15: Re: request for simple UART
    54984: 03/04/23: Re: DC requirement in FFT
    55297: 03/05/02: Re: I want a 800 k gates FPGA in 40 pin DIL
    55314: 03/05/03: Re: I want a 800 k gates FPGA in 40 pin DIL
    55316: 03/05/03: Re: I want a 800 k gates FPGA in 40 pin DIL
    55339: 03/05/04: Re: PLL chips
    55342: 03/05/04: Re: PLL chips
    55451: 03/05/08: Re: FPGA Design with Protel DXP
    55990: 03/05/26: Re: New Architectures
    55995: 03/05/26: Re: Any recommendation for an FPGA kit ?
    55997: 03/05/26: Re: Any recommendation for an FPGA kit ?
    56269: 03/06/02: Re: Help an Italian Student
    56606: 03/06/10: Re: Acex1k100 & Quartus
    56607: 03/06/10: Pseudo random shift register - > DAC
    56667: 03/06/11: Re: Pseudo random shift register - > DAC
    57096: 03/06/23: Re: Programmable Delay (not clock driven)
    57097: 03/06/23: Re: Programmable Delay (not clock driven)
    57157: 03/06/24: Re: Quartus II - Acex1k - Routing resources
    57182: 03/06/25: Re: Quartus II - Acex1k - Routing resources
    57587: 03/07/02: NIOS tutorial for the Stratix1S10
    57624: 03/07/03: Re: NIOS tutorial for the Stratix1S10
    57626: 03/07/03: Re: NIOS tutorial for the Stratix1S10
    57668: 03/07/03: Re: NIOS tutorial for the Stratix1S10
    57717: 03/07/04: Re: NIOS tutorial for the Stratix1S10
    57857: 03/07/08: Re: Copy Altera Config EPC2 via JTAG?
    59713: 03/08/26: Re: Free FPGA samples anywhere?
    59794: 03/08/28: Re: Free FPGA samples anywhere?
    59896: 03/08/31: Re: Free FPGA samples anywhere?
    60735: 03/09/20: Re: show-ahead FIFOs
    60790: 03/09/22: Re: Synchronous counter enable pulse length
    60817: 03/09/23: Re: Synchronous counter enable pulse length
    62087: 03/10/18: Re: Altium DXP for designing Xilinx FPGA
    62133: 03/10/20: Re: Italy is out of FPGA world?
    62134: 03/10/20: Re: Altium DXP for designing Xilinx FPGA
    62344: 03/10/27: Re: Altera ACEX1K configuration and initialisation
    62839: 03/11/09: Re: ASIC vs FPGA
    63085: 03/11/14: Re: Altera MAX3000 device required.
    64664: 04/01/10: Altera Cyclone Serial Configuration devices.
    64666: 04/01/10: Programming and debugging the Altera Cyclone family
    64682: 04/01/11: Altera Cyclone data is incomplete or messy
    64683: 04/01/11: Altera Cyclone Programming device programming
    64688: 04/01/11: Re: Programming and debugging the Altera Cyclone family
    64689: 04/01/11: Re: Altera Cyclone Serial Configuration devices.
    64691: 04/01/11: Re: Programming and debugging the Altera Cyclone family
    64739: 04/01/12: Re: Altera Cyclone data is incomplete or messy
    64813: 04/01/14: Re: Altera Cyclone data is incomplete or messy
    64823: 04/01/14: Re: Altera Cyclone data is incomplete or messy
    64853: 04/01/15: Re: Altera Cyclone data is incomplete or messy
    64854: 04/01/15: Re: Generating clock delays
    64948: 04/01/16: Re: Hardware to test (FPGA-based) prototype?
    64950: 04/01/16: Re: Altera Cyclone data is incomplete or messy
    64951: 04/01/16: Re: Generating clock delays
    65046: 04/01/19: Re: Altera/Xilinx Distributor in Europe?
    65554: 04/02/02: Re: Clocking an FPGA??
    65556: 04/02/02: Re: Differences between Xilinx ISE and Altera Quartus software
    65571: 04/02/02: Re: Differences between Xilinx ISE and Altera Quartus software
    65802: 04/02/06: Re: Pricing, 101
    65831: 04/02/07: Re: Pricing, 101
    65842: 04/02/08: Re: Pricing, 101
    65852: 04/02/08: Re: Pricing, 101
    65898: 04/02/09: Re: Pricing, 101
    65932: 04/02/10: Re: [Altera/Quartus] Tools to regenerate block schematics from .vhd
    66002: 04/02/11: Re: Pricing, 101
    66228: 04/02/15: Re: Programming an EPC1 conf.Dev. from Altera
    66232: 04/02/15: Re: Programming an EPC1 conf.Dev. from Altera
    66573: 04/02/23: erasing a MAX device
    66577: 04/02/23: Re: erasing a MAX device
    66719: 04/02/25: Re: difference btw H/W & S/W implementations !!
    66930: 04/03/01: Re: Configuring Altera FLEX10KE using EPC2 device
    66958: 04/03/02: Re: TRST Pin in Altera FPGAs
    67709: 04/03/17: Re: =?ISO-8859-1?Q?EAB=B4s_in_ACEX_1K_devices?=
    68011: 04/03/24: Re: cheapest & best FPGA???
    68236: 04/03/31: Re: speed vs. temperature
    68270: 04/03/31: Re: speed vs. temperature
    68427: 04/04/04: Re: The Logic Behind License Renewal
    68430: 04/04/04: Re: The Logic Behind License Renewal
    68725: 04/04/15: Re: DDS-Based PLL
    68772: 04/04/17: Re: Protel 2004 for FPGA design?
    68773: 04/04/17: Re: PLL and DLL
    68799: 04/04/19: Re: FPGA techniques for D/A and A/D
    68973: 04/04/23: Re: OT - Generating a 20MHz clock that can be adjusted by +- 2%
    69017: 04/04/25: Re: Byteblaster Download cable schematics not available from altera
    69038: 04/04/26: Re: Byteblaster Download cable schematics not available from altera
    69039: 04/04/26: Re: Altera ByteBlaster II schematic
    69198: 04/04/29: Re: Altera ByteBlaster II schematic
    69233: 04/05/01: Re: Altera ByteBlaster II schematic
    69469: 04/05/11: Re: FPGA vs Microprocessor: newbie question
    69487: 04/05/12: Re: FPGA + CF
    69579: 04/05/14: Re: Quartus II Web Edition
    69887: 04/05/23: Re: Altium FPGA board
    69935: 04/05/25: Re: Altium FPGA board
    69936: 04/05/25: Re: Driving fpga pin out over long cable
    70003: 04/05/26: Re: Altium FPGA board
    70024: 04/05/27: Re: Driving fpga pin out over long cable
    70109: 04/06/03: Re: Three-phase PWM generator in VHDL
    70330: 04/06/12: Re: Costs of IPs
    70833: 04/06/29: Re: FPGA jobs in Germany
    70921: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
    71135: 04/07/09: Re: *RANT* Ridiculous EDA software "user license agreements"?
    71310: 04/07/14: Re: Altium CircuitStudio 2004 vs for FPGA support
    71341: 04/07/15: Re: Altium CircuitStudio 2004 vs for FPGA support
    71531: 04/07/21: Re: Altera FPGA's
    71637: 04/07/26: Re: Gate Count vs Logic Element (LE)
    71714: 04/07/28: Re: FPGA vs CPLD
    71804: 04/07/30: Re: FPGA vs CPLD
    72215: 04/08/11: Re: How important are software tools while choosing FPGA
    72895: 04/09/07: Quartus2 V4.1 SP1
    72979: 04/09/09: Re: Quartus2 V4.1 SP1
    73026: 04/09/10: Re: new to fpga
    73184: 04/09/15: Re: I/O state of max7000s during power-up?
    73231: 04/09/16: Re: I/O state of max7000s during power-up?
    73232: 04/09/16: Re: problem with ALtera CPLD
    73299: 04/09/18: Re: Statix II vs. Virtex 4
    73325: 04/09/19: Re: problem with ALtera CPLD
    73609: 04/09/25: Re: HDL Behaviorial Model for an LCD Controller
    73690: 04/09/28: Re: fast adder and equal
    75050: 04/10/25: Re: PLL Clocks on Cyclone Devices
    75051: 04/10/25: Re: Low-power FPGAs?
    74224: 04/10/06: Re: Is the Xilinx's silicon better than Altera's?
    74859: 04/10/20: Re: How To Provide External Input & Output To Startix 1S40..?
    76063: 04/11/23: Re: Altera chip identification
    76661: 04/12/08: Re: Fpga prices
    76707: 04/12/09: Re: Fpga prices
    77004: 04/12/19: Re: Clock Synchronization
    77629: 05/01/12: Re: Programming and copyright
    77781: 05/01/17: Re: USB Host
    77801: 05/01/17: Re: FPGA Board with RF Front end
    78000: 05/01/22: Re: Microscope examination of a PLD
    78328: 05/01/29: Re: Quartus II megafunction
    78446: 05/02/01: Re: Synchronizing multibit bus
    78510: 05/02/02: Re: Synchronizing multibit bus
    78511: 05/02/02: Re: Synchronizing multibit bus - 2
    78512: 05/02/02: Re: Synchronizing multibit bus - 2
    79182: 05/02/15: Re: Any Altera FIFO not a power of 2?
    79269: 05/02/16: Re: Protecting IP in China
    79519: 05/02/20: Re: why are PCI-based FPGA cards so expensive ?
    79540: 05/02/20: Re: why are PCI-based FPGA cards so expensive ?
    79541: 05/02/20: Re: Design security
    80358: 05/03/04: Re: Newby Getting started with FPGA
    80375: 05/03/04: Re: Newby Getting started with FPGA
    80378: 05/03/04: Re: Newby Getting started with FPGA
    80379: 05/03/04: Re: Newby Getting started with FPGA
    84751: 05/05/26: Re: Single-endec clocks
    84886: 05/05/31: Re: What is a typical job scope when FPGAs are involved?
    84975: 05/06/02: Re: Clock Generation : FPGA
    84987: 05/06/02: Re: Clock Generation : FPGA
    85036: 05/06/03: Re: Clock Generation : FPGA
    85039: 05/06/03: Re: Protecting IP in China
    85192: 05/06/06: Re: FPGA/CPLD trend
    86019: 05/06/20: Re: FPGAs: Where will they go?
    86044: 05/06/21: Re: FPGAs: Where will they go?
    86220: 05/06/23: Re: Minimum allowed clock frequency for Nios 2 processor (Stratix
    87057: 05/07/14: Re: Problems programing FPGAs..
    87615: 05/07/27: Datasheet error in the Altera Cyclone 2C8F256 pindescription
    87624: 05/07/27: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
    88218: 05/08/12: Re: Clocks
    89123: 05/09/06: Re: High baud rate chips for RS232 protocol
    89897: 05/09/29: Re: CPLD program editing
    89964: 05/09/30: Re: PCB Software....
    91254: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91306: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91849: 05/11/15: Re: RoHS
    91851: 05/11/15: Re: Having trouble Detecting ethernet packets using ethereal
    91930: 05/11/17: Re: RoHS
    92491: 05/11/30: Re: DSP vs FPGA
    92492: 05/11/30: Re: Download old Quartus versions (4.0, 4.1)
    92801: 05/12/07: Re: How to connect 2 FPGA?
    92814: 05/12/07: Re: Stratix EP1S80 DSP development board (Problem for ADC/DAC conversion
    93994: 06/01/04: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
    94655: 06/01/16: Re: Don't even get me started on lead,
    95662: 06/01/25: Re: encryption
    96284: 06/02/01: Re: Maximum system frequency on FPGA/CPLD
    96618: 06/02/07: Re: NMEA Decoder/Display
    96794: 06/02/10: Re: Altera EPLD
    96806: 06/02/10: Re: Altera EPLD
    97483: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
    98130: 06/03/06: Re: How to choose FPGA/CPLD ?
    98251: 06/03/07: Re: How to choose FPGA/CPLD ?
    98722: 06/03/15: Re: Spread Spectrum Cores ??
    99261: 06/03/22: Re: Fixed vs Float ?
    100134: 06/04/04: Re: embedded design prototyping
    100152: 06/04/04: Re: about the low power design
    100610: 06/04/13: Re: PCB Stack
    100817: 06/04/18: MaxPlus2 and the Byteblaster MV
    100818: 06/04/18: Re: FPGA availability & distribution options.
    100844: 06/04/19: Re: MaxPlus2 and the Byteblaster MV
    100845: 06/04/19: Re: How is the max clock rate of a device fixed?
    100851: 06/04/19: Re: MaxPlus2 and the Byteblaster MV
    101063: 06/04/25: Re: Heating problem of the CPLD
    101096: 06/04/25: Re: FPGA with ASIC FPU units
    101097: 06/04/25: Re: clock multiplication
    101103: 06/04/25: Re: clock multiplication
    101165: 06/04/26: The use of analog switches as level translators
    101351: 06/04/29: Re: What would be the tariff classification of an FPGA development
    101586: 06/05/03: Re: Reliability CPLD/FPGA vs Microcontroller
    101644: 06/05/04: Re: Phase alignment of DCMs on different boards/devices
    101714: 06/05/05: Re: Phase alignment of DCMs on different boards/devices
    101876: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
    101885: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
    101895: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
    102247: 06/05/12: Re: How to decide Fanout limit?
    102711: 06/05/19: Re: ADC implementation on FPGA ?
    103275: 06/05/30: Re: Power Up delay in FPGA !!!!!
    103481: 06/06/03: Re: VHDL code For Floating point adder and Multiplier
    104530: 06/06/29: Re: Preserve patent materials through a notary
    104588: 06/06/30: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    106442: 06/08/13: Re: Maximum Current Draw of FPGA
Rene van Leuken:
    67745: 04/03/18: Synopsys behavior compiler and Xilinx
    108178: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
renjini:
    38035: 02/01/02: floorplanning
renjith:
    79305: 05/02/17: Re: binary constant divider theory
Rennie Allen:
    22377: 00/05/06: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22449: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22451: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22452: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22482: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
Renniks:
    93408: 05/12/21: Spartan 3 Digilent Board Expansion Connectors
reno:
    9224: 98/03/03: Re: Xilinx X3000: Does XACT6 accept the "L" or "SC=n" attribs?
    9226: 98/03/03: Re: Xilinx X3000: Does XACT6 accept the "L" or "SC=n" attribs?
    8906: 98/02/06: Re: Q: Workview Office and M1
Renoir Support:
    5685: 97/03/06: Introducing Renoir
    5720: 97/03/10: Re: Introducing Renoir
Rensheng Horng:
    4143: 96/09/18: Wanted: Verilog, Synopsys, ASIC
Renu Raman:
    2582: 96/01/06: Re: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
renuka:
    140472: 09/05/14: arrays in VHDL
renupriya:
    139808: 09/04/14: Ethernet on Altera FPGA: Help required
    140301: 09/05/08: Help required on Ethernet with FPGA
Renzo Marcanzin:
    23838: 00/07/12: newbi question
Renzo Venturi:
    24688: 00/08/17: Re: Permanently programming FPGAs
    26758: 00/10/27: Re: Lazio Promises End to Long Island FPGA Crisis
    32237: 01/06/20: Re: Phase Locked loop implementation on FPGA
<renzo.arce@st.com>:
    13581: 98/12/10: Magazine IEEE for FPGA ???
    13586: 98/12/10: Synthesis with Actel
    13961: 99/01/05: FPGA development system
Replace_latter8717_with_manorsway:
    57768: 03/07/06: Re: division
    57797: 03/07/07: Re: division
    57914: 03/07/09: Re: division
reply in the newsgroup:
    45928: 02/08/11: Re: I seek a FPFA developer
    45949: 02/08/12: Re: Reconfiguration in Xilinx FPGA
    45963: 02/08/12: Re: Reconfiguration in Xilinx FPGA
    46007: 02/08/13: Re: Reconfiguration in Xilinx FPGA
    46244: 02/08/22: Re: combinatorial clocks
    46685: 02/09/05: Re: Neural hardware containing many neurons but very simple computation
Repzak:
    70640: 04/06/22: Newbie Q
    70643: 04/06/22: Re: Newbie Q
    70755: 04/06/26: GCK0 Problem
    70767: 04/06/27: PROTEL DXP 2004 / NANOBOARD / 3rd Part board
    70770: 04/06/27: Re: clk inputs, are they all same?
    70775: 04/06/28: Re: How to add clock delay in CPLD?
    71605: 04/07/24: VHDL
    71611: 04/07/25: Re: VHDL
    75108: 04/10/26: Re: Altium board again
    76702: 04/12/09: Re: BurchED FPGA Newsletter, December 2004
    80869: 05/03/13: seriel prom
    82022: 05/04/06: Re: FPGA with 2 JTAG ports
res0rsef:
    80804: 05/03/11: SelectLink For Virtex-II
res0uffu:
    70320: 04/06/12: Re: Effects of moisture on CPLD
res19j1c:
    45084: 02/07/12: FPGA CPU?
    45093: 02/07/12: Re: FPGA CPU?
    45145: 02/07/13: Re: FPGA CPU?
<researchstudy2001@yahoo.com>:
Reto Stamm:
    15986: 99/04/26: Re: Xilinx FPGA eval board
    16846: 99/06/14: Re: Free IP library?????
Reto Zimmermann:
    4378: 96/10/22: Multipliers on Xilinx FPGAs
    29162: 01/02/08: Re: VHDL-Mode
    29243: 01/02/10: Emacs VHDL Mode 3.31 released
    29391: 01/02/18: Emacs VHDL Mode 3.32 beta
    30312: 01/04/02: Re: adding std_logic_vectors
Retro:
    90044: 05/10/03: Re: Reading a PAL fusemap with a microscope
Reuven:
    130536: 08/03/26: Re: VHDL document generation utilities
<revkarol@gmail.com>:
    156384: 14/03/24: looking for a basic PCIe example
Rex Fisher:
    27322: 00/11/17: Altera MAX+PlusII v.s. Xilinx Foundation
Reynald Pireyre:
    25782: 00/09/20: FPGA compiler abort 219
Reza:
    92536: 05/12/01: Help : Code works in synthesizer (silos), but warnings w/ webpack
    92568: 05/12/01: Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
Reza Bohrani:
    11490: 98/08/19: Manchester decoding
    11580: 98/08/25: FPGA vendors
    11581: 98/08/25: SYNTHESIS TOOLS
    11679: 98/08/31: A Johnson counter
    11832: 98/09/12: A Linear Feedback Shiftregister
    11910: 98/09/18: Synthesis warning
Reza Naima:
    93310: 05/12/19: More beginner's verilog questions
    93323: 05/12/19: Re: More beginner's verilog questions
    93326: 05/12/19: Re: More beginner's verilog questions
    93364: 05/12/20: Re: More beginner's verilog questions
    93365: 05/12/20: Re: More beginner's verilog questions
    93375: 05/12/20: Re: More beginner's verilog questions
    93384: 05/12/21: Re: More beginner's verilog questions
    93416: 05/12/21: Re: More beginner's verilog questions
    93423: 05/12/21: Re: More beginner's verilog questions
    93433: 05/12/21: Re: More beginner's verilog questions
    93449: 05/12/22: Re: More beginner's verilog questions
    93450: 05/12/22: Re: More beginner's verilog questions
    93576: 05/12/25: Re: More beginner's verilog questions
RF:
    76206: 04/11/28: VGA signal generator using CPLD
    76329: 04/11/30: Re: VGA signal generator using CPLD
rfbrw:
    20844: 00/02/24: Re: Xchecker schematic?
RFrank1234:
    50026: 02/11/28: Where can I find low cost 3rd party Xilinx j-tag programmer?
rg:
    40647: 02/03/12: Re: RTL/Gate-Level Simulation
<rg.jones@rogers.com>:
    125441: 07/10/25: ISE PACE Question
    129913: 08/03/09: Trying to contact Jeung Joon Lee
Rgamer:
    126549: 07/11/27: Re: Global Reset using Global Buffer
    126598: 07/11/28: Re: Global Reset using Global Buffer
    126619: 07/11/28: Re: Global Reset using Global Buffer
    126666: 07/11/29: Re: Global Reset using Global Buffer
    126697: 07/11/29: Re: Global Reset using Global Buffer
rgamer1981@gmail.com:
    126540: 07/11/27: Global Reset using Global Buffer
<rganapa@gmail.com>:
    135061: 08/09/12: Interfacing external memory
rgebru:
    81136: 05/03/18: Spartan 3 to tempsensor interface
    81415: 05/03/23: Re: Spartan 3 to tempsensor interface
    82850: 05/04/18: re:Spartan 3 to tempsensor interface
    83108: 05/04/23: re:Spartan 3 to tempsensor interface
    83202: 05/04/25: re:Spartan 3 to tempsensor interface
    83246: 05/04/26: re:Spartan 3 to tempsensor interface
    83673: 05/05/04: re:Spartan 3 to tempsensor interface
rgf:
    39122: 02/01/31: www.easics.com
    39194: 02/02/03: Re: www.easics.com
Rgr:
    55704: 03/05/16: Re: Moore Vs Mealy machine ..
    56766: 03/06/14: ERROR:iMPACT:1210
    60040: 03/09/04: More EDK Problems..... :-(
    127752: 08/01/07: Processor in CPLD
    127760: 08/01/07: Re: Processor in CPLD
    127797: 08/01/08: Re: Processor in CPLD
    127798: 08/01/08: Low Power CPU Implementation
    128420: 08/01/25: Initialize RAM in IGLOO
<rgr@freedomnet.com>:
    7370: 97/09/03: Is this you?
rha_x:
    91506: 05/11/07: To create an IPCORE
    91513: 05/11/08: Re: BRAMs readback
    131243: 08/04/16: ICAP_VIRTEX4 primitive
<rha_x@yahoo.com>:
    126527: 07/11/26: scanf and printf in EDK's BSP
    126530: 07/11/26: Re: scanf and printf in EDK's BSP
    126547: 07/11/27: Re: scanf and printf in EDK's BSP
    133464: 08/06/30: on FRAME_ECC_VIRTEX4 functionality
RHigginbotham:
    153886: 12/06/21: Re: Data transfers between MicroBlaze and VHDL
    153887: 12/06/21: Re: Data transfers between MicroBlaze and VHDL
Rhishi:
    124768: 07/10/03: XUPV2P serial connection through serial-to-usb cable
rhnlogic:
    93153: 05/12/14: Re: Xilinx floating point core 1.0
    98004: 06/03/02: Re: How do I make dual-port RAM from single port RAM?
rhnlogic@yahoo.com:
    89798: 05/09/26: Re: Synchronizer Flip Flop / Metastability
    89829: 05/09/27: Re: Synchronizer Flip Flop / Metastability
    90080: 05/10/04: Re: Avoiding meta stability?
    90097: 05/10/04: Re: Avoiding meta stability?
    90211: 05/10/06: Re: Avoiding meta stability?
    90249: 05/10/07: Re: Avoiding meta stability?
    90275: 05/10/07: Re: Question about metastability that's been on my mind for a while
    90276: 05/10/07: Re: Question about metastability that's been on my mind for a while
    90343: 05/10/10: Re: Eliminates meta stability (yes or no)?
    90421: 05/10/12: Re: Avoiding meta stability?
    90769: 05/10/20: Re: MAC Architectures
<rhodes@gigaops.com>:
    6613: 97/06/05: Re: New Reconfigurable Computing newsgroup?
    6617: 97/06/05: Re: Fine Pitch PQFP : anyone any hassles?
Rhondalee Rohleder:
    5332: 97/02/07: Re: Embedded SRAM in FPGAs
    5349: 97/02/09: Re: Altera support better than Xilinx
    5585: 97/02/26: Re: Market share - synthesis tools?
    5674: 97/03/05: Re: Altera support better than Xilinx
    5972: 97/04/01: Re: XC2018
    6021: 97/04/05: Re: Vendors (Xilinx, Cypress) leaving antifuse market
    6057: 97/04/08: Re: Reconfig computing and multimedia?
    6059: 97/04/08: Re: Vendors (Xilinx, Cypress) leaving antifuse market
    6138: 97/04/16: Re: benchmarks
RHowngtn:
    10042: 98/04/23: PLEASE HELP, IF YOU CAN (Ignore after May 1)
RHPerez:
    1108: 95/04/30: Re: Free Hardware
    1109: 95/04/30: Microcontrollers
    1110: 95/04/30: Re: Is anybody using FPGA's to do PCI interfaces?
    1191: 95/05/12: Re: Is anybody using FPGA's to do PCI interfaces?
    1192: 95/05/12: Re: Anybody using Synario ?
    1193: 95/05/12: Re: Verilog Won & VHDL Lost? -- You Be The Judge!
    1194: 95/05/12: Re: How to choose an FPGA vendor
Rhydian:
    148481: 10/07/27: Problems with VHDL lookup table in Quartus
    148498: 10/07/28: Re: Problems with VHDL lookup table in Quartus
    148501: 10/07/28: Re: Problems with VHDL lookup table in Quartus
    148533: 10/07/30: Re: Problems with VHDL lookup table in Quartus
Riad:
    13470: 98/12/04: package/footprint/layout
Riad BOURGUIBA:
    20666: 00/02/17: CLAy 31 datasheet
    21289: 00/03/15: Re: About atmel's FPGA and JBit
    21348: 00/03/17: Looking for informations about VCC's EVC1 architecture.
ric:
    62039: 03/10/17: LUT and latch in the FPGA
    62160: 03/10/20: Re: LUT and latch in the FPGA
    62190: 03/10/21: Re: LUT and latch in the FPGA
    62736: 03/11/06: Re: LUT and latch in the FPGA
Ricardo:
    68547: 04/04/07: Re: Cyclone and ByteBlasterMV?
    68567: 04/04/08: Re: Cyclone and ByteBlasterMV?
    69711: 04/05/18: Re: How to select an FPGA size (beginner)
    71320: 04/07/14: Re: new Lattice FPGAs vs Cyclone and SpartanIII
    78378: 05/01/31: Re: Is Atmel producing Altera EPCS memories???
    78947: 05/02/10: Re: Plea for help with MAX7000S
    85356: 05/06/08: Re: Pissed off with Xilinx - Spartan 3
    90135: 05/10/05: Re: Avoiding meta stability?
    92423: 05/11/29: Re: Cypress FX2 bandwidth problem
    92471: 05/11/30: Re: Cypress FX2 bandwidth problem
    100546: 06/04/11: PCI speed.
    100606: 06/04/13: Re: PCI speed.
    104305: 06/06/23: Re: stimulus for FPGA
    104755: 06/07/05: Re: "Large" memory array in VHDL
    104795: 06/07/06: Re: "Large" memory array in VHDL
Ricardo Matias Moreno Moll:
    22026: 00/04/13: XCHECKER 3V adapter
    22038: 00/04/14: Re: XCHECKER 3V adapter
Ricardo Menotti:
    67356: 04/03/10: Embedded Systems Books
Ricardo Ruiz:
Ricardo Wiggers:
    47000: 02/09/13: Re: exploiting metastability
<ricardo.ribalda@gmail.com>:
    117362: 07/03/29: We need avnet fx12 mini module URGENTLY!
Ricaud:
    73009: 04/09/10: Simple FPGA board
    73014: 04/09/10: Re: Simple FPGA board
Riccardo Fregonese:
    76430: 04/12/02: How to direct download to SRAM on Xilinx Spartan3?
    76593: 04/12/06: How to direct download to SRAM on Xilinx Spartan3?
Riccardo Rubini:
    44574: 02/06/24: [Newbie] Help with 20L8 PAL
    51761: 03/01/21: WTB: 16L8 / 20L8 programmer
Riccardo Zambon:
    30370: 01/04/04: High Speed PLA/FPGA
Rice:
    148563: 10/08/02: Modify UCF file generated with MIG
    148569: 10/08/02: Re: Modify UCF file generated with MIG
    148677: 10/08/17: SDK example from Xilinx do not compile
    148692: 10/08/17: Re: SDK example from Xilinx do not compile
    148773: 10/08/20: Re: SDK example from Xilinx do not compile
Rich:
    1385: 95/06/12: Re: Need access to Actel ALS tool
    151401: 11/04/02: Re: Ideal FPGA Development Kit
    151412: 11/04/04: Re: Ideal FPGA Development Kit
    151428: 11/04/07: What are the preferred Virtex5/Virtex6 configuration methods?
    151430: 11/04/07: Re: What are the preferred Virtex5/Virtex6 configuration methods?
Rich Fournier:
    11765: 98/09/08: Re: FPGA Cost ?
Rich Grise:
    54584: 03/04/14: Re: Testing engineering ability prior to work?
    75574: 04/11/10: Re: Data Swtich from LPT to LCD Module!
    77762: 05/01/16: Re: Exportability of EDA industry from North America?
    77763: 05/01/17: Re: Exportability of EDA industry from North America?
    77769: 05/01/17: Re: What is the difference between ASIC and FPGA?.
    77774: 05/01/17: Re: Exportability of EDA industry from North America?
    77858: 05/01/18: Re: Exportability of EDA industry from North America?
    81108: 05/03/17: Re: How much current does an LED take?
    90822: 05/10/21: Re: MAC Architectures
    90895: 05/10/25: Re: MAC Architectures
    95244: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95466: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95504: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95505: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95506: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95508: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95509: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    96678: 06/02/08: Re: latest XILINX WebPack is totally broken
    99664: 06/03/28: Re: deglitching a clock
    99728: 06/03/28: Re: deglitching a clock
    99875: 06/03/30: Re: deglitching a clock
    103468: 06/06/03: Xilinx ISE 7.1i Tutorial: Test Bench road block
    103545: 06/06/05: Re: Xilinx ISE 7.1i Tutorial: Test Bench road block
    103555: 06/06/06: Re: Webpack larger than CDs
    103616: 06/06/07: Re: FPGA board for USB experiments?
    103764: 06/06/10: Xilinx ISE S/W Install kernel version "mismatch"
    103765: 06/06/10: Re: Xilinx ISE S/W Install kernel version "mismatch"
    103817: 06/06/12: Re: Xilinx ISE S/W Install kernel version "mismatch"
    104250: 06/06/21: Re: Xilinx ISE S/W Install kernel version "mismatch"
    104281: 06/06/22: Re: Xilinx ISE S/W Install kernel version "mismatch"
    107542: 06/08/29: Re: September training?
    107893: 06/09/02: Re: Performance Appraisals
    125851: 07/11/06: Re: not totally repulsive
    150452: 11/01/22: Re: Xilinx news
Rich Grise, but drunk:
    95464: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95465: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95470: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95474: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95478: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95487: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95489: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95491: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95492: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95494: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95502: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95510: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95516: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95518: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95522: 06/01/23: Re: OT:Shooting Ourselves in the Foot
Rich Grise, Plainclothes Hippie:
    107543: 06/08/29: Re: September training?
    107894: 06/09/02: Re: Performance Appraisals
    107896: 06/09/02: Re: Performance Appraisals
Rich Hatcher:
    4300: 96/10/11: Re: Reversible LFSR?
    10839: 98/06/24: Re: books on vhdl
Rich K.:
    4917: 96/12/30: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4918: 96/12/30: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4919: 96/12/30: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4926: 96/12/31: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4927: 96/12/31: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4949: 97/01/03: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4973: 97/01/07: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5016: 97/01/13: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5048: 97/01/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5049: 97/01/16: Re: Safety Critical Apps -> Xilinx Checker.
    5053: 97/01/17: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5160: 97/01/27: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5186: 97/01/29: Re: Synthesizing fast counter (carry look ahead adder)
    5235: 97/01/31: Re: Actel Designer 3.1 Problem
    5252: 97/02/01: Re: Altera support better than Xilinx
    5657: 97/03/04: viewlogic ...
    5733: 97/03/11: viewoffice compatibility - dumb question
    5770: 97/03/13: Re: FPGA Reliability
    5812: 97/03/17: Re: viewoffice compatibility - dumb question
    5823: 97/03/18: Re: viewlogic ...
    5909: 97/03/25: viewoffice <--> viewoffice compatibility
    5941: 97/03/27: Re: viewoffice <--> viewoffice compatibility
    6056: 97/04/08: fpga technologies and Iddq testing
    6086: 97/04/10: Re: viewoffice <--> viewoffice compatibility
    6099: 97/04/11: Re: fpga technologies and Iddq testing
    6365: 97/05/18: Re: Anyone using Actel software?
    6404: 97/05/21: Gate Count Claims
    6412: 97/05/22: Re: FPGA technology: No truth in MARKETING
    6819: 97/06/30: Re: Any designs to avoid in FPGAs
    6820: 97/06/30: Re: Any designs to avoid in FPGAs
    6627: 97/06/06: Re: Actel Designer Series 3.1 and NT 4.0?
    7072: 97/07/29: Re: Design Protection in FPGAs
    7157: 97/08/07: Re: digitizer design, high speed
    7342: 97/08/28: Re: FIFO in Altera
    7371: 97/09/03: Re: Flexible tools and FIFOs
    7416: 97/09/08: Re: Which FPGA ?
    7438: 97/09/10: Re: Which FPGA ?
    7445: 97/09/10: Re: Reading Viewlogic files
    7478: 97/09/15: Re: HELP: FIFO's on an FPGA
    7558: 97/09/22: Re: Hacking bitstream formats
    7582: 97/09/24: Re: Pro series software
    7774: 97/10/14: viewlogic question
rich katz:
    11068: 98/07/16: Registration for 1998 Military and Aerospace Applications of Programmable Devices and Technologies Conference
    13295: 98/11/24: Re: Actel FPGA libraries for Synopsys
    13584: 98/12/10: Re: A short digression...
    13589: 98/12/10: Re: HELP, Tool selection
    13483: 98/12/04: Array Range Legal?
    13498: 98/12/06: Re: Array Range Legal?
    13591: 98/12/10: Re: Array Range Legal?
    13515: 98/12/07: a bit off topic - sram pointer needed
    13516: 98/12/07: computer requirements for CAE systems
    13604: 98/12/11: Re: Synthesis with Actel
    13632: 98/12/15: Re: multi-dimensional arrays and viewlogic
Rich LeGrand:
    43719: 02/05/30: Atmel and IDS 7.5
Rich Maes:
    9902: 98/04/12: Synopsys FPGA Express package pricing?
Rich McNeil:
    16362: 99/05/18: JTAG program Altera and Xilinx same chain?
    16450: 99/05/23: Re: JTAG: Altera & Xilinx
    31004: 01/05/09: Re: Looking for a prototyping board
    77252: 05/01/01: Re: Quartus and Cyclone programming problem
Rich Seifert:
    127763: 08/01/07: Re: Ethernet on recent FPGAs
    127775: 08/01/07: Re: Ethernet on recent FPGAs
Rich The Philosophizer:
    95595: 06/01/24: Re: OT:Shooting Ourselves in the Foot
Rich Walker:
    15710: 99/04/09: Re: Best FPGA for High Speed DSP Logic?
    16695: 99/06/03: Re: FPGA/ VHDL books: any stores in central London
    19267: 99/12/09: Vantis MACH ISP
    136349: 08/11/12: Re: Linux on Microblaze
Rich Webb:
    70959: 04/07/02: Re: Xilinx $99 Spartan-3 kit
    70968: 04/07/03: Re: Xilinx $99 Spartan-3 kit
    71297: 04/07/14: Re: WinCUPL state machine for 16V8
    71331: 04/07/15: Re: WinCUPL state machine for 16V8
    71599: 04/07/23: Re: How to program a spartan-3
    74671: 04/10/16: Re: BCD to bin convertor
    75384: 04/11/04: Re: need an fpga board
    76986: 04/12/18: Re: Need help with CUPL
    77217: 04/12/30: Re: Need help with CUPL
    78683: 05/02/06: Re: Digilent JTAG cable parallel port pinout (Spartan 3)
    78696: 05/02/06: Re: Digilent JTAG cable parallel port pinout (Spartan 3)
    80052: 05/03/01: Re: FPGA interface to an asynchronous microcontroller memory bus
    97232: 06/02/19: Re: FPGA - software or hardware?
    100002: 06/04/01: Re: Atmel microcontroller
    132797: 08/06/06: Re: 1 Pin MTE Cable
    132875: 08/06/09: Re: how to prevent timer code firmware running on Microblaze from being optimised
    133942: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
    134910: 08/09/06: Re: Are Xilinx tools that bad, or am I missing something?
    135560: 08/10/08: Re: Those FPGA boards
    135594: 08/10/09: Re: Packet sniffer help
    136494: 08/11/19: Re: USB JTAG
    137423: 09/01/15: Re: Webpack 10.1 on Windows XP
    138268: 09/02/11: Re: Logic Analyzer
    138586: 09/03/01: Re: New person to CPLD programming
    138974: 09/03/17: Re: Zero operand CPUs
    140370: 09/05/11: Re: Getting started with FPGA
    140944: 09/05/30: Re: patent free ARM cores
    140986: 09/06/01: Re: Open Source FPGA circuit design.
    141003: 09/06/02: Re: Open Source FPGA circuit design.
    141914: 09/07/16: Re: Do you prefer paper or plastic... er, I mean paper or e-books?
    143075: 09/09/18: Re: FPGA for acoustic adaptive beamforming
    145399: 10/02/08: Re: different JTAG programming cables
    147214: 10/04/19: Re: Need to run old 8051 firmware
    147353: 10/04/23: Re: Quartus II under Windows7?
    147922: 10/06/02: Re: Job experience? How?
    148123: 10/06/22: Re: Why is Google so F****** dense about SPAM?
    148129: 10/06/22: Re: Why is Google so F****** dense about SPAM?
    148856: 10/09/04: Re: We need an administrator for the group to fight spam
    148878: 10/09/06: Re: We need an administrator for the group to fight spam
    149183: 10/10/06: Re: Driving a design via TCP/IP
    151369: 11/03/28: Re: fpga express 3.6
Rich Wilson:
    10: 94/07/28: Re: Does the iFX780 qualify for discussion here?
rich12345:
    145932: 10/02/28: Re: using an FPGA to emulate a vintage computer
    148122: 10/06/22: Re: Why is Google so F****** dense about SPAM?
    148364: 10/07/15: Re: Another Xilinx webpack download rant
Richad Klosinski:
    76012: 04/11/22: Xilinx OPB custom interface
richard:
    96608: 06/02/07: latest XILINX WebPack is totally broken
    96728: 06/02/09: Re: latest XILINX WebPack is totally broken
    96729: 06/02/09: Re: latest XILINX WebPack is totally broken
    96887: 06/02/12: Re: digital logic library by 74xxxx part number?
    96919: 06/02/13: Re: digital logic library by 74xxxx part number?
    96921: 06/02/13: SCHEMATICS ... Is anybody as frustrated as I am with the software?
    97899: 06/03/01: Re: latest XILINX WebPack is totally broken
    98363: 06/03/08: need doc's for Insight Spartan II demo board
    119605: 07/05/23: Re: Signal Assignment bugs in Quartus-II ... AGAIN!
    119606: 07/05/23: Re: Signal Assignment bugs in Quartus-II ... AGAIN!
    119663: 07/05/24: Re: 6502 and CPU licences in general
Richard:
    51712: 03/01/20: Parsing Xilinx Timing Reports
    51763: 03/01/21: Re: Parsing Xilinx Timing Reports
    51817: 03/01/22: Re: Parsing Xilinx Timing Reports
    51946: 03/01/27: Map report in XML?
    63286: 03/11/19: Xilinx microblaze : SRAM external mem controller
    92430: 05/11/29: Bit-serial arithmetic on Spartan II
    92431: 05/11/29: Q-bus or Unibus bus transactions in FPGA?
    92442: 05/11/30: Re: Q-bus or Unibus bus transactions in FPGA?
    92498: 05/11/30: Re: Q-bus or Unibus bus transactions in FPGA?
    93028: 05/12/12: FreeRTOS.org has support for Microblaze
    148298: 10/07/06: Q: Standard Programming Idiom
    148495: 10/07/28: Getting started with partial reconfiguration
    149461: 10/10/26: Simulating Xilinx FIFOs
    149513: 10/11/01: Xilinx ConstraintSystem:59
    149517: 10/11/02: Re: Xilinx ConstraintSystem:59
    149521: 10/11/02: Re: Xilinx ConstraintSystem:59
    152025: 11/06/23: Depth of logical Circuit
    152029: 11/06/23: Re: Depth of logical Circuit
    152030: 11/06/23: Re: Depth of logical Circuit
Richard A Springer:
    1947: 95/09/22: Re: Altera and Synopsys Interface
Richard Aikman:
    39185: 02/02/03: VHDL-FPGA design survey
Richard Aplin:
    3024: 96/03/15: Re: Multiple FPGA Partitioning
    3098: 96/04/01: Re: experience with Actel Act2 family
Richard Auletta:
    38474: 02/01/15: ASIC 2002 Call For Papers
    40990: 02/03/19: ASIC/SOC 2002 CALL FOR CORPORATE PARTICIPATION AND PAPERS
    45741: 02/08/02: CALL FOR PARTICIPATION 15th Annual IEEE International ASIC/SOC Conference
Richard B. Katz:
    6566: 97/06/03: Re: New Reconfigurable Computing newsgroup?
    6801: 97/06/29: Re: Any designs to avoid in FPGAs
    6640: 97/06/08: fpga usage by capacity
    6802: 97/06/29: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
    6904: 97/07/08: Re: VHDL to EDIF translater
    7093: 97/07/31: digitizer design, high speed
    7041: 97/07/26: Re: Epitaxial Layer on EPLD
    7200: 97/08/14: Re: FPGA power consumption
    7249: 97/08/19: Re: FPGA power consumption
    7343: 97/08/29: Re: VHDL Synthesis for Linux?
    7434: 97/09/09: Re: Which FPGA ?
    7455: 97/09/12: Re: Cheap (sub $10) hardwired FPGA? Which manufacturers?
    7463: 97/09/13: Re: Text Book and VHDL Simulator $50.00
    7467: 97/09/14: Re: Text Book and VHDL Simulator $50.00
    7702: 97/10/04: Re: Xilinx license idiocy
    7691: 97/10/02: Re: High Speed FPGAs
    7937: 97/11/01: 'compatible' fpgas
    8051: 97/11/12: Re: 'compatible' fpgas
    8106: 97/11/18: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
    8146: 97/11/21: Re: what is metastability time of a flip_flop
    8239: 97/12/02: Re: what is metastability time of a flip_flop
    8251: 97/12/03: Re: what is metastability time of a flip_flop
    8256: 97/12/04: Re: what is metastability time of a flip_flop
    8279: 97/12/05: Re: what is metastability time of a flip_flop
    9747: 98/04/03: Re: One time programmables
    9749: 98/04/03: Re: One time programmables
    10518: 98/05/26: Rad Hard
    10907: 98/06/29: Re: Xilinx Foundation simulator problem?
    11095: 98/07/18: Re: Too much advertising in this news group?
    11295: 98/08/02: Re: Symbols, design changes, pin changes
    11354: 98/08/05: Re: Silicore VHDL 8-bit RISC uC core for FPGA
    11359: 98/08/06: Re: Silicore VHDL 8-bit RISC uC core for FPGA
    11372: 98/08/07: Re: Silicore VHDL 8-bit RISC uC core for FPGA
    15134: 99/03/09: test - please ignore
    15182: 99/03/11: Announcement and Second Call for Papers - 1999 MAPLD Internation Conference
    15554: 99/03/30: Re: FPGAs with ECL-compatible I/Os
    16710: 99/06/03: Registration is Open and Call for Papers - 1999 MAPLD International Conference
    16731: 99/06/04: Re: Actel Desktop installation of Synplify won't work
    17539: 99/08/08: Registration is Open and Program - 1999 MAPLD International Conference
    19292: 99/12/10: test message
    19293: 99/12/10: test message
    22144: 00/04/26: Design Study
    23505: 00/06/27: MAPLD 1999 Conference Proceedings
    23939: 00/07/16: 2000 MAPLD International Conference - Program and Registration
    24002: 00/07/20: Re: FPGA Conferences
    25131: 00/08/26: Re: Metastability and antifuze
    25559: 00/09/13: MAPLD 2000 - Schedule Released and Final Registration
    29318: 01/02/13: 2001 MAPLD Conference - 1st Call for Papers
    30718: 01/04/25: MAPLD Conference - Call for Papers and Registration Open
    32762: 01/07/07: 2001 MAPLD Conference: Program Announced, Registration Open, and Last
    34141: 01/08/15: 2001 MAPLD Conference: Early Registration Closing, Last CFP
    38650: 02/01/20: CFP: 5th Annual MAPLD International Conference
    43351: 02/05/20: 2002 MAPLD: Registration Open, Call for Papers, and Announcements
    51364: 03/01/12: Call for Papers: 6th MAPLD International Conference
    54637: 03/04/15: 2nd CFP and Registration Open, 6th MAPLD International Conference
    54687: 03/04/16: Re: Are there any FPGA magazines/journals?
    57291: 03/06/27: Program Announcement and Registration Open: 6th MAPLD Int'l Conference
    57515: 03/07/02: Seminar: Digital Signal Processing, Programmable Device Architecture, and Military/Aerospace Applications
    58993: 03/08/06: 6th MAPLD: End of Early Registration and Program Announcement
    61753: 03/10/10: FPGA/PLD Reliability: High Speeds and Advanced Processes
    63777: 03/12/04: CFP: 7th Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD)
    65270: 04/01/23: CFP: 2004 MAPLD International Conference
    67333: 04/03/10: CFP: 7th Mil/Aerospace Applications of Programmable Logic Devices (MAPLD) Int'l Conference
    68875: 04/04/21: MAPLD CFP: Abstracts Due April 26, 2004
    70102: 04/06/03: MAPLD 2004: Registration Open and Program Announced
    77684: 05/01/13: First Call for Papers: 2005 MAPLD International Conference
    80599: 05/03/08: Call for Papers: 2005 MAPLD International Conference
    87013: 05/07/12: MAPLD 2005: Program Announced and Registration Open
    89754: 05/09/24: MAPLD 2005 Postings On-line
richard benfield:
Richard Brogle:
    15268: 99/03/17: Job Openings -- Tampa Bay Area
    15370: 99/03/21: Re: i2c specification
Richard Cant:
    12601: 98/10/19: Re: Library of boards
    12649: 98/10/21: Re: Schematic entry?
    12670: 98/10/22: Re: Schematic entry?
    13334: 98/11/26: Detailed Configuration Format
    13487: 98/12/05: Re: Will XILINX survive?
Richard Carey:
    88666: 05/08/24: Re: DCM does not do anything?
    89048: 05/09/03: Re: Creating higher bit multipliers from low bit.
Richard Chapman:
    9682: 98/03/30: programming XC4000A
    16186: 99/05/07: problem with Prentice-Hall student edition Xilinx
Richard Chidester:
    26808: 00/10/30: WebPACK ISE V3.2i is available for immediate download!
    26836: 00/10/31: Re: WebPACK ISE V3.2i is available for immediate download!
    26898: 00/11/02: Re: OT: Xilinx T-Shirt
    26933: 00/11/03: Re: OT: Xilinx T-Shirt
Richard Cooke:
    70556: 04/06/20: 8 ch countdown timer - doable in a CPLD?
Richard Coster:
    51583: 03/01/16: SpartanII DLL lock issue
    51740: 03/01/20: Re: SpartanII DLL lock issue
Richard Cotterill:
    8792: 98/01/27: XC4000XL negative hold time
Richard Crewe:
    50342: 02/12/09: Re: problem in Handel-C
    50413: 02/12/10: Re: problem in Handel-C
    72470: 04/08/20: Re: A timer with Celoxica RC100
Richard D. Copeland, Jr.:
    55206: 03/04/30: Xilinx OPB DDR Core
Richard D. Hunt:
    16689: 99/06/02: Rice Decompression Algorithm
Richard D. Mohlere:
    30700: 01/04/24: Re: Something about the counter
Richard Damon:
    8706: 98/01/21: Re: FPGA Info.
    9073: 98/02/18: Re: Altera CPLD power-up procedure?
    9717: 98/04/01: Re: Altera Bitblaster or Byteblaster??
    9944: 98/04/15: Re: MAXPLUS II ver7.1 & EPM 7128LC84,7160LC84
    12242: 98/10/06: Re: RAM Implementation in Altera Flex10K100A
    18095: 99/09/29: Re: How can I use an Altera .gdf file in my text file?
    18751: 99/11/11: Re: read back Altera
    47646: 02/10/01: Re: Unused pins in Apex20KE
    155012: 13/03/27: Re: What a Xilinx fpga could do in 1988
    155326: 13/06/23: Re: Ask about finding maximum and second's maximum number in array
    155596: 13/07/28: Re: serial protocol specs and verification
    155608: 13/07/30: Re: serial protocol specs and verification
    155656: 13/08/01: Re: serial protocol specs and verification
    155667: 13/08/02: Re: serial protocol specs and verification
    155681: 13/08/02: Re: serial protocol specs and verification
    155983: 13/11/02: Re: Simulation of VHDL code for a vending machine
    156028: 13/11/11: Re: generating clocks
    156053: 13/11/14: Re: generating clocks
    156165: 14/01/04: Re: Optimising pin allocation
    156669: 14/05/31: Re: shift register (invariable size) FIFO = ?
    156831: 14/07/06: Re: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit
    157511: 14/12/14: Re: Using FPGA to feed 80386
    157626: 15/01/08: Re: Image rotation
Richard Dempster:
    20625: 00/02/16: Choosing the correct size FPGA
Richard Dungan:
    6312: 97/05/14: Anyone using Actel software?
    8112: 97/11/18: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
    8288: 97/12/05: Re: A suggestion for Xilinx
    9708: 98/04/01: Re: XactStep6 - The cure for a dongle
    13523: 98/12/07: Re: Will XILINX survive?
    13735: 98/12/21: Re: Atmel's PLD
    15477: 99/03/25: Re: DIY Xilinx Download Cable
    17140: 99/07/02: Re: FW: Xilinx Acquisition of CoolRunners
    18774: 99/11/14: Re: How many bits in an FPGA bitstream?
    20249: 00/02/02: Re: Tools and how little guy is treated (was Xilinx Tools)
    25580: 00/09/14: Re: Virtex 'shutdown' phenomenon
    26931: 00/11/03: Re: OT: Xilinx T-Shirt
    27603: 00/11/29: Re: Xilinx Coolrunner going on last time buy?
    28749: 01/01/23: Program Atmel CPLD with Xilinx JTAG Cable?
    30931: 01/05/03: Re: High resolution time measurement?
    31727: 01/06/04: Re: Xilinx Coolrunner 100% routable - but the tools aren't
    33098: 01/07/17: Re: Coolrunner: availability
    34564: 01/08/29: Re: Defending Austin Franklin
    35409: 01/10/03: Xilinx Foundation vs. ISE
Richard Erlacher:
    12071: 98/09/27: Re: A Johnson counter
    12065: 98/09/26: Re: shareware
    17620: 99/08/15: file format conversion for obsolete 3000-series XILINX parts?
    17678: 99/08/23: Re: microcontroller vs FPGA
    17763: 99/09/01: Re: microcontroller vs FPGA
    17961: 99/09/19: Re: fpga board : make it or buy it?
    17962: 99/09/19: Re: microcontroller vs FPGA
    17874: 99/09/15: Re: differences between ALTERA-XILINX
    17929: 99/09/17: Re: Xilinx XC4005E
    17930: 99/09/17: List of free development tools for FPGA/CPLD devices?
    18093: 99/09/29: Re: Reasonable out-of-circuit programming platform desired
    18521: 99/10/28: Re: schematics ==> www
    18767: 99/11/13: Re: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
    18621: 99/11/03: Re: Xlinx FPGA
    18803: 99/11/17: Re: Q: implementing TCP/IP on PLD
    18827: 99/11/18: Re: COM1-FPGA communication
    19300: 99/12/11: Re: AM2901 bit slice processor
    19301: 99/12/11: Re: hobbyist friendly pld?
    19302: 99/12/11: Re: Simple programmator for EP910
    19578: 00/01/02: Re: Design security
    19581: 00/01/02: Re: hobbyist friendly pld?
    19670: 00/01/07: Re: Design security
    19671: 00/01/07: Re: Design security
    19672: 00/01/07: Re: Design security
    19926: 00/01/18: Re: hc11 core & fpga or cpld
    20008: 00/01/23: Re: Biphase mark decoder
    20854: 00/02/24: Re: Design security
    21081: 00/03/06: Re: Design security
    21296: 00/03/15: Re: Difference between FPGA, PLD, CPLD ?
    22733: 00/05/21: Re: Why are there no "cheap" FPGAs?
    22732: 00/05/21: Re: Do you know xilinx FPGAs well?
    23931: 00/07/16: Re: search free pcb programmer FPGA or CPLD
    27125: 00/11/11: Re: Configuring Xilinx FPGA using PIC16F84
    27126: 00/11/11: Re: Configuring Xilinx FPGA using PIC16F84
    29665: 01/03/04: Re: Xilinx question
    29759: 01/03/08: Re: Parallel Port EPP
    30113: 01/03/23: Re: Parallel Port EPP
    30149: 01/03/26: Re: cpul vs vhdl
    30452: 01/04/09: Re: Alternative to Xilink Foundation schematic editor
    30453: 01/04/09: Re: Handel-C
    31631: 01/06/01: Re: My80-- i8080A instruction compatible processor core
    31690: 01/06/03: Re: My80-- i8080A instruction compatible processor core
    32723: 01/07/06: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (1/1)
    36221: 01/11/02: Re: Cheap programming of XC2018?
    36222: 01/11/02: Re: GAL compiler
    36906: 01/11/24: Re: How to make an implementable big counter?
    36925: 01/11/26: Re: How to make an implementable big counter?
    37086: 01/11/29: Re: Is there a full open-source synthesis path for any FPGA?
    40005: 02/02/24: Re: CPLD PROJECT
    55605: 03/05/13: CollRunner-II EVB problems
    55683: 03/05/15: Re: CollRunner-II EVB problems
    55821: 03/05/20: Re: CollRunner-II EVB problems
    56470: 03/06/05: Simulation problem with XILINX library component
    56486: 03/06/06: Re: Simulation problem with XILINX library component
    56862: 03/06/17: Re: An All Digital Phase Lock Loop
    56913: 03/06/18: applying SCHMITT_TRIGGER to CoolRunner-II CPLD's
    56914: 03/06/18: defective netlist in ISE 5.2.03
    57156: 03/06/24: Re: defective netlist in ISE 5.2.03
    57159: 03/06/24: Re: applying SCHMITT_TRIGGER to CoolRunner-II CPLD's
    57160: 03/06/24: Re: PALs, GALs and ABEL
    57365: 03/06/28: Re: Xilinx Webpack bugs bugs bugs
    66514: 04/02/20: old CPLD programmer wanted
Richard Evans:
    290: 94/10/13: Re: Xilinx configuration
Richard F. Man:
    23882: 00/07/13: Re: Silicon Valley Housing Nightmare?
Richard G.:
    149576: 10/11/06: Statemachine debugging with Chipscope
Richard Gaupsas:
    4852: 96/12/20: CPLD / VHDL question
    7231: 97/08/17: 160 pin PGA socket in stock?
Richard George x 7247 sun:
    446: 94/11/18: any XC4000 Horror Stories?
Richard Gerber:
    8810: 98/01/27: Call For Papers -- IEEE Real-Time Systems Symposium 1998
Richard Gregg:
    1182: 95/05/12: Power consumption of Xilinx FPGAs
    3507: 96/06/12: Re: Xilinx 4013E and PCI
Richard Griffin:
    18265: 99/10/11: Re: Fineline BGAs
Richard Griffith:
    77636: 05/01/12: Re: Exportability of EDA industry from North America?
Richard Guerin:
    15113: 99/03/08: Manchester Decoder VHDL Model
    15151: 99/03/10: Re: micro computer using Xilinx
    15206: 99/03/13: Power Estimiation
    15213: 99/03/14: Re: Actel FPGA
    15241: 99/03/16: Re: Power Estimiation
    15266: 99/03/17: Re: Power Estimiation
    15267: 99/03/17: Re: How can I improve an adder?
    15300: 99/03/18: Re: Power Estimiation - report.zip (0/1)
    15303: 99/03/18: Re: Power Estimiation
    15361: 99/03/20: Re: FPGA vendor comparison
    15369: 99/03/21: Free Xilinx Vendor Tools ... NOT :-(
    15374: 99/03/21: Re: Free Xilinx Vendor Tools ... NOT :-(
    15376: 99/03/21: Re: From VHDL to FPGA?
    15412: 99/03/23: Re: Free Xilinx Vendor Tools ... NOT :-(
    15488: 99/03/26: Re: Free Xilinx Vendor Tools ... NOT :-(
    15490: 99/03/26: Re: Free Xilinx Vendor Tools ... NOT :-(
    15502: 99/03/26: Re: IBM 600MHz FPGA
    15505: 99/03/27: Re: What do you think about philips XPLA?
    15510: 99/03/28: Re: Free Xilinx Vendor Tools ... NOT :-(
    15511: 99/03/28: Re: Info about FPGA/PLD
    15515: 99/03/29: Re: Info about FPGA/PLD
    15516: 99/03/29: Re: Free Xilinx Vendor Tools ... NOT :-(
    15520: 99/03/29: Re: Info about FPGA/PLD
    15531: 99/03/29: Re: Info about FPGA/PLD
    15532: 99/03/29: Re: Free Xilinx Vendor Tools ... NOT :-(
    15567: 99/03/31: Re: Free Xilinx Vendor Tools ... NOT :-(
    15581: 99/04/01: Re: Schematic Capture & FPGA synthesis
    15595: 99/04/02: Re: Schematic Capture & FPGA synthesis
    15609: 99/04/02: Re: Schematic Capture & FPGA synthesis
    15696: 99/04/09: Re: Levels of logic
    15765: 99/04/13: Re: FIFO
    15852: 99/04/16: Re: std_logic_arith
    15969: 99/04/23: Re: Free Xilinx CPLD design software on the web
    16963: 99/06/21: Re: Actel's proASIC
    17783: 99/09/03: Re: QuickLogic FPGAs
    17839: 99/09/10: Re: Newbie question: Reading FPGA programming?
    18103: 99/09/30: Re: Fine grain vs. Coarse grain
Richard He:
    56558: 03/06/09: where have some arithmetic of verilog or vhdl?
Richard Head:
    136571: 08/11/22: Re: Generate sample rate ...
Richard Heathfield:
    104777: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
    118877: 07/05/05: Re: debounce state diagram FSM
Richard Henry:
    95586: 06/01/24: Re: Very OT: Americanized family names
    95040: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95061: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95143: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95236: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95267: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95484: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95488: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    107509: 06/08/29: September training?
    107532: 06/08/29: Re: September training?
    113529: 06/12/15: Re: electrical level conversion
    119389: 07/05/17: Visio logic symbols
    119399: 07/05/17: Re: Visio logic symbols
    119410: 07/05/17: Re: Visio logic symbols
    121174: 07/06/27: Bidirectional LVDS
    121181: 07/06/27: Re: Bidirectional LVDS
    121186: 07/06/27: Re: Bidirectional LVDS
    121274: 07/06/29: Re: Bidirectional LVDS
Richard Hogers:
    14765: 99/02/16: Anyone experience with Aptix?
Richard I. Guerin:
    21346: 00/03/17: Re: Actel Design with A42MX36 Help
Richard Iachetta:
    7154: 97/08/07: Re: Are 2 PCs better than One?
    7240: 97/08/18: Re: FPGA Express...
    7300: 97/08/22: Re: MaxPlusII from Altera.
    7315: 97/08/25: Re: MaxPlusII from Altera.
    8440: 97/12/15: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
    8446: 97/12/15: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
    8464: 97/12/17: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
    8728: 98/01/22: Re: XC4000E CLB utilization
    8897: 98/02/05: Re: Off topic...Netiquite and Emoticons WAS Re: VHDL vs schematics, I vote for VHDL and this is why...
    9328: 98/03/06: Re: Whats wrong with this method
    9801: 98/04/06: Re: Counter problem ?
    10209: 98/05/04: Re: Creating a clock with a clock enable
    10210: 98/05/04: Re: How to make FIFO's in Altera FLEX8000 or FLEX6000
    10411: 98/05/17: Re: "Inferred" I/O flip-flops in XC4000E
    10453: 98/05/19: Re: Building signal delays inside an FPGA
    10744: 98/06/15: Re: Representing Registers?
    11053: 98/07/15: Re: high-speed place and route
    12568: 98/10/16: Re: gray code counter in a Xilinx fpga???
    13455: 98/12/03: Re: Minimum clock freq reqd
    14534: 99/02/03: Re: VHDL clocked one-shot Implementation Problem
    15122: 99/03/08: Re: newbie question about PALASM 1.5
    21646: 00/03/27: Re: RTL vs. gate level simulation
    21674: 00/03/28: Re: RTL vs. gate level simulation
    22724: 00/05/19: Re: Translate to verilog
    30374: 01/04/04: Re: PCI-X core
    34372: 01/08/22: Re: Slowing PCI for FPGA
    34410: 01/08/23: Re: Slowing PCI for FPGA
    36191: 01/11/01: Re: Verilog vs. VHDL
    38095: 02/01/04: Re: asic vs. fpga
    44678: 02/06/26: Re: why not pipeline by default?
    45896: 02/08/09: Re: ... milk for free, Opencores?
    49257: 02/11/06: Re: Incremental design question
    51208: 03/01/06: Re: asynchronous inputs
    52707: 03/02/19: Re: Messaging Unit + Dorbells etc ..
    53035: 03/02/28: Re: PCI specification question
    59818: 03/08/28: Re: Thinking out loud about metastability
    61776: 03/10/10: Re: pci-x133 to parallel pci-66
    63743: 03/12/02: Re: Exact Timing Constraints vs. Over-Constraining
Richard J Warburton:
    10802: 98/06/21: Control skew due to routing in Xilinx M1
    10805: 98/06/21: Re: Control skew due to routing in Xilinx M1
    10806: 98/06/21: Re: Foundation M1.4 functional simulation problems
    10841: 98/06/24: Re: Control skew due to routing in Xilinx M1
Richard J. Auletta:
    518: 94/12/17: Call For Papers ASIC '95
    3324: 96/05/13: Windows NT & Xilinx & Cypress
    4009: 96/09/02: Re: ANNOUNCE: $499 PeakVHDL Training Edition Simulator
    4129: 96/09/16: Re: Good Starting points to learn FPGA for hobbyist?
    5621: 97/03/02: Re: Instatiation of Xilinx Primitives in VHDL?
    5622: 97/03/02: Re: Cypress says good-bye to Anti-Fuse
    5645: 97/03/04: Re: Cypress says good-bye to Anti-Fuse
    5942: 97/03/27: Xilinx RAM & Synopsys BC
    6093: 97/04/11: Re: comp.arch.fpga archiv dead?
    6172: 97/04/22: CFP ASIC 97 (April 24th Deadline)
    6102: 97/04/12: Re: Seeking PALASM/ABEL/CUPL/?
    8255: 97/12/03: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
Richard John:
    11789: 98/09/09: Re: Constraining Xilinx tools to NOT use certain pins?
Richard John Farmer:
    1379: 95/06/09: Re: 256k Serial Configuration PROM for Xilinx???
Richard Jozefowski:
    4052: 96/09/06: ORCA and Viewlogic - any good?
    4072: 96/09/08: Re: ORCA and Viewlogic - any good?
    4284: 96/10/09: ORCA 2C10A - RAM placement advice
richard katz:
    8566: 98/01/09: Re: Xilinx Stock
    8583: 98/01/11: Re: Xilinx Stock
    8590: 98/01/12: Re: Xilinx Stock
    8591: 98/01/12: Re: Xilinx Stock
    8598: 98/01/12: Re: Clock net skew simulation
    8609: 98/01/13: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8645: 98/01/16: Re: Clock net skew simulation
    8646: 98/01/16: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8655: 98/01/17: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8659: 98/01/17: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8661: 98/01/18: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8676: 98/01/19: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8679: 98/01/19: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8681: 98/01/20: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8702: 98/01/21: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8716: 98/01/22: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8718: 98/01/22: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8763: 98/01/24: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8575: 98/01/10: Re: Altera Flex10K Standby Current
    8734: 98/01/22: Re: Radhard FPGA Vendors?
    8767: 98/01/25: Re: Military FPGAs
Richard Keaney:
    160: 94/09/05: XC3000 vs XC3100 series FPGAs
Richard Klingler:
    112677: 06/11/27: nios2 toolchain sources
    112679: 06/11/27: Re: nios2 toolchain sources
    112707: 06/11/27: Re: nios2 toolchain sources
    112708: 06/11/27: Re: nios2 toolchain sources
    118027: 07/04/16: License Key based on WLAN/Bluetooth MAC
    118032: 07/04/16: Re: License Key based on WLAN/Bluetooth MAC
    118289: 07/04/23: Lattice pricing
    118413: 07/04/26: Re: License Key based on WLAN/Bluetooth MAC
    118955: 07/05/08: Re: License problems with Quartus 7.0 on Linux
    119483: 07/05/21: Cyclone FPGAs in Switzerland
    120772: 07/06/16: ispLever 7.0
    122369: 07/07/26: Re: Altera or Xilinx
    122667: 07/08/02: Forwarding engines
    122844: 07/08/08: Mico32
    123007: 07/08/14: mixed Verilog/VHDL in ispLever 7.0 broken
    123011: 07/08/14: Re: mixed Verilog/VHDL in ispLever 7.0 broken
    123079: 07/08/15: Mico32 bootloader
Richard Knispel:
    30482: 01/04/10: help with ABEL-HDL and CPLDs
    30504: 01/04/11: Re: help with ABEL-HDL and CPLDs
Richard Lamb:
    67170: 04/03/08: Re: Implementing a reliable counter inside SDRAM memory mapped device
Richard Lamoreaux:
    19812: 00/01/13: Reliability of programming SRAM FPGAs
    25103: 00/08/25: Xilinx 18V02 Prom Parallel mode fails
Richard Lazarus:
    2919: 96/02/29: Re: Languages for reconfigurable computing.
    2942: 96/03/04: Re: Languages for reconfigurable computing.
richard lee:
    11257: 98/07/31: How to use fpga do a programmable clock generator(50hz to 50k )
    11728: 98/09/04: How to use fpga do a sync/async converter
Richard Lomas:
    3524: 96/06/14: Re: Double Port Ram - Xact Libs
Richard M. Greene:
    2321: 95/11/20: Re: [q][Reverse Engineering Protection]
    3067: 96/03/26: FPGA for military and space environments
    3230: 96/04/30: Re: FPGA for Space Application
    3289: 96/05/09: Reposting of: FPGA for SPACE/RADIATION applications
Richard Martineau:
    30422: 01/04/07: xilinx price lists
    30423: 01/04/07: Re: XCV1000BG560: onchip ram
Richard Meacham:
    3569: 96/06/26: XC3100A Tristates
    3608: 96/07/03: Re: Need recommendation for PCI interface on 68332
Richard Meester:
    24117: 00/07/27: Crossbar Switch.
    24257: 00/08/01: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
    24644: 00/08/16: fifo;s
    24702: 00/08/17: multiple drivers & foundation 2.1i
    25491: 00/09/12: flipflops/statemachine/fifos and timing
    25513: 00/09/13: Re: flipflops/statemachine/fifos and timing
    25515: 00/09/13: Re: flipflops/statemachine/fifos and timing
    25613: 00/09/15: timing constraints
    25921: 00/09/26: Global clock buffers and secondary clock buffers.
    25929: 00/09/26: Re: Global clock buffers and secondary clock buffers.
    25960: 00/09/28: Re: timing constraints
    26110: 00/10/04: Re: JVM processor
    27150: 00/11/13: LUT and EDIF
    27183: 00/11/14: Re: LUT and EDIF
    27371: 00/11/20: Re: 8-way MIMD multiprocessor in an XCV50E
    29364: 01/02/16: Optimization problem with SPARTANII
    29412: 01/02/20: Re: UCF problem "- Could not find NET "
    30545: 01/04/13: ad: Spartan II Prototyping boards.
    30773: 01/04/28: Re: C++ To Gates
    30777: 01/04/28: Re: C++ To Gates
    30806: 01/04/30: Re: C++ To Gates
    30834: 01/05/01: Re: C++ To Gates
    30837: 01/05/01: Re: C++ To Gates
    30847: 01/05/01: Re: C++ To Gates
    31284: 01/05/17: Re: Getting Started with FPGAs
    31425: 01/05/23: SPARTANII prototype boards + microcontroller available
    31454: 01/05/25: JTAG source
    32108: 01/06/14: Re: Flash programming via FPGA's JTAG ?
    32295: 01/06/22: Re: Searching any 144 pin SO-DIMM module
    35525: 01/10/09: anyone know of SDRDRAM controller for free?
    36148: 01/10/31: searchin for High density non bga packages something like PGA.
    39363: 02/02/07: Multiple clock domein synchronization.
    39393: 02/02/08: Re: Multiple clock domein synchronization.
    39409: 02/02/08: Help on bus interface needed.
    39433: 02/02/09: Re: Help on bus interface needed.
    39499: 02/02/12: Re: Help on bus interface needed.
    39522: 02/02/12: Re: Help on bus interface needed.
    39547: 02/02/13: Re: Help on bus interface needed.
Richard Newman:
    75348: 04/11/02: Re: information about Nuhorizon Spartan-3 Development Board ?
Richard Nuth:
    6385: 97/05/20: Re: Cadence or World Technology, or other NT vendors...
Richard Owlett:
    66460: 04/02/19: Re: Dual-stack (Forth) processors
    66462: 04/02/19: Re: Dual-stack (Forth) processors
    88038: 05/08/07: Re: System Engineering in the R/D World
    95092: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95125: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95133: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95137: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    99436: 06/03/24: FPGA introduction/FAQ?
    133964: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
Richard Padovan:
    38221: 02/01/09: Interpreting Xilinx Timing Analyser report files
Richard Pennington:
    69820: 04/05/21: Re: Nios II Going Live...
    71244: 04/07/13: Re: NIOS 2 HAL, libraries, ...
    112773: 06/11/29: Re: nios2 toolchain sources
    117697: 07/04/07: A new way to define systems of systems?
    117700: 07/04/07: Re: A new way to define systems of systems?
    117713: 07/04/08: Re: A new way to define systems of systems?
    117716: 07/04/08: Re: A new way to define systems of systems?
    117718: 07/04/08: Re: A new way to define systems of systems?
    117787: 07/04/10: Re: A new way to define systems of systems?
    117874: 07/04/12: Re: A new way to define systems of systems?
    140328: 09/05/09: Re: OpenCores CAN/Ethernet cores
Richard Rooney:
    27209: 00/11/15: Problem with Endianess in Xilinx Tools.
    29629: 01/03/02: [AD]: PIC-based Embedded Webserver/Webclient available.
Richard Russell:
    1474: 95/06/27: Re: Xilinx PLDMAP usage. Pro's and Cons?
    2435: 95/12/05: Re: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
    14947: 99/02/26: Re: Xilinx ABEL?
Richard Schwarz:
    3851: 96/08/09: Re: Commercial:gap in the market! ANIMAL
    3852: 96/08/09: FPGA TEST BOARDS
    3860: 96/08/10: Re: Commercial:gap in the market! ANIMAL
    3861: 96/08/10: Re: Commercial:gap in the market! ANIMAL
    3862: 96/08/10: Shareware XILINX Synthesis Tool???
    3863: 96/08/10: ASIC simulations in multiple FPGAs
    3936: 96/08/22: Biggest FPGA
    3937: 96/08/22: CHEAP XILINX FPGA ROUTING SOFTWARE ?
    3949: 96/08/23: BIG FPGA
    3947: 96/08/23: Low Cost/Shareware XILINX synthesis software?
    3946: 96/08/23: Low cost or shareware into-level routing/synthesis softwae
    3948: 96/08/23: BIGGEST FPGA
    3957: 96/08/24: TEST
    3993: 96/08/30: VHDL/VERILOG SIMULATORS
    4177: 96/09/22: Re: Are there any FPGA Starter Kits?
    4178: 96/09/22: Re: FPGAs design tools for PC
    4179: 96/09/22: Inexpensive XILINX FPGA STARTER BOARDS
    4215: 96/09/28: Re: FIR filter using FPGAs??
    4438: 96/10/29: Need fast/small SRAMS
    4670: 96/11/27: Re: FPGA TEST BOARDS
    4770: 96/12/13: XILINX TEST BOARD WITH ROUTING SOFTWARE
    4893: 96/12/26: Low $$$ XLNX Kits w Routing
    5036: 97/01/15: Re: Great Xilinx FPGA Kits & prices
    5062: 97/01/18: Re: advice request
    5140: 97/01/26: Re: FPGA Lab. KIT
    5241: 97/02/01: Re: Reconfigurable Logic Query
    5242: 97/02/01: Re: FPGA Lab.
    5243: 97/02/01: Re: FPGA with SRAM
    5244: 97/02/01: Re: FPGAs with internal Tri-state busses ?
    5339: 97/02/08: Re: [Q] Xilinx FPGA Resources
    5340: 97/02/08: Re: Q is Xilinx Foundation BASE worth buying?
    5341: 97/02/08: X84 board VHDL examples
    5409: 97/02/14: Re: Random Number Generators with Xilinx FPGA xc4000 series
    5438: 97/02/15: Re: Random Number Generators with Xilinx FPGA xc4000 series
    5505: 97/02/21: Re: Q: Search Engines for Electronic Parts?
    5504: 97/02/21: Re: [Q] Xilinx FPGA Resources
    5616: 97/03/01: ACTEL RAM BASED FPGAs
    5748: 97/03/12: Re: VHDL & ABEL synthesis tools on 95/NT
    5749: 97/03/12: Re: DEVICE SELECTION
    5779: 97/03/14: Re: Development board with multiple FPGAs
    5792: 97/03/15: Re: VHDL & ABEL synthesis tools on 95/NT
    5805: 97/03/16: Re: ACTEL RAM BASED FPGAs
    5806: 97/03/16: Re: Xilinx/NeoCAD software vs. XC4KE question
    5888: 97/03/23: Re: What tools for $8000?
    5889: 97/03/23: Re: Sole source
    5890: 97/03/23: Re: Accolade
    5956: 97/03/31: Free VHDL /FPGA newsletter
    6002: 97/04/03: Re: QAM in FPGA
    6111: 97/04/12: XILINX FOUNDATION STUFF!!
    6122: 97/04/13: Re: XILINX FOUNDATION STUFF!!
    6253: 97/05/04: Test
    6254: 97/05/04: ANNOUNCE: XILINX FPGA Kits prices
    6294: 97/05/09: NEW XILINX M1 Release
    6350: 97/05/17: Re: Cheap way to develop for FPGAs?
    6359: 97/05/18: FPGA Lab Kits available NOW
    6361: 97/05/18: Re: Gatefield FPGA Design Experiences
    6430: 97/05/23: Re: Cheap way to develop for FPGAs?
    6431: 97/05/23: Re: Pointer to a BER Circuits
    6456: 97/05/25: New ON-LINE VHDL/FPGA TUTORIAL
    6483: 97/05/27: Re: Best way to learn VHDL?
    6484: 97/05/27: Re: What is M1?
    6466: 97/05/26: Re: Cheap way to develop for FPGAs?
    6840: 97/07/01: BEST FPGA/EDA INFORMATION SITE
    6855: 97/07/02: FREE EDA Newsletter
    6901: 97/07/07: Re: Vhdl synthesis tools for PC
    6976: 97/07/17: Re: FPGA design tools
    7014: 97/07/22: Re: VHDL Synthesis in Xilinx Foundation Series
    7099: 97/07/31: Re: VHDL Synthesis in Xilinx Foundation Series
    7202: 97/08/14: Re: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
    7203: 97/08/14: Re: free FPGA software from actel
    7100: 97/07/31: Re: Quick prototyping? Best solution?
    7289: 97/08/21: X84 FPGA Board $199.00
    7392: 97/09/05: ANNOUNCE APS Low cost LUCENT FPGA Kits
    7394: 97/09/05: Announce APS-Synth-All Multi-Vendor kits
    7444: 97/09/10: Text Book and VHDL Simulator $50.00
    7457: 97/09/12: Re: Text Book and VHDL Simulator $50.00
    7464: 97/09/13: Re: Text Book and VHDL Simulator $50.00
    7458: 97/09/12: pellerin@seanet.com
    7592: 97/09/24: bo3468ma@uscolo.edu
    7593: 97/09/24: Re: bo3468ma@uscolo.edu
    7595: 97/09/25: Free FPGA/EDA Newsletter
    7619: 97/09/28: Re: Still for sale OrCAD SDT & Xilinx XACT
    7676: 97/10/02: Re: XILINX and ALTERA development boards
    7678: 97/10/02: Re: Wanted: cheap way to learn VHDL
    7748: 97/10/10: WOW! Complete XILINX dev kits WITH X84 BOARD $300.00
    7749: 97/10/10: Very Low Cost VHDL Windows Simulator
    7778: 97/10/14: Re: VHDL Simulation
    7813: 97/10/17: FREE APS EDA QUARTERLY NEWSLETTER END Q3 RELEASED
    7850: 97/10/22: Shrink wrapped Lucent VHDL kits
    8045: 97/11/11: Re: FPGA basics please ?
    8220: 97/11/29: Re: FPGAs for hobbyist, HELP
    8221: 97/11/29: ROUTER/TEST BOARD/CPLD/FPGA all for $350.00
    8314: 97/12/08: Useable demo VHDL Synthesis/Simulation Software
    8459: 97/12/16: Best way to get Started with FPGAs
    8465: 97/12/17: Re: FPGA Prototyping on the ISA Bus
    8501: 97/12/26: XILINX and Lucent FPGA Test Boards
    8523: 98/01/04: XILINX Test boards Lowest prices
    8537: 98/01/06: Re: Newbe to fpga
    8746: 98/01/23: Free EDA VHDL/FPGA Newsletter
    8847: 98/02/01: Re: VHDL book
    9195: 98/03/01: Re: Xilinx Info.
    8899: 98/02/05: Power consumption
    8900: 98/02/05: Re: can u give me some advice?
    8940: 98/02/08: Re: Free FPGA tools???
    8941: 98/02/08: Complete VHDL system
    8987: 98/02/11: X84 BOARD with demo VHDL CD and examples
    9181: 98/02/28: Free FPGA VHDL newsletter
    9193: 98/03/01: Re: Dsp Fpga and vhdl project
    9194: 98/03/01: Re: Newbie Question : FPGA and VHDL
    9384: 98/03/08: LARGE SELECTION OF FPGA BOARDS & KITS
    9417: 98/03/11: Re: LARGE SELECTION OF FPGA BOARDS & KITS
    9476: 98/03/16: Re: FPGA/VHDL design tools review < $10K
    9477: 98/03/16: Re: Ideas for an FPGA Project?
    9523: 98/03/20: To: Paul Young of Caterpillar
    9589: 98/03/24: Lowest POWER FPGAs???
    9590: 98/03/24: Re: To Richard Schwarz of APS
    9645: 98/03/27: Re: Request..
    9662: 98/03/29: Re: Q: Random number generator
    9786: 98/04/05: Re: Choosing the right FPGA tools...
    9787: 98/04/05: Re: Choosing the right tools and company....
    9936: 98/04/14: Tutorials and Support Kits
    9935: 98/04/14: Re: Someone with Foundation Express version 1.4, please help me
    10068: 98/04/25: Re: How low can they go?
    10072: 98/04/25: XILINX,LUCENT, ATMEL FPGA Test BOARDS
    10081: 98/04/26: Prototyping and VHDL tips, tutorials and tools
    10085: 98/04/26: VHDL and Prototyping tips
    10199: 98/05/03: Free FPGA/EDA Quarterly Newsletter
    10812: 98/06/22: Re: Getting into using FPGAs
    10813: 98/06/22: Re: books on vhdl
    11322: 98/08/04: Re: VHDL std_logic_vector to integer
    11686: 98/09/01: Re: FPGA vendors
    11687: 98/09/01: Re: SYNTHESIS TOOLS
    11688: 98/09/01: Re: VHDL std_logic_vector to integer
    11887: 98/09/16: Good EDN article on FPGA Synthesis
    12033: 98/09/25: Re: Which FPGA tool is better
    12034: 98/09/25: Re: FPGA information
    12130: 98/09/30: Re: Simple programmable device suggestions please?
    12138: 98/10/01: Re: Simple programmable device suggestions please?
    12182: 98/10/02: VHDL Consultant needed
    12702: 98/10/23: 3.3V FPGAs on the ISA bus?????
    12714: 98/10/24: Re: Need VHDL tools for Win NT/ Win 95
    12737: 98/10/27: FPGA Decouple Capacitor values
    12903: 98/11/04: Re: Q: Configure FPGA from an ISA bus?
    12904: 98/11/04: XILINX NODELAY Attribute
    12906: 98/11/04: Need FPGA/VHDL designers in Balt/Washington area
    13313: 98/11/25: Free VHDL/FPGA Newsletter released q498
    13312: 98/11/25: Re: Add-in board with FPGA Secondary Processor
    13451: 98/12/03: Re: Will XILINX survive?
    13452: 98/12/03: Re: Will XILINX survive?
    13453: 98/12/03: Re: Will XILINX survive?
    13701: 98/12/18: Async Fifo Core or Macro for Xilinx FPGA
    14018: 99/01/07: Re: FPGA development system
    15661: 99/04/06: Re: newbie: FPGA suggestion
    15662: 99/04/06: Announce:Network ready XILINX FPGA boards to be be released
    15690: 99/04/08: Re: EEPROM for XC4010XL
    15692: 99/04/08: Re: Data Types and Synthesis
    15694: 99/04/08: Re: FPGA testing board
    15806: 99/04/15: Re: Obsolete Xilinx series - how to use them?
    15833: 99/04/16: Re: Some FPGA questions
    17002: 99/06/22: Re: FPGA in Wireless Designs
    17683: 99/08/24: FAST CORRELATOR 4096 by 1 40 Mhz
    21797: 00/03/31: Re: APS V240 board
    41788: 02/04/08: FPGA HDL APS Newsletter released
    45810: 02/08/06: Re: VIRTEX-II pro -> LVTTL 3.3
    45811: 02/08/06: Standardized IO connectors for RocketIO 3GIO (ExpressPCI) LVDS
    45812: 02/08/06: New XILINX ISE not supporting 4000 series FPGAs?
Richard Sloan:
    8739: 98/01/23: Looking for someone to help......
    8759: 98/01/24: PCMCIA inteface
Richard Staley:
    4615: 96/11/21: Lattice ISP Question
    4650: 96/11/26: Re: Lattice ISP Question
    9420: 98/03/12: Altera Programmer with NT4
    9433: 98/03/13: Re: Altera Programmer with NT4
Richard Steven Walz:
    1575: 95/07/20: Re: Intel FLEXLogic
    7173: 97/08/10: Re: free FPGA software from actel
    7197: 97/08/13: Re: free FPGA software from actel
    35667: 01/10/12: Re: Lattice discontinues all smaller MACH circuits and other devices
    46562: 02/09/03: Re: Hardware Code Morphing?
    46564: 02/09/03: Re: Hardware Code Morphing?
richard taylor:
    1682: 95/08/15: Final CFP : Verification and Validation of Hardware-Software Codesigns
    2070: 95/10/10: IEE Colloquium : Verification of hardware-software codesigns
    2385: 95/11/27: Second CFP : Cosynthesis for reconfigurable systems
Richard Temple:
    64504: 04/01/06: Re: Spartan3 availability
    64769: 04/01/13: Re: Altera NIOS cyclone edition development board problem
    64770: 04/01/13: Re: Altera Cyclone Serial Configuration devices.
    64851: 04/01/15: Re: Microblaze simulation
Richard the Dreaded Libertarian:
    95241: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95495: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95496: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95499: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95514: 06/01/23: Re: OT:Shooting Ourselves in the Foot
Richard Thompson:
    79867: 05/02/25: IP unnecessarily using Spartan-3 DCM?
    79872: 05/02/25: Re: IP unnecessarily using Spartan-3 DCM?
    79886: 05/02/25: Re: IP unnecessarily using Spartan-3 DCM?
    79904: 05/02/25: Re: IP unnecessarily using Spartan-3 DCM?
    80077: 05/03/01: SR latches in Xilinx devices?
    80083: 05/03/01: Re: SR latches in Xilinx devices?
    80101: 05/03/01: Re: SR latches in Xilinx devices?
    80150: 05/03/02: Re: SR latches in Xilinx devices?
    80153: 05/03/02: Xilinx ISE history?
    80159: 05/03/02: Re: Xilinx ISE history?
    80168: 05/03/02: Re: Xilinx ISE7.1
    80387: 05/03/04: Re: SR latches in Xilinx devices?
    80395: 05/03/04: Re: SR latches in Xilinx devices?
Richard Tierney:
    77317: 05/01/04: Free JTAG board test software?
Richard Tse-Woon Paw:
    2091: 95/10/12: Re: [Q] Looking for VHDL models for FPGA
Richard Vireday:
    34: 94/08/01: Re: Help: Homebrew development hardware source
    150: 94/09/01: Re: PLDshell/Intel ftp site
    211: 94/09/22: Re: Software costs (was Re: Lattice ISP softw
    207: 94/09/21: Software costs (was Re: Lattice ISP software)
    250: 94/10/03: iFX8160 & PLDshell status
    692: 95/02/08: Re: Question on 22v10 fitting in Warp2
    1513: 95/07/06: Re: JEDEC File format
    2803: 96/02/09: Re: New Reconfigurable Computing Threads.
    2975: 96/03/07: Bits vs. Arrays (was Reconfigurable Computing Languages)
    3064: 96/03/25: Re: Low-power FPGA or EPLD
    3189: 96/04/22: Comp.arch.fpga FAQ- Frequently Asked Questions List
    4100: 96/09/10: Re: Gate Count - Notion of Gate
    4258: 96/10/05: Re: Altera Checksums
Richard Wieler:
    3713: 96/07/19: Re: What about the XC6200 ?
Richard Wilkinson:
    27581: 00/11/29: Synplify Benchmarks
    27593: 00/11/29: Re: Synplify Benchmarks
    29190: 01/02/09: Synplify on Windows2000?
    35023: 01/09/18: Synplify BUFG instantiation bug
Richard Young:
    5215: 97/01/31: Newbie Q about Viewlogic and Altera tools
Richard Yu:
    7754: 97/10/11: FPGA News Resource Page
    7755: 97/10/11: FPGA News Resource Page
<richard.draelos@gmail.com>:
    135593: 08/10/09: how to share infered ROM memories in synplify?
<richard.melikson@gmail.com>:
    124019: 07/09/11: Uses of Gray code in digital design
    124037: 07/09/11: Re: Uses of Gray code in digital design
    124038: 07/09/11: Re: Uses of Gray code in digital design
    124040: 07/09/11: Re: Uses of Gray code in digital design
    124042: 07/09/11: Re: Uses of Gray code in digital design
    124047: 07/09/11: Re: Uses of Gray code in digital design
    124048: 07/09/11: Re: Uses of Gray code in digital design
    124049: 07/09/11: Re: Uses of Gray code in digital design
<Richard>:
    118076: 07/04/17: No Synplify evaluation?
<richard_hein@shaw.ca>:
    127652: 08/01/04: Re: xilinx v5 configeration problem
<richard_steinman@cmagroup.com>:
    4527: 96/11/08: Upstate NY; Senior Engineer Wanted; FPGA; High Speed Digital
    4570: 96/11/15: Job; Upstate NY; Medical Imaging; FPGA; High Speed Digital; Altera
    6245: 97/05/02: Job-Upstate NY; Senior Engineer; FPGA; Altera
    6653: 97/06/09: Job-Upstate NY; Senior Engineer; FPGA; Altera
    6954: 97/07/15: Job; Senior Engineer; Altera; FPGA; High Speed Digital
    7427: 97/09/09: Job-USA; Charlotte, NC; Electrical engineer; FPGA, DSP; 50 Mghtz
    7523: 97/09/19: Job-Charlotte, NC; Electrical engineer; FPGA, DSP; 50 Mghtz
    8508: 97/12/29: Job-Colorado: Electrical Engineer; FPGA, telephony, embedded software
    9530: 98/03/21: Job-Colorado; Design Engineer; High Speed Digital, FPGA, DSPs
    11033: 98/07/13: Job- New York; Senior Engineer; Hardware, Imaging, Video, FPGA
Richi:
    150994: 11/02/28: Question regarding bitstream generation
richi:
    151022: 11/03/01: Re: Question regarding bitstream generation
richie singh:
    60857: 03/09/23: Accessing local GSR net of a Spartan-II
    63820: 03/12/04: Floorplanning techniques
    63855: 03/12/05: Re: Floorplanning techniques
richk:
    143058: 09/09/17: Re: Looking for Virtex-6 PCIe development board
RichKol:
    10709: 98/06/11: Looking for "A" designers only
richm:
    23280: 00/06/20: Re: Battery backup for 5V Xilinx Spartan devices
<richng01@gmail.com>:
    121991: 07/07/16: Xilinx System generator vs Simulink HDL Coder
rick:
    39913: 02/02/22: what's different between Foundation series and FPGA express
Rick:
    97: 94/08/15: Re: FPGA Hobbyist and their software/programmer/hardware
    103: 94/08/15: Re: FPGA Hobbyist and their software/programmer/hardware
    12433: 98/10/12: Re: Xilinx F1.5/FPGA Express wackiness
    12434: 98/10/12: Re: Xilinx F1.5/FPGA Express wackiness
    14440: 99/01/29: Re: Ratings for Synplicity Synplify
    14441: 99/01/29: Re: Ratings for Synplicity Synplify
    14442: 99/01/29: Re: Ratings for Synplicity Synplify
    15420: 99/03/23: Re: Xilinx Batchfile?
    43942: 02/06/06: Xilinx guided PAR problem
    43962: 02/06/07: Re: Xilinx guided PAR problem
    43963: 02/06/07: Re: xc3042
    49284: 02/11/07: Re: WebPACK 5.1 SP2
    53526: 03/03/15: JPEG encoder implementation
    66206: 04/02/14: Re: ARM+FPGA tiny board
    144734: 09/12/29: Seeking some advice
    144739: 09/12/30: Re: Seeking some advice
    144751: 09/12/30: Re: Seeking some advice
    144752: 09/12/30: Re: Seeking some advice
    144877: 10/01/11: Old School Hurts
    144880: 10/01/11: Re: Old School Hurts
    145462: 10/02/10: Re: using an FPGA to emulate a vintage computer
    145480: 10/02/11: Re: using an FPGA to emulate a vintage computer
    145733: 10/02/21: Re: using an FPGA to emulate a vintage computer
    146147: 10/03/06: Re: using an FPGA to emulate a vintage computer
    151505: 11/04/15: Simili
    151509: 11/04/15: Re: Simili
    152814: 11/10/25: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152839: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152869: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152916: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152957: 11/11/04: Re: Fundamental DSP/speech processing patent for sale
Rick C.:
    127440: 07/12/25: Re: FPGA Project Support
Rick C. Hodgin:
    157379: 14/12/02: Re: Which Altera to buy?
    157383: 14/12/02: Re: Which Altera to buy?
    157387: 14/12/02: Re: Which Altera to buy?
    157392: 14/12/02: Re: Which Altera to buy?
    157394: 14/12/02: Re: Which Altera to buy?
    157396: 14/12/02: Re: Which Altera to buy?
    157398: 14/12/02: Re: Which Altera to buy?
    157400: 14/12/02: Re: Which Altera to buy?
    157405: 14/12/03: Re: Which Altera to buy?
    157407: 14/12/03: Re: Which Altera to buy?
    157408: 14/12/03: Re: Which Altera to buy?
    157410: 14/12/03: Re: Which Altera to buy?
    157412: 14/12/03: Re: Which Altera to buy?
    157418: 14/12/04: Re: Which Altera to buy?
    157420: 14/12/04: Re: Which Altera to buy?
    157422: 14/12/04: Re: Which Altera to buy?
    157425: 14/12/04: Re: Which Altera to buy?
    157427: 14/12/04: Re: Which Altera to buy?
    157429: 14/12/04: Re: Which Altera to buy?
    157431: 14/12/05: Re: Which Altera to buy?
    157436: 14/12/08: Re: Which Altera to buy?
    157449: 14/12/10: Re: Which Altera to buy?
    157458: 14/12/11: Using FPGA to feed 80386
    157461: 14/12/11: Re: Using FPGA to feed 80386
    157462: 14/12/11: Re: Using FPGA to feed 80386
    157466: 14/12/11: Re: Using FPGA to feed 80386
    157471: 14/12/11: Monitor connections
    157474: 14/12/11: Re: Using FPGA to feed 80386
    157475: 14/12/11: Re: Using FPGA to feed 80386
    157477: 14/12/11: Re: Which Altera to buy?
    157478: 14/12/11: Re: Which Altera to buy?
    157490: 14/12/12: Re: Using FPGA to feed 80386
    157492: 14/12/12: Re: Using FPGA to feed 80386
    157495: 14/12/12: Re: Using FPGA to feed 80386
    157501: 14/12/12: Re: Using FPGA to feed 80386
    157506: 14/12/12: Re: Using FPGA to feed 80386
    157510: 14/12/14: Re: Using FPGA to feed 80386
    157513: 14/12/14: Re: Using FPGA to feed 80386
    157514: 14/12/14: Re: Using FPGA to feed 80386
    157516: 14/12/14: Re: Using FPGA to feed 80386
    157519: 14/12/14: Re: Using FPGA to feed 80386
    157521: 14/12/14: Re: Using FPGA to feed 80386
    157522: 14/12/14: Re: Using FPGA to feed 80386
    157523: 14/12/14: Re: Using FPGA to feed 80386
    157524: 14/12/14: Re: Using FPGA to feed 80386
    157528: 14/12/14: Re: Using FPGA to feed 80386
    157530: 14/12/14: Re: Using FPGA to feed 80386
    157533: 14/12/15: Re: Using FPGA to feed 80386
    157536: 14/12/15: Re: Using FPGA to feed 80386
    157538: 14/12/15: Re: Using FPGA to feed 80386
    157539: 14/12/15: Re: Using FPGA to feed 80386
    157542: 14/12/15: Re: Using FPGA to feed 80386
    157544: 14/12/15: Re: Using FPGA to feed 80386
    157548: 14/12/15: Re: Using FPGA to feed 80386
Rick Carmichael:
    8917: 98/02/06: Re: FPGA/ASIC - same difference?
    9040: 98/02/16: ASIC_designers_needed_Colorado!
    9039: 98/02/16: Re: Walace tree???
    9575: 98/03/24: Re: Synthesizable 8B/10B Encoder/Decoder wanted
Rick Collins:
    8417: 97/12/13: Xilinx Copy Protection
    9184: 98/02/28: Re: Correlation implementation...
    9442: 98/03/13: Re: The case for Linux and EDA
    9388: 98/03/08: Re: Help with ViewLogic 4
    9389: 98/03/08: Re: Viewlogic file format for schematic symbols
    9447: 98/03/14: Re: Strange Xilinx question?
    9466: 98/03/16: Re: Strange Xilinx question?
    9487: 98/03/17: Re: Strange Xilinx question?
    9524: 98/03/20: Re: Ideas for an FPGA Project?
    9560: 98/03/23: Re: Dual port
    9561: 98/03/23: Re: "CORE Competency" ???
    9562: 98/03/23: Re: USB bus interface (12 mbit/sec) in an FPGA - how difficult?
    9563: 98/03/23: Re: Strange Xilinx question?
    9584: 98/03/24: Re: Orca Floorplanning tools
    9591: 98/03/24: Re: "CORE Competency" ???
    9592: 98/03/24: Re: Dual port
    9609: 98/03/25: Re: Dual port
    9610: 98/03/25: Re: xilinx M1.4 / XC3000 problem
    9611: 98/03/25: Re: XactStep6 - The cure for a dongle
    9612: 98/03/25: Re: VHDL shareware editor?
    9725: 98/04/01: Re: XactStep6 - The cure for a dongle
    9746: 98/04/02: Re: XactStep6 - The cure for a dongle
    9793: 98/04/05: Re: XactStep6 - The cure for a dongle
    9804: 98/04/06: Re: XactStep6 - The cure for a dongle
    22655: 00/05/16: Re: Best choice between FPGA and CPLD
    22678: 00/05/17: Re: PC104+ FPGA Board
    22687: 00/05/17: Re: Spartan II availability and pricing
    22690: 00/05/18: Re: Spartan II availability and pricing
    23199: 00/06/17: Re: spartan and virtex on the same board ?
    23207: 00/06/17: Problem copying text from the Spartan II data sheet
    27689: 00/12/03: Issues with Spartan II
    27696: 00/12/03: Re: Issues with Spartan II
    27697: 00/12/04: Re: Issues with Spartan II
    27747: 00/12/06: Re: ORCAD EXPRESS / Synplicity (feeling stuck)
    27788: 00/12/08: Altera free development tools
    28678: 01/01/20: Re: DSP->FPGA development board
    28680: 01/01/20: Re: Virtex-II officially launched
    28684: 01/01/21: Re: Virtex-II officially launched
    28707: 01/01/22: Re: Virtex-II officially launched
    28842: 01/01/25: Re: grey code counters
    28844: 01/01/26: Re: how to reduce number of gates in xor reducing in crc computing?
    28848: 01/01/26: looping and ranges
    28860: 01/01/26: Re: looping and ranges
    28887: 01/01/27: Re: looping and ranges
    28889: 01/01/27: Re: looping and ranges
    29047: 01/02/03: Re: How to program FPGA with PROTEL? (ORCA OR2C06 serie)
    29048: 01/02/03: Re: Spartan 2 DLL
    29057: 01/02/04: Re: Encryption is supported in new Virtex II but.....
    29431: 01/02/21: Re: Spartan II power
    29514: 01/02/24: Re: cpul vs vhdl
    29515: 01/02/24: Re: ERROR on Xilinx fundation
    29519: 01/02/24: Re: DLL jitter "bake-off" vs. PLL
    29527: 01/02/25: Re: Spartan II power
    29567: 01/02/27: Re: Spartan II power
    29597: 01/02/27: Re: Spartan II power
    29688: 01/03/05: Re: Metastability
    29689: 01/03/05: Re: Spartan II power
    29690: 01/03/05: Re: Spartan II power
    29794: 01/03/10: Re: Metastability
    29925: 01/03/18: FFT in FPGAs
    29929: 01/03/18: Re: FFT in FPGAs
    29930: 01/03/18: Re: FFT in FPGAs
    29937: 01/03/19: Re: FFT in FPGAs
    29981: 01/03/20: Re: FFT in FPGAs
    30009: 01/03/20: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
    30010: 01/03/20: Re: FFT in FPGAs
    30028: 01/03/21: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
    30059: 01/03/22: Re: DLL jitter "bake-off" vs. PLL
    30102: 01/03/23: Re: Globals are plenty fast
    30642: 01/04/20: Re: FPGAs & Combinatorial Chew
    30355: 01/04/04: Re: salary info for FPGA/HardwareEng's
    30419: 01/04/07: Re: pseudo random numbers
    30580: 01/04/18: Re: Getting license for Modelsim in Xilinx webpack?
    30634: 01/04/20: Re: wanted: dig. board with FPGA and processor
    30705: 01/04/25: Re: Altera Mercury comments
    31104: 01/05/11: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
    31124: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
    31127: 01/05/12: Re: Shannon Capacity, a quote from the paper
    31128: 01/05/12: Re: Shannon Capacity
    31131: 01/05/12: Re: Shannon Capacity
    31141: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
    31346: 01/05/20: Re: Can anyone comment on the difference between modelsim PE and XE
    31347: 01/05/20: Re: FPGA Express 3.5 One hot state machine Synthesis problem
    31348: 01/05/20: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
    31792: 01/06/06: Re: Pentium 4 or AMD ?
    31793: 01/06/06: Re: one state machine
    31983: 01/06/10: Re: one state machine
    31984: 01/06/10: Re: one state machine
    32001: 01/06/10: Re: Pentium 4 or AMD ?
    32002: 01/06/10: Re: Xilinx webpack annoyances (long and whiny)
    32003: 01/06/10: Re: one state machine
    32078: 01/06/13: Re: Xilinx webpack annoyances (long and whiny)
    32229: 01/06/20: Re: ee
    32230: 01/06/20: Re: FPGA Boards
    32231: 01/06/20: Re: Verilog or VHDL?
    32232: 01/06/20: Re: Force routing on an Apex
    32360: 01/06/24: IOB FF in Synplicity
    32451: 01/06/27: Re: Stupid Xilinx Patent
    32769: 01/07/08: Re: Large Power up Current on Spartan2
    32770: 01/07/08: Re: Altera ACEX
    32780: 01/07/09: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
    32793: 01/07/09: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
    33498: 01/07/28: Re: IOB FF in Synplicity
    33521: 01/07/29: Re: 3.3i service pack 8
    33522: 01/07/29: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
    33627: 01/08/01: Spanning the heirarchy
    33774: 01/08/04: Re: finite defect statistics
    33791: 01/08/05: Slightly off topic - PCs for running FPGA tools
    33808: 01/08/06: Re: Slightly off topic - PCs for running FPGA tools
    33860: 01/08/06: Re: Slightly off topic - PCs for running FPGA tools
    34018: 01/08/11: Re: Q: Revision and Database Control for FPGA Designs
    34043: 01/08/12: Re: Q: Revision and Database Control for FPGA Designs
    34044: 01/08/12: Re: Slightly off topic - PCs for running FPGA tools
    34046: 01/08/12: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
    34047: 01/08/12: Re: Why did Zephram spool outside all the users? We can't post
    34062: 01/08/13: Re: Q: Revision and Database Control for FPGA Designs
    34129: 01/08/15: Re: Q: Revision and Database Control for FPGA Designs
    34130: 01/08/15: Replication of FFs in Xilinx XC4000
    65837: 04/02/07: Re: Do Xilinx Fix Their Prices?
    65838: 04/02/07: Re: Pricing, 101
    65839: 04/02/07: Re: Pricing, 101
Rick Cortese:
    24627: 00/08/15: Re: Non-disclosures in job interviews
    24663: 00/08/16: Re: Non-disclosures in job interviews
Rick Cox:
    2865: 96/02/20: Re: Verilog vs. VHDL comparison
Rick Farmer:
    2105: 95/10/15: vertical 20 pin LCC sockets?
    2856: 96/02/17: Lowest power FPGA or PLD
Rick Filipkewicz:
    8111: 97/11/18: Altera Flash EPX880 devices
    8151: 97/11/21: Re: what is metastability time of a flip_flop
    8168: 97/11/24: ABEL6 and Xilinx Foundation
    8317: 97/12/08: Xilinx M1 ABEL-EDIF problem
    8639: 98/01/15: Re: Xilinx Configuration Problem
    8742: 98/01/23: Military FPGAs
    9053: 98/02/17: Atmel SPROMs for Xilinx
    9941: 98/04/15: Re: Version Control for schematics?
    9819: 98/04/07: Xilinx Foundation Express
    9897: 98/04/11: Re: Xilinx Foundation Express
    9943: 98/04/15: Re: Xilinx Foundation Express
    10046: 98/04/24: Re: Xilinx Serial Proms
    10633: 98/06/08: Atmel serial EEPROMs
    10769: 98/06/17: Re: XILINX Foundation - how to minimize project archive?
Rick Filipkiewicz:
    1334: 95/06/02: Re: PCI ALTERA design
    1335: 95/06/02: ATMEL 6000 question
    1600: 95/07/25: Re:FLEX8000 programming
    4491: 96/11/05: Re: Info on FPGA Internal Architecture/ Programming
    4543: 96/11/12: Xilinx 9500 CPLDs
    4592: 96/11/19: Re: Fast FPGA
    4591: 96/11/19: Re: Async with FPGA?
    4685: 96/11/29: Re: SRAM Programming on the Altera NFX780
    5197: 97/01/30: Xilinx/Synario question
    5214: 97/01/31: Re: What is the different between FPGA and CPLD?
    5329: 97/02/07: Xilinx EZTag question
    5854: 97/03/20: Re: Sole source
    8332: 97/12/09: Xilinx ABEL to EDIF problem
    10970: 98/07/08: Re: Xilinx Foundation Frustartions
    12173: 98/10/02: Re: NFX780, where to get?
    12174: 98/10/02: Verilog Simulators
    12260: 98/10/07: Re: USAGE of XILINX "FROM:TO" for VHDL and IMPLEMENTATION
    12265: 98/10/07: Re: Verilog Simulators
    12608: 98/10/20: Re: Schematic entry?
    12614: 98/10/20: Re: State machines in VHDL/Verilog
    12639: 98/10/21: Re: State machines in VHDL/Verilog
    12655: 98/10/22: Re: State machines in VHDL/Verilog
    12685: 98/10/23: Foundation Express in M1.5
    12963: 98/11/08: Re: A suggestion for Xilinx
    13493: 98/12/05: Xilinx F1.5 Installation - HELP!
    13501: 98/12/06: Xilinx Dongles under NT
    13541: 98/12/08: FPGA Synthesis tools
    13955: 99/01/05: Question on Exemplar synthesis
    14184: 99/01/18: Synthesis tools for Xilinx FPGAs
    14239: 99/01/21: Re: Synthesis tools for Xilinx FPGAs (an apology to Synplify)
    14377: 99/01/27: Re: multiple clock domains
    14381: 99/01/27: Re: Ratings for Synplicity Synplify
    14444: 99/01/29: Re: Ratings for Synplicity Synplify
    15478: 99/03/25: Re: FPGA Express Synthesis Problem
    15492: 99/03/26: Re: FPGA Express Synthesis Problem
    16003: 99/04/27: Re: Viewlogic FPGA Express vs Xilinx FPGA Express....any difference?
    16193: 99/05/08: Re: BGA Prototyping ?
    18077: 99/09/27: Re: Obtaining a Synopsys site ID
    18078: 99/09/27: Re: New Xilinx Virtex-E is out!
    18182: 99/10/06: Xilinx post route simulation
    18192: 99/10/06: Re: Xilinx post route simulation
    18453: 99/10/25: Re: XILINX: XDL - is this a secret?
    18455: 99/10/25: Re: FPGA Timing Problem
    18506: 99/10/28: Hold times for Xilinx FPGAs
    18520: 99/10/28: Re: Hold times for Xilinx FPGAs
    18569: 99/11/01: Virtex hardware debugging - help needed
    18667: 99/11/05: Re: Simulation of FPGA design. Please Help!
    18700: 99/11/08: Re: Downloading Xilinx FPGA with just .bit file???
    18729: 99/11/10: Re: Simulation of FPGA design. Please Help!
    18738: 99/11/11: Re: Altera Files vho and sdo too big
    18759: 99/11/12: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
    18859: 99/11/19: Re: Need advice on interfacing SDRAM modules
    19059: 99/11/26: Re: Programming Virtex device via JTAG
    19070: 99/11/26: Re: HDL editor?
    19381: 99/12/17: Re: VirtexE availability?
    19611: 00/01/04: Re: M1 timings
    19658: 00/01/07: Re: Virtex 5V io
    19675: 00/01/07: Xilinx Spartan2
    19921: 00/01/18: Virtex to ASIC conversion
    20045: 00/01/25: Re: How to access standard sdram ?
    20067: 00/01/26: Re: Atmel config PROMs
    20623: 00/02/16: Re: Xilinx Virtex Reset
    20624: 00/02/16: Re: A FPGA hickup
    20626: 00/02/16: Re: 100% slice utilization in Virtex FPGA
    20949: 00/02/29: How to use the Xilinx FG676 package ?
    21073: 00/03/06: Re: SpartanXL route and place
    21074: 00/03/06: Re: Synplicity for sale
    21075: 00/03/06: Re: To use synplify in command mode
    21115: 00/03/07: Re: SpartanXL route and place
    21179: 00/03/09: Re: Synplicity for sale
    21180: 00/03/09: Re: ModelSim 2.1i ?
    21181: 00/03/09: Re: SpartanXL route and place
    21281: 00/03/15: Re: Virtex IOB T register
    21288: 00/03/15: Re: Virtex IOB T register
    21985: 00/04/11: Re: Altering Xilinx FPGA version/ID after PAR
    22032: 00/04/14: Virtex readback
    22192: 00/05/01: Re: ? economical SPROM programmer for Xilinx
    22193: 00/05/01: Re: A Question on Virtex Configuration
    22237: 00/05/02: Re: A Question on Virtex Configuration
    22267: 00/05/03: Re: How to Prevent theft of FPGA design
    22395: 00/05/08: Re: How to Prevent theft of FPGA design
    22431: 00/05/09: Re: How to Prevent theft of FPGA design
    22210: 00/05/02: Re: Xilinx CPLD Make file
    22397: 00/05/08: Re: Virtex clock buffers
    22441: 00/05/09: Re: Xilinx Block Select Ram+ and LeonardoSpectrum
    22461: 00/05/09: Re: pipeline shiftreg in virtex
    22611: 00/05/13: Re: virtex configuration with synplify
    22629: 00/05/15: Re: Future of FPGAs?
    22842: 00/05/26: Re: Abel conversion to VHDL
    22597: 00/05/12: Re: pipeline shiftreg in virtex
    22926: 00/06/02: Re: Virtex Block Select RAM Timing Problem
    23194: 00/06/16: Re: Hand soldering a PQ208 - It looks tough to do.
    23256: 00/06/19: Re: Problem copying text from the Spartan II data sheet
    23409: 00/06/24: Re: Problem copying text from the Spartan II data sheet
    23482: 00/06/27: Re: Problem copying text from the Spartan II data sheet
    23484: 00/06/27: Re: IDE-Interface for FPGA
    23518: 00/06/28: Re: I cant stand it any more.
    23696: 00/07/05: Re: Powering XCV300
    23699: 00/07/05: Re: Virtex-E PCI (MB with 3.3Vsignaling)
    23750: 00/07/07: Re: Virtex-E PCI (MB with 3.3Vsignaling)
    23791: 00/07/09: Re: Remedies after the Fathers' Day Massacre
    23849: 00/07/12: Re: hold time errors in FPGA's ?
    24054: 00/07/25: Re: Real time sims with NC-Verilog
    24224: 00/07/31: Re: Foreign generated EDIF file in Foundation 2.1i
    24410: 00/08/07: Xilinx Foundation 3.1i
    24427: 00/08/08: Re: Xilinx Foundation 3.1i
    24428: 00/08/08: Re: Place&Route report of spartan2
    25216: 00/08/31: Re: Synthesis
    25898: 00/09/25: Re: Xilinx and CD databooks (rant)
    25245: 00/09/01: Re: Error during synthesis
    25246: 00/09/01: Xilinx Web pack ABEL tools
    25319: 00/09/06: Re: Slow routing of PWR/GND (Virtex)
    25425: 00/09/11: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
    25442: 00/09/11: Re: Clock skew in XILINX CPLD
    25547: 00/09/13: Re: Clock skew in XILINX CPLD
    25549: 00/09/13: Re: Virtex 'shutdown' phenomenon
    25566: 00/09/14: Re: Complaint: Xilinx functional simulation libraries
    25950: 00/09/27: Re: ABEL truth table for 8-1 Mux
    25996: 00/09/29: Re: Xilinx Logicore Generator
    26004: 00/09/30: Re: some question about synplify tool
    26012: 00/09/30: Re: Pack I/O Reg/Latches into IOBs
    26043: 00/10/01: Re: FPGA Express strikes again! Xilinx response
    26055: 00/10/02: Re: FPGA Express strikes again! Xilinx response
    26199: 00/10/08: Re: FPGA Express strikes again! Xilinx response
    26056: 00/10/02: Re: GPIO on AVNET Xilinx FPGA board? any cables?!?
    26066: 00/10/02: Re: "Xilinx Adds FPGA Support to Free Web Design Tools"
    26121: 00/10/04: Re: Category : virtex e I/O bank contention
    26125: 00/10/05: Re: Xilinx Licensing.
    26161: 00/10/06: Re: Xilinx Licensing.
    26176: 00/10/06: Re: Non-standard vhdl expressions
    26177: 00/10/06: Re: programm Xilinx FPGAs via JTAG
    26181: 00/10/07: Re: Project Leader, Architecture Modeling
    26200: 00/10/08: Re: Long Island Verilog and VHDL people wanted!!
    26397: 00/10/14: Re: 5V compatible Virtex
    26477: 00/10/18: Re: Asynchronous pulse generation with Spartan.
    26506: 00/10/18: Re: 5V compatible Virtex
    26676: 00/10/24: Re: How to reduce Tco?
    26686: 00/10/25: Re: Design theft story in EDN. New security ?
    26780: 00/10/29: Re: High fan out CE signal.
    26781: 00/10/29: Re: death of rloc ?
    26812: 00/10/30: Re: High fan out CE signal.
    26904: 00/11/03: Re: Alliance under Linux?
    26853: 00/11/01: Re: Spartan II ?
    26905: 00/11/03: Re: OT: Xilinx T-Shirt
    26953: 00/11/05: Re: Spartan2 prototype boards
    27195: 00/11/15: Re: Webpack 3.2WP3.x from Xilinx is useless
    27357: 00/11/19: Synthesis & Routing speed
    27365: 00/11/20: Re: Synthesis & Routing speed
    27381: 00/11/20: Re: In the news
    27382: 00/11/20: Re: Synthesis & Routing speed
    27393: 00/11/20: Re: In the news
    27396: 00/11/20: Re: Xilinx and Tri state I/O
    27433: 00/11/22: Re: Webpack 3.2: Problem with Design Implementation
    27465: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
    27486: 00/11/24: Re: Clock Skew : Does Xilinx know what they're doing?
    27492: 00/11/24: Re: How to reduce the Tco
    27495: 00/11/24: Re: How to reduce the Tco
    27502: 00/11/24: NGDBUILD/UCF Problem
    27505: 00/11/25: Re: Clock Skew : Does Xilinx know what they're doing?
    27506: 00/11/25: Re: NGDBUILD/UCF Problem
    27526: 00/11/27: Re: Clock Skew : Does Xilinx know what they're doing?
    27537: 00/11/28: Re: Virtex ROM ques.
    27584: 00/11/29: Re: Synthesis & Routing speed
    27585: 00/11/29: Re: Wide AND function.
    27586: 00/11/29: Re: Synplify Benchmarks
    27602: 00/11/29: Re: NGDBUILD/UCF Problem
    27604: 00/11/29: Re: Fifo design problem
    27606: 00/11/29: Re: Synplify Benchmarks
    27607: 00/11/29: Re: Fifo design problem
    27611: 00/11/29: Re: Reverse-engineering FPGA's
    27635: 00/11/30: Re: FC II & Xilinx libraries macros
    27651: 00/12/01: Re: Synplify Benchmarks
    27652: 00/12/01: Re: jtag for fpga
    27690: 00/12/03: Re: Hey there anybody!!
    27715: 00/12/04: Re: Issues with Spartan II
    27742: 00/12/05: Re: Issues with Spartan II
    27743: 00/12/05: Re: which I/O pin belongs to each bank
    27744: 00/12/05: Re: Gate Level Simulation Questions
    27779: 00/12/07: Re: XC9500/9500XL CPLD Clocks
    27801: 00/12/08: Re: FPGA starter kit
    27823: 00/12/11: Re: Linear Regulator troubles
    27874: 00/12/13: Re: Hold time constraints in virtex?
    27894: 00/12/14: Re: Issues with Spartan II
    27921: 00/12/15: Re: Verilog or VHDL
    27937: 00/12/15: Re: Setup violation
    27938: 00/12/15: Re: Verilog or VHDL
    27945: 00/12/16: Re: Verilog or VHDL
    27968: 00/12/18: Virtex and metastability
    27974: 00/12/18: Re: Spartan configuration : Why Done returns to Low?
    27984: 00/12/18: Re: Setup violation
    28043: 00/12/19: Re: Methodology
    28046: 00/12/20: Re: Verilog or VHDL
    28155: 00/12/23: Re: Metastability rant (was Re: dual port ram for altera)
    28156: 00/12/23: Re: Is it necessary to synchronize the reset signal in an FPGA ?
    28157: 00/12/23: Re: Methodology
    28535: 01/01/16: Re: Fixing pins on Spartan II
    28536: 01/01/16: Re: Foundation P&R + location constraint
    28538: 01/01/16: Re: Virtex-II officially launched
    28539: 01/01/16: Re: Xilinx UCF/ngdbuild problem
    28541: 01/01/16: Re: Synplicity newsgroup?
    28573: 01/01/17: Re: revision control tools ??
    28662: 01/01/20: Re: About programming cables
    28922: 01/01/29: Re: Xilinx JEDEC files to SVF format
    28950: 01/01/31: Re: Encryption is supported in new Virtex II but.....
    29056: 01/02/04: Re: Can Virtex-II be programmed with MultiLINX?
    29145: 01/02/07: Verilog model of I2C/SMB
    29178: 01/02/09: Re: Xilinx vs Altera
    29221: 01/02/10: Re: Help for a novice. Where to begin?
    29230: 01/02/10: Re: Help for a novice. Where to begin?
    29377: 01/02/16: Re: Implementing a 64-bit/66MHz PCI controller
    29379: 01/02/16: Re: Vertex Place & Route Time
    29385: 01/02/17: Re: Vertex Place & Route Time
    29393: 01/02/19: Re: Altera process change....
    29406: 01/02/20: Re: ALtera CPLD
    29478: 01/02/22: Re: Virtex II availability
    29513: 01/02/24: Re: Soldering and Unsoldering PQFP by hand ...
    29596: 01/02/28: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
    29625: 01/03/02: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
    29626: 01/03/02: Re: What about speed-grade?
    29636: 01/03/02: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
    29637: 01/03/02: Re: Differences in VHDL coding for FPGA & CPLD
    29675: 01/03/05: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
    29676: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29707: 01/03/06: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29801: 01/03/11: Re: Metastability
    29807: 01/03/12: Re: Configuration devices
    29879: 01/03/15: Re: Metastability
    29919: 01/03/16: Re: Senior I/O Designer - Canada
    30023: 01/03/21: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
    30173: 01/03/27: Re: Asynchronus Mashine States
    30222: 01/03/29: Re: Pinout tables
    30224: 01/03/29: Re: PCI-X core
    30286: 01/03/31: Re: PCI-X core
    30287: 01/03/31: Re: FPGA V CPLD
    30324: 01/04/03: Re: Dist_ram :Memory instantiation
    30378: 01/04/04: Re: Timing Error
    30409: 01/04/06: Re: Modlesim5.5
    30436: 01/04/08: Re: Handel-C
    30449: 01/04/08: Re: Asynchronus Mashine States
    30450: 01/04/08: Re: Handel-C
    30466: 01/04/09: Re: Modlesim5.5
    30508: 01/04/11: Virtex readback
    30601: 01/04/18: Re: PAR single pass vs multi-pass differences
    30652: 01/04/21: Re: PAR single pass vs multi-pass differences
    30675: 01/04/23: Virtex-E & 5V tolerance
    30715: 01/04/25: Re: Virtex-E & 5V tolerance
    30776: 01/04/28: Re: C++ To Gates
    30797: 01/04/30: Re: C++ To Gates
    30827: 01/04/30: Re: C++ To Gates
    30994: 01/05/08: Re: Routing: Completed - errors found.
    31001: 01/05/09: Virtex-2 - experiences ?
    31036: 01/05/09: Re: Virtex-2 - experiences ?
    31039: 01/05/10: Re: Virtex-2 - experiences ?
    31068: 01/05/10: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
    31073: 01/05/11: Synplicity online support problem
    31090: 01/05/11: Re: Waveforms painting
    31120: 01/05/12: Re: SRAM fpga cell
    31150: 01/05/13: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
    31167: 01/05/14: Bizarre PAR phenomenon
    31226: 01/05/15: Re: Virtex-2 - experiences ?
    31240: 01/05/16: Re: SRAM fpga cell
    31241: 01/05/16: Re: Bizarre PAR phenomenon
    31265: 01/05/16: Re: SRAM fpga cell
    31266: 01/05/16: Re: Bizarre PAR phenomenon
    31267: 01/05/16: Re: PROGRAMMABLE LOGIC SEQUENCER CORRECTIONS
    31269: 01/05/16: Re: Ideas for Faster XILINX compilations ?
    31302: 01/05/18: Re: FPGA Express 3.5 One hot state machine Synthesis problem
    31331: 01/05/19: Re: Xilinx Webfitter fails with exit code 0002
    31341: 01/05/19: Re: FPGA consultant needed
    31390: 01/05/22: Re: FPGA consultant needed
    31391: 01/05/22: Re: Synplicity newsgroup?
    31392: 01/05/22: Re: Maximum clock frequency to expect in Xilinx Virtex FPGA ?
    31503: 01/05/28: Re: what cables and softwares do you need to use "Xilinx FPGA
    31520: 01/05/29: Re: xilinx webpack warning !!
    31577: 01/05/30: Foundation 3.3i memory useage
    31620: 01/05/31: Re: Xilinx XC4010E Problem
    31629: 01/06/01: Re: Xilinx XC4010E Problem
    31630: 01/06/01: Re: Xilinx webpack and modelsim
    31654: 01/06/01: Re: Xilinx webpack and modelsim
    31695: 01/06/03: Re: [Q]setup-time violation
    31732: 01/06/04: Re: one state machine
    31747: 01/06/05: Re: one state machine
    31783: 01/06/06: Re: one state machine
    31852: 01/06/07: Re: FPGA / starterkit / VHDL
    31866: 01/06/07: Re: Pentium 4 or AMD ?
    31889: 01/06/07: Re: Help in FIFO design
    31971: 01/06/10: Re: problem: bahavior simulation of xilinx's coregen cores
    31972: 01/06/10: Re: Flash programming via FPGA's JTAG ????
    31985: 01/06/10: Re: problem: bahavior simulation of xilinx's coregen cores
    32000: 01/06/10: Re: one state machine
    32018: 01/06/11: Re: one state machine
    32040: 01/06/11: Doing Ethernet in a Virtex ?
    32081: 01/06/13: Re: Xilinx webpack annoyances (long and whiny)
    32099: 01/06/14: Re: Xilinx webpack annoyances (long and whiny)
    32100: 01/06/14: Re: From EDF to VHDL?
    32105: 01/06/14: Cores needed
    32117: 01/06/14: Re: From EDF to VHDL?
    32163: 01/06/17: Xilinx web site ?
    32167: 01/06/18: Re: Xilinx web site ?
    32188: 01/06/19: Re: ee
    32233: 01/06/20: Synplify register replication
    32278: 01/06/21: Re: synplicity 6.2.4 'optimizing' instantiated designs
    32280: 01/06/21: Re: Synplify register replication
    32290: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
    32292: 01/06/22: Re: what tools run OK on windows 2000?
    32320: 01/06/22: Re: Verilog or VHDL?
    32334: 01/06/23: Re: what tools run OK on windows 2000?
    32366: 01/06/25: Re: IOB FF in Synplicity
    32368: 01/06/25: Re: IOB FF in Synplicity
    32388: 01/06/25: Re: IOB FF in Synplicity
    32389: 01/06/25: Re: Xilinx Spartan - Power Rail Related Timing Problem
    32392: 01/06/25: Re: black box instantiation in Spartan II Design
    32405: 01/06/26: Re: IOB FF in Synplicity
    32490: 01/06/28: Re: Stupid Xilinx Patent
    32515: 01/06/28: Re: IOB FF in Synplicity
    32616: 01/07/02: Re: Date/Time at synthesis -> std_logic_vector => just use a ROM
    32617: 01/07/02: Re: IOB FF in Synplicity
    32623: 01/07/03: Re: XC9500 drive capability
    32641: 01/07/04: Re: Jtag programmer, and the WinNT Parallel port
    32655: 01/07/04: Re: 'Initial' opinions...
    32779: 01/07/09: Re: Need some help using Synplify ... and also considering Xilinx
    32812: 01/07/10: Re: XC9500 drive capability
    32813: 01/07/10: Re: What chip!?
    32822: 01/07/10: Re: What chip!?
    32874: 01/07/10: Re: What chip!?
    32917: 01/07/11: Re: need help implementing state diagram of a 2input mealy machine!
    32981: 01/07/14: Re: Xilinx BRAM failures
    32990: 01/07/14: Re: Help needed: why am I getting device programming errors on Webpack.
    33038: 01/07/16: Re: Design entry
    33177: 01/07/18: Re: Xilinx BRAM failures
    33180: 01/07/18: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
    33342: 01/07/24: Re: Homemade Xilinx parallel cable problem
    33349: 01/07/24: Re: any vb sample code for access database function
    33374: 01/07/25: Re: Homemade Xilinx parallel cable problem
    33375: 01/07/25: Re: Xilinx Foundation Software Eval Pkg Won't Instal
    33414: 01/07/25: Re: What chip!?
    33423: 01/07/26: Re: Application obstacle course
    33426: 01/07/26: Re: Application obstacle course
    33432: 01/07/26: PQFP sockets
    33452: 01/07/26: Re: PQFP sockets
    33457: 01/07/27: Re: PQFP sockets
    33463: 01/07/27: Re: Opinions on cypress warp 6.1 and devices?
    33475: 01/07/27: Re: Xilinx/Altera "behavioral" verilog
    33476: 01/07/27: Re: Xilinx/Altera "behavioral" verilog
    33500: 01/07/28: Re: IOB FF in Synplicity
    33502: 01/07/28: Re: The Continuing Saga of Installing Modelsim software on Windows 2000
    33576: 01/07/30: Re: Xilinx/Altera "behavioral" verilog
    33612: 01/07/31: Re: computer science Vs Computer Enginnering
    33629: 01/08/01: Re: Xilinx/Altera "behavioral" verilog
    33779: 01/08/04: Re: Alliance tools going away?
    33788: 01/08/05: Re: Why did Zephram spool outside all the users? We can't post
    33926: 01/08/08: Re: Which is the best Design Toolchain?
    34009: 01/08/10: Re: Spartan-II serial configuration problem from ATMEL device
    34010: 01/08/11: Re: Low Cost FPGA or PLD
    34079: 01/08/13: Re: Keep Xilinx Webpack from removing unused NETs?
    34080: 01/08/13: Re: virtex2 Block Ram: dual port ram with different da
    34089: 01/08/14: Re: virtex2 Block Ram: dual port ram with different da
    34122: 01/08/14: Porno Junk cluttering up CAF
    34181: 01/08/16: Re: Replication of FFs in Xilinx XC4000
    34229: 01/08/16: Re: Virtex-II and 5V devices
    34323: 01/08/21: Re: Slowing PCI for FPGA
    34379: 01/08/22: Re: JTAG issue again ...
    34395: 01/08/23: Re: Slowing PCI for FPGA
    34405: 01/08/23: Re: Optical Bay Area Start-up! SW/HW Engs needed
    34406: 01/08/23: Testing ... please ignore
    34409: 01/08/23: Carry chain warnings from Xilinx MAP
    34411: 01/08/23: Re: DRAM Burst Mode
    34415: 01/08/23: Re: DRAM Burst Mode
    34432: 01/08/24: Re: Carry chain warnings from Xilinx MAP
    34447: 01/08/25: Re: DRAM burst mode
    34504: 01/08/28: Re: Help needed: simulation OK, synthesis OK, but doesnt work :-<
    34529: 01/08/28: Re: Defending Austin Franklin
    34530: 01/08/28: Re: System Requirements
    34531: 01/08/28: Re: Level sensitive latches in Xilinx Virtex
    34541: 01/08/29: Re: Defending Austin Franklin
    34545: 01/08/29: Re: Gate Count Definition
    34569: 01/08/29: Re: Defending Austin Franklin
    34570: 01/08/29: Re: System Requirements
    34590: 01/08/30: Re: Version Control
    34651: 01/09/01: Re: How to connect a clock to a non-clock pad ?
    34683: 01/09/04: Multi-cycle constraints
    34689: 01/09/04: Re: Multi-cycle constraints
    34813: 01/09/09: Re: Selection of a suitable FPGA board
    34823: 01/09/10: Re: Selection of a suitable FPGA board
    34825: 01/09/10: Re: Selection of a suitable FPGA board
    34860: 01/09/12: Re: Selection of a suitable FPGA board
    34883: 01/09/12: Re: Programming Delays in ABEL
    34887: 01/09/13: Re: Block RAM initialization
    34953: 01/09/15: Re: A vs. X
    34957: 01/09/16: Virtex-2 availability
    35005: 01/09/17: Re: A vs. X
    35006: 01/09/17: Re: Virtex-E1600 unsupported?
    35007: 01/09/17: Re: Virtex-2 availability
    35037: 01/09/18: Re: Virtex-2 availability
    35042: 01/09/18: Re: Synplicity logic replication
    35096: 01/09/21: Stopping a DLL
    35116: 01/09/21: Re: Stopping a DLL
    35127: 01/09/22: Re: Stopping a DLL
    35176: 01/09/25: Re: comp.arch.fpga : Unusual clock divider ckt
    35234: 01/09/26: Re: Xilinx 4.1 software
    35245: 01/09/26: Re: Spartan-IIE?
    35285: 01/09/27: Re: Programming flash connected to CPLD via JTAG
    35309: 01/09/28: Re: Meta-stability
    35325: 01/09/28: Re: Active-HDL back annotated simulation and PC memory usage
    35352: 01/09/30: Re: Xilinx 4.1 software
    35404: 01/10/03: Re: Virtex II current consumption
    35438: 01/10/04: Re: Xilinx Spartan2E samples availability?
    35462: 01/10/06: Re: ROM based FSMs
    35467: 01/10/06: Re: ROM based FSMs
    35478: 01/10/07: Re: ROM based FSMs
    35482: 01/10/07: Re: ROM based FSMs
    35565: 01/10/10: Re: Synplify vs. Leonardo
    35566: 01/10/10: Re: Synplicity/Leonardo License Agreement Information
    35568: 01/10/10: Re: Synplicity/Leonardo License Agreement Information
    35570: 01/10/10: Re: High level synthesis will never work well :)
    35628: 01/10/12: Re: High level synthesis will never work well :)
    35630: 01/10/12: Re: Error : Operand divide
    35680: 01/10/13: Re: future Xilinx products wish list ...
    35681: 01/10/13: Re: High level synthesis will never work well :)
    35682: 01/10/13: Re: Reassemble a BGA560 device
    35700: 01/10/14: Re: How to instantiate I/O port with both registered input and output?
    35717: 01/10/15: Re: Improving timing
    35830: 01/10/19: Re: Career advice in fpga/asic design
    35832: 01/10/19: Re: Timing Constarint Error message
    35840: 01/10/19: Re: Timing Constarint Error message
    35841: 01/10/19: Re: Glitch Hunting, a true story ;-)
    35847: 01/10/20: Re: Glitch Hunting, a true story ;-)
    35848: 01/10/20: Re: Glitch Hunting, a true story ;-)
    35886: 01/10/22: Re: Verilog vs. VHDL
    35891: 01/10/22: Re: one-hot statemachine
    35919: 01/10/24: Re: Verilog vs. VHDL
    36171: 01/11/01: Re: Leonardo bugs
    36181: 01/11/01: XC18V04 serial EEPROM problem - 5V tolerance ?
    36182: 01/11/01: Re: Leonardo bugs
    36242: 01/11/03: Re: XC6000
    36296: 01/11/05: Re: Virtex II introduction schedule
    36316: 01/11/06: Re: Xilinx Floorplanner Effectiveness
    36321: 01/11/06: Re: Guided Design, Xilinx Virtex-E
    36322: 01/11/06: Re: Counter detects both edge of clock?? (verilog)
    36335: 01/11/06: Re: How can I use the instance of block RAM of Spartan2 in Synplify?
    36373: 01/11/07: Re: Modifying BlockRAM contents in a bitstream?
    36374: 01/11/08: Re: Xilinx machine readable package info
    36623: 01/11/13: Re: Timing constraints for multiple clock logic paths
    36651: 01/11/14: Re: Xilinx s/w upgrade 4.1 problems
    36738: 01/11/18: Re: Decoupling capacitors on Virtex II
    36739: 01/11/18: Re: Clock Divider or Multiplier ???
    36740: 01/11/18: Re: 'Timing' simulation in ModelSIM
    36844: 01/11/22: Re: Decoupling capacitors on Virtex II
    36845: 01/11/22: Re: slew rate of virtex output buffers figures
    36878: 01/11/22: Re: slew rate of virtex output buffers figures
    36954: 01/11/27: Re: wget of WebPack
    36977: 01/11/27: Re: Got enough mebibytes of RAM ?
    37019: 01/11/28: SpartanIIE
    37083: 01/11/29: Re: DLL cycle-to-cycle jitter
    37084: 01/11/29: Re: SpartanIIE
    37085: 01/11/29: Re: FPGA startup current
    37365: 01/12/08: Re: I need a Xilinx Spartan PCI Development Board
    37387: 01/12/09: Re: For Sale: Huge Xilinx FPGA lots
    37449: 01/12/11: Re: About special promotion of Synplicity's Synplify? FPGA synthesis
    37471: 01/12/12: Re: Initialization of RAM
    37502: 01/12/12: Re: Initialization of RAM
    37615: 01/12/17: Xilinx ChipScope - experiences ?
    37768: 01/12/20: Re: annoying problem and "simple and clever solution"
    37769: 01/12/20: Re: Kindergarten Stuff
    37770: 01/12/20: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
    37773: 01/12/20: Re: Spartan-IIE schematic symbol?
    37812: 01/12/20: Re: You take the low road and I'll ......
    37813: 01/12/20: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
    37842: 01/12/21: Re: Hardware FPGA questions
    37843: 01/12/21: Re: CE on XILINX FFs and Metastability
    37863: 01/12/21: Re: A ram wish
    37894: 01/12/23: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
    37910: 01/12/24: Re: Kindergarten Stuff
    37940: 01/12/26: Re: Kindergarten Stuff
    37941: 01/12/26: Re: Innoveda Speedwave vs. Modelsim?
    37949: 01/12/27: Re: Innoveda Speedwave vs. Modelsim?
    37950: 01/12/27: Re: vector reversed in netlist of XC9572XL
    37975: 01/12/28: Re: Innoveda Speedwave vs. Modelsim?
    37987: 01/12/29: Re: How to generate .edn in Webpack ?
    37998: 01/12/29: Re: Spartan LUT question
    38009: 01/12/30: Re: How to generate .edn in Webpack ?
    38010: 01/12/30: Re: Innoveda Speedwave vs. Modelsim?
    38013: 01/12/31: Re: Innoveda Speedwave vs. Modelsim?
    38040: 02/01/02: Re: Virtex-2 maximum clock speed
    38081: 02/01/04: Re: Spartan-IIE interfacing issues
    38108: 02/01/05: Re: asic vs. fpga
    38164: 02/01/08: Re: Regarding frequency achieving in fpga design
    38206: 02/01/09: Re: latch vs. register
    38240: 02/01/09: Re: please tell me how to solve xilinx error xml
    38242: 02/01/09: Re: comp.arch.fpga : Problem with modelsim and ISE4.1
    38243: 02/01/09: Re: Spartan IIE pinout compatibililty with Virtex E
    38276: 02/01/10: Re: asic vs. fpga
    38277: 02/01/10: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
    38389: 02/01/13: Re: Repost: Should clock skew be included for setup time analysis?
    38390: 02/01/13: Re: modelsim
    38455: 02/01/15: Re: .sdf question
    38456: 02/01/15: Re: Falling edge in PLD
    38457: 02/01/15: Re: how do i implement it?
    38458: 02/01/15: Synplify and CoolRunner - Help
    38460: 02/01/15: Re: Synplify and CoolRunner - Help
    38482: 02/01/15: Re: Virtex-2 Frequency Synhtesis
    38540: 02/01/17: Re: Virtex-2 Frequency Synhtesis
    38660: 02/01/21: Re: bottom up synthesis with synplicity?
    38804: 02/01/25: Re: Intel vs. AMD
    38844: 02/01/26: Re: Xilinx webpack
    38845: 02/01/26: Re: Xlx simprim library
    38876: 02/01/27: Re: Coregen Half-Band FIR filter implemenation does not work
    38877: 02/01/27: Re: Xilinx webpack
    38883: 02/01/27: Re: Xilinx webpack
    38967: 02/01/29: Re: Xilinx webpack
    39073: 02/01/31: Re: glitchless clock enable/disable in spartanII
    39074: 02/01/31: Re: The LUT puzzle, Iam on the way
    39117: 02/02/01: Re: the cause of the simulation/synthesis mismatch
    39119: 02/02/01: Re: glitchless clock enable/disable in spartanII
    39157: 02/02/02: Re: glitchless clock enable/disable in spartanII
    39233: 02/02/04: Re: solutions manuals, and no they are not for school
    39300: 02/02/06: Re: Virtex-II and SDRAM Controller at 133MHz
    39301: 02/02/06: Re: FPGA vs GAL : Lattice Its a TROLL
    39332: 02/02/06: Re: FPGA vs GAL : Lattice
    39346: 02/02/07: Re: Virtex-II and SDRAM Controller at 133MHz
    39391: 02/02/08: Re: FPGA vs GAL : Lattice
    39406: 02/02/08: Re: Xilinx ISE 3.3 upgrade to 4.1
    39408: 02/02/08: NT parallel port driver
    39425: 02/02/08: Re: Xilinx ISE 3.3 upgrade to 4.1
    39447: 02/02/10: Re: Xilinx EDIF to BIT transation
    39452: 02/02/10: Re: Xilinx EDIF to BIT transation
    39545: 02/02/13: Re: Spartan Program/Verify
    39572: 02/02/13: Re: Xilinx ISE 3.3 upgrade to 4.1
    39687: 02/02/15: Re: SpartanXL & VHDL -- free software?
    39705: 02/02/16: Re: Xilinx ISE 3.3 upgrade to 4.1
    39725: 02/02/17: Re: Virtex-II and SDRAM Controller at 133MHz
    39735: 02/02/18: Re: FPGA: JTAG CABLE
    39744: 02/02/18: Re: JTAG CABLE
    39754: 02/02/19: Xilinx XDL documentation
    39812: 02/02/20: Re: Mux implemented as tristate
    39820: 02/02/20: Re: Counter does not fit CPLD?
    39852: 02/02/21: Re: Do I need to install software in order to use Multilinx?
    39853: 02/02/21: Re: PCI/FPGA evaluation board
    39891: 02/02/21: Re: Do I need to install software in order to use Multilinx?
    39892: 02/02/21: Re: Problems : INOUT not allowed, alternatives
    39902: 02/02/21: Re: How can I do a Verilog/VHDL mixed language design in ISE WebPACK 4.1
    39931: 02/02/22: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
    40003: 02/02/24: Re: Coolrunner and ISP
    40048: 02/02/25: Re: Virtex-II and SDRAM Controller at 133MHz
    40089: 02/02/27: Re: Xilinx XDL documentation
    40099: 02/02/27: Re: Virtex-E,Spartan2 and cpld jtag chain problem
    40242: 02/03/03: Re: turnaround cycle?
    40243: 02/03/03: Re: Xilinx WebPack Simulation
    40250: 02/03/03: Re: Embedding counting in an FSM.
    40253: 02/03/03: Re: Embedding counting in an FSM.
    40291: 02/03/04: Re: can "initial signal values" and other "for.....use" statements
    40305: 02/03/05: Re: Synthesizing with CORE Generator
    40377: 02/03/06: Re: Xilinx announces Virtex-II Pro is shipping
    40406: 02/03/06: Re: exceeding 2GB limits in xilinx
    40541: 02/03/09: Re: exceeding 2GB limits in xilinx
    40543: 02/03/09: Re: high active and low active reset signal mixed in a design
    40685: 02/03/13: Re: Mystery two wire interface, or am I being dense?
    40771: 02/03/15: Re: minimum value for clock to output
    40772: 02/03/15: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
    40773: 02/03/15: Re: Xilinix FPGA width 5V IO
    40774: 02/03/15: Re: where to start with constraining..
    40826: 02/03/16: Re: Spartan II IOB tristate control FF use
    40828: 02/03/16: FPGA tools and Win2000 - problems
    40868: 02/03/17: Re: minimum value for clock to output
    40869: 02/03/17: Re: Spartan II IOB tristate control FF use
    40871: 02/03/17: Re: Spartan II IOB tristate control FF use
    40874: 02/03/17: Re: FPGA tools and Win2000 - problems
    40875: 02/03/17: Re: FPGA tools and Win2000 - problems
    40897: 02/03/17: Re: FPGA tools and Win2000 - problems
    40922: 02/03/18: Re: Lies, damn lies and Synplicity
    40923: 02/03/18: Re: questions from a newby
    41494: 02/03/30: Re: Possibility of RTL and Gate-level simulation dont match?
    41535: 02/04/01: Re: powerpc in virtex2pro
    41536: 02/04/01: Re: HELP me, about chipscope analyzer
    41783: 02/04/08: Re: Xilinx 4.2i not working on my design
    41789: 02/04/08: Re: clock source
    42432: 02/04/24: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
    42433: 02/04/24: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
    42582: 02/04/28: Re: uniquifying a synplicity netlist
    42583: 02/04/28: Re: ChipScope ILA, cable requirements
    43042: 02/05/10: Re: fpga limitation
    43069: 02/05/12: Re: simultaneous switching of LVPECL outputs
    43099: 02/05/14: Re: Neverending ISA bus interface drama, Spartan-II
    43112: 02/05/14: Re: Architecture for high-level reconfigurable computing
    43129: 02/05/14: Re: Neverending ISA bus interface drama, Spartan-II
    43171: 02/05/15: Re: Architecture for high-level reconfigurable computing
    43277: 02/05/17: Re: virtex 2 block rams
    43291: 02/05/18: Re: virtex 2 block rams
    43304: 02/05/18: Re: virtex 2 block rams
    43307: 02/05/18: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
    43332: 02/05/19: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
    43334: 02/05/19: Re: button & 3 LED's
    43339: 02/05/19: Re: SDRAM pricing
    43350: 02/05/20: Disti web sites
    43425: 02/05/21: Re: SDRAM pricing
    43432: 02/05/21: Re: Synchronous Single Clock Designs
    43435: 02/05/21: Re: Synchronous Single Clock Designs
    43452: 02/05/21: Re: 5V differential -> Virtex 2
    43460: 02/05/21: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
    43468: 02/05/21: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
    43483: 02/05/22: Re: i need help getting started with fpgas
    43556: 02/05/24: Re: Xilinx chip scope: Comments
    43760: 02/06/01: Re: LFSR with 2^n instead of (2^n)-1
    43838: 02/06/04: Re: chipscope
    43839: 02/06/04: Re: divide by 5
    43850: 02/06/04: Re: fpga cpu
    43863: 02/06/04: Re: FPGA destruction possible?
    43883: 02/06/05: Re: divide by 5
    43900: 02/06/05: Re: FPGA destruction possible?
    43975: 02/06/07: Re: Do I have metastability issues?
    43986: 02/06/07: Re: Do I have metastability issues?
    44017: 02/06/10: Re: Cascaded PROMS
    44024: 02/06/10: Re: where did my MHz go!
    44033: 02/06/10: synthesis query: Xilinx + Synplify
    44042: 02/06/10: Re: synthesis query: Xilinx + Synplify
    44050: 02/06/11: Re: synthesis query: Xilinx + Synplify
    44051: 02/06/11: Re: synthesis query: Xilinx + Synplify
    44059: 02/06/11: Re: surely this is mad? (clock rate issues)
    44082: 02/06/11: Re: synthesis query: Xilinx + Synplify
    44093: 02/06/11: MAP problem with RLOC'ed macros
    44121: 02/06/12: Re: MAP problem with RLOC'ed macros
    44136: 02/06/12: Re: virtual ground in Xilinx XC9572 CPLD?
    44144: 02/06/12: Re: MAP problem with RLOC'ed macros
    44147: 02/06/12: Re: synthesis query: Xilinx + Synplify
    44212: 02/06/14: Re: MAP problem with RLOC'ed macros
    44226: 02/06/14: Re: 20,000 gates?
    44227: 02/06/14: Re: MAP problem with RLOC'ed macros
    44249: 02/06/14: Re: MAP problem with RLOC'ed macros
    44250: 02/06/14: Re: MAP problem with RLOC'ed macros
    44280: 02/06/16: Re: TTL library in Xilinx?
    44307: 02/06/17: Re: Xilinx ISE BaseX... What is it?
    44311: 02/06/17: Re: Power supply caps on PCB
    44370: 02/06/18: Re: what's the use of BlockRAM
    44374: 02/06/18: Re: Initial of virtex II block ram
    44395: 02/06/19: Re: 5V tolerance
    44396: 02/06/19: Re: beginer's question: what does tran means in verilog
    44468: 02/06/20: Re: 5V tolerance
    44495: 02/06/21: Re: How to get Unisims netlist?
    44496: 02/06/21: Re: Xilinx's 4.1i's Lastest webpack
    44531: 02/06/22: Re: Xilinx's 4.1i's Lastest webpack
    44535: 02/06/22: Re: Xilinx's 4.1i's Lastest webpack
    44544: 02/06/23: Re: Xilinx's 4.1i's Lastest webpack
    44546: 02/06/23: Re: Xilinx's 4.1i's Lastest webpack
    44579: 02/06/24: Re: [Newbie] Help with 20L8 PAL
    44636: 02/06/25: Re: Xilinx tools under WinXP
    44638: 02/06/25: Re: Xilinx cpld under Windows?
    44660: 02/06/26: Re: Xilinx tools under WinXP
    44663: 02/06/26: Re: Library declaration in Verilog?
    44709: 02/06/27: Re: Xilinx tools under WinXP
    44710: 02/06/27: Re: why not pipeline by default?
    44789: 02/07/01: Re: blank CPLD
    44798: 02/07/01: Re: combine the Verilog code
    44815: 02/07/02: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
    44841: 02/07/02: Re: Power consumtion simulation for FPGA?
    44920: 02/07/05: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
    44956: 02/07/08: Re: Communication between FPGA and PC
    44989: 02/07/09: Re: Are these design guideline safe ?
    45035: 02/07/10: Re: how to keep info. in RAM during reconfiguration?
    45114: 02/07/12: Re: Communication between FPGA and PC
    45115: 02/07/12: Re: FPGA CPU?
    45182: 02/07/15: Re: Foundation 2.1i --- does it support vertexII?
    45183: 02/07/15: Virtex-2 configuration: Device check ?
    45272: 02/07/17: Re: problem porting sync write, async read RAM to Xilinx...
    45745: 02/08/03: Re: Pipelined Multiplier Implemented in Slices in Virtex II
    45825: 02/08/06: Re: parameterized / variable ucf
    45837: 02/08/07: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
    45838: 02/08/07: Re: Programming bits reverse engineering
    45839: 02/08/07: Re: xilinx: map -k
    45840: 02/08/07: Re: xilinx: map -k
    45924: 02/08/11: Re: xilinx: map -k
    45941: 02/08/12: Re: What does the question lie in?
    46288: 02/08/24: Re: upgrade S/W -> timing worse
    46577: 02/09/04: Re: IT consultant vs Engineer
    46750: 02/09/07: Re: Synthesis problem, my inputs are never used?
    46767: 02/09/08: Re: Metastability numbers, even better!
    46856: 02/09/10: Re: XCR3384XL availability
    46987: 02/09/13: Re: exploiting metastability
    47024: 02/09/14: Re: Clcok divison : Rational clock divider
    47092: 02/09/17: Re: Has ISE 5.1i shipped?
    47200: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
    47246: 02/09/21: Re: Xilinx ISE5.1 and Windows NT
    47273: 02/09/22: Re: Can a fpga replace external inverters in a crystal osc ?
    47286: 02/09/22: Re: Timing accuracy with Modelsim
    47486: 02/09/26: Re: Timing accuracy with Modelsim
    47600: 02/09/30: Re: Dual Port RAM
    47686: 02/10/02: Re: Altera Cyclone 'FPGA'
    47688: 02/10/02: Re: design multiplier
    47793: 02/10/04: Re: Need advice wiring up a CPLD
    47942: 02/10/08: Re: LPT voltage level and Xilinx CPLD programming?
    47943: 02/10/08: Re: Xilinx ISE does not use Resgisters in IOB
    47995: 02/10/09: Re: LPT voltage level and Xilinx CPLD programming?
    48298: 02/10/15: Re: Xilinx microblaze vs. picoblaze
    48331: 02/10/16: Re: Upgrading...
    48546: 02/10/20: Re: Xilinx microblaze vs. picoblaze
    48547: 02/10/20: Re: Virtex2 5V tolerant I/O ??
    48548: 02/10/20: Re: Virtex2 5V tolerant I/O ??
    48549: 02/10/20: Re: Floorplanner RPM. How to use it?
    48557: 02/10/21: Re: Virtex2 5V tolerant I/O ??
    48638: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
    48640: 02/10/22: Re: Beginner question
    49130: 02/11/01: 5.1i and Win-NT
    49207: 02/11/05: Re: tips for cutting down on slice usage in a VirtexII
    49530: 02/11/14: Re: HDL vs RTL
    49531: 02/11/14: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
    49532: 02/11/14: Re: How to disable IOB register packing?
    49533: 02/11/14: Re: Efficient implementation memory-mapped regisetrs
    49549: 02/11/14: Re: xc9500 tristate question
    49560: 02/11/15: Re: why systemc?
    49601: 02/11/17: Re: DLL again :-)
    49687: 02/11/19: Re: Metastability in FPGAs
    49806: 02/11/21: Re: Metastability in FPGAs
    49809: 02/11/21: Re: Global clock routing
    49873: 02/11/23: Re: Virtex timing problem
    49894: 02/11/24: Re: Why do post-synthesis simulation result fall into unknow output
    50279: 02/12/07: Re: meaning of system gates vs. logic gates?
    50620: 02/12/14: Re: MTBF Calculation
    50826: 02/12/20: Re: Multi cycle Paths..
    51116: 03/01/02: Re: what is bus keeper / bus gate.
    51605: 03/01/17: Re: Short FIFO in Verilog / Spartan IIE
    51882: 03/01/24: Re: dualport ram instantiation in Spartan IIE
    51985: 03/01/28: Re: AND gate into CPLD
    53255: 03/03/08: Re: FPGA arch.
    53282: 03/03/10: Re: PCI specification doubt
    53283: 03/03/10: Re: scripting leonardo spectrum
    53284: 03/03/10: Re: Issues in Outsourcing?
    53578: 03/03/17: Re: Using divided clock
Rick Fox:
    78888: 05/02/09: Plea for help with MAX7000S
Rick Haver:
    57039: 03/06/21: Re: PALs, GALs and ABEL
Rick HORMIGO:
    55585: 03/05/13: Spartan 3 Power requirements
    55592: 03/05/13: Re: Spartan 3 Power requirements
Rick Jackson:
    92184: 05/11/23: Re: Case expression?
Rick Jones:
    135384: 08/09/29: Re: Sending UDP packets over Ethernet
Rick Kwan:
    9241: 98/03/04: Re: The case for Linux and EDA
    9282: 98/03/05: Re: The case for Linux and EDA
    9321: 98/03/06: Re: The case for Linux and EDA
    9325: 98/03/06: Re: The case for Linux and EDA
    9280: 98/03/05: Re: The case for free operating systems and EDA
    9404: 98/03/09: Re: The case for free operating systems and EDA
    9362: 98/03/07: Re: The case for Linux and EDA
    9363: 98/03/07: Re: The case for free operating systems and EDA
Rick Lyons:
    20905: 00/02/26: Re: MRP systems
    39180: 02/02/03: Re: solutions manuals, and no they are not for school
    39260: 02/02/05: Re: solutions manuals, and no they are not for school
    39317: 02/02/06: Re: solutions manuals, and no they are not for school
    39397: 02/02/08: Re: solutions manuals, and no they are not for school
    39398: 02/02/08: Re: solutions manuals, and no they are not for school
    39435: 02/02/09: Re: solutions manuals, and no they are not for school
    88190: 05/08/11: Re: System Engineering in the R/D World
    107753: 06/09/01: Re: Performance Appraisals
    113551: 06/12/16: Re: IQ multiplier
Rick McBain:
    10807: 98/06/21: FPGA design tools for Xilinx and Altera on WinNT and Alpha
    10808: 98/06/21: Re: VHDL testbench in Maxplus2
Rick Milado:
    22156: 00/04/27: FPGA + DSP24 = Super Performance DSP
Rick North:
    77756: 05/01/16: Virtex-II start up
    78001: 05/01/22: Good references for ADPLL in FPGA?
    78394: 05/01/31: Init of BRAMs with ISE flow.
    78437: 05/01/31: Init of BRAMs with ISE flow.
    90767: 05/10/20: RPM reference for xilinx
    90820: 05/10/21: Re: RPM reference for xilinx
    91775: 05/11/12: Re: Add files to Xilinx ISE Project w/script
    113981: 07/01/01: PPC PLB <=> FPGA fabric
    116575: 07/03/13: Can you change the default settings for XST when running platgen?
    127369: 07/12/19: Quartus and simulation libraries...
Rick Spanbauer:
    348: 94/10/26: Re: I/O pin currents on Xilinx FPGAs?
Rick Thompson:
    77824: 05/01/18: Re: Exportability of EDA industry from North America?
    77854: 05/01/18: Re: Exportability of EDA industry from North America?
    77873: 05/01/19: Re: Exportability of EDA industry from North America?
    78093: 05/01/24: Scripted Xilinx flow with free Webpack tools?
    78152: 05/01/25: Re: Scripted Xilinx flow with free Webpack tools?
<rick.c.hodgin@gmail.com>:
    157371: 14/12/01: Which Altera to buy?
    157376: 14/12/02: Re: Which Altera to buy?
    157378: 14/12/02: Re: Which Altera to buy?
<Rick>:
    12338: 98/10/09: What is an embedded IrDA (infrared) software protocol stack?
<rick@mips.com>:
    106941: 06/08/22: Running DDR below the min frequency
    106944: 06/08/22: Re: Running DDR below the min frequency
    107207: 06/08/25: Re: Running DDR below the min frequency
Rickard Norberg:
    15135: 99/03/09: Spartan Configuration
    15793: 99/04/14: What to see in New York?
<rickballantyne@home.com>:
    23133: 00/06/15: Re: Mutating Virtex FPGA
    25300: 00/09/05: ADV7185 & AVD7194
rickman:
    23936: 00/07/16: Re: Looking for 'FREE' FPGA software
    23752: 00/07/07: Re: VHDL code for LFSR
    23770: 00/07/07: Re: BIST in FPGAs?
    23777: 00/07/07: Re: BIST in FPGAs?
    23778: 00/07/07: Re: Clock Buffer
    23792: 00/07/08: Re: Remedies after the Fathers' Day Massacre
    23803: 00/07/10: Re: Remedies after the Fathers' Day Massacre
    23805: 00/07/10: Xilinx buys LavaLogic
    23812: 00/07/10: Re: XC2018 development system xact5 or xact6 sale?
    23831: 00/07/12: Re: C++/Java generators vs. synthesizers
    23832: 00/07/12: Re: Xilinx Logic Cell counts and carry chains
    23856: 00/07/12: Re: Boundary-Scan Tests with JTAG Technologies Tools
    23857: 00/07/12: Re: hold time errors in FPGA's ?
    23858: 00/07/12: Re: C++/Java generators vs. synthesizers
    23865: 00/07/13: Re: Boundary-Scan Tests with JTAG Technologies Tools
    23866: 00/07/13: Re: Boundary-Scan Tests with JTAG Technologies Tools
    23874: 00/07/13: Re: Init time of Xilinx Virtex / Spartan II
    23878: 00/07/13: Re: XC2018 development system xact5 or xact6 sale?
    23901: 00/07/14: Re: Init time of Xilinx Virtex / Spartan II
    23908: 00/07/14: Re: Dual Port RAM
    23910: 00/07/14: Re: Init time of Xilinx Virtex / Spartan II
    23911: 00/07/14: Re: Boundary-Scan Tests with JTAG Technologies Tools
    23913: 00/07/14: Re: Timing Analysis
    23919: 00/07/14: Re: Boundary-Scan Tests with JTAG Technologies Tools
    23920: 00/07/14: Re: Dual Port RAM
    23927: 00/07/15: Re: hold time errors in FPGA's ?
    23943: 00/07/17: Re: better than a long explanation, the LFSR testbench
    23972: 00/07/19: Re: Dual Port RAM
    23983: 00/07/19: Re: Fundation serial & Alliance serial
    23995: 00/07/19: Re: Xilinx Logic Cell counts and carry chains
    23997: 00/07/20: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
    24059: 00/07/25: Re: Spartan II Pin
    24073: 00/07/26: Re: Xilinx Logic Cell counts and carry chains
    24074: 00/07/26: Re: Xilinx "MUX_OP not inferred" error.
    24087: 00/07/26: Re: Xilinx "MUX_OP not inferred" error.
    24089: 00/07/26: Re: Variable shifting
    24097: 00/07/26: Re: Variable shifting
    24100: 00/07/26: Re: Pad trireg in XLA FPGA
    24101: 00/07/26: Re: Variable shifting
    24108: 00/07/26: Re: Pad trireg in XLA FPGA
    24109: 00/07/26: Re: Variable shifting
    24113: 00/07/26: Re: Variable shifting
    24115: 00/07/27: Re: Which one is good coding style?
    24116: 00/07/27: Viewlogic Licencing
    24129: 00/07/27: Re: Which one is good coding style?
    24132: 00/07/27: Re: Spartan-II power consumption
    24143: 00/07/27: Re: Spartan-II power consumption
    24144: 00/07/27: Re: Pad trireg in XLA FPGA (beating a horse to death)
    24160: 00/07/28: Re: Viewlogic Licencing
    24161: 00/07/28: Re: Spartan-II power consumption
    24162: 00/07/28: Re: LFSR as a divider
    24165: 00/07/28: Re: Variable shifting
    24167: 00/07/28: Re: LFSR as a divider
    24177: 00/07/28: Re: Pad trireg in XLA FPGA (beating a horse to death)
    24181: 00/07/28: Re: LFSR as a divider
    24187: 00/07/28: Re: Which one is good coding style?
    24197: 00/07/28: Re: Variable shifting
    24205: 00/07/29: Re: Variable shifting
    24206: 00/07/29: Re: Viewlogic Licencing
    24211: 00/07/30: Re: Viewlogic Licencing
    24212: 00/07/30: Re: Viewlogic Licensing
    24226: 00/07/30: Re: Viewlogic Licensing
    24227: 00/07/30: Re: Virtex SelectMAP download from CPU problem
    24229: 00/07/30: Re: Viewlogic Licencing
    24247: 00/08/01: Re: Virtex DLL and external clocks
    24248: 00/08/01: Re: tbuf
    24275: 00/08/02: Re: Viewlogic Licencing
    24286: 00/08/02: Re: Viewlogic Licensing
    24311: 00/08/03: Re: tbuf
    24331: 00/08/03: Re: Viewlogic Licencing
    24334: 00/08/04: Re: Viewlogic Licensing
    24314: 00/08/03: Re: 8251A USART
    24332: 00/08/04: Re: Who needs all those printed ac parameters?
    24333: 00/08/04: Re: Large CPLD
    24335: 00/08/04: Re: PWM implementation suggested sought for Spartan FPGA
    24359: 00/08/04: Re: Who needs all those printed ac parameters?
    24362: 00/08/04: Re: 5v -> 1.8v switcher supply for FPGA ??
    24364: 00/08/04: Re: Memory specification
    24375: 00/08/05: Re: Memory specification
    24387: 00/08/06: Re: Category : Subject
    24414: 00/08/07: Re: Crossing Clock Domains.
    24415: 00/08/07: Re: Xilinx Foundation 3.1i
    24416: 00/08/07: Re: Help! Troubles using async FIFO cores in Virtex
    24417: 00/08/07: Re: Help!! Virtex system gate count.
    24426: 00/08/07: Re: Xilinx Foundation 3.1i
    24430: 00/08/07: Re: XST?
    24434: 00/08/08: Re: Memory specification
    24456: 00/08/09: Re: XST?
    24490: 00/08/10: Re: Further FPGA metastability questions
    24510: 00/08/11: Re: Further FPGA metastability questions
    24511: 00/08/11: Re: Comparing Xilinx FPGAs
    24528: 00/08/11: Re: Easy question on programming
    24547: 00/08/13: Re: state encoding in Synplify!!!
    24584: 00/08/14: Re: Xilinx chip not programming correctly
    24592: 00/08/14: Re: state encoding in Synplify!!!
    24596: 00/08/14: Non-disclosures in job interviews
    24600: 00/08/14: Re: Non-disclosures in job interviews
    24603: 00/08/14: Re: Non-disclosures in job interviews
    24606: 00/08/14: Re: Non-disclosures in job interviews
    24621: 00/08/15: Re: Non-disclosures in job interviews
    24622: 00/08/15: Re: 8251 USART
    24623: 00/08/15: Re: what does 0.35 micron mean
    24641: 00/08/16: Re: 8251 USART
    24642: 00/08/16: Re: what does 0.35 micron mean
    24643: 00/08/16: Re: Non-disclosures in job interviews
    24654: 00/08/16: Re: error during synthesis
    24655: 00/08/16: Re: 8251 USART
    24673: 00/08/16: Re: Non-disclosures in job interviews
    24674: 00/08/16: Re: Non-disclosures in job interviews
    24675: 00/08/16: Re: Non-disclosures in job interviews
    24676: 00/08/16: Re: Non-disclosures in job interviews
    24699: 00/08/16: Re: Non-disclosures in job interviews, Round One
    24700: 00/08/17: Re: 8251 USART
    24718: 00/08/17: Re: Non-disclosures in job interviews, Round One
    24747: 00/08/17: Re: Non-disclosures in job interviews
    24748: 00/08/17: Re: Non-disclosures in job interviews
    24750: 00/08/17: Re: Non-disclosures in job interviews
    24766: 00/08/17: Re: Non-disclosures in job interviews
    24767: 00/08/17: Re: Non-disclosures in job interviews
    24770: 00/08/17: Re: state encoding in Synplify!!!
    24785: 00/08/18: Re: Permanently programming FPGAs
    24786: 00/08/18: Re: Permanently programming FPGAs
    24789: 00/08/18: Re: Xilinx design flow with Mentor
    24795: 00/08/18: Re: Non-disclosures in job interviews, Round One
    24837: 00/08/20: Re: Non-disclosures in job interviews, Round One
    24922: 00/08/22: Re: Mealy vs Moore FSM model
    24923: 00/08/22: Re: Mealy vs Moore FSM model
    24954: 00/08/23: Re: Non-disclosures in job interviews
    24955: 00/08/23: Re: Non-disclosures in job interviews, Round Two
    24956: 00/08/23: Re: Mealy vs Moore FSM model
    24957: 00/08/23: Re: Mealy vs Moore FSM model
    24958: 00/08/23: Re: Looks like Xilinx is at it again!
    24980: 00/08/23: Re: Non-disclosures in job interviews, Round Two
    24983: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
    24994: 00/08/23: Re: Some notes on metastability
    25004: 00/08/23: Re: Mealy vs Moore FSM model
    25005: 00/08/23: Re: Looks like Xilinx is at it again!
    25006: 00/08/23: Re: Looks like Xilinx is at it again!
    25015: 00/08/23: Re: Non-disclosures in job interviews, Round Two
    25035: 00/08/24: Re: Non-disclosures in job interviews, Round Two
    25066: 00/08/25: Re: Non-disclosures in job interviews, Round Two
    25114: 00/08/26: Re: Non-disclosures in job interviews, Round Two
    25116: 00/08/26: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
    25117: 00/08/26: Re: Balls!
    25151: 00/08/28: Re: Large amout of Interconnect between FPGAs
    25182: 00/08/29: Re: availability of Spartan II
    25183: 00/08/29: Re: Spartan II vs. Virtex
    25184: 00/08/29: Re: Xilinx and CD databooks (rant)
    25185: 00/08/29: Re: Xilinx and CD databooks (rant)
    25198: 00/08/30: Re: Spartan II vs. Virtex
    25208: 00/08/30: Re: Non-disclosures in job interviews, Round One
    25209: 00/08/30: Re: Large amout of Interconnect between FPGAs
    25210: 00/08/30: Re: Xilinx and CD databooks (rant)
    25211: 00/08/30: Re: Xilinx and CD databooks (rant)
    24916: 00/08/22: Re: Mealy vs Moore FSM model
    25241: 00/08/31: Re: Spartan II vs. Virtex
    25651: 00/09/16: Re: Xilinx and CD databooks (rant)
    25344: 00/09/07: Re: 3.3/2.5 voltage regulators
    25345: 00/09/07: Re: About XNF, EDIF and UCF
    25380: 00/09/09: Re: 3.3/2.5 voltage regulators
    25381: 00/09/09: Re: 3.3/2.5 voltage regulators
    25383: 00/09/09: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
    25384: 00/09/09: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
    25392: 00/09/09: Re: VirtexE availability?
    25417: 00/09/11: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
    25427: 00/09/11: Re: 3.3/2.5 voltage regulators
    25428: 00/09/11: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
    25429: 00/09/11: Nanoseconds and seasons
    25451: 00/09/11: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
    25496: 00/09/12: Re: computing difference between Gray values?
    25499: 00/09/12: Re: virtex shape
    25500: 00/09/12: Re: Code distribution without loss of IP?
    25495: 00/09/12: Re: flipflops/statemachine/fifos and timing
    25498: 00/09/12: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
    25652: 00/09/16: Re: 3.3/2.5 voltage regulators
    25653: 00/09/16: Re: VirtexE availability?
    25654: 00/09/16: Re: hardware compatibility and patent infringement
    25655: 00/09/16: Re: hardware compatibility and patent infringement
    25657: 00/09/16: Re: hardware compatibility and patent infringement
    25659: 00/09/16: Re: Simon , decoupling caps
    25660: 00/09/16: Re: FPGA Express Strikes Again!
    25681: 00/09/17: Re: MAX PLUS 2
    25682: 00/09/17: Re: Simon , decoupling caps
    25687: 00/09/17: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
    25691: 00/09/17: Re: MAX PLUS 2
    25692: 00/09/17: Xilinx Web Pack
    25701: 00/09/17: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
    25726: 00/09/18: Re: 3.3/2.5 voltage regulators
    25728: 00/09/18: Re: hardware compatibility and patent infringement
    25729: 00/09/18: Re: Virtex clock fanout
    25757: 00/09/19: Re: Xilinx Web Pack
    25758: 00/09/19: Re: Xilinx Web Pack
    25759: 00/09/19: Re: Safe voltage regulator for Xilinx XC2S150 part?
    25848: 00/09/22: Re: Xilinx Web Pack
    25875: 00/09/24: Re: CORDIC COS/SIN with FPGA implementation
    25896: 00/09/25: Re: 20 bit to 64 bit bus conversion
    25899: 00/09/25: Re: FPGA for PCM coded DTMF transmission?
    25903: 00/09/25: Re: Difference between Foundation Base and Foundation ISE Base Express?
    25948: 00/09/27: Re: ABEL truth table for 8-1 Mux
    26015: 00/09/30: Re: atmel verses altera
    26023: 00/09/30: Re: atmel verses altera
    26041: 00/10/01: Re: Migrating PAL/TTL design to FPGA
    26060: 00/10/02: Re: "Xilinx Adds FPGA Support to Free Web Design Tools"
    26068: 00/10/02: Re: Synthesis failures
    26072: 00/10/02: Re: Synthesis failures
    26098: 00/10/03: Re: Xilinx Licensing.
    26122: 00/10/04: Re: Xilinx Licensing.
    26143: 00/10/05: Re: Xilinx Licensing.
    26153: 00/10/05: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26193: 00/10/07: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26194: 00/10/07: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26209: 00/10/08: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26210: 00/10/08: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26214: 00/10/08: Re: Xilinx and CD databooks (rant)
    26227: 00/10/09: Re: Analogue FPGAs ?
    26241: 00/10/09: Alternative hardware development tools Was: Amplify experience
    26244: 00/10/09: ModelSim XE/Starter speed issues
    26255: 00/10/10: Re: ModelSim XE/Starter speed issues
    26272: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26273: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26274: 00/10/10: Re: ModelSim XE/Starter speed issues
    26298: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26326: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26327: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26328: 00/10/11: Re: Analogue FPGAs ?
    26329: 00/10/11: Re: Analogue FPGAs ?
    26343: 00/10/12: Re: Category : Subject:Floorplanning
    26344: 00/10/12: Re: Xilinx and CD databooks (rant) re: startup I
    26359: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26360: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26361: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26362: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26363: 00/10/13: Re: Analogue FPGAs ?
    26403: 00/10/14: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26404: 00/10/14: Re: Sinusoidal PWM on Xilinx FPGA
    26406: 00/10/15: Re: 35 CLB 8-bit MCU
    26415: 00/10/15: Re: Xilinx and CD databooks (rant)
    26416: 00/10/15: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26422: 00/10/16: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26442: 00/10/16: Re: Xilinx and CD databooks (rant)
    26443: 00/10/16: Re: Asynchronous pulse generation with Spartan.
    26464: 00/10/17: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26469: 00/10/17: Re: Asynchronous pulse generation with Spartan.
    26554: 00/10/19: Re: DS2401 security from pirating an FPGA
    26611: 00/10/22: Re: UCF Question
    26613: 00/10/22: Re: UCF Question
    26617: 00/10/22: Re: UCF Question
    26745: 00/10/26: Re: How safe is the algorithm implemented with FPGA?
    26657: 00/10/23: Re: UCF Question
    26744: 00/10/26: Re: UCF Question
    26794: 00/10/29: Re: death of rloc ?
    26958: 00/11/05: Re: Alliance under Linux?
    26957: 00/11/05: Re: High fan out CE signal.
    27111: 00/11/10: CRC, LFSR and scramblers
    27123: 00/11/11: Re: CRC, LFSR and scramblers
    27128: 00/11/11: Re: CRC, LFSR and scramblers
    27133: 00/11/12: Re: CRC, LFSR and scramblers
    27201: 00/11/14: Re: CRC, LFSR and scramblers
    27298: 00/11/17: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
    27446: 00/11/22: Re: HELP! Lucent ORCA datasheets needed!
    27496: 00/11/24: Re: Power consumption FPGA...
    27569: 00/11/28: Re: question on initial states of FFs and GSR in Virtex
    36101: 01/10/29: Re: Verilog vs. VHDL
    36263: 01/11/04: JBITS and modular FPGA configuration
    36288: 01/11/05: Virtex II introduction schedule
    36473: 01/11/09: Re: Decoupling capacitors on Virtex II
    36754: 01/11/19: Re: Decoupling capacitors on Virtex II
    36755: 01/11/19: Re: Xilinx and Multirate clock ??
    36756: 01/11/19: Re: Virtex-II Pin-Incompatibility
    36831: 01/11/21: Re: don't cares and X's in a case statement?
    36832: 01/11/21: Re: ISA interface
    36852: 01/11/21: Re: Decoupling capacitors on Virtex II
    36935: 01/11/26: Device Support in Webpack
    36943: 01/11/26: Re: Device Support in Webpack
    37022: 01/11/28: Re: FPGA startup current
    37023: 01/11/28: Re: SpartanIIE
    37024: 01/11/28: Re: Device Support in Webpack
    37026: 01/11/28: Re: Device Support in Webpack
    37033: 01/11/28: Re: FPGA startup current
    37056: 01/11/29: Re: 128-bit scrambling and CRC computations
    37057: 01/11/29: Re: Is there a full open-source synthesis path for any FPGA?
    37060: 01/11/29: Re: 128-bit scrambling and CRC computations
    37067: 01/11/29: Re: FPGA startup current
    37099: 01/11/29: Re: 128-bit scrambling and CRC computations
    37101: 01/11/29: Re: SpartanIIE
    37102: 01/11/29: Re: SpartanIIE
    37103: 01/11/29: Re: FPGA startup current
    37104: 01/11/29: Re: Is there a full open-source synthesis path for any FPGA?
    37145: 01/12/01: Re: 128-bit scrambling and CRC computations
    37146: 01/12/01: Re: Is there a full open-source synthesis path for any FPGA?
    37158: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
    37159: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
    37164: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
    37165: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
    37166: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
    37169: 01/12/02: Re: 128-bit scrambling and CRC computations
    37173: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
    37174: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
    37189: 01/12/03: Re: 128-bit scrambling and CRC computations
    37215: 01/12/04: Re: 128-bit scrambling and CRC computations
    37232: 01/12/04: Re: What do you like/dislike about place and route tools?
    37233: 01/12/04: Re: What do you like/dislike about place and route tools?
    37243: 01/12/04: Re: What do you like/dislike about place and route tools?
    37400: 01/12/10: Re: ISA syncronization?
    37437: 01/12/10: Re: ISA syncronization?
    37990: 01/12/29: Re: Innoveda Speedwave vs. Modelsim?
    37991: 01/12/29: Re: Innoveda Speedwave vs. Modelsim?
    38241: 02/01/09: Spartan IIE pinout compatibililty with Virtex E
    38244: 02/01/09: Re: Spartan IIE pinout compatibililty with Virtex E
    38272: 02/01/10: Re: Avoid routing through a certain area (Xilinx)
    38275: 02/01/10: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
    38298: 02/01/11: Re: Spartan-IIE interfacing issues
    38321: 02/01/11: Re: Avoid routing through a certain area (Xilinx)
    38322: 02/01/11: Re: Avoid routing through a certain area (Xilinx)
    38324: 02/01/11: Picking an FPGA
    38339: 02/01/11: Re: Picking an FPGA
    38341: 02/01/11: Re: Picking an FPGA
    38364: 02/01/12: Re: Picking an FPGA
    38380: 02/01/13: Re: Picking an FPGA
    38381: 02/01/13: Re: FPGA configuration
    38382: 02/01/13: Re: MSP430 + Xilinx via JTAG
    38398: 02/01/13: Re: FPGA configuration
    38403: 02/01/14: Re: MSP430 + Xilinx via JTAG
    38656: 02/01/20: Re: APEX-II vs VIRTEX-II
    38847: 02/01/26: Re: MSP430 + Xilinx via JTAG
    38871: 02/01/27: Re: tri-state vs. Mux
    38872: 02/01/27: Re: MSP430 + Xilinx via JTAG
    38874: 02/01/27: Re: MSP430 + Xilinx via JTAG
    38925: 02/01/28: Re: FPGA or Micro-controller in Lowpower designs?
    38969: 02/01/28: Boundary Scan Chain and JTAG Emulation of MSP430
    39008: 02/01/29: Re: FPGA or Micro-controller in Lowpower designs?
    39009: 02/01/29: Re: Spartan II power-up current - again
    39011: 02/01/29: Re: Pin assignment on ACEX1K
    39123: 02/02/01: Re: Flex10KA vs MAX7000S
    39125: 02/02/01: Re: JTAG Emulator Tutorial
    39127: 02/02/01: Re: FPGA or Micro-controller in Lowpower designs?
    39128: 02/02/01: Re: FPGA or Micro-controller in Lowpower designs?
    39129: 02/02/01: Re: Pin assignment on ACEX1K
    39130: 02/02/01: Re: MSP430 + Xilinx via JTAG
    39176: 02/02/03: JTAG Boundary Scan with the XDS510
    39178: 02/02/03: Re: FPGA or Micro-controller in Lowpower designs?
    39182: 02/02/03: Re: MSP430 + Xilinx via JTAG
    39193: 02/02/03: Re: JTAG Boundary Scan with the XDS510
    39495: 02/02/11: Re: Altera's new family Stratix
    39590: 02/02/13: Re: Altera's new family Stratix
    39638: 02/02/14: Re: Orca ngdbuild error: could not expand block
    39640: 02/02/14: Configuration in SelectMAP mode and CCLK
    39666: 02/02/15: Re: FPGA choices and questions
    39713: 02/02/17: Re: Spartan-II becomes Vertex.
    39714: 02/02/17: Re: Altera's new family Stratix
    39715: 02/02/17: Re: Speaking of ORCA...
    39716: 02/02/17: Re: FPGA choices and questions
    39717: 02/02/17: Re: FPGA choices and questions
    39718: 02/02/17: Re: FPGA choices and questions
    39719: 02/02/17: Re: Virtex-II and SDRAM Controller at 133MHz
    39720: 02/02/17: Re: APEX-II vs VIRTEX-II
    39727: 02/02/17: Re: Virtex-II and SDRAM Controller at 133MHz
    39769: 02/02/19: Coolrunner and ISP
    39770: 02/02/19: Re: Orca FPSC synthesizing issue
    39810: 02/02/20: Re: Coolrunner and ISP
    39906: 02/02/21: Re: Coolrunner and ISP
    39908: 02/02/21: Re: FPGA choices and questions
    39954: 02/02/22: Re: INIT on XC2S30
    39955: 02/02/22: Re: Coolrunner and ISP
    39957: 02/02/22: Re: Coolrunner and ISP
    39959: 02/02/22: Re: Orca FPSC synthesizing issue
    39983: 02/02/23: Re: Coolrunner and ISP
    39984: 02/02/23: Re: Coolrunner and ISP
    39985: 02/02/23: Re: Coolrunner and ISP
    39989: 02/02/23: Re: Coolrunner and ISP
    40000: 02/02/24: Re: Coolrunner and ISP
    40006: 02/02/24: Re: Few pins but more gates
    40008: 02/02/24: Re: Virtex-II and SDRAM Controller at 133MHz
    40196: 02/03/01: Re: stuck in state in Spartan-II!
    40248: 02/03/03: Re: Embedding counting in an FSM.
    40249: 02/03/03: Re: Altera's new family Stratix
    40366: 02/03/06: Re: Xilinx announces Virtex-II Pro is shipping
    40564: 02/03/11: Spartan II E output voltage characteristics
    40599: 02/03/11: Re: Spartan II E output voltage characteristics
    40600: 02/03/11: Re: Xilinx Download Cable Connectors
    40630: 02/03/12: Re: Spartan II E output voltage characteristics
    40631: 02/03/12: Mystery two wire interface, or am I being dense?
    40656: 02/03/12: Re: Mystery two wire interface, or am I being dense?
    40779: 02/03/15: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
    40788: 02/03/15: High speed clock routing
    40791: 02/03/15: Re: High speed clock routing
    40798: 02/03/15: Re: High speed clock routing
    40806: 02/03/15: Re: High speed clock routing
    40808: 02/03/15: Re: Xilinix FPGA with 5V IO
    40821: 02/03/16: Re: High speed clock routing
    40883: 02/03/17: Re: just bought...
    40898: 02/03/17: Re: just bought...
    40904: 02/03/18: Re: Difference between Virtex-II(E) und Virtex-E
    40927: 02/03/18: Re: just bought...
    40939: 02/03/18: Re: High speed clock routing
    40940: 02/03/18: XC2S configuration... one more time
    40942: 02/03/18: Re: High speed clock routing
    40946: 02/03/18: Re: High speed clock routing
    40958: 02/03/19: Re: High speed clock routing
    41071: 02/03/20: Re: High speed clock routing
    41112: 02/03/21: Re: High speed clock routing
    41134: 02/03/21: Re: High speed clock routing
    41194: 02/03/22: Re: High speed clock routing
    41199: 02/03/22: Poor availability problems on Coolrunner
    41217: 02/03/22: Re: Poor availability problems on Coolrunner
    41221: 02/03/22: Re: Poor availability problems on Coolrunner
    41223: 02/03/22: Re: Poor availability problems on Coolrunner
    41225: 02/03/22: Re: Poor availability problems on Coolrunner
    41231: 02/03/22: Re: Poor availability problems on Coolrunner
    41232: 02/03/22: GREAT availability on Coolrunner!!! (was: Poor availability problems on
    41235: 02/03/22: A poor man's boundary scan test tool
    41245: 02/03/22: Re: GREAT availability on Coolrunner!!! (was: Poor availability problems
    41246: 02/03/22: Re: Poor availability problems on Coolrunner
    41247: 02/03/22: Re: Electronic Parts Locator
    41261: 02/03/23: Re: Altera Stratix compared to Xilinx Virtex
    41262: 02/03/23: Re: Altera Stratix compared to Xilinx Virtex
    41264: 02/03/23: Re: High speed clock routing
    41296: 02/03/25: Re: High speed clock routing
    41385: 02/03/27: Re: clock source
    41386: 02/03/27: Re: I2C Slave sampling edge
    41407: 02/03/27: Re: I2C Slave sampling edge
    41410: 02/03/27: I2C complexity
    41439: 02/03/28: Re: I2C Slave sampling edge
    41447: 02/03/28: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
    41456: 02/03/28: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
    41569: 02/04/02: Re: pricing and gate count info
    41615: 02/04/03: Re: Pullup of Spartan-2
    42169: 02/04/17: Re: Reconfiguring Spartan II after boot-up
    42354: 02/04/21: Re: Xilinx Easypath- Selling parts with known defects
    42490: 02/04/25: Re: Using 74HCT245N between Spartan-II and ISA
    42493: 02/04/25: Re: SpartanII design considerations...
    42495: 02/04/25: Re: sharing SDRAM between processor and VirtexII?
    42512: 02/04/25: Re: Using 74HCT245N between Spartan-II and ISA
    42518: 02/04/25: Re: SpartanII design considerations...
    42560: 02/04/27: Re: SpartanII design considerations...
    42561: 02/04/27: Re: SpartanII design considerations...
    42562: 02/04/27: Availability of XC2S150E-6FG456I
    42569: 02/04/27: Re: SpartanII design considerations...
    42587: 02/04/28: Re: SpartanII design considerations...
    42663: 02/04/30: SpartanIIE hold timing
    42671: 02/04/30: Re: SpartanIIE hold timing
    42677: 02/04/30: Re: SpartanIIE hold timing
    42712: 02/05/01: Re: Availability of XC2S150E-6FG456I
    42716: 02/05/01: Re: SpartanIIE hold timing
    42730: 02/05/01: Re: Availability of XC2S150E-6FG456I
    42747: 02/05/01: Re: Availability of XC2S150E-6FG456I
    42771: 02/05/02: Re: Availability of XC2S150E-6FG456I
    42772: 02/05/02: Re: Availability of XC2S150E-6FG456I
    42781: 02/05/02: Re: Availability of XC2S150E-6FG456I
    42782: 02/05/02: Re: Availability of XC2S150E-6FG456I
    42783: 02/05/02: Re: Availability of XC2S150E-6FG456I
    42784: 02/05/02: Re: Delivery problems..
    42805: 02/05/02: Re: Availability of XC2S150E-6FG456I
    42817: 02/05/03: Re: Availability of XC2S150E-6FG456I
    42875: 02/05/06: Re: Frequency synthesiser
    42923: 02/05/07: Re: Availability of XC2S150E-6FG456I
    42980: 02/05/08: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
    42997: 02/05/08: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
    43020: 02/05/09: Re: JTAG 5V tollerance...?
    43227: 02/05/16: Re: Need Help on FPGA and Spiking Neurons
    43262: 02/05/17: SDRAM pricing
    43274: 02/05/17: Re: SDRAM pricing
    43327: 02/05/18: Re: Need Help on FPGA and Spiking Neurons
    43328: 02/05/18: Re: SDRAM pricing
    43329: 02/05/18: Re: SDRAM pricing
    43338: 02/05/19: Re: SDRAM pricing
    43389: 02/05/20: Re: Need Help on FPGA and Spiking Neurons
    43391: 02/05/20: Re: Disti web sites
    43392: 02/05/20: Re: Spartan2 on a Compact Flash card
    43393: 02/05/20: Re: Synchronous Single Clock Designs
    43553: 02/05/23: Re: SDRAM pricing
    43583: 02/05/24: Re: Time for a new computer. Suggestions?
    43588: 02/05/24: IO simulations
    43727: 02/05/31: Re: IO simulations
    43775: 02/06/02: Re: Time for a new computer. Suggestions?
    43776: 02/06/02: Re: fpga cpu
    43813: 02/06/03: Re: fpga cpu
    43976: 02/06/07: Xilinx ISE BaseX... What is it?
    43977: 02/06/07: Re: Xilinx ise software?
    43979: 02/06/07: Re: OFFSET timing contraints
    44003: 02/06/09: Re: OFFSET timing contraints
    44131: 02/06/12: Re: OFFSET constraint for internal clock
    44132: 02/06/12: Re: Power supply caps on PCB
    44192: 02/06/13: Re: Power supply caps on PCB
    44241: 02/06/14: Re: Power supply caps on PCB
    44295: 02/06/17: Re: Power supply caps on PCB
    44367: 02/06/18: Re: Xilinx ISE BaseX... What is it?
    44403: 02/06/19: Re: what's the use of BlockRAM
    44404: 02/06/19: Re: 5V tolerance
    44416: 02/06/19: Re: ATMEL CPLD
    44418: 02/06/19: Re: new computer
    44453: 02/06/20: Re: WebPack - How to view synthesis results?
    44454: 02/06/20: Re: what's the use of BlockRAM
    44525: 02/06/22: Re: Xilinx's 4.1i's Lastest webpack
    44526: 02/06/22: Re: new computer
    44540: 02/06/23: Re: Xilinx's 4.1i's Lastest webpack
    44541: 02/06/23: Re: Xilinx's 4.1i's Lastest webpack
    44542: 02/06/23: Re: Xilinx's 4.1i's Lastest webpack
    44543: 02/06/23: Re: new computer
    44553: 02/06/23: Re: new computer
    44566: 02/06/24: Re: new computer
    44567: 02/06/24: Re: new computer
    44568: 02/06/24: Re: Xilinx's 4.1i's Lastest webpack
    44569: 02/06/24: Re: Xilinx webpack if - else if statement ??
    44603: 02/06/24: Xilinx tools under WinXP
    44614: 02/06/24: Re: Xilinx's 4.1i's Lastest webpack
    44676: 02/06/26: Re: 5V tolerance
    44686: 02/06/27: Re: 5V tolerance
    44707: 02/06/27: Re: 5V tolerance
    44736: 02/06/28: Re: Silly questions about configuring Spartan 2's
    44762: 02/06/29: Re: 5V tolerance
    44764: 02/06/29: Re: Xilinx's 4.1i's Lastest webpack
    44775: 02/06/30: Re: 5V tolerance
    44793: 02/07/01: Re: Can Coolrunner's be daisy chained?
    44855: 02/07/03: Re: Xilinx's 4.1i's Lastest webpack
    44930: 02/07/06: Re: Converting to Altera Quartus
    44958: 02/07/08: Re: 3.3 volt tolerance in Virtex-II Pro?
    45005: 02/07/09: Re: how to keep info. in RAM during reconfiguration?
    45367: 02/07/20: Re: spiral / waterfall /watersluice : Which are your methods?
    45369: 02/07/20: Re: Problem with OpenCore PCI IP Core
    45378: 02/07/21: Re: spiral / waterfall /watersluice : Which are your methods?
    45502: 02/07/24: Re: delay pipes in verilog for spartan IIe?
    45503: 02/07/24: Re: 8bit Magnitude Comparator
    45560: 02/07/26: Re: logic elements v/s logic cells
    45576: 02/07/27: Re: logic elements v/s logic cells
    45579: 02/07/27: Re: ALU in VHDL and a bunch of questions
    46645: 02/09/04: Re: What's wrong with clearLogic?
    46646: 02/09/04: Re: Polyphase filtering...
    46647: 02/09/04: Re: Polyphase filtering...
    46655: 02/09/04: Re: What's wrong with clearLogic?
    46656: 02/09/04: Re: What's wrong with clearLogic?
    46689: 02/09/05: Re: What's wrong with clearLogic?
    46690: 02/09/05: Re: Xilinx's ISE 5.1i
    46692: 02/09/05: XCR3384XL availability
    46722: 02/09/06: Re: XCR3384XL availability
    46724: 02/09/06: Re: What's wrong with clearLogic?
    46798: 02/09/09: Re: XCR3384XL availability
    46800: 02/09/09: Re: XCR3384XL availability
    46806: 02/09/09: Re: XCR3384XL availability
    46808: 02/09/09: Re: Polyphase filtering...
    46832: 02/09/09: Re: XCR3384XL availability
    46833: 02/09/09: Re: XCR3384XL availability
    46838: 02/09/09: Re: XCR3384XL availability
    46841: 02/09/09: Re: XCR3384XL availability
    46847: 02/09/10: Re: XCR3384XL availability
    46865: 02/09/10: Re: XCR3384XL availability
    46866: 02/09/10: Re: Polyphase filtering...
    46868: 02/09/10: Re: XCR3384XL availability
    46885: 02/09/10: Re: XCR3384XL availability
    46887: 02/09/10: Re: XCR3384XL availability
    46917: 02/09/11: Re: Polyphase filtering...
    46952: 02/09/12: Re: Xilinx TBUFs
    46962: 02/09/13: Re: number of IOBs in Spartan IIE is fishy
    46971: 02/09/13: Re: exploiting metastability
    46974: 02/09/13: Re: 2-D resistor array
    46985: 02/09/13: Re: 2-D resistor array
    46986: 02/09/13: Re: exploiting metastability
    46991: 02/09/13: Re: 2-D resistor array
    46992: 02/09/13: Re: number of IOBs in Spartan IIE is fishy
    46993: 02/09/13: Re: exploiting metastability
    47002: 02/09/13: Re: exploiting metastability
    47003: 02/09/13: Re: exploiting metastability
    47004: 02/09/13: Re: 2-D resistor array
    47007: 02/09/13: Re: sustainable rate for Random Read of DDR SDRAM
    47015: 02/09/14: Re: number of IOBs in Spartan IIE is fishy
    47020: 02/09/14: Re: number of IOBs in Spartan IIE is fishy
    47021: 02/09/14: XCR3xxxXL family architechture
    47028: 02/09/15: Re: number of IOBs in Spartan IIE is fishy
    47040: 02/09/15: Re: 1.8V regulator needed for Spartan IIE
    47055: 02/09/16: Re: exploiting metastability
    47192: 02/09/20: Re: Multiple divide by 10
    47193: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
    47196: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
    47237: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
    47242: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
    47306: 02/09/23: Re: Altera Cyclone low-cost FPGA chips?
    47310: 02/09/23: Re: Altera Cyclone low-cost FPGA chips?
    47327: 02/09/23: Re: writing across a column in an SDRAM
    47424: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
    47493: 02/09/26: Re: PCB Design for Altera FPGA
    47501: 02/09/26: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
    47529: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
    47587: 02/09/29: Re: Does it need any protection circuit for Interfacing FPGA device with
    47589: 02/09/30: Re: Does it need any protection circuit for Interfacing FPGA device
    47662: 02/10/01: Re: USB2 in FPGA?
    47769: 02/10/03: Re: Altera FPGA as ISA I/O device
    47841: 02/10/05: Re: Low power design
    47915: 02/10/07: Re: Xilinx ISE does not use Resgisters in IOB
    47916: 02/10/07: Re: Xilinx XST VHDL Compiler does not pack Registers in IOB
    47918: 02/10/07: Re: Xilinx WebPack ISE 5.1.01i XC9500 Implement problems
    47968: 02/10/08: Re: Why can Xilinx sw be as good as Altera's sw?
    48043: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48076: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48079: 02/10/10: Re: Booting a FPGA via USB
    48080: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48096: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48097: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48099: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48199: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
    48200: 02/10/14: Re: Verilog vs VHDL discussion on comp.arch.verilog group
    48201: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
    48202: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
    48230: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
    48231: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
    48353: 02/10/16: Re: Why can Xilinx sw be as good as Altera's sw?
    48357: 02/10/16: Re: Why can Xilinx sw be as good as Altera's sw?
    48358: 02/10/16: Re: Why can Xilinx sw be as good as Altera's sw?
    48359: 02/10/16: Re: Why can Xilinx sw be as good as Altera's sw?
    48370: 02/10/16: Re: Xilinx microblaze vs. picoblaze
    48401: 02/10/17: Re: Why can Xilinx sw be as good as Altera's sw?
    48454: 02/10/17: Re: Standing on the shores of Stratix-land
    48459: 02/10/17: Re: Why can Xilinx sw be as good as Altera's sw?
    48467: 02/10/17: Re: Xilinx microblaze vs. picoblaze
    49557: 02/11/15: Metastability in FPGAs
    49595: 02/11/16: Re: Metastability in FPGAs
    49616: 02/11/18: Re: Metastability in FPGAs
    49645: 02/11/18: Re: Metastability in FPGAs
    49647: 02/11/18: Re: Metastability in FPGAs
    49649: 02/11/18: Re: Metastability in FPGAs
    49665: 02/11/18: Re: Metastability in FPGAs
    49666: 02/11/18: Re: Metastability in FPGAs
    49667: 02/11/18: Re: Metastability in FPGAs
    49668: 02/11/18: Re: Metastability in FPGAs
    49697: 02/11/19: Re: Metastability in FPGAs
    49698: 02/11/19: Re: Metastability in FPGAs
    49777: 02/11/20: Re: What combinational logic will produce a falling edge only.
    49829: 02/11/21: Re: Metastability in FPGAs
    50057: 02/11/29: Re: question about PCB traces for FPGA board... ?
    50058: 02/11/29: Re: SDRAM technology
    50080: 02/11/30: Re: Interfacing DSP to PCI bridge using a FPGA
    50088: 02/12/01: Re: Interfacing DSP to PCI bridge using a FPGA
    50140: 02/12/03: Re: question about PCB traces for FPGA board... ?
    50141: 02/12/03: Re: ISA bus VGA
    50352: 02/12/09: Re: Interfacing DSP to PCI bridge using a FPGA
    50380: 02/12/10: Re: Clocking in a Spartan IIE
    50381: 02/12/10: Re: Tiny Forth Processors
    50422: 02/12/10: Re: Tiny Forth Processors
    50423: 02/12/10: Re: ISA bus VGA
    50424: 02/12/10: Re: Clocking in a Spartan IIE
    50500: 02/12/11: Re: Tiny Forth Processors
    50503: 02/12/11: Re: Tiny Forth Processors
    50529: 02/12/12: Re: Power consumption question
    50600: 02/12/13: Re: MTBF Calculation
    50602: 02/12/13: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50634: 02/12/14: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50657: 02/12/16: Re: what makes an implementation a patent?
    50658: 02/12/16: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50679: 02/12/17: Re: Tiny Forth Processors
    50793: 02/12/19: Re: A/D converter in FPGA
    50795: 02/12/19: Re: A/D converter in FPGA
    50802: 02/12/19: Re: What voltage level is considered as "floating"?
    50827: 02/12/20: Re: Multi cycle Paths..
    50879: 02/12/21: Re: FPGA Supercomputing