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Messages from 52250

Article: 52250
Subject: Re: Xilinx ISE optimization
From: <khtsoi@pc90026.cse.cuhk.edu.hk>
Date: 5 Feb 2003 09:35:20 GMT
Links: << >>  << T >>  << A >>
Hal Murray <murray@suespammers.org> wrote:
>>I have a design that part of it will be optimized away by MAP tools
>>as loadless. But I need to keep that part. I know I can use the '-u'
>>option to disable the trimming function. But I *do* want the optimizer
>>to work on the rest of the design to get better performance. Is this
>>possible (without going to FPGA Editor as I am doing)?

> Take the "loadless" signals that you want to preserve and put a load
> on them, perhaps by connecting them to an output pin.  Or AND several
> of them together and send that signal to a pin.

They are actually loaded and adding extra input will change the function
of the circuit. I know one can add a BUF or two cascaded INVs on a line.
But how?

> -- 
> The suespammers.org mail server is located in California.  So are all my
> other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's.  I hate spam.


-- 
Tsoi Kuen Hung (Brittle)
CSE CUHK

Article: 52251
Subject: Distributing component without source
From: "Niels Thomsen" <dynamite.no.spam@kanoop.com>
Date: Wed, 5 Feb 2003 10:39:33 -0000
Links: << >>  << T >>  << A >>
I have a design (more accurately, a set of components) that I want to ship
to a customer as binary only, i.e. without shipping the VHDL source to the
customer.  I am using Xilinx foundation 2.1i (I know - it's ancient!).

First of all, is this possible with the tools I've got?  I haven't been able
to find a tutorial out there on what files I need to ship, where to put
them, and how to instantiate the component set in the project that needs to
use them.

Any help/advice is much appreciated.

- Niels



Article: 52252
Subject: clock ditribution tree
From: "Skillwood" <skillwoodNOSPAM@hotmail.com>
Date: Wed, 5 Feb 2003 16:33:28 +0530
Links: << >>  << T >>  << A >>
Hi all,
what is a clock distribution tree?
Skillwood



Article: 52253
Subject: Re: low pass FIR filter in FPGA
From: vt313@comsys.ntu-kpi.kiev.ua
Date: Wed, 05 Feb 2003 13:42:10 +0200
Links: << >>  << T >>  << A >>
Hi Garry,

Xilinx PDA filters have the maximum order equal to 20,
and such filters could not fit a small device because of
long enough Relatively Placed Macros.

I know that Aldec Active HDL simulator 
has the built in FIR core generator
which supports both any filter length and any bit width,
and generates filters up to 200 MHz of the clock frequency.

Anatoli Sergyienko

Garry Allen wrote:
> 
> I have just started a new design where I am looking to implement a FIR
> filter in a SPartan IIe FPGA (actually 4, all with identical
> characteristics)
> To start with
> filter characteristics
> input data is 9 bit samples at 33.325714 MHz (or possibly 31.104 MHz)
> 1 dB ripple allowed in pass band (0 - 7MHz), minimum of 65 dB down in
> the stop band. (8 MHz)
> data is output at a rate of 1/2 the sampling frequency (decimation by
> 2) - 9 bit
> 
> I have a reasonable amount of freedom in the implementation of the
> design(the chip currently designed on the board is the XC2S150E)
> I am looking for suggestions on the implementation of the filter
> structure (eg multipliers, use of the block ram) and comments on the
> quality of dsp tools such as the tools from systolix and convern from
> Momentum Data Systems
> Has anyone used the filters in the Xilinx Core generator? What did you
> think of them? I am also happy to look at cores from other vendors if
> the pricing is reasonable.
> Garry Allen

Article: 52254
Subject: Virtex-2 Timing Simulation - 5.1i Service pack-3
From: virss@yahoo.com (Viral Shah)
Date: 5 Feb 2003 04:28:42 -0800
Links: << >>  << T >>  << A >>
Hello All,

In timing simulation, I found that LUT4's ouput is going undefined.
Even if its input are valid. I could not find any reason as why LUT's
ouput should go undefined. Since LUT is a combinatorial circuit its
output should never go undefined, until and unless one of the input
itself is undefined which is getting further propogated.

Can anyone pls let me know if they have came across the similar kind
of problem and if yes then what is the solution for it.

Thanks and Regards,
Viral

Article: 52255
Subject: Re: clock ditribution tree
From: Jeffrey Turner <jturner@localnet.com>
Date: Wed, 05 Feb 2003 07:58:37 -0500
Links: << >>  << T >>  << A >>
Skillwood wrote:
> Hi all,
> what is a clock distribution tree?
> Skillwood

The lines that carry the clock signal
around a chip.

--Jeff


Article: 52256
Subject: Re: clock ditribution tree
From: Sander Vesik <sander@haldjas.folklore.ee>
Date: Wed, 5 Feb 2003 13:22:39 +0000 (UTC)
Links: << >>  << T >>  << A >>
In comp.arch Skillwood <skillwoodNOSPAM@hotmail.com> wrote:
> Hi all,
> what is a clock distribution tree?

A christmas tree with packaged clocks underneath it.

> Skillwood
> 
> 

-- 
	Sander

+++ Out of cheese error +++

Article: 52257
Subject: Re: Distributing component without source
From: <khtsoi@pc90026.cse.cuhk.edu.hk>
Date: 5 Feb 2003 13:27:52 GMT
Links: << >>  << T >>  << A >>
Niels Thomsen <dynamite.no.spam@kanoop.com> wrote:
> I have a design (more accurately, a set of components) that I want to ship
> to a customer as binary only, i.e. without shipping the VHDL source to the
> customer.  I am using Xilinx foundation 2.1i (I know - it's ancient!).
First you should try Xilinx Webpack if your devices are supported
(small E/II as I remember).

> First of all, is this possible with the tools I've got?  I haven't been able
> to find a tutorial out there on what files I need to ship, where to put
> them, and how to instantiate the component set in the project that needs to
> use them.
If you are talking FPGA, all the client need is the bitstream (*.bit) of
your design and the program to download it to the FPGA. The cheapest way
should be using the parallel port if the client have access to a
standard PC. In most case, if the client have the FPGA hardware, the
downloading tools should be also there.

> Any help/advice is much appreciated.

> - Niels



-- 
Tsoi Kuen Hung (Brittle)
CSE CUHK

Article: 52258
Subject: Re: DSP design in fpga - general guidelines please.
From: Ray Andraka <ray@andraka.com>
Date: Wed, 05 Feb 2003 13:51:32 GMT
Links: << >>  << T >>  << A >>
You usually need to adapt the algorithm somewhat for a hardware implementation.
Most of the time full parallel multipliers are a huge overkill.  Instead, you
can play tricks with refactoring (see the distributed arithmetic page on my
website) or use multiple clocks per sample to reduce the hardware size.  A 10K20
is on the smallish size, but you can certainly do a fair amount of DSP with that
part...but not by using full parallel multipliers.

David wrote:

> Hi,
> I'm trying to implement regular dsp blocks (sigma-delta modulator, filters
> etc...) into an fpga and I'm having a hard time choosing the right design
> implementation / devices. For example, lets say you want to build a 3rd
> order sigma-delta modulator using 32 bits registers. There are about 5
> multipliers and three integrators (adder + Dff). Implementing this system in
> vhdl with LPM multipliers simply doesn't fit in the fpga I have access to
> (EPF10k20RC240 - the one on the university board from altera).
>
> I wonder if this is because people simply do not blindly write code
> describing the system exactly as it appears in block diagram or if the fpga
> device I have is simply not used for this kind of work. I know there exist
> better multiplier than the LPM but say I stick with them.
>
> When doing this kind of design, do people usually use one or two multipliers
> with muxes and a state machine to save on hardware? I thought the whole idea
> of using an fpga was to increase speed --> avoid rebuilding some sort of a
> dsp processor.
>
> Thank you very much
>
> David

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 52259
Subject: Nallatech Ballynuey 3
From: Salman Sheikh <sheikh@pop500.gsfc.nasa.gov>
Date: Wed, 05 Feb 2003 09:35:42 -0500
Links: << >>  << T >>  << A >>
Hello,

Has anybody had any success using the Ballynuey 3 card from Nallatech?


Salman


Article: 52260
Subject: Xilinx Foundation 5.1: reasons to upgrade
From: "Alphaboran" <alphaboran@yahoo-no-spam.com>
Date: Wed, 5 Feb 2003 17:27:44 +0200
Links: << >>  << T >>  << A >>
Hello all,

I just received the new version of the Xilinx Foundation tool. I now use the
4.1 sp3 for my implementations, in the synthesis phase I use FPGA Express
3.6.1. My target devices are Virtex-EM.

Are there any good reasons to upgrade my system? Does the new tool offer
something really new and useful?

I heard that with the new version you can keep the place AND routing of an
implemented design and use it on later on altered design. If that's true it
seems very nice because with the 4.1 version even I make minor changes the
only thing I can do is to keep the placement and not the routing. Is this
the case or a rumor?

Thanks in advance for your help.

Best Regards,
Harris




Article: 52261
Subject: Re: Writing and Reading into RC100 Flash RAM
From: "Sameer D. Sahasrabuddhe" <NO-EMAIL-FOLLOWUP-sameerds@it.iitb.ac.in>
Date: 5 Feb 2003 15:40:36 GMT
Links: << >>  << T >>  << A >>
On Thu, 30 Jan 2003 at 06:45 GMT, Poolar Bear wrote:

> I tried using the Flash RAM, but so far I am unable to write into the
> Flash RAM and also upload the readings from the Flash RAM to my PC. I
> have tried the example given in the RC100 Function Library Manual. But
> I don't get the desired readings as well.

I assume you are talking about the board provided by Celoxica / Embedded
Solutions ... accessing the Flash RAM is fairly easy with the file
transfer utitity (FTU) they provide.

What exactly goes wrong?

Try writing a small program that reads a byte from the Flash RAM and
displays it on the LED's, or on the seven segment display.

Sameer.
-- 
As flies to wanton boys are we to the gods; they kill us for their sport.
		-- Shakespeare, "King Lear"

Article: 52262
(removed)


Article: 52263
Subject: Help needed
From: "Florin Franovici" <ffranovici@redlinecommunications.com>
Date: Wed, 5 Feb 2003 11:29:51 -0500
Links: << >>  << T >>  << A >>
Hello all,

Does enyone knows some good resources on-line about binary representation
and arithmetic algorithms suitable for hardware implemetation?

Thanks



Article: 52264
Subject: Re: Help needed
From: "John_H" <johnhandwork@mail.com>
Date: Wed, 05 Feb 2003 16:44:52 GMT
Links: << >>  << T >>  << A >>
Arithmetic algorithms for... balancing ones checkbook?  For determining
optimum firing thrust to have a satellite achieve martian orbit?

You'll have to be a little more precise about your needs.


"Florin Franovici" <ffranovici@redlinecommunications.com> wrote in message
news:b1re56$16gpvd$1@ID-95060.news.dfncis.de...
> Hello all,
>
> Does enyone knows some good resources on-line about binary representation
> and arithmetic algorithms suitable for hardware implemetation?
>
> Thanks



Article: 52265
Subject: Re: Xilinx ISE optimization
From: "John_H" <johnhandwork@mail.com>
Date: Wed, 05 Feb 2003 16:48:01 GMT
Links: << >>  << T >>  << A >>
What's it gonna be?
If the logic *is* really used, it won't get optimized out.

<khtsoi@pc90026.cse.cuhk.edu.hk> wrote in message
news:b1qlso$77u$1@eng-ser1.erg.cuhk.edu.hk...
> Hal Murray <murray@suespammers.org> wrote:

First item:
> >>I have a design that part of it will be optimized away by MAP tools
> >>as loadless.

Second item:
> They are actually loaded



Article: 52266
Subject: Re: Clock Enables
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Wed, 05 Feb 2003 11:53:50 -0500
Links: << >>  << T >>  << A >>
Peter,
    You forgot those who sleep through class, either at home or in the
classroom, as well as those who do not speak the same language as the
instructor.  This is intended to reference both students and instructors who (in
the case of the USA) are non-native speakers of English.  This is not intendend
as a slam to those who do adequately learn the language of the country where the
instruction is being given.  It is merely a comment on the sad state of affairs
where instructors and/or students need not and do not learn the language
sufficiently to be able to communicate technical concepts.  In fact, in some
cases, the instructor cannot communicate technical data because they themselves
are technically incompetent.  However, I suspect that the problem you are
discussing here is one of laziness.  Unfortunately, these people will graduate
and be hired by unsuspecting companies.  Due to a fear of lawsuits, these same
people will be passed along to unsuspecting employer after unsuspecting
employer.

Enough of the rant...

Thanks,
Theron Hicks

Peter Alfke wrote:

> Is this newsgroup deteriorating into a remedial help service for students
> who did not pay attention in class, or cannot read a text book or data
> sheet?
>
> CE controls a mux that makes the D input either look at the Q output ( clock
> disabled) or look at the incoming signal ( clock enabled). CE is, therefore,
> a synchronous signal.
>
> Peter Alfke
> ==========================
> Vishker wrote:
>
> > Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ???
> > Pl. justify the answers.
> >
> > Thanks
> >
> > Vs


Article: 52267
Subject: Re: Help needed
From: "Florin Franovici" <ffranovici@redlinecommunications.com>
Date: Wed, 5 Feb 2003 11:54:55 -0500
Links: << >>  << T >>  << A >>
Basic arithmetic operations like: multiplication, adition, etc. Please don't
point me to printed textbooks becase I can't afford to buy any of these.




"John_H" <johnhandwork@mail.com> wrote in message
news:8cb0a.24$KH.3701@news-west.eli.net...
> Arithmetic algorithms for... balancing ones checkbook?  For determining
> optimum firing thrust to have a satellite achieve martian orbit?
>
> You'll have to be a little more precise about your needs.
>
>
> "Florin Franovici" <ffranovici@redlinecommunications.com> wrote in message
> news:b1re56$16gpvd$1@ID-95060.news.dfncis.de...
> > Hello all,
> >
> > Does enyone knows some good resources on-line about binary
representation
> > and arithmetic algorithms suitable for hardware implemetation?
> >
> > Thanks
>
>



Article: 52268
Subject: Re: Help needed
From: Buddy Smith <nullset@dookie.net>
Date: Wed, 5 Feb 2003 17:17:47 +0000 (UTC)
Links: << >>  << T >>  << A >>
Florin Franovici <ffranovici@redlinecommunications.com> wrote:
> Basic arithmetic operations like: multiplication, adition, etc. Please don't
> point me to printed textbooks becase I can't afford to buy any of these.
> 

Where I am from, we have these magical places called 'libraries'.  Do they 
not exist in your area?

--buddy

Article: 52269
Subject: A forum for SystemC
From: bigg_badd_wolf_x@yahoo.com (Ravi Bhormish)
Date: 5 Feb 2003 10:26:04 -0800
Links: << >>  << T >>  << A >>
HellO all,
 
   A new group called "systemc-hq" has been created on yahoogroups.
This group has been created with SystemC beginers/newbies in mind,
whose questions are a little too basic for the official SystemC
mailing list. So here's a hearty welcome to all interested.
   You can visit http://groups.yahoo.com/group/systemc-hq to join or
send an email to systemc-hq-subscribe@yahoogroups.com.
 
 Thanks and Regards,
   Ravi Bhormish

Article: 52270
Subject: Re: PCI protocol - assigning an address to my device
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Wed, 5 Feb 2003 14:15:23 -0500
Links: << >>  << T >>  << A >>
Hi Kevin,

You're right, but my assumption was that the poster really wanted memory
space (as I believe I said), not I/O space...so I believe he meant to set
memory and 64 bit addressing, and I wondered why.

Austin


"Kevin Brace" <kev0inbr1aceusen2et@ho3tma4il.c5om> wrote in message
news:b1pa0m$7d2$1@newsreader.mailgate.org...
> Austin,
>
> To make a correction of what you said, if bit 0 of a BAR is 1, that will
> indicate that BAR is for IO space, and if so, bit 2 and 1 will not
> indicate 64 bit addressing.
> For IO space, bit 2 can only be a register or hardwired to 0, and bit 1
> is currently reserved (Has to be hardwired to 0.).
>
>
> Kevin Brace (If someone wants to respond to what I wrote, I prefer if
> you will do so within the newsgroup.)
>
>
>
> Austin Franklin wrote:
> >
> >
> > You get a 4k space starting at 0x0200_0xxx.  BUT, why are you setting
bit 0
> > to 1 for?  You are asking for 4k of I/O space...and you probably really
want
> > memory space.  Why are you setting bit 2?  Setting bit 2 and 1 to 10b
asks
> > the system to locate you in 64 bit address space...
> >



Article: 52271
Subject: Re: clock ditribution tree
From: "Tauno Voipio" <tauno.voipio@iki.fi.SPAMBAIT_REMOVE.invalid>
Date: Wed, 05 Feb 2003 19:21:51 GMT
Links: << >>  << T >>  << A >>

"Skillwood" <skillwoodNOSPAM@hotmail.com> wrote in message
news:b1qqmt$15umdr$1@ID-159866.news.dfncis.de...
> Hi all,
> what is a clock distribution tree?
> Skillwood
>

Homework?

Tauno Voipio
tauno voipio @ iki fi



Article: 52272
Subject: Re: Clock Enables
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Wed, 05 Feb 2003 19:30:58 GMT
Links: << >>  << T >>  << A >>
On 4 Feb 2003 15:50:15 -0800, vishker@yahoo.com (Vishker) wrote:

>Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ??? 
>Pl. justify the answers.
>
>Thanks
>
>Vs

Why stop at asking for help with homework problems?  I can imagine the
series of posts we'll see in years to come.

Post to comp.arch.fpga, December  3, 2006
-----
Can you think of a good algorithm for improving the quality of logic
placement in an FPGA?  Please supply the answer in dissertation
format, and don't skimp on the references.

Post to comp.arch.fpga, April 7, 2008
------
Suppose you were a newly-minted PhD who was hired to develop a
revolutionary FPGA architecture.  What would that architecture be?
And don't just wave your arms; I'd like to see a spec.  With lots and
lots of pictures.

Post to sci.electronics, November 1, 2014
-----
I know that this seems pretty hypothetical, but imagine you were
promoted to head of product development at a big IC company, based on
your success in developing a revolutionary FPGA architecture, some of
which--OK, maybe all of which--you happened to find on Usenet (thanks,
Peter!).  What would you do now?  Specifically, what kinds of new
devices would you develop?  And do you happen to have detailed data
sheets for those devices?

Post to alt.help.legal, July 2, 2020
-----
What would you do if you, the CEO of a Fortune 500 company, suddenly
found yourself the subject of an investigation by the US Attorney
General, who claims that every idea your company profited from was
stolen?  (Personally, I prefer the term "redeployed" to "stolen," but
the Attorney General refuses to budge on this.  Whoever thought that
Jenna Bush would be such a stickler for the law?)  Is this a
leave-the-country kind of thing, or do you think a person could get
the kind of deal that those Enron guys got?  Just wondering.

Bob Perlman
Cambrian Design Works


  


Article: 52273
Subject: Switching synthesis tools
From: hereisjunk@yahoo.com (Nicholas Girde)
Date: 5 Feb 2003 11:53:16 -0800
Links: << >>  << T >>  << A >>
Hi,

I've been using Synopsys' FPGA Compiler2 for about a year now (and
their FPGA Express that came with Xilinx Foundation before that) I
know lot of people complain that its slower, supports lesser vhdl
cosntructs etc., but its worked fine for me so far. Could you guys let
me know if there is any other reason why I should trying the other
tools out there? (Btw, I work on VIRTEX2 currently and am thinking of
using STRATIX some time soon.)

Any advice, welcome!

- Nick

Article: 52274
Subject: JTAG from CAN
From: Tom <T.Otermans_REMOVE_THIS@home.nl>
Date: Wed, 05 Feb 2003 20:15:32 GMT
Links: << >>  << T >>  << A >>

Hello,

I'm currently working on a project that includes updating a node that has an altera 10K30
(fpga with configuration eeprom) and a TI 2407 dsp onboard (model with bootloader).
The preferred way is to update this node via the to the dsp connected CAN bus (both the fpga and dsp must be updated).

Has anyone any experience with doing updates (new flash data in the dsp and new data in the configuration eeprom) via the CAN bus? if so could you give me some tips on tackling this problem.

I'm thinking of writing a new bootloader that initialises the CAN bus and flashes the dsp and fpga. Currently the dsp and fpga(configuration eeprom) are updated via JTAG. An other option for me is to develop (or buy) some extra hardware that can do a CAN to JTAG conversion.

Hope you can help,

Thanks in advance,

Tom Otermans



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