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Messages from 52325

Article: 52325
Subject: Quartus II 2.2 doesn't run when installed to a newly transferred hard
From: Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om>
Date: Thu, 06 Feb 2003 18:40:09 -0600
Links: << >>  << T >>  << A >>
Hi,

I recently replaced my 5.7GB hard drive with a 60GB hard drive because
the 5.7GB hard drive was getting full.
Rather than reinstalling the recovery CD that came with the computer to
the new 60GB hard drive, I used a disk copying utility (Western Digital
Data Lifeguard is an OEM product of Phoenix Technologies.) to transfer
files from the old hard drive to the new hard drive.
The new hard drive booted Windows 98SE correctly, and other software
(ISE WebPACK, ModelSim XE-Starter, and LeonardoSpectrum-Altera) I used
ran correctly.
However, when I install Quartus II 2.2 Web Edition to this hard drive,
the installer will install the software, but when I try to run Quartus
II 2.2, I will see the Quartus II 2.2 splash screen, but Quartus II
doesn't reach the GUI (Quartus II simply won't go beyond the splash
screen.).
No, this is not a FlexLM issue because even if I didn't have a correct
license for Quartus II 2.2 Web Edition, it will give me a warning after
I reach Quartus II's GUI.
The problem is, I don't even reach Quartus II's GUI . . .
Interestingly, when I install Quartus II 2.2 Web Edition to my older
5.7GB hard drive, the software starts normally (I can reach the GUI.).
        Just as an experiment, I installed Quartus II Web Edition Ver.
1.1 and 2.0 to the 60GB hard drive, and they worked perfectly fine (I
had to use an older license of Quartus II Web Edition, and I had to move
the clock back a few months.).
However, when Quartus II Web Edition 2.1SP1 was installed, I had the
exact same problem I had with 2.2.
Something must have changed something when Quartus II 2.1 was released.
        Trying to analyze what is going on, is Quartus II 2.1 and 2.2
doing something fishy like checking something specific to the hard
drive?
When going from a 5.7GB hard drive to a 60GB hard drive, FAT32 cluster
size did change from 4KB to 32KB if I am correct.
The copying utility I used seems to have copied all the files correctly,
including the dates (directory and file), file attributes, and DOS's 8.3
file names.


Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)

Article: 52326
Subject: Contract Rates?
From: "Gregory C. Read" <readgc.invalid@hotmail.com.invalid>
Date: Fri, 07 Feb 2003 00:42:45 GMT
Links: << >>  << T >>  << A >>
What is the current range of salaries for short term contract work for FPGA
designers?

--
Greg
mailto:readgc.invalid@hotmail.com.invalid
(Remove the '.invalid' twice to send Email)



Article: 52327
Subject: debounce circuit
From: cvmnk@yahoo.com (naveen)
Date: 6 Feb 2003 17:27:39 -0800
Links: << >>  << T >>  << A >>
hi ,
     iam implementing a 32 ALU using vertex 2 fpga. i have to make use
of pushbutton for my clock enable pin of my counter. i have to make
use of 24 MHZ clock. so when i push button, ie give CE to my counter,
counter should increment by only one count, i have to make use of
debounce circuit for my CE input to make my counter to increment by
only one when i push the button.

    can ne one suggest me a debounce circuit i can use.

thanx
 regards
 naveen

Article: 52328
Subject: Re: debounce circuit
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 06 Feb 2003 17:58:42 -0800
Links: << >>  << T >>  << A >>
If you have a single-pole, double-throw switch:
Connect the switch arm to an I/O pin, and the other two terminals to Vcc
and Grd.
Configure the  I/O as an input driving itself as an output. Make the
output rather weak.
Now you have a debouncing latch.
To generate a single pulse, feed the input into a 2-stage shift register,
and decode the one-zero condition of the two flip-flops. That's called a
digital differentiator.
If you still get double pulses, insert a shift register with low clock
rate between the input and the differentiator. But I doubt this would be
necessary.

You can also design a more elaborate debouncer with the switch arm
connected to ground, and the other two terminals driving the set and
reset of a latch, but don't forget the pull-up resistors in that case.

With a single-pole, single-throw switch, the circuit gets more
complicated.

Peter Alfke
==========
naveen wrote:

> hi ,
>      iam implementing a 32 ALU using vertex 2 fpga. i have to make use
> of pushbutton for my clock enable pin of my counter. i have to make
> use of 24 MHZ clock. so when i push button, ie give CE to my counter,
> counter should increment by only one count, i have to make use of
> debounce circuit for my CE input to make my counter to increment by
> only one when i push the button.
>
>     can ne one suggest me a debounce circuit i can use.
>
> thanx
>  regards
>  naveen


Article: 52329
Subject: Re: Clock Enables
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Thu, 06 Feb 2003 21:12:04 -0500
Links: << >>  << T >>  << A >>


Theron Hicks wrote:

> Yves Tchapda wrote:
>
> > Theron Hicks <hicksthe@egr.msu.edu> wrote in message news:<3E41419E.ADE8C2CF@egr.msu.edu>...
> > > Peter,
> > >     You forgot those who sleep through class, either at home or in the
> > > classroom, as well as those who do not speak the same language as the
> > > instructor.  This is intended to reference both students and instructors who (in
> > > the case of the USA) are non-native speakers of English.  This is not intendend
> > > as a slam to those who do adequately learn the language of the country where the
> > > instruction is being given.  It is merely a comment on the sad state of affairs
> > > where instructors and/or students need not and do not learn the language
> > > sufficiently to be able to communicate technical concepts.  In fact, in some
> > > cases, the instructor cannot communicate technical data because they themselves
> > > are technically incompetent.  However, I suspect that the problem you are
> > > discussing here is one of laziness.  Unfortunately, these people will graduate
> > > and be hired by unsuspecting companies.  Due to a fear of lawsuits, these same
> > > people will be passed along to unsuspecting employer after unsuspecting
> > > employer.
> > >
> > > Enough of the rant...
> > >
> > > Thanks,
> > > Theron Hicks
> > >
> >
> > Theron,
> > This is hardly the forum to place your grievance, which goes far
> > beyond what this newsgroup is intended for, and is very unwarranted.
>
> You are right.  It is probably the wrong forum.  It is also the wrong forum for getting homework
> answers.
>
> As for unwaranted, I see you are a PHd.  Are you also a university proffessor?  I am not, but I
> do work in a university setting.  I do see a lot of lazy students who cheat their way through
> tests and homework semester after semester.  I have suffered through incompetent professors.
> While most of my professors speak the language fairly well, I have had to deal with incompetent
> and arrogant professors in classes I have taken recently.

Apology... It has been pointed out that I am (quite unintentionally) implying a link between
inability to "speak the language" and technical incompetence and arrogance.  This was not my
intention, rather my intention was to lump them together in terms that they all have a negative
effect on the quality of engineering education.  I have no doubt that some of the best engineering
minds out there speak some other language than English (my only language).  I would also admit that
_any_ of the non-native speakers who struggle with my language do far better than I do with their
language.  By the way, I can easily overlook a language difficulty if the individual is willing to
try.  Likewise, I will try to overlook arrogance, if the individual has earned the arrogance by
means of extreme competence.  I can even overlook ignorance if it is not coupled with arrogance, but
rather with a willingness to listen and to try learn.  About the only item I mentioned that I have
an absolute problem with is laziness (and especially trying to get someone else to do your work.)

Sorry,
Theron


>  These professors are widely
> recognized as incompetent within the university.   I have also had to deal with students who
> cannot speak the language.  Stories of Professors who do not speak the language are far to
> common.  By the way, I also have had the pleasure of incredibly talented and motivated
> professors and students as co-workers and instructors.  The "bad apples" are fortunately a small
> percentage.
>
> Theron
>
> >
> > Let's concentrate on technical issues, and could we please be humble
> > enough and have patience for those with less knowledge?
> >
> > "I know one thing: I know nothing"
> >
> > Dr Yves Tchapda


Article: 52330
Subject: Re: Clock Enables
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Thu, 06 Feb 2003 21:31:21 -0500
Links: << >>  << T >>  << A >>


Bob Perlman wrote:

> On 4 Feb 2003 15:50:15 -0800, vishker@yahoo.com (Vishker) wrote:
>
> >Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ???
> >Pl. justify the answers.
> >
> >Thanks
> >
> >Vs
>
> Why stop at asking for help with homework problems?  I can imagine the
> series of posts we'll see in years to come.
>
> Post to comp.arch.fpga, December  3, 2006
> -----
> Can you think of a good algorithm for improving the quality of logic
> placement in an FPGA?  Please supply the answer in dissertation
> format, and don't skimp on the references.
>
> Post to comp.arch.fpga, April 7, 2008
> ------
> Suppose you were a newly-minted PhD who was hired to develop a
> revolutionary FPGA architecture.  What would that architecture be?
> And don't just wave your arms; I'd like to see a spec.  With lots and
> lots of pictures.
>
> Post to sci.electronics, November 1, 2014
> -----
> I know that this seems pretty hypothetical, but imagine you were
> promoted to head of product development at a big IC company, based on
> your success in developing a revolutionary FPGA architecture, some of
> which--OK, maybe all of which--you happened to find on Usenet (thanks,
> Peter!).  What would you do now?  Specifically, what kinds of new
> devices would you develop?  And do you happen to have detailed data
> sheets for those devices?
>
> Post to alt.help.legal, July 2, 2020
> -----
> What would you do if you, the CEO of a Fortune 500 company, suddenly
> found yourself the subject of an investigation by the US Attorney
> General, who claims that every idea your company profited from was
> stolen?  (Personally, I prefer the term "redeployed" to "stolen," but
> the Attorney General refuses to budge on this.  Whoever thought that
> Jenna Bush would be such a stickler for the law?)  Is this a
> leave-the-country kind of thing, or do you think a person could get
> the kind of deal that those Enron guys got?  Just wondering.
>
> Bob Perlman
> Cambrian Design Works
>
>

Great!!!



Article: 52331
Subject: USB2 or firewire or 100Mb ethernet link to FPGA design
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Thu, 06 Feb 2003 21:48:40 -0500
Links: << >>  << T >>  << A >>
Hi,
    I am looking at design upgrade of an existing instrumentation
project.  Currently the design talks over a high speed bus to a rather
expensive (~$1600 US) parrallel digital input board.  The data rate
would be on the order of 50M bits per second not including any
overhead.  I do not think I want to go to an all FPGA based solution.
Currently the FPGA in the system is the smallest Spartan2e series
device.  By the way, quantities are very small, on the order of less
than 50 pieces per year.

    So here are my questions...

1.    Does anyone happen to know what the USB2 or firewire is rated for
in terms of the longest cable length?  I had thought USB2 was limited to
about 2 meters but I have seen USB cables about 5 meters long recently.
A longer length interconnect would appear to be desireable.  I know that
ethernet is good for several hundred meters.  That would be far beyond
my needs.

2.    Has anyone had any experience with either USB2 or 100mB or
firewire as an interconnect to an FPGA based design?

3.    Do you happen to have any recommendations as to a possible
off-the-shelf solution (either a small board or a 1 or two chip
solution, ideally something with a demo board available)?

Thanks,
Theron Hicks


Article: 52332
Subject: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 7 Feb 2003 02:51:43 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3E431E87.905ECF6F@egr.msu.edu>,
Theron Hicks (Terry) <hicksthe@egr.msu.edu> wrote:
>2.    Has anyone had any experience with either USB2 or 100mB or
>firewire as an interconnect to an FPGA based design?

The CS150 class at Berkeley uses 100 Mb ethernet to communicate to an
FPGA board as part of the student projects.  They used a simplified
RTP over Ethernet implementation.


-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 52333
Subject: Re: debounce circuit
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Thu, 06 Feb 2003 22:09:38 -0500
Links: << >>  << T >>  << A >>
Naveen,
    I hope this is not homework as I have already goitten myself in enough
trouble with my rants on do your own work.  You can use a counter based
one-shot.  Start a counter running on the first edge and mask any edges
until the counter reaches terminal count.  Typically, bounce time is
usually on the order of a few milliseconds per bounce cycle.  You will
need to verify your switch's bounce period.  I suspect that the bounce
period will vary drastically as the switch ages.  By the way, the switch
should be rated for dry circuit applications (as opposed to high current
applications.)  Check with the switch manufacturer.  Of course you could
look at some of the old fashioned debounce circuits using an RS flipflop
but they all require more than a single pole - single throw switch and use
two inputs to the FPGA.  However, they are almost fool proof.  For details
see the CD4043B data sheet from TI.  (Other manufacturers seem to not have
the application detail in the data sheet for this item.)  I have used both
types of circuits succesfully.    Alternatively, if you can get away with
using a keeper circuit (specific to Xilinx's later devices, I think) you
might get something like that to work.

Theron


naveen wrote:

> hi ,
>      iam implementing a 32 ALU using vertex 2 fpga. i have to make use
> of pushbutton for my clock enable pin of my counter. i have to make
> use of 24 MHZ clock. so when i push button, ie give CE to my counter,
> counter should increment by only one count, i have to make use of
> debounce circuit for my CE input to make my counter to increment by
> only one when i push the button.
>
>     can ne one suggest me a debounce circuit i can use.
>
> thanx
>  regards
>  naveen


Article: 52334
Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Thu, 06 Feb 2003 22:15:56 -0500
Links: << >>  << T >>  << A >>


Kevin Brace wrote:

> Hi,
>
> I recently replaced my 5.7GB hard drive with a 60GB hard drive because
> the 5.7GB hard drive was getting full.
> Rather than reinstalling the recovery CD that came with the computer to
> the new 60GB hard drive, I used a disk copying utility (Western Digital
> Data Lifeguard is an OEM product of Phoenix Technologies.) to transfer
> files from the old hard drive to the new hard drive.
> The new hard drive booted Windows 98SE correctly, and other software
> (ISE WebPACK, ModelSim XE-Starter, and LeonardoSpectrum-Altera) I used
> ran correctly.
> However, when I install Quartus II 2.2 Web Edition to this hard drive,
> the installer will install the software, but when I try to run Quartus
> II 2.2, I will see the Quartus II 2.2 splash screen, but Quartus II
> doesn't reach the GUI (Quartus II simply won't go beyond the splash
> screen.).
> No, this is not a FlexLM issue because even if I didn't have a correct
> license for Quartus II 2.2 Web Edition, it will give me a warning after
> I reach Quartus II's GUI.
> The problem is, I don't even reach Quartus II's GUI . . .
> Interestingly, when I install Quartus II 2.2 Web Edition to my older
> 5.7GB hard drive, the software starts normally (I can reach the GUI.).
>         Just as an experiment, I installed Quartus II Web Edition Ver.
> 1.1 and 2.0 to the 60GB hard drive, and they worked perfectly fine (I
> had to use an older license of Quartus II Web Edition, and I had to move
> the clock back a few months.).
> However, when Quartus II Web Edition 2.1SP1 was installed, I had the
> exact same problem I had with 2.2.
> Something must have changed something when Quartus II 2.1 was released.
>         Trying to analyze what is going on, is Quartus II 2.1 and 2.2
> doing something fishy like checking something specific to the hard
> drive?

Very likely it is checking the serial number on the drive.  If I recall
correctly some of the Xilinx software does that.  If I am wrong about the
Xilinx reference I appologize.  It may have been some other CAE software,
but I am almost certain that some of the CAE software I have does so.  The
license can be either linked to the hard-drive serial number, the ethernet
card address or something similar if I remember.  I guess that they must
never need to change a hard drive or ethernet card at those places.


>
> When going from a 5.7GB hard drive to a 60GB hard drive, FAT32 cluster
> size did change from 4KB to 32KB if I am correct.
> The copying utility I used seems to have copied all the files correctly,
> including the dates (directory and file), file attributes, and DOS's 8.3
> file names.
>
> Kevin Brace (If someone wants to respond to what I wrote, I prefer if
> you will do so within the newsgroup.)


Article: 52335
Subject: Re: clock ditribution tree
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Thu, 06 Feb 2003 22:19:32 -0500
Links: << >>  << T >>  << A >>


MR wrote:

> Interesting theory,  but wrong.

That is the risk you take with homework (or real job) answers from the
newsgroups. Make sure the answer you get is correct.

>
>
> (except for the last clause that begins with "the clock tree often...")
>
> Thomas wrote:
>
> > Tauno Voipio wrote:
> >
> >>> what is a clock distribution tree?
> >>
> >
> >> Homework?
> >
> >
> > It is a network of dividers to make useful frequencies out of the clock.
> > The 1 GHz that some processor runs at must be divided to L2 cache
> > frequency (/2), memory access frequency (often /64 or /128), all the way
> > down to timer tick frequency.
> >
> > Because most of the divisions throw away half the clock frequency (and
> > thus energy) as there is no need for a thousand million different 1 Hz
> > signals, the clock tree often consumes a substantial fraction of the
> > power of a chip.
> >
> >
> > Thomas
> >


Article: 52336
Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
From: "Mahesh M. Bandi" <mab77+@pitt.edu>
Date: Thu, 6 Feb 2003 22:24:48 -0500
Links: << >>  << T >>  << A >>
Both MaxPlus and Quartus II from Altera use the Hard Disk Serial Number
Information to generate the user license for their "web versions". This is
known.

One way out for you would probably be to request a new license for your
web version, by which the new license will be encoded to suit your new
hard disk's serial no.

Thank You,
Best Regards,
Mahesh

On Thu, 6 Feb 2003, Theron Hicks (Terry) wrote:

> Date: Thu, 06 Feb 2003 22:15:56 -0500
> From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
> Newsgroups: comp.arch.fpga
> Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred  hard drive
> 
> 
> 
> Kevin Brace wrote:
> 
> > Hi,
> >
> > I recently replaced my 5.7GB hard drive with a 60GB hard drive because
> > the 5.7GB hard drive was getting full.
> > Rather than reinstalling the recovery CD that came with the computer to
> > the new 60GB hard drive, I used a disk copying utility (Western Digital
> > Data Lifeguard is an OEM product of Phoenix Technologies.) to transfer
> > files from the old hard drive to the new hard drive.
> > The new hard drive booted Windows 98SE correctly, and other software
> > (ISE WebPACK, ModelSim XE-Starter, and LeonardoSpectrum-Altera) I used
> > ran correctly.
> > However, when I install Quartus II 2.2 Web Edition to this hard drive,
> > the installer will install the software, but when I try to run Quartus
> > II 2.2, I will see the Quartus II 2.2 splash screen, but Quartus II
> > doesn't reach the GUI (Quartus II simply won't go beyond the splash
> > screen.).
> > No, this is not a FlexLM issue because even if I didn't have a correct
> > license for Quartus II 2.2 Web Edition, it will give me a warning after
> > I reach Quartus II's GUI.
> > The problem is, I don't even reach Quartus II's GUI . . .
> > Interestingly, when I install Quartus II 2.2 Web Edition to my older
> > 5.7GB hard drive, the software starts normally (I can reach the GUI.).
> >         Just as an experiment, I installed Quartus II Web Edition Ver.
> > 1.1 and 2.0 to the 60GB hard drive, and they worked perfectly fine (I
> > had to use an older license of Quartus II Web Edition, and I had to move
> > the clock back a few months.).
> > However, when Quartus II Web Edition 2.1SP1 was installed, I had the
> > exact same problem I had with 2.2.
> > Something must have changed something when Quartus II 2.1 was released.
> >         Trying to analyze what is going on, is Quartus II 2.1 and 2.2
> > doing something fishy like checking something specific to the hard
> > drive?
> 
> Very likely it is checking the serial number on the drive.  If I recall
> correctly some of the Xilinx software does that.  If I am wrong about the
> Xilinx reference I appologize.  It may have been some other CAE software,
> but I am almost certain that some of the CAE software I have does so.  The
> license can be either linked to the hard-drive serial number, the ethernet
> card address or something similar if I remember.  I guess that they must
> never need to change a hard drive or ethernet card at those places.
> 
> 
> >
> > When going from a 5.7GB hard drive to a 60GB hard drive, FAT32 cluster
> > size did change from 4KB to 32KB if I am correct.
> > The copying utility I used seems to have copied all the files correctly,
> > including the dates (directory and file), file attributes, and DOS's 8.3
> > file names.
> >
> > Kevin Brace (If someone wants to respond to what I wrote, I prefer if
> > you will do so within the newsgroup.)
> 
> 
> 


Article: 52337
Subject: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Thu, 06 Feb 2003 22:25:33 -0500
Links: << >>  << T >>  << A >>


"Nicholas C. Weaver" wrote:

> In article <3E431E87.905ECF6F@egr.msu.edu>,
> Theron Hicks (Terry) <hicksthe@egr.msu.edu> wrote:
> >2.    Has anyone had any experience with either USB2 or 100mB or
> >firewire as an interconnect to an FPGA based design?
>
> The CS150 class at Berkeley uses 100 Mb ethernet to communicate to an
> FPGA board as part of the student projects.  They used a simplified
> RTP over Ethernet implementation.
>
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Nicholas,
    Thanks, do you have any info or a link to someinfo on exactly what they
used, etc?  This sounds as if it might be exactly like what I want.  By the
way, this is not homework.  I would just rather not re-invent the wheel.

Theron Hicks


Article: 52338
Subject: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 7 Feb 2003 03:28:21 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3E43272D.DEBA1B69@egr.msu.edu>,
Theron Hicks (Terry) <hicksthe@egr.msu.edu> wrote:
>Nicholas,
>    Thanks, do you have any info or a link to someinfo on exactly what they
>used, etc?  This sounds as if it might be exactly like what I want.  By the
>way, this is not homework.  I would just rather not re-invent the wheel.

Class page at
http://www-inst.eecs.berkeley.edu/~cs150/

I'm not sure if the Fall 2002 page is online still.



-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 52339
Subject: Re: Clock Enables
From: jabayja@yahoo.com (Jay)
Date: 6 Feb 2003 19:33:15 -0800
Links: << >>  << T >>  << A >>
Wow its becoming intresting. 

Well How about the following circuit ? I hope my format wont get
screwed up.
If you can find a flop with zero c2o or match it with the delay of CLK
signal to tri-buf (very easy I guess), then I think we can produce
TRUE CLOCK ENABLE circuit (may be) :-) and we can say CE is
Synchronous.

			_________
		    	|	|			
		CE -----|	|-------
			|	|	|
	CLK ____________|       |	|
		  |	---------	|
		  |		      |\|	
		  |		      |	\
		  |___________________|	 \______
				      |	 /	|
				      |	/	|
				      |/	|
						|	_________
						|  D ---|	|								|	|	|----- Q
						------- |	|
							|	|	
							---------


- Jay

Ray Andraka <ray@andraka.com> wrote in message news:<3E42C36A.3375B035@andraka.com>...
> Not entirely true.  The synchronous set/reset in Virtex is not affected by the
> clock enable, yet it happens as a result of the clock edge.  I know...I am
> splitting hairs now.  For an edge triggered flip-flop, which is how they are
> generally used in FPGAs, 'clock' infers 'clockedge'
> 
> John_H wrote:
> 
> > How about if we call it Clockedge Enable?
> >
> > The register changes at the clock edge, not the clock level.
> >
> > The CE suppresses the behavior independent of whether a multiplexer is used
> > in the data path or if the master/slave flip-flop has presistent clock
> > gating that will make the clock-enable gate out the entire latch enable
> > window on the input latch of the master slave pair.
> >
> > If the signal is deasserted, the clock edge will have no effect on the
> > register.
> >
> > It has everything to do with the clock.
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com

Article: 52340
Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred
From: Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om>
Date: Thu, 06 Feb 2003 22:44:23 -0600
Links: << >>  << T >>  << A >>
Mahesh,

I downloaded a software called volumeid.exe to restore the original
volume serial number.
It didn't help.
If you go to Altera's licensing page, they will let you license MAX+PLUS
II-BASELINE, but an ethernet card is required for Quartus II Web
Edition.
 

Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)



"Mahesh M. Bandi" wrote:
> 
> Both MaxPlus and Quartus II from Altera use the Hard Disk Serial Number
> Information to generate the user license for their "web versions". This is
> known.
> 
> One way out for you would probably be to request a new license for your
> web version, by which the new license will be encoded to suit your new
> hard disk's serial no.
> 
> Thank You,
> Best Regards,
> Mahesh
>

Article: 52341
Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred
From: Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om>
Date: Thu, 06 Feb 2003 22:57:28 -0600
Links: << >>  << T >>  << A >>
Terry,

I used the exact same hardware except the hard drive.
I used a program called volumeid.exe to restore the original volume
serial number.
But it didn't help.
The thing about Quartus II is that, it can reach to the GUI without a
valid license, but, of course, Quartus II will let you know that you
won't be able to run the software.
In my case, the software doesn't even reach that point (Stops loading
the software after the Quartus II splash screen.).


Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)


"Theron Hicks (Terry)" wrote:
> 
> 
> Very likely it is checking the serial number on the drive.  If I recall
> correctly some of the Xilinx software does that.  If I am wrong about the
> Xilinx reference I appologize.  It may have been some other CAE software,
> but I am almost certain that some of the CAE software I have does so.  The
> license can be either linked to the hard-drive serial number, the ethernet
> card address or something similar if I remember.  I guess that they must
> never need to change a hard drive or ethernet card at those places.
>

Article: 52342
(removed)


Article: 52343
Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
From: "Mahesh M. Bandi" <mab77+@pitt.edu>
Date: Fri, 7 Feb 2003 00:01:28 -0500
Links: << >>  << T >>  << A >>
Kevin,

You confirm my fears, because I have downloaded Quartus II licenses at
school via network, but MaxPlus license at home via dial-up connection.

But even so, you suggest this is not a licensing problem. In that case I
do not know what to suggest, the question to be answered I suppose is,
what different dependencies can this software have with underlying
hardware in order to achieve functionality, that too without taking into
account licensing constraints.

Thank You,
Best Regards,
Mahesh

On Thu, 6 Feb 2003, Kevin Brace wrote:

> Date: Thu, 06 Feb 2003 22:44:23 -0600
> From: Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om>
> Newsgroups: comp.arch.fpga
> Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred   hard drive
> 
> Mahesh,
> 
> I downloaded a software called volumeid.exe to restore the original
> volume serial number.
> It didn't help.
> If you go to Altera's licensing page, they will let you license MAX+PLUS
> II-BASELINE, but an ethernet card is required for Quartus II Web
> Edition.
>  
> 
> Kevin Brace (If someone wants to respond to what I wrote, I prefer if
> you will do so within the newsgroup.)
> 
> 
> 
> "Mahesh M. Bandi" wrote:
> > 
> > Both MaxPlus and Quartus II from Altera use the Hard Disk Serial Number
> > Information to generate the user license for their "web versions". This is
> > known.
> > 
> > One way out for you would probably be to request a new license for your
> > web version, by which the new license will be encoded to suit your new
> > hard disk's serial no.
> > 
> > Thank You,
> > Best Regards,
> > Mahesh
> >
> 
> 


Article: 52344
Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
From: "Mahesh M. Bandi" <mab77+@pitt.edu>
Date: Fri, 7 Feb 2003 00:02:16 -0500
Links: << >>  << T >>  << A >>


Thank You,
Best Regards,
Mahesh

On Thu, 6 Feb 2003, Kevin Brace wrote:

> Date: Thu, 06 Feb 2003 22:44:23 -0600
> From: Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om>
> Newsgroups: comp.arch.fpga
> Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred   hard drive
> 
> Mahesh,
> 
> I downloaded a software called volumeid.exe to restore the original
> volume serial number.
> It didn't help.
> If you go to Altera's licensing page, they will let you license MAX+PLUS
> II-BASELINE, but an ethernet card is required for Quartus II Web
> Edition.
>  
> 
> Kevin Brace (If someone wants to respond to what I wrote, I prefer if
> you will do so within the newsgroup.)
> 
> 
> 
> "Mahesh M. Bandi" wrote:
> > 
> > Both MaxPlus and Quartus II from Altera use the Hard Disk Serial Number
> > Information to generate the user license for their "web versions". This is
> > known.
> > 
> > One way out for you would probably be to request a new license for your
> > web version, by which the new license will be encoded to suit your new
> > hard disk's serial no.
> > 
> > Thank You,
> > Best Regards,
> > Mahesh
> >
> 
> 


Article: 52345
Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
From: "Mahesh M. Bandi" <mab77+@pitt.edu>
Date: Fri, 7 Feb 2003 00:10:58 -0500
Links: << >>  << T >>  << A >>
Sorry about the previous blank mail. For some reason the mail refuses to
go out on Kevin's address.

Kevin,

You confirm my fears, because I have downloaded Quartus II licenses at
school via network, but MaxPlus license at home via dial-up connection.

But even so, you suggest this is not a licensing problem. In that case I
do not know what to suggest, the question to be answered I suppose is,
what different dependencies can this software have with underlying
hardware in order to achieve functionality, that too without taking into
account licensing constraints.

Thank You,
Best Regards,
Mahesh

On Fri, 7 Feb 2003, Mahesh M. Bandi wrote:

> Date: Fri, 7 Feb 2003 00:00:26 -0500
> From: "Mahesh M. Bandi" <mab77+@pitt.edu>
> To: Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om>
> Newsgroups: comp.arch.fpga
> Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred   hard drive
> 
> Kevin,
> 
> You confirm my fears, because I have downloaded Quartus II licenses at
> school via network, but MaxPlus license at home via dial-up connection.
> 
> But even so, you suggest this is not a licensing problem. In that case I
> do not know what to suggest, the question to be answered I suppose is,
> what different dependencies can this software have with underlying
> hardware in order to achieve functionality, that too without taking into
> account licensing constraints.
> 
> Thank You,
> Best Regards,
> Mahesh
> 
> On Thu, 6 Feb 2003, Kevin Brace wrote:
> 
> > Date: Thu, 06 Feb 2003 22:44:23 -0600
> > From: Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om>
> > Newsgroups: comp.arch.fpga
> > Subject: Re: Quartus II 2.2 doesn't run when installed to a newly transferred   hard drive
> > 
> > Mahesh,
> > 
> > I downloaded a software called volumeid.exe to restore the original
> > volume serial number.
> > It didn't help.
> > If you go to Altera's licensing page, they will let you license MAX+PLUS
> > II-BASELINE, but an ethernet card is required for Quartus II Web
> > Edition.
> >  
> > 
> > Kevin Brace (If someone wants to respond to what I wrote, I prefer if
> > you will do so within the newsgroup.)
> > 
> > 
> > 
> > "Mahesh M. Bandi" wrote:
> > > 
> > > Both MaxPlus and Quartus II from Altera use the Hard Disk Serial Number
> > > Information to generate the user license for their "web versions". This is
> > > known.
> > > 
> > > One way out for you would probably be to request a new license for your
> > > web version, by which the new license will be encoded to suit your new
> > > hard disk's serial no.
> > > 
> > > Thank You,
> > > Best Regards,
> > > Mahesh
> > >
> > 
> > 
> 
> 
> 


Article: 52346
Subject: Re: Contract Rates?
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Fri, 7 Feb 2003 00:50:24 -0500
Links: << >>  << T >>  << A >>

"Gregory C. Read" <readgc.invalid@hotmail.com.invalid> wrote in message
news:9iD0a.5636$5g7.336@nwrddc02.gnilink.net...
> What is the current range of salaries for short term contract work for
FPGA
> designers?

Er, well, that all depends on the level of experience, what the job entails,
skill of the individual, and what the terms of the contract are...as in do
you supply equipment, or does the client?

Anywhere from $25/hour to $250/hour.  Give me more info, and I'll give you a
better answer ;-)

Austin



Article: 52347
Subject: Re: debounce circuit
From: "Bill Turnip" <BTurnip@acm.org>
Date: Fri, 07 Feb 2003 05:54:24 GMT
Links: << >>  << T >>  << A >>
Naveen -

    If you have the Xilinx tools, under the "Synthesis Templates" you'll
find the VHDL and Verilog code for a Debounce circuit.
At least in WebPACK they're there...

Bill


"naveen" <cvmnk@yahoo.com> wrote in message
news:b7f5eb6a.0302061727.11783405@posting.google.com...
> hi ,
>      iam implementing a 32 ALU using vertex 2 fpga. i have to make use
> of pushbutton for my clock enable pin of my counter. i have to make
> use of 24 MHZ clock. so when i push button, ie give CE to my counter,
> counter should increment by only one count, i have to make use of
> debounce circuit for my CE input to make my counter to increment by
> only one when i push the button.
>
>     can ne one suggest me a debounce circuit i can use.
>
> thanx
>  regards
>  naveen



Article: 52348
Subject: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
From: "Nobody" <nobody@nowhere.com>
Date: Fri, 07 Feb 2003 06:50:10 GMT
Links: << >>  << T >>  << A >>
Terry,

Check out our QuickUSB module and kits.  It is designed to do exactly what
you're looking for.

Thanks,
Blake

"Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote in message
news:3E431E87.905ECF6F@egr.msu.edu...
> Hi,
>     I am looking at design upgrade of an existing instrumentation
> project.  Currently the design talks over a high speed bus to a rather
> expensive (~$1600 US) parrallel digital input board.  The data rate
> would be on the order of 50M bits per second not including any
> overhead.  I do not think I want to go to an all FPGA based solution.
> Currently the FPGA in the system is the smallest Spartan2e series
> device.  By the way, quantities are very small, on the order of less
> than 50 pieces per year.
>
>     So here are my questions...
>
> 1.    Does anyone happen to know what the USB2 or firewire is rated for
> in terms of the longest cable length?  I had thought USB2 was limited to
> about 2 meters but I have seen USB cables about 5 meters long recently.
> A longer length interconnect would appear to be desireable.  I know that
> ethernet is good for several hundred meters.  That would be far beyond
> my needs.
>
> 2.    Has anyone had any experience with either USB2 or 100mB or
> firewire as an interconnect to an FPGA based design?
>
> 3.    Do you happen to have any recommendations as to a possible
> off-the-shelf solution (either a small board or a 1 or two chip
> solution, ideally something with a demo board available)?
>
> Thanks,
> Theron Hicks
>



Article: 52349
Subject: Re: Interfacing to a PC using EPP parallel port
From: "Blake" <nobody@nowhere.com>
Date: Fri, 07 Feb 2003 06:55:10 GMT
Links: << >>  << T >>  << A >>
Bob,

I would suggest that you consider using USB 2.0 rather than an EPP parallel
port.  The quickest way to do that is to use our QuickUSB module.  Its a
plug-in board that takes all the headac
"Ernest Jamro" <jamro@agh.edu.pl> wrote in message
news:3E39483A.3090702@agh.edu.pl...
> I have done a similar project and it does not work on
> every computer.
>
> 1. EPP signals are often not TTL compatible on some computers in EPP mode,
> 2. PCs motherboard chip set (or PP cable) does not work correctly on
> some PCs (e.g. when the transferred data change from 0x00 to 0xFF
> the EPP data_stobeN goes high even when waitN signal is still low)
> 3. some PC does not support EPP mode at all.
> 4. Transfer depends strongly on a PC you've got.
>
> You need not bother about the DMA - use a standard memory transfer
> unless your PC must do some other critical calculation.
>
> Good luck anyway
>
> Ernest Jamro
>
> Bob Fischer wrote:
> > I will be testing an FPGA design that is intended to drive a PC for
> > initial checkout and later to an embedded computer using parallel
> > port.  I selected the EPP protocol as it looks like it can support
> > what I need to do.
> >
> > The FPGA will output 10 bytes of data to the PC each cycle of
> > operation.  The data consists of five 14 bit values output in two
> > bytes each.  The FPGA will be performing about 40,000 cycles per
> > second.  Think of each cycle as a 25 us frame.  Data collection (about
> > 4 us), processing (about 7-8 us) occurs for the first 11-12 us of each
> > frame.  When the data is ready the parallel port Interrupt line is
> > asserted.
> >
> > The burst rate during the available 13 us data output portion is
> > around 770 Khz.  The times have already been verified in the
> > simulations.  For the simulation I used an 800 ns byte cycle.  The
> > testbench emulates the PC by responding to the Interrupt, invoking the
> > byte cycle timing as expected from the PC by cycling the Data Strobe
> > line (400 ns low then 400 ns high for each byte).  The FPGA responds
> > with Waits and presentation of data bytes at the time defined for the
> > EPP port.  I used the timing found in web site
> > www.beyondlogic.org/epp/epp.htm
> >
> > The output of the FPGA is configured for TTL levels, slow transitions.
> >  I intend to pipe the FPGA directly to the DB connector and through a
> > 3 ft parallel cable to the PC parallel port.
> >
> > In the PC we will DMA the data to memory and accumulate it for several
> > seconds.  A display program will access that memory and generate
> > graphs, etc for visual analysis of the performance and results.
> >
> > Does this approach to PC interfaceing sound feasible?  Has anyone out
> > there any prior experience they would like to share?  Some Do's and
> > Don'ts?
> >
> > Bob Fischer
> > FPGA independent designer
>





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