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Messages from 53200

Article: 53200
Subject: Re: filter coefficients from sig. proc. toolbox to xilinx
From: Paul Costa <pc@mathworks.com>
Date: Thu, 06 Mar 2003 08:41:30 -0500
Links: << >>  << T >>  << A >>
Hi,

The R13 version of the Filter Design Toolbox shipped with a function, 
coewrite, which writes a XILINX CORE Generator coefficient (.coe) file
from a quantized direct-form FIR filter (QFILT object). Here's the help:

COEWRITE(Hq) writes a XILINX Distributed Arithmetic FIR filter 
coefficient .COE file which can be loaded into the XILINX CORE 
Generator.  The coefficients are extracted from the quantized filter 
object, Hq. A dialog box is displayed to fill in a file name. The 
default file name is 'untitled.coe'.

COEWRITE(Hq,RADIX) indicates the radix (number base) being used to 
specify the FIR filter coefficients.  Valid RADIX values are 2, 10, and 
16 (default).

COEWRITE(...,FILENAME) writes a XILINX .COE file to a disk file
called FILENAME. The extension '.coe' will be added to FILENAME if it 
doesn't already have an extension.

EXAMPLE:
b = firceqrip(30,0.4,[0.05 0.03]);
Hq = qfilt('fir',{b});
coewrite(Hq,10,'mycoefile');


HTH,

Paul Costa


RM wrote:
> I am attempting to use the Matlab signal processing toolbox
> to generate filter coefficients to use as inputs to Xilinx
> core generator filter tool.
> 
> As far as I can see, the numerical coefficients from Matlab
> are always normalized -1 < c < 1. There does not seem to be
> any sort of a switch on this. Xilinx appears to accept only
> whole numbers, decimal or hex.
> 
> Anyone know of a way to make these two talk to each other
> that does not involve me writing a conversion routine?


Article: 53201
Subject: Week Keepers and Pull ups
From: Anup Kumar Raghavan <anup@csee.uq.edu.au>
Date: Fri, 07 Mar 2003 00:54:40 +1030
Links: << >>  << T >>  << A >>


Hello, I am using tri-state muxes in my design (device - Virtex II) and
I want to use Bus-keeper circuits. I instantiated the Keeper component
in my design and assigned the keeper ckt to the output of the tri-state
mux signals. This design was synthesised without any warnings, but when
I took it to the Implementation, using Xillinx ISE 5.1i, I got an error
reporting that both Pull ups and Week keeper circuits are trying to be
inferred for these tri-state signals. I am not sure how to disable the
Pull up Cktry.
Can anyone pass me their suggestions?

Thanks heaps

Anup




Article: 53202
Subject: implementing unfinished designs
From: "Andreas Purde" <purde@ei.tum.de>
Date: Thu, 6 Mar 2003 15:47:58 +0100
Links: << >>  << T >>  << A >>
Hi,

I have a problem with unfinished designs:

    * Synplifly bounds the unused signals to zero
    * map fails due to loadless signals
    * changing map option  "Trim unconnected signals"  to off will make map
work
    * P&R generates warnings about signals with no driver
    * Generate Programming File fails due to nets with no source

My questions: how can I suceessfully implement an unfinished design?

Thank you very much.

Andi



Software used: Synplify, Xilinx ISE 5.1




Article: 53203
Subject: Re: implementing unfinished designs
From: "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com>
Date: Thu, 6 Mar 2003 15:02:11 -0000
Links: << >>  << T >>  << A >>
"Andreas Purde" <purde@ei.tum.de> wrote

> I have a problem with unfinished designs:

[unconnected signals are optimised away, or confuse the
P&R software]

Temporarily, bring out all the unused signals through
top-level ports so that they get connected to I/O pads.

> My questions: how can I suceessfully implement an unfinished design?

I guess you could finish it  ;-)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Article: 53204
Subject: Re: filter coefficients from sig. proc. toolbox to xilinx
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Mar 2003 15:08:42 GMT
Links: << >>  << T >>  << A >>
And if you chose not to spend the $ for the filter design toolbox (about
$1000) then it is simply a matter of multiplying the normalized coefficients
by 2^bits and then rounding:

coef_set= round(coefs * (2^(bits-1));
dlmwrite('coefs.coe',coef_set);



Paul Costa wrote:

> Hi,
>
> The R13 version of the Filter Design Toolbox shipped with a function,
> coewrite, which writes a XILINX CORE Generator coefficient (.coe) file
> from a quantized direct-form FIR filter (QFILT object). Here's the help:
>
> COEWRITE(Hq) writes a XILINX Distributed Arithmetic FIR filter
> coefficient .COE file which can be loaded into the XILINX CORE
> Generator.  The coefficients are extracted from the quantized filter
> object, Hq. A dialog box is displayed to fill in a file name. The
> default file name is 'untitled.coe'.
>
> COEWRITE(Hq,RADIX) indicates the radix (number base) being used to
> specify the FIR filter coefficients.  Valid RADIX values are 2, 10, and
> 16 (default).
>
> COEWRITE(...,FILENAME) writes a XILINX .COE file to a disk file
> called FILENAME. The extension '.coe' will be added to FILENAME if it
> doesn't already have an extension.
>
> EXAMPLE:
> b = firceqrip(30,0.4,[0.05 0.03]);
> Hq = qfilt('fir',{b});
> coewrite(Hq,10,'mycoefile');
>
> HTH,
>
> Paul Costa
>
> RM wrote:
> > I am attempting to use the Matlab signal processing toolbox
> > to generate filter coefficients to use as inputs to Xilinx
> > core generator filter tool.
> >
> > As far as I can see, the numerical coefficients from Matlab
> > are always normalized -1 < c < 1. There does not seem to be
> > any sort of a switch on this. Xilinx appears to accept only
> > whole numbers, decimal or hex.
> >
> > Anyone know of a way to make these two talk to each other
> > that does not involve me writing a conversion routine?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53205
Subject: Re: Partial reconfiguration
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Mar 2003 15:33:27 GMT
Links: << >>  << T >>  << A >>
Can't speak for Lattice.  The Atmel parts are configured within a
rectangular window that can be anywhere from one cell to a whole
device.  See the data sheet for the particulars on the bitstream
format.  Everything within the window (logic, routing, memory) is
configured with the new bitstream.  If the new cell and old cell have
the same configuration, it will continue to run even if the clock is
active during and asynchronous to the configuration.  Changing cells
and routing with the clock running does require care to avoid
upsetting parts of the logic you don't want upset and to avoid
contention.  I discuss that somewhat in my paper on dynamic hardware
video processor (available on my website) which used reconfiguration
in an array of NSC CLAY FPGAs (which are for the most part the same
as the Atmel 6K series).  As far as I know, that work represented the
first partial reconfiguration with the process clock not suspended
during configuration.


Sumanth Donthi wrote:

> Hi!
>
>   Can anyone let me how partial reconfiguration achieved in Atmel
> AT40k and lattice ispXPGA FPGAs
>
> regards,
> Sumanth

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53206
Subject: altera quartusII help
From: "sarah shen" <sarahshenca@yahoo.ca>
Date: Thu, 6 Mar 2003 11:26:57 -0500
Links: << >>  << T >>  << A >>
Hi,

I am using altera Quartus II now. When i complied, there is error:

"Internal Error: Sub-system: CDB_ADD, File: ../h\cdb_add_visitor_export.h,
Line: 195
Subprogram not supported
Quartus II Version 2.0 Build 190 01/22/2002 SJ Limited Edition"

I can't open compliation.

I am suspecting there is something wrong with recalling synchroniser
component in one entity.
Could anybody can help me? Thank you very much.

Sarah

My code is below:

library ieee;
use ieee.std_logic_1164.all;

entity TxUnit is
  port (
     Clk    : in  std_logic;  -- Clock signal
     Reset  : in  std_logic;  -- Reset input
     Enable : in  std_logic;  -- Enable input
     LoadA  : in  std_logic;  -- Asynchronous Load
     TxD    : out std_logic;  -- RS-232 data output
     Busy   : out std_logic;  -- Tx Busy
     DataI  : in  std_logic_vector(7 downto 0)); -- Byte to transmit
end TxUnit;

architecture Behaviour of TxUnit is

  component synchroniser
  port (
     C1 : in std_logic;  -- Asynchronous signal
     C :  in std_logic;  -- Clock
     O :  out Std_logic);-- Synchronised signal
  end component;

  signal TBuff    : std_logic_vector(7 downto 0); -- transmit buffer
  signal TReg     : std_logic_vector(7 downto 0); -- transmit register
  signal TBufL    : std_logic;  -- Buffer loaded
  signal LoadS    : std_logic; -- Synchronised load signal

begin
  -- Synchronise Load on Clk
  SyncLoad : Synchroniser port map
  (C1=>LoadA,
   C=> Clk,
   O=> LoadS );  ------------i am suspecting this method.



  -- Tx process
  TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL)
  variable BitPos : INTEGER range 0 to 10; -- Bit position in the frame
  begin
     if Reset = '1' then
        TBufL <= '0';
        BitPos := 0;
        TxD <= '1';
     elsif Rising_Edge(Clk) then
        if LoadS = '1' then
           TBuff <= DataI;
           TBufL <= '1';
        end if;
        if Enable = '1' then
           case BitPos is
              when 0 => -- idle or stop bit
                 TxD <= '1';
                 if TBufL = '1' then -- start transmit. next is start bit
                    TReg <= TBuff;
                    TBufL <= '0';
                    BitPos := 1;
                 end if;
              when 1 => -- Start bit
                 TxD <= '0';
                 BitPos := 2;
              when others =>
                 TxD <= TReg(BitPos-2); -- Serialisation of TReg
                 BitPos := BitPos + 1;
           end case;
           if BitPos = 10 then -- bit8. next is stop bit
              BitPos := 0;
           end if;
        end if;
     end if;
  end process;

Busy <= LoadS or TBufL;

end Behaviour;




Article: 53207
Subject: Re: altera quartusII help
From: "SDL" <S.DeLuca@nospamUSA.NET>
Date: Thu, 06 Mar 2003 16:52:05 GMT
Links: << >>  << T >>  << A >>

I have tried to compile with Quartus 2.2 SP1s and I get the following error:

"Node instance SyncLoad instantiates undefined entity synchroniser"


In relationship to the line:   SyncLoad : Synchroniser port map

Bye
Salvo



"sarah shen" <sarahshenca@yahoo.ca> ha scritto nel messaggio
news:b47ssh$ksu7@mercury.cc.uottawa.ca...
> Hi,
>
> I am using altera Quartus II now. When i complied, there is error:
>
> "Internal Error: Sub-system: CDB_ADD, File: ../h\cdb_add_visitor_export.h,
> Line: 195
> Subprogram not supported
> Quartus II Version 2.0 Build 190 01/22/2002 SJ Limited Edition"
>
> I can't open compliation.
>
> I am suspecting there is something wrong with recalling synchroniser
> component in one entity.
> Could anybody can help me? Thank you very much.
>
> Sarah
>
> My code is below:
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity TxUnit is
>   port (
>      Clk    : in  std_logic;  -- Clock signal
>      Reset  : in  std_logic;  -- Reset input
>      Enable : in  std_logic;  -- Enable input
>      LoadA  : in  std_logic;  -- Asynchronous Load
>      TxD    : out std_logic;  -- RS-232 data output
>      Busy   : out std_logic;  -- Tx Busy
>      DataI  : in  std_logic_vector(7 downto 0)); -- Byte to transmit
> end TxUnit;
>
> architecture Behaviour of TxUnit is
>
>   component synchroniser
>   port (
>      C1 : in std_logic;  -- Asynchronous signal
>      C :  in std_logic;  -- Clock
>      O :  out Std_logic);-- Synchronised signal
>   end component;
>
>   signal TBuff    : std_logic_vector(7 downto 0); -- transmit buffer
>   signal TReg     : std_logic_vector(7 downto 0); -- transmit register
>   signal TBufL    : std_logic;  -- Buffer loaded
>   signal LoadS    : std_logic; -- Synchronised load signal
>
> begin
>   -- Synchronise Load on Clk
>   SyncLoad : Synchroniser port map
>   (C1=>LoadA,
>    C=> Clk,
>    O=> LoadS );  ------------i am suspecting this method.
>
>
>
>   -- Tx process
>   TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL)
>   variable BitPos : INTEGER range 0 to 10; -- Bit position in the frame
>   begin
>      if Reset = '1' then
>         TBufL <= '0';
>         BitPos := 0;
>         TxD <= '1';
>      elsif Rising_Edge(Clk) then
>         if LoadS = '1' then
>            TBuff <= DataI;
>            TBufL <= '1';
>         end if;
>         if Enable = '1' then
>            case BitPos is
>               when 0 => -- idle or stop bit
>                  TxD <= '1';
>                  if TBufL = '1' then -- start transmit. next is start bit
>                     TReg <= TBuff;
>                     TBufL <= '0';
>                     BitPos := 1;
>                  end if;
>               when 1 => -- Start bit
>                  TxD <= '0';
>                  BitPos := 2;
>               when others =>
>                  TxD <= TReg(BitPos-2); -- Serialisation of TReg
>                  BitPos := BitPos + 1;
>            end case;
>            if BitPos = 10 then -- bit8. next is stop bit
>               BitPos := 0;
>            end if;
>         end if;
>      end if;
>   end process;
>
> Busy <= LoadS or TBufL;
>
> end Behaviour;
>
>
>



Article: 53208
Subject: Re: Issues in Outsourcing?
From: paul.lee@sli-institute.ac.uk (Paul)
Date: 6 Mar 2003 09:18:42 -0800
Links: << >>  << T >>  << A >>
anglomont@yahoo.com (TI) wrote in message news:<18a34598.0303041845.33b150a0@posting.google.com>...
> Hello 
> we are an ASIC/FPGA company currently understaffed but with a very
> limited budget; so I wonder under what circumstances and what type of
> projects(non crucial?) we could consider outsourcing to some(which?)
> developing country team?
> Thanks
> MA

Hi MA

I will do the work for you for free. If you are interested, email me
at eziggurat@hotmail.com.

I have one year work experience in VHDL and have some knowledge of
verilog.

Paul

Article: 53209
(removed)


Article: 53210
Subject: Re: Multi cpu Nios processor through SoPC Builder
From: fredrik_he_lang@hotmail.com (Fredrik)
Date: 6 Mar 2003 09:39:34 -0800
Links: << >>  << T >>  << A >>
Hi Arkaitz,
What version of NIOS and SOPC builder are you using, there have been
smaller bugs reported in some versions on diffrent things and also
patchs has been avalible on Alters Nios web site. The latest version
of NIOS is working with Native syntesize and produces very good
results booth for Stratix, APEX20KE (my nios board) and cyclone. So it
might be a good Idea to upgrade to QuartusWeb version 2.2. (Yes the
download is a megabyte nightmare:)
Good luck
Fredrik
arkagaz@yahoo.com (arkaitz) wrote in message news:<c1408b8c.0303040155.59f483ed@posting.google.com>...
> Hi guys,
> 
> I'm trying to configure 2 cpu Nios processor using the SoPC Builder.
> Firstly I tried creating 2 independent system modules but the Quartus
> Leonardo level1 synthetizer caused an error argueing that there were
> some "vhd" files that didn't cohere with one of the system modules
> that I've created. So I tried creating an unique Nios system module
> which have had incorporated the both CPUs. But when I try to
> synthesize with Leonardo Spectrum level 1 it causes a Quartus internal
> error that impedes me doing anything.
> 
> I use a dual port ram to enable the comunication between both CPUs,
> but as you'll image I haven't proved it yet.
> 
> I would be very grateful if someone could help me.
> 
> Arkaitz.
> 
> Note: I've tried with Quartus v1.1 and Quartus v2.1. Both of them are
> Limited Edition.

Article: 53211
Subject: Re: questions about RS232 IN Altera FPGA
From: fredrik_he_lang@hotmail.com (Fredrik)
Date: 6 Mar 2003 09:48:17 -0800
Links: << >>  << T >>  << A >>
Hi Sarah,
You would only be able to implement the logic part it the Apex you
would need a levelshifter on the outside like the ICL3232ECV-16 from
Intersil. You should use 3.3V to supply the I/O bank where you put the
RS-232 inteface on (pins talking to and from the inteface curcit).
There is a UART core on the opencore website (I think). Second way
around is to use a NIOS system then you get the UART interface for
"free".
Hope this helps
Fredrik 
"sarah shen" <sarahshenca@yahoo.ca> wrote in message news:<b416lj$ksq1@mercury.cc.uottawa.ca>...
> Hi:
> 
> I have a question about how to realise RS232 srial coomunication between PC
> an Altera APEX20KE.
> I have less experience . Do I need to inplement UART in APEX20KE or just
> implemet RS232 logic control part? Anyone can give some suggestions ?
> 
> Thank you very much.
> 
> Sarah(sarahshenca@yahoo.ca)

Article: 53212
Subject: Re: Annapolis Microsystems Wildcard
From: justgivemeanamedammit@hotmail.com (ABloke)
Date: 6 Mar 2003 09:49:02 -0800
Links: << >>  << T >>  << A >>
Hi Ray,

Thanks for the reply - I forget to check back on this thread.

You would think that they would give them to me. I bought the card a
couple of years ago, but it only came with Windows 98 drivers, which
are useless to me. It has been lying around for ages, so I thought I'd
put it to some use. Unfortunately, Annapolis want to charge nearly
$700 for the privelege of using it again, so it will just sit around
here doing nothing because the price is ludicrous.

It must be their business model to charge for long-term driver support
for their baords, but I will certainly never buy anything from them
again based on this evidence. It is a shame because it could be good
fun to play with the card - and I could have done something good with
it.

:-(

A

Ray Andraka <ray@andraka.com> wrote in message news:<3E444CC1.FE48476F@andraka.com>...
> Talk to Annapolis, I'm sure they'd be happy to get you the latest drivers
> (assuming you are a paying customer, of course!).  It is in their best
> interest for you to have a positive experience.  None of the people I
> know there bite either.
> 
> ABloke wrote:
> 
> > Does anyone out there have the latest drivers for their Wildcard (The
> > CardBus one with a V300)? I can't seem to find them on their website
> > or anywhere else on the web.
> >
> > Thanks
> >
> > A
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 53213
Subject: Re: altera quartusII help
From: "Thomas Siebert" <siebert.Thomas@t-online.de>
Date: Thu, 6 Mar 2003 19:00:08 +0100
Links: << >>  << T >>  << A >>
is it possible to update to V2.2SP1?
The VHDL support and synthesis is much better in
this version of Quartus. In fact it's better since V2.1
but without the source of the synchroniser module the
SW cannot find the entity. Thats why salvo (SDL) sees
an error, too.

regards Thomas


"sarah shen" <sarahshenca@yahoo.ca> schrieb im Newsbeitrag
news:b47ssh$ksu7@mercury.cc.uottawa.ca...
> Hi,
>
> I am using altera Quartus II now. When i complied, there is error:
>
> "Internal Error: Sub-system: CDB_ADD, File: ../h\cdb_add_visitor_export.h,
> Line: 195
> Subprogram not supported
> Quartus II Version 2.0 Build 190 01/22/2002 SJ Limited Edition"
>
> I can't open compliation.
>
> I am suspecting there is something wrong with recalling synchroniser
> component in one entity.
> Could anybody can help me? Thank you very much.
>
> Sarah
>
> My code is below:
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity TxUnit is
>   port (
>      Clk    : in  std_logic;  -- Clock signal
>      Reset  : in  std_logic;  -- Reset input
>      Enable : in  std_logic;  -- Enable input
>      LoadA  : in  std_logic;  -- Asynchronous Load
>      TxD    : out std_logic;  -- RS-232 data output
>      Busy   : out std_logic;  -- Tx Busy
>      DataI  : in  std_logic_vector(7 downto 0)); -- Byte to transmit
> end TxUnit;
>
> architecture Behaviour of TxUnit is
>
>   component synchroniser
>   port (
>      C1 : in std_logic;  -- Asynchronous signal
>      C :  in std_logic;  -- Clock
>      O :  out Std_logic);-- Synchronised signal
>   end component;
>
>   signal TBuff    : std_logic_vector(7 downto 0); -- transmit buffer
>   signal TReg     : std_logic_vector(7 downto 0); -- transmit register
>   signal TBufL    : std_logic;  -- Buffer loaded
>   signal LoadS    : std_logic; -- Synchronised load signal
>
> begin
>   -- Synchronise Load on Clk
>   SyncLoad : Synchroniser port map
>   (C1=>LoadA,
>    C=> Clk,
>    O=> LoadS );  ------------i am suspecting this method.
>
>
>
>   -- Tx process
>   TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL)
>   variable BitPos : INTEGER range 0 to 10; -- Bit position in the frame
>   begin
>      if Reset = '1' then
>         TBufL <= '0';
>         BitPos := 0;
>         TxD <= '1';
>      elsif Rising_Edge(Clk) then
>         if LoadS = '1' then
>            TBuff <= DataI;
>            TBufL <= '1';
>         end if;
>         if Enable = '1' then
>            case BitPos is
>               when 0 => -- idle or stop bit
>                  TxD <= '1';
>                  if TBufL = '1' then -- start transmit. next is start bit
>                     TReg <= TBuff;
>                     TBufL <= '0';
>                     BitPos := 1;
>                  end if;
>               when 1 => -- Start bit
>                  TxD <= '0';
>                  BitPos := 2;
>               when others =>
>                  TxD <= TReg(BitPos-2); -- Serialisation of TReg
>                  BitPos := BitPos + 1;
>            end case;
>            if BitPos = 10 then -- bit8. next is stop bit
>               BitPos := 0;
>            end if;
>         end if;
>      end if;
>   end process;
>
> Busy <= LoadS or TBufL;
>
> end Behaviour;
>
>
>



Article: 53214
Subject: Re: Issues in Outsourcing?
From: johnjakson@yahoo.com (john jakson)
Date: 6 Mar 2003 10:20:28 -0800
Links: << >>  << T >>  << A >>
"Garrett Mace" <g.ryan@macetech.com> wrote in message news:<

> 
> I've often wondered how well a startup company would do, if it were to begin
> with several dozen to several hundred experienced, skilled engineers
> (formerly laid off on the advice of fast-talking managing consultants). All
> of them, of course, committed to the long-term survival and knowledge pool
> of the company, while fostering new talent and encouraging new research.
> 
> They wouldn't last a year, of course.
> 
> Still, an interesting idea.


Only as well as the investors will allow. If the team of experienced
experts doen't have a few glam stars who can pull in stable investors,
then all is for nought. Investors are funny, follow the herd types,
(but not the nerd hehe). Investors only talk to or see a handfull of
top people in any startup.


On 4 Mar 2003 18:45:28 -0800, the renowned anglomont@yahoo.com (TI) 
wrote: 

> Hello 
> we are an ASIC/FPGA company currently understaffed but with a very 
> limited budget; so I wonder under what circumstances and what type of 
> projects(non crucial?) we could consider outsourcing to some(which?) 
> developing country team? 
> Thanks 
> MA 

This is one of a long series of questions which confuse the hell out
of me as to what & where & who you really are. What is your real
agenda? It seems like you are gathering ASIC related business info for
a paper? Are you a student or EE or what?




As for outsourcing, well I wouldn't send work abroad myself (except
maybe home to UK), I am sure Russia, India and others have many fine
EEs, Mathematicians etc, but will you get a product-shipping
market-aware experienced and good English speaking EE on the team all
at the same time, probably not. My exp of Indian SW for an outsourcing
I am familiar with didn't inspire any confidence.

In other words only hire people that have already built & shipped
product as good or better than your own that you can verify. Where you
find em is your business.

Article: 53215
Subject: Re: Need help! Any experienced Handel-C user?
From: johnjakson@yahoo.com (john jakson)
Date: 6 Mar 2003 10:40:59 -0800
Links: << >>  << T >>  << A >>
mchain@sh163.net (gps) wrote in message news:<6e873b9c.0303051749.775865f9@posting.google.com>...
> Hi,I am now doing a project on testing Handel-C program.  Any
> experienced user on handel-C can tell me any common mistakes
> PROGRAMMER always made when coding ,especially for the NEW user?  I
> try to find a methodology to detect the bugs.


I notice that many HandelC novices are coming here these days with
homework.

HandelC is a tool that lets C programmers who don't usually know much
about HW design & architecture turn C into HW. Since this can only
really be done on FPGA, they end up here. So we end up teaching basic
HW 101 lessons for free.

I am wondering if any really experienced HW guys who have done real
schematics & real HDL have anything good to say about using HandelC
for a high performance project v Vxx. Apart from it being potentially
faster at cranking something out, I want to know if its worth spending
time on it.

The issue with HandelC is that it is a proprietary language with a
tiny paid up license base with no ASIC support and an expensive
license at that. Is it being handed out in all the schools for free
academic use as the new HW-Java hoping that when these people graduate
there will be new customers?

I am also seeing HandelC specs for HW that has SW thinking written all
over it, that a HW guy wouldn't even consider such a path. Sure their
algorithm can be synthesized into HW, but such an approach will end up
no faster than a P4 running C/x86 code directly. IE the huge serial
speed advantage that a P4 has over say a 30MHz HandelC design would
require that HandelC must produce 100x more parallelism to even match
speed and then some.

Do HandleC designs ever get into production?

JJ

Article: 53216
Subject: How to create a top level VHDL file for given EDIF files
From: scottiecs@yahoo.com (Scott)
Date: 6 Mar 2003 10:50:19 -0800
Links: << >>  << T >>  << A >>
I am trying to implement Xilinx's XAPP233(UART implementatin).  The
files are given in the form of EDIF files.  From my understanding all
I need to do is create a top level VHDL file using the I/O that is
used in the 2 EDIF files(Tx and Rx).  I am new to VHDl and programming
FPGA's, which is why this is giving me so much trouble.  Can anyone
help me out in writing the top level file, or know of a good source
where I can see some examples of other top level files implementing
EDIF files?

I am using Xilinx's Webpack 4.1 with a Digilab 2E FPGA(Spartan IIe).  

Thanks in advance!!

Scott Sullivan

Article: 53217
Subject: Re: Implementation of latch in FPGA
From: nimrodm@yahoo.com (Nimrod Mesika)
Date: 6 Mar 2003 11:03:24 -0800
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote in message news:<3E654FF4.B03BCACE@xilinx.com>...
> Here is what I say in seminars:
> Latches are only used by very inexperienced designers, and by very
> experienced designers.
> The inexperienced ones don't realize the pitfalls ( and get themselves
> into bad trouble), the really experienced ones appreciated the
> advantages ( and know how to stay out of trouble).
> The average designer is much better off with only flip-flops.

Can you elaborate a little about the advantages of using latches (or
point us at some paper)?

The only advantage I know of is that latches may sometimes give better
performance if your pipeline isn't well balanced (i.e., you may get a
higher maximum clock).

From what I recall disadvantages are difficult testability and
sensitivity to clock duty cycle. Both of these shouldn't be an issue
for FPGA design, I assume.

Just an interesting discussion.

Nimrod.

Article: 53218
Subject: Re: Annapolis Microsystems Wildcard
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Mar 2003 19:39:05 GMT
Links: << >>  << T >>  << A >>
My biggest gripe about the Annapolis stuff is the closed architecture ala microsoft.
Where they don't exactly have a microsoft sized customer base, you would think they would
be a bit more accommodating, especially seeing you already dropped a sizable sum for the
board in the first place.  Oh well, I can't vouch for their business model (nor do I
understand it, if this is how they are doing it).  Didn't the board also come with NT
drivers?  Perhaps those may work out a bit better

ABloke wrote:

> Hi Ray,
>
> Thanks for the reply - I forget to check back on this thread.
>
> You would think that they would give them to me. I bought the card a
> couple of years ago, but it only came with Windows 98 drivers, which
> are useless to me. It has been lying around for ages, so I thought I'd
> put it to some use. Unfortunately, Annapolis want to charge nearly
> $700 for the privelege of using it again, so it will just sit around
> here doing nothing because the price is ludicrous.
>
> It must be their business model to charge for long-term driver support
> for their baords, but I will certainly never buy anything from them
> again based on this evidence. It is a shame because it could be good
> fun to play with the card - and I could have done something good with
> it.
>
> :-(
>
> A
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3E444CC1.FE48476F@andraka.com>...
> > Talk to Annapolis, I'm sure they'd be happy to get you the latest drivers
> > (assuming you are a paying customer, of course!).  It is in their best
> > interest for you to have a positive experience.  None of the people I
> > know there bite either.
> >
> > ABloke wrote:
> >
> > > Does anyone out there have the latest drivers for their Wildcard (The
> > > CardBus one with a V300)? I can't seem to find them on their website
> > > or anywhere else on the web.
> > >
> > > Thanks
> > >
> > > A
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53219
Subject: Re: Issues in Outsourcing?
From: mrand@my-deja.com (Marc Randolph)
Date: 6 Mar 2003 13:32:54 -0800
Links: << >>  << T >>  << A >>
"Garrett Mace" <g.ryan@macetech.com> wrote in message news:<v6dhcnhj5avf02@corp.supernews.com>...
> J. Michael Milner" <jmmilner@wideopenwest.com> wrote in message
> news:3E66BD67.5B82AAC9@wideopenwest.com...
>> I agree with all you've said but the sad fact is that you are, by
your own
>> words, "a consulting engineer" and American firms have long ago
been sold on
>> the notion that "a managerial consultant" is the expert on the
subject under
>> discussion.  They'll suggest you pay someone outside who has
special knowledge
>> but can't see how paying somebody inside to gain, apply, and retain
the same
>> special knowledge works.  I assume this must mean that the only
thing that can be
>> assigned a dollar value is the result of applying special
knowledge, not the
>> cost of gaining or the value of retaining the same.

As I hint at below, there is more too it than simply dollars. 
Available resources and other market factors also come into play. 
Lastly, perhaps the dollars aren't under your control... if the entity
controlling your budget has capped the amount of salary for permanent
employees, contractors or consultants may be the most effective way to
get something done without distracting your employees away from the
other things that must get done [when nearly everything is top
priority].

> I've often wondered how well a startup company would do, if it were to begin
> with several dozen to several hundred experienced, skilled engineers
> (formerly laid off on the advice of fast-talking managing consultants). All
> of them, of course, committed to the long-term survival and knowledge pool
> of the company, while fostering new talent and encouraging new research.
> 
> They wouldn't last a year, of course.
> 
> Still, an interesting idea.

This topic is quickly moving off topic for these news groups.

The (telecom!) startup that I work for has very few engineers fresh
out of school - even though it was doing its most aggressive hiring at
the absolute height of the bubble in 2000 and 2001, when experienced
engineers were VERY difficult to find.  The vast majority are
engineers with a proven track record.  Management viewed time to
market as the most important item, and realized that you have a better
chance of hitting your targets if you get good, experienced engineers.
 And honestly, of the few new hires that we did bring in, a
significant percentage didn't work out.

Of course, I wonder if you are hinting that the engineers wouldn't be
paid (or paid a very very small amount) unless the product was a
success.  I would think that would only work in the situation that
they could not find a job.  Otherwise, you might be getting what you
paid for.  Wasn't it Ben & Jerry's that hired a low salary CEO, only
to find the performance reflected the salary they were paying?

   Marc

Article: 53220
Subject: VCC XC6216 Hotworks board for sale
From: Ray Andraka <ray@andraka.com>
Date: Fri, 07 Mar 2003 00:18:33 GMT
Links: << >>  << T >>  << A >>
I put a Virtual Computer Corp XC6216DS Hotworks board up for
auction on Ebay.  There had been several queries here in the
recent past as to where people could get 6200's to
experiment with genetic and evolutionary circuits with.
Well, this is the board you need.  Only 3 days left.  The
URL is:
http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=3404173840

Sorry 'bout the plug, just figured there would have been
more interest gauging by the queries here.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin
Franklin, 1759



Article: 53221
Subject: Re: Implementation of latch in FPGA
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Thu, 06 Mar 2003 20:18:02 -0500
Links: << >>  << T >>  << A >>


Peter Alfke wrote:

> Here is what I say in seminars:
> Latches are only used by very inexperienced designers, and by very
> experienced designers.
> The inexperienced ones don't realize the pitfalls ( and get themselves
> into bad trouble), the really experienced ones appreciated the
> advantages ( and know how to stay out of trouble).
> The average designer is much better off with only flip-flops.
>
> Peter Alfke
> ==================

Peter,
    I don't seem to have been bitten by this problem yet, but I would rather
not be bitten either so could I get a few clarifications please....

1.    How do you define a flipflop vs a latch?
        Is a latch a register with a level sensitive strobe?
        What is a flip-flop then?  To me a Flip-flop is, for example, a pair of
cross-coupled nand or nor gates (R-S flip-flop), or else a J-K, toggle, or
D-type (edge sensitive.)  Is the definition here different?

2.    Why are latches bad?  Is it due to timing of clock distribution?

3.    Can you point me at some examples of pitfalls and advantages?  (Really I
would like to just find them here, but I am not that lazy.)

4.    How does one stay out of trouble with latches?

5.    Are you saying, "Stick with edge sensitive devices, not level sensitive
devices"?  If I understand correctly, you really want us to stick with one
clock domain and thus one clock frequency throughout the device, if at all
possible, right?

Thanks,
Theron


>
> David R Brooks wrote:
> >
> >  As others have written, your code doesn't actually infer a latch.
> >
> >  Indeed, you should not be using latches unless you are very sure what
> > you are doing. One of their few uses on a FPGA is in linking
> > asynchronous clock domains (itself a very specialised business).
> >  There is a design note on Xilinx TechXclusives that does this.
> >
> >  Download a copy of the Xilinx Libraries Guide: it includes sample
> > code to instantiate all the different primitives.
> >  Xilinx will implement a latch using the asynchronous set/reset inputs
> > to a flipflop.
> >
> > J_Jeniffer@excite.com (Jeniffer) wrote:
> >
> > :Hi all,
> > :I am trying to implement a design in virtex device. My design contains
> > :quite a few latches (intended). When I implement the design and open
> > :the design in the FPGA editor, I see that the latches are implemented
> > :using LUTs and not using the registers in the slice. The device contains
> > :free resources of registers. Is there a way, I can force the latches to
> > :be implemented in registers (other than using primitives)? I would
> > :prefer the code to be portable.
> > :
> > :My code (VHDL) for latch looks something like this:
> > :
> > :process (enable, din)
> > :begin
> > :if (enable = 0) then
> > :dout <= din;
> > :else
> > :dout <= dout;
> > :end if;
> > :end process;
> > :
> > :Thankyou for your time,
> > :Jeniffer


Article: 53222
Subject: Re: Implementation of latch in FPGA
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 06 Mar 2003 17:23:24 -0800
Links: << >>  << T >>  << A >>
Registers really isolate the input side from the output side. If you
have tight clock distribution and pay attention to set-up times, you can
analyze each part of the circuitry in its own clock period, and you
never get any strange race-condition effects, Something like the
revolving door at the hotel entrance, there is never any blast of wind
through it.

A latch is transparent during one half cycle of the clock. Now you must
pay attention to signals that might be racing through the latch.
On the other hand, latches can make your system faster, since you can
avoid the worst-case delay in every pipeline stage.

Peter Alfke
=========
Nimrod Mesika wrote:
> 
> Peter Alfke <peter@xilinx.com> wrote in message news:<3E654FF4.B03BCACE@xilinx.com>...
> > Here is what I say in seminars:
> > Latches are only used by very inexperienced designers, and by very
> > experienced designers.
> > The inexperienced ones don't realize the pitfalls ( and get themselves
> > into bad trouble), the really experienced ones appreciated the
> > advantages ( and know how to stay out of trouble).
> > The average designer is much better off with only flip-flops.
> 
> Can you elaborate a little about the advantages of using latches (or
> point us at some paper)?
> 
> The only advantage I know of is that latches may sometimes give better
> performance if your pipeline isn't well balanced (i.e., you may get a
> higher maximum clock).
> 
> From what I recall disadvantages are difficult testability and
> sensitivity to clock duty cycle. Both of these shouldn't be an issue
> for FPGA design, I assume.
> 
> Just an interesting discussion.
> 
> Nimrod.

Article: 53223
Subject: Re: Need help! Any experienced Handel-C user?
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Fri, 07 Mar 2003 11:36:28 +1000
Links: << >>  << T >>  << A >>
john jakson wrote:

> HandelC is a tool that lets C programmers who don't usually know much
> about HW design & architecture turn C into HW. Since this can only
> really be done on FPGA, they end up here. So we end up teaching basic
> HW 101 lessons for free.

Interestingly, that is also the common error when software folks (like I 
was) start to learn VHDL.  If you think of it as a programming language 
per se, you are doomed to failure.

I read up a bit on Handel C, and being in a University environment we 
have licenses for it as well.  I didn't have time to explore it 
properly, but it certainly seemed interesting.  I think basically what 
it does is treat the variables of a C program as the state vector of a 
huge state machine, and synthesises it from there (with some clever 
optimisations to avoid producing insanely large state machines).

Control flow constructs within Handel-C would translate to state 
transitions.

But the same point remains, if you think in software, and write Handel 
C, you may well produce something that synthesises, but will it do what 
you want, and in a reasonably efficient manner?  Who knows.  If you 
think in hardware, and write Handel-C accordingly, you could probably 
create circuits of great beauty.  But then you could probably do that in 
VHDL anyway...

Sorry, not really an answer, just some musings while I wait for my 
Microblaze system to build :)

John


Article: 53224
Subject: Re: altera quartusII help
From: "Subroto Datta" <sdatta@altera.com>
Date: Fri, 07 Mar 2003 03:22:14 GMT
Links: << >>  << T >>  << A >>
Quartus II 2.1 and newer versions have a much improved VHDL and Verilog
processing capability, especially with regard to language coverage. If you
can, do update to Quartus II 2.2 at least.

You will also need to add the files containing your entity definitions to
the Quartus project. In Quartus II 2.2 This is done using the menu command
Project->Add/Remove Files in Project, or by right clicking on Files in the
Project Navigator and selecting the Add/Remove Files in Project. Finally you
may need to get the order of files setup correctly. This is done using the
same dialog used for Adding Files to the Project, using the Up/Down buttons.

- Subroto Datta
Altera Corporation



"sarah shen" <sarahshenca@yahoo.ca> wrote in message
news:b47ssh$ksu7@mercury.cc.uottawa.ca...
> Hi,
>
> I am using altera Quartus II now. When i complied, there is error:
>
> "Internal Error: Sub-system: CDB_ADD, File: ../h\cdb_add_visitor_export.h,
> Line: 195
> Subprogram not supported
> Quartus II Version 2.0 Build 190 01/22/2002 SJ Limited Edition"
>
> I can't open compliation.
>
> I am suspecting there is something wrong with recalling synchroniser
> component in one entity.
> Could anybody can help me? Thank you very much.
>
> Sarah
>
> My code is below:
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity TxUnit is
>   port (
>      Clk    : in  std_logic;  -- Clock signal
>      Reset  : in  std_logic;  -- Reset input
>      Enable : in  std_logic;  -- Enable input
>      LoadA  : in  std_logic;  -- Asynchronous Load
>      TxD    : out std_logic;  -- RS-232 data output
>      Busy   : out std_logic;  -- Tx Busy
>      DataI  : in  std_logic_vector(7 downto 0)); -- Byte to transmit
> end TxUnit;
>
> architecture Behaviour of TxUnit is
>
>   component synchroniser
>   port (
>      C1 : in std_logic;  -- Asynchronous signal
>      C :  in std_logic;  -- Clock
>      O :  out Std_logic);-- Synchronised signal
>   end component;
>
>   signal TBuff    : std_logic_vector(7 downto 0); -- transmit buffer
>   signal TReg     : std_logic_vector(7 downto 0); -- transmit register
>   signal TBufL    : std_logic;  -- Buffer loaded
>   signal LoadS    : std_logic; -- Synchronised load signal
>
> begin
>   -- Synchronise Load on Clk
>   SyncLoad : Synchroniser port map
>   (C1=>LoadA,
>    C=> Clk,
>    O=> LoadS );  ------------i am suspecting this method.
>
>
>
>   -- Tx process
>   TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL)
>   variable BitPos : INTEGER range 0 to 10; -- Bit position in the frame
>   begin
>      if Reset = '1' then
>         TBufL <= '0';
>         BitPos := 0;
>         TxD <= '1';
>      elsif Rising_Edge(Clk) then
>         if LoadS = '1' then
>            TBuff <= DataI;
>            TBufL <= '1';
>         end if;
>         if Enable = '1' then
>            case BitPos is
>               when 0 => -- idle or stop bit
>                  TxD <= '1';
>                  if TBufL = '1' then -- start transmit. next is start bit
>                     TReg <= TBuff;
>                     TBufL <= '0';
>                     BitPos := 1;
>                  end if;
>               when 1 => -- Start bit
>                  TxD <= '0';
>                  BitPos := 2;
>               when others =>
>                  TxD <= TReg(BitPos-2); -- Serialisation of TReg
>                  BitPos := BitPos + 1;
>            end case;
>            if BitPos = 10 then -- bit8. next is stop bit
>               BitPos := 0;
>            end if;
>         end if;
>      end if;
>   end process;
>
> Busy <= LoadS or TBufL;
>
> end Behaviour;
>
>
>





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