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Threads Starting Dec 2007

126762: 07/12/01: <shunsl@gmail.com>: Configuration via JTAG using an Embedded Controller
    126825: 07/12/03: <ghelbig@lycos.com>: Re: Configuration via JTAG using an Embedded Controller
126763: 07/12/01: create: Using SRAM Memory CY7C1386C
    126766: 07/12/01: Duane Clark: Re: Using SRAM Memory CY7C1386C
    126797: 07/12/02: Ben Jackson: Re: Using SRAM Memory CY7C1386C
126773: 07/12/01: fl: What option can change the path sign "\" in Quartus ?
    126775: 07/12/01: fl: Re: What option can change the path sign "\" in Quartus ?
    126778: 07/12/02: cms: Re: What option can change the path sign "\" in Quartus ?
    126779: 07/12/02: cms: Re: What option can change the path sign "\" in Quartus ?
126776: 07/12/02: blisca: can't genarate block memory cores in ISE 7.1i
    126777: 07/12/02: blisca: R: can't genarate block memory cores in ISE 7.1i
    126790: 07/12/02: argee: Re: can't genarate block memory cores in ISE 7.1i
    126826: 07/12/03: Mike Treseler: Re: can't genarate block memory cores in ISE 7.1i
        126832: 07/12/03: blisca: Re: can't genarate block memory cores in ISE 7.1i
126786: 07/12/02: hiroyuki.kawai0914@gmail.com: XHwICAP functions on EDK
126794: 07/12/02: Eric Smith: Memec Flancter app note?
    126835: 07/12/03: Eric Smith: Re: Memec Flancter app note?
126796: 07/12/02: <lyonscf@gmail.com>: Researching Reconfigurable Computing
    126852: 07/12/04: Jecel: Re: Researching Reconfigurable Computing
    126885: 07/12/05: lyonscf@gmail.com: Re: Researching Reconfigurable Computing
126810: 07/12/03: Mike: Xilinx ISE Bugs
    126811: 07/12/03: comp.arch.fpga: Re: Xilinx ISE Bugs
    126813: 07/12/03: Joseph Samson: Re: Xilinx ISE Bugs
    126816: 07/12/03: John Retta: Re: Xilinx ISE Bugs
126815: 07/12/03: Barry: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?
    126817: 07/12/03: John_H: Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same
    126818: 07/12/03: Sean Durkin: Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same
    126820: 07/12/03: Symon: Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?
        126828: 07/12/03: Symon: Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?
    126823: 07/12/03: Barry: Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same
    126824: 07/12/03: Barry: Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same
126829: 07/12/03: motty: Power PC ISOCM Simulation
126831: 07/12/03: Andrew Ganger: Xilinx Platform USB Cable
    126834: 07/12/04: Symon: Re: Xilinx Platform USB Cable
    126836: 07/12/03: Eric Smith: Re: Xilinx Platform USB Cable
126840: 07/12/03: fazulu deen: calculation of clock cycle /instructions...
    126854: 07/12/04: Mike Treseler: Re: calculation of clock cycle /instructions...
    126855: 07/12/04: Nico Coesel: Re: calculation of clock cycle /instructions...
126843: 07/12/04: Timo Gerber: EDK does not find Modelsim
    126847: 07/12/04: Mike Treseler: Re: EDK does not find Modelsim
126848: 07/12/04: Michael Laajanen: XILINX XABEL
    126857: 07/12/05: Jim Granville: Re: XILINX XABEL
        126865: 07/12/05: Michael Laajanen: Re: XILINX XABEL
126849: 07/12/04: <dbeck88@gmail.com>: UK FPGA supplier
126853: 07/12/04: General Schvantzkopf: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
    126858: 07/12/04: Tommy Thorn: Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
        127398: 07/12/20: RCIngham: Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
    126864: 07/12/04: General Schvantzkopf: Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
    127392: 07/12/19: HenktenBakker: Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
    127402: 07/12/20: General Schvantzkopf: Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
126859: 07/12/04: axr0284: clock lines
    126863: 07/12/04: John_H: Re: clock lines
        126922: 07/12/05: PatC: Re: clock lines
    126905: 07/12/05: axr0284: Re: clock lines
    126915: 07/12/05: Goli: Re: clock lines
    126955: 07/12/06: Marc Randolph: Re: clock lines
126860: 07/12/04: Anuja: converting verilog to vhdl
    126861: 07/12/04: Eric Smith: Re: converting verilog to vhdl
        126935: 07/12/06: RCIngham: Re: converting verilog to vhdl
            126963: 07/12/07: RCIngham: Re: converting verilog to vhdl
    126921: 07/12/06: Matthew Hicks: Re: converting verilog to vhdl
    126928: 07/12/06: Anuja: Re: converting verilog to vhdl
    126937: 07/12/06: Anuja: Re: converting verilog to vhdl
    126969: 07/12/07: Anuja: Re: converting verilog to vhdl
    126972: 07/12/07: Dave: Re: converting verilog to vhdl
    126973: 07/12/07: Anuja: Re: converting verilog to vhdl
    126974: 07/12/07: Andy: Re: converting verilog to vhdl
    126979: 07/12/07: Anuja: Re: converting verilog to vhdl
    126990: 07/12/07: Anuja: Re: converting verilog to vhdl
    126992: 07/12/07: Anuja: Re: converting verilog to vhdl
126866: 07/12/05: fazulu deen: clock cycle per Instructions
    126874: 07/12/05: RCIngham: Re: clock cycle per Instructions
126871: 07/12/05: u_stadler@yahoo.de: BUFGCE
    126882: 07/12/05: John_H: Re: BUFGCE
        126886: 07/12/05: David Spencer: Re: BUFGCE
            126933: 07/12/06: John_H: Re: BUFGCE
    126883: 07/12/05: u_stadler@yahoo.de: Re: BUFGCE
    126924: 07/12/06: u_stadler@yahoo.de: Re: BUFGCE
126873: 07/12/05: Alex Freed: Spartan 3e and SDRAM
    126895: 07/12/05: <ghelbig@lycos.com>: Re: Spartan 3e and SDRAM
        126908: 07/12/05: Alex Freed: Re: Spartan 3e and SDRAM
            127433: 07/12/24: Thomas Rudloff: Re: Spartan 3e and SDRAM
    127393: 07/12/19: HenktenBakker: Re: Spartan 3e and SDRAM
126876: 07/12/05: Rob: RAM32X1D and Virtex-5
126877: 07/12/05: <wojjed@gmail.com>: "simultaneously switching output"
    126879: 07/12/05: Symon: Re: "simultaneously switching output"
        126900: 07/12/05: Symon: Re: "simultaneously switching output"
    126884: 07/12/05: Rob: Re: "simultaneously switching output"
126878: 07/12/05: <larstore@gmail.com>: Need help with Altera .pof format!
126887: 07/12/05: Helpme: can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation
    126888: 07/12/05: Jan Pech: Re: can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation
    126890: 07/12/05: General Schvantzkopf: Re: can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation
126894: 07/12/05: <MikeShepherd564@btinternet.com>: Mixed language design
    126904: 07/12/05: John McCaskill: Re: Mixed language design
        126906: 07/12/05: <MikeShepherd564@btinternet.com>: Re: Mixed language design
            126912: 07/12/05: Mike Treseler: Re: Mixed language design
        126910: 07/12/05: Gabor: Re: Mixed language design
        126917: 07/12/05: John McCaskill: Re: Mixed language design
    126916: 07/12/05: Ray Andraka: Re: Mixed language design
        126920: 07/12/05: glen herrmannsfeldt: Re: Mixed language design
    126923: 07/12/06: <MikeShepherd564@btinternet.com>: Re: Mixed language design
126896: 07/12/05: guy: why do i see negative clock hold time
    126898: 07/12/05: David Spencer: Re: why do i see negative clock hold time
    126901: 07/12/05: KJ: Re: why do i see negative clock hold time
126897: 07/12/05: John Adair: Drigmorn1 - The Cheapest FPGA Development Board???
    126927: 07/12/06: <posedge52@yahoo.com>: Re: Drigmorn1 - The Cheapest FPGA Development Board???
        126930: 07/12/06: HT-Lab: Re: Drigmorn1 - The Cheapest FPGA Development Board???
            126931: 07/12/06: Mike Harrison: Re: Drigmorn1 - The Cheapest FPGA Development Board???
    126929: 07/12/06: Mike Harrison: Re: Drigmorn1 - The Cheapest FPGA Development Board???
    126936: 07/12/06: John Adair: Re: Drigmorn1 - The Cheapest FPGA Development Board???
    126938: 07/12/06: John Adair: Re: Drigmorn1 - The Cheapest FPGA Development Board???
    126967: 07/12/07: Dave Pollum: Re: Drigmorn1 - The Cheapest FPGA Development Board???
    126971: 07/12/07: John Adair: Re: Drigmorn1 - The Cheapest FPGA Development Board???
    128286: 08/01/20: Bogdan Paraschiv: Re: Drigmorn1 - The Cheapest FPGA Development Board???
126909: 07/12/05: l.s.rockfan@web.de: reconfigurable, modular design and clock signals - Question
    126911: 07/12/05: austin: Re: reconfigurable, modular design and clock signals - Question
        126913: 07/12/06: L. Schreiber: Re: reconfigurable, modular design and clock signals - Question
            126940: 07/12/06: austin: Re: reconfigurable, modular design and clock signals - Question
                127040: 07/12/10: L. Schreiber: Re: reconfigurable, modular design and clock signals - Question
126918: 07/12/05: Yui: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
    126944: 07/12/06: <ghelbig@lycos.com>: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
        127005: 07/12/08: KJ: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?
    126946: 07/12/06: Tommy Thorn: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
    126949: 07/12/06: KJ: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
    126959: 07/12/06: Aiken: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
    126965: 07/12/07: KJ: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
    126977: 07/12/07: Tommy Thorn: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
    127000: 07/12/08: Tommy Thorn: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
126926: 07/12/06: <posedge52@yahoo.com>: Spartan-3E starter kit, USB Jtag
126932: 07/12/06: <wei.wang.cantab@googlemail.com>: Synplify .sdc file
    126976: 07/12/07: kkoorndyk: Re: Synplify .sdc file
126939: 07/12/06: ratemonotonic: Using FSL with Interrupts
    126956: 07/12/07: John Williams: Re: Using FSL with Interrupts
    126975: 07/12/07: ratemonotonic: Re: Using FSL with Interrupts
126941: 07/12/06: <truongt1024@gmail.com>: student requiring assistance :)
    126942: 07/12/06: Guenter Dannoritzer: Re: student requiring assistance :)
    126943: 07/12/06: <ghelbig@lycos.com>: Re: student requiring assistance :)
    126945: 07/12/06: BobW: Re: student requiring assistance :)
    126958: 07/12/06: Aiken: Re: student requiring assistance :)
    127237: 07/12/14: <truongt1024@gmail.com>: Re: student requiring assistance :)
126947: 07/12/06: =?GB2312?B?y7y/vCAosfMp?=: Seeking help on xilkernel
126950: 07/12/06: <matadouros.home@gmail.com>: For God's sake !! It did not work at all !!!
    126951: 07/12/06: Kevin Neilson: Re: For God's sake !! It did not work at all !!!
        126964: 07/12/07: Symon: Re: For God's sake !! It did not work at all !!!
    126952: 07/12/06: John_H: Re: For God's sake !! It did not work at all !!!
126953: 07/12/06: Alex Freed: SDRAM and S3E - is the example broken?
    126982: 07/12/07: <jaroslav.sykora@gmail.com>: Re: SDRAM and S3E - is the example broken?
126961: 07/12/06: axalay: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
    126962: 07/12/07: axalay: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
    126981: 07/12/07: Ed McGettigan: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
        126998: 07/12/08: Sean Durkin: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
            127054: 07/12/10: Ed McGettigan: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
        127055: 07/12/10: Ed McGettigan: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
    127038: 07/12/09: axalay: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
    127079: 07/12/11: axalay: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
126966: 07/12/07: Andre van der Avoird: usb cable driver
    126968: 07/12/07: John_H: Re: usb cable driver
        126970: 07/12/07: Andre van der Avoird: Re: usb cable driver
            126987: 07/12/07: Andre van der Avoird: Re: usb cable driver
                126994: 07/12/07: Matthew Hicks: Re: usb cable driver
                    127042: 07/12/10: <google@becanus.nl>: Re: usb cable driver
        126980: 07/12/07: John_H: Re: usb cable driver
126978: 07/12/07: bish: selecting FPGA
    126983: 07/12/07: John Adair: Re: selecting FPGA
    126986: 07/12/07: Kris Vorwerk: Re: selecting FPGA
126985: 07/12/07: SvenA: virtex II pro - own core on plb with 2 interrupts
    126993: 07/12/07: Matthew Hicks: Re: virtex II pro - own core on plb with 2 interrupts
126988: 07/12/07: steve_blah: Pin assignment with Quartus II for PCB placement
    126989: 07/12/07: KJ: Re: Pin assignment with Quartus II for PCB placement
    126991: 07/12/07: Mike Treseler: Re: Pin assignment with Quartus II for PCB placement
    126996: 07/12/07: Subroto Datta: Re: Pin assignment with Quartus II for PCB placement
    127027: 07/12/09: steve_blah: Re: Pin assignment with Quartus II for PCB placement
    127028: 07/12/09: steve_blah: Re: Pin assignment with Quartus II for PCB placement
    127029: 07/12/09: steve_blah: Re: Pin assignment with Quartus II for PCB placement
126995: 07/12/07: <guochenglv@gmail.com>: the FPGA gate way
126997: 07/12/07: Alex Freed: Which FPGA and memory to use? The eternal X vs. A question.
    127003: 07/12/08: Marc Randolph: Re: Which FPGA and memory to use? The eternal X vs. A question.
        127020: 07/12/08: Alex Freed: Re: Which FPGA and memory to use? The eternal X vs. A question.
            127035: 07/12/09: Alex Freed: Re: Which FPGA and memory to use? The eternal X vs. A question.
    127004: 07/12/08: Marc Randolph: Re: Which FPGA and memory to use? The eternal X vs. A question.
    127008: 07/12/08: Kris Vorwerk: Re: Which FPGA and memory to use? The eternal X vs. A question.
    127009: 07/12/08: Nico Coesel: Re: Which FPGA and memory to use? The eternal X vs. A question.
        127012: 07/12/08: KJ: Re: Which FPGA and memory to use? The eternal X vs. A question.
            127016: 07/12/08: Nico Coesel: Re: Which FPGA and memory to use? The eternal X vs. A question.
        127021: 07/12/08: Alex Freed: Re: Which FPGA and memory to use? The eternal X vs. A question.
    127011: 07/12/08: Subroto Datta: Re: Which FPGA and memory to use? The eternal X vs. A question.
    127017: 07/12/08: Nico Coesel: Re: Which FPGA and memory to use? The eternal X vs. A question.
        127022: 07/12/08: Alex Freed: Re: Which FPGA and memory to use? The eternal X vs. A question.
            127032: 07/12/09: Nico Coesel: Re: Which FPGA and memory to use? The eternal X vs. A question.
    127030: 07/12/09: rickman: Re: Which FPGA and memory to use? The eternal X vs. A question.
    127031: 07/12/09: Marc Randolph: Re: Which FPGA and memory to use? The eternal X vs. A question.
126999: 07/12/08: naliali: problem interfacing AD9510 via serial controller
    127034: 07/12/09: rickman: Re: problem interfacing AD9510 via serial controller
127001: 07/12/08: Frank Buss: DDS generator with interpolated samples for Spartan3E development board
    127014: 07/12/08: Mike Treseler: Re: DDS generator with interpolated samples for Spartan3E development
    127015: 07/12/08: emeb: Re: DDS generator with interpolated samples for Spartan3E development
        127074: 07/12/11: chesi: Re: DDS generator with interpolated samples for Spartan3E development
            127078: 07/12/11: John_H: Re: DDS generator with interpolated samples for Spartan3E development
    127018: 07/12/08: KJ: Re: DDS generator with interpolated samples for Spartan3E development board
    127025: 07/12/09: Allan Herriman: Re: DDS generator with interpolated samples for Spartan3E development board
        127036: 07/12/09: John Larkin: Re: DDS generator with interpolated samples for Spartan3E development board
            127037: 07/12/10: Frank Buss: Re: DDS generator with interpolated samples for Spartan3E development board
                127041: 07/12/10: John Larkin: Re: DDS generator with interpolated samples for Spartan3E development board
                    127064: 07/12/11: Frank Buss: Re: DDS generator with interpolated samples for Spartan3E development board
                        127068: 07/12/10: John Larkin: Re: DDS generator with interpolated samples for Spartan3E development board
                            127070: 07/12/11: Frank Buss: Re: DDS generator with interpolated samples for Spartan3E development board
                                127102: 07/12/11: John Larkin: Re: DDS generator with interpolated samples for Spartan3E development board
                                    127105: 07/12/12: Frank Buss: Re: DDS generator with interpolated samples for Spartan3E development board
                                    127119: 07/12/12: Brian Drummond: Re: DDS generator with interpolated samples for Spartan3E development board
                                        127136: 07/12/12: John Larkin: Re: DDS generator with interpolated samples for Spartan3E development board
    127051: 07/12/10: Kevin Neilson: Re: DDS generator with interpolated samples for Spartan3E development
        127067: 07/12/11: Frank Buss: Re: DDS generator with interpolated samples for Spartan3E development board
            127097: 07/12/11: Kevin Neilson: Re: DDS generator with interpolated samples for Spartan3E development
                127103: 07/12/12: Frank Buss: Re: DDS generator with interpolated samples for Spartan3E development board
                127194: 07/12/13: Kevin Neilson: Re: DDS generator with interpolated samples for Spartan3E development
                    127208: 07/12/14: Frank Buss: Re: DDS generator with interpolated samples for Spartan3E development board
        127098: 07/12/11: Brian Davis: Re: DDS generator with interpolated samples for Spartan3E development
        127205: 07/12/13: Brian Davis: Re: DDS generator with interpolated samples for Spartan3E development
        127279: 07/12/16: Chris Maryan: Re: DDS generator with interpolated samples for Spartan3E development
    127063: 07/12/10: Symon: Re: DDS generator with interpolated samples for Spartan3E development board
        127065: 07/12/11: Frank Buss: Re: DDS generator with interpolated samples for Spartan3E development board
127002: 07/12/08: John Adair: Drigmorn1 More Info
127006: 07/12/08: <wei.wang.cantab@googlemail.com>: What to look for when synthesising verilog code originally written
    127013: 07/12/08: emeb: Re: What to look for when synthesising verilog code originally
127007: 07/12/08: cwoodring: Xilinx EDK simulation
    127010: 07/12/08: Daniel Koethe: Re: Xilinx EDK simulation
127019: 07/12/08: Louis Dupont: Net hierarchy with Xilinx 9.1
    127057: 07/12/10: Patrick Dubois: Re: Net hierarchy with Xilinx 9.1
    127077: 07/12/11: Brian Drummond: Re: Net hierarchy with Xilinx 9.1
127026: 07/12/09: commone: Questions about Timing closure Floorplan and individual timing constraints
127044: 07/12/10: theosib@gmail.com: keep_hierarchy attribute equivalent for Lattice/Synplicity?
    127046: 07/12/10: John_H: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
    127056: 07/12/10: theosib@gmail.com: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
    127060: 07/12/10: John_H: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
    127081: 07/12/11: theosib@gmail.com: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
    127083: 07/12/11: John_H: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
127045: 07/12/10: Mike Gragger: ERROR iMPACT 477 - The bsdl for the device 'UNKNOWN' is out of date
127047: 07/12/10: mozilla: Xilinx ise 9.2i clean up project files
    127049: 07/12/10: Gabor: Re: Xilinx ise 9.2i clean up project files
        127053: 07/12/10: Dan K: Re: Xilinx ise 9.2i clean up project files
        127069: 07/12/11: Daniel O'Connor: Re: Xilinx ise 9.2i clean up project files
    127082: 07/12/11: Gabor: Re: Xilinx ise 9.2i clean up project files
    127099: 07/12/11: Tim P: Re: Xilinx ise 9.2i clean up project files
    127115: 07/12/12: mozilla: Re: Xilinx ise 9.2i clean up project files
    127116: 07/12/12: mozilla: Re: Xilinx ise 9.2i clean up project files
    127118: 07/12/12: Gabor: Re: Xilinx ise 9.2i clean up project files
127058: 07/12/10: Martin Charlwood: GAL16V8
    127059: 07/12/10: General Schvantzkopf: Re: GAL16V8
        127062: 07/12/11: Jim Granville: Re: GAL16V8
    127061: 07/12/10: Andrew Holme: Re: GAL16V8
    127094: 07/12/11: <mikeandmax@aol.com>: Re: GAL16V8
127066: 07/12/10: ee_ether: PCI Parallel port card for JTAG / programming?
    127084: 07/12/11: Peter Wallace: Re: PCI Parallel port card for JTAG / programming?
        127091: 07/12/11: Anton Erasmus: Re: PCI Parallel port card for JTAG / programming?
            127292: 07/12/17: pes: Re: PCI Parallel port card for JTAG / programming?
    127298: 07/12/17: Chris H: Re: PCI Parallel port card for JTAG / programming?
127071: 07/12/11: SvenA: Different synthesis report between ISE-xst and EDK-xst
    127075: 07/12/11: SvenA: Re: Different synthesis report between ISE-xst and EDK-xst
127072: 07/12/11: Jon Neerup Lassen: Trouble with instantiation of RPM core - RLOCs are not obeyed
127073: 07/12/11: Joseph: Xilinx : Incorrect PACE file generation from schematic
    127093: 07/12/11: PatC: Re: Xilinx : Incorrect PACE file generation from schematic
127076: 07/12/11: rossalbi: sobel in vhdl
    127080: 07/12/11: RCIngham: Re: sobel in vhdl
    127117: 07/12/12: Martin Thompson: Re: sobel in vhdl
    131774: 08/05/01: Kevin Neilson: Re: sobel in vhdl
        131777: 08/05/01: Jim Lewis: Re: sobel in vhdl
127085: 07/12/11: Paul: Chipscope 7.1 and JTAG TAP
    127092: 07/12/11: PatC: Re: Chipscope 7.1 and JTAG TAP
    127109: 07/12/11: naliali: Re: Chipscope 7.1 and JTAG TAP
    127142: 07/12/12: Ed McGettigan: Re: Chipscope 7.1 and JTAG TAP
127086: 07/12/11: John Adair: Craignell and Darnaw1 Website Updates
    127087: 07/12/11: John_H: Re: Craignell and Darnaw1 Website Updates
        127088: 07/12/12: Jim Granville: Re: Craignell and Darnaw1 Website Updates
    127089: 07/12/11: John_H: Re: Craignell and Darnaw1 Website Updates
    127090: 07/12/11: John Adair: Re: Craignell and Darnaw1 Website Updates
    127095: 07/12/11: <ghelbig@lycos.com>: Re: Craignell and Darnaw1 Website Updates
    127096: 07/12/11: John_H: Re: Craignell and Darnaw1 Website Updates
    127107: 07/12/11: Uncle Noah: Re: Craignell and Darnaw1 Website Updates
127100: 07/12/11: ereader: Poor quality Xilinx boards ? Your experience ?
    127104: 07/12/11: Alex Freed: Re: Poor quality Xilinx boards ? Your experience ?
    127106: 07/12/12: Matthew Hicks: Re: Poor quality Xilinx boards ? Your experience ?
    127110: 07/12/11: PatC: Re: Poor quality Xilinx boards ? Your experience ?
    127111: 07/12/12: Frank Buss: Re: Poor quality Xilinx boards ? Your experience ?
        127121: 07/12/12: John_H: Re: Poor quality Xilinx boards ? Your experience ?
            127126: 07/12/12: ereader: Re: Poor quality Xilinx boards ? Your experience ?
                127139: 07/12/12: ereader: Re: Poor quality Xilinx boards ? Your experience ?
                    127177: 07/12/13: Brian Drummond: Re: Poor quality Xilinx boards ? Your experience ?
                        127183: 07/12/13: ereader: Re: Poor quality Xilinx boards ? Your experience ?
                            127195: 07/12/13: ereader: Re: Poor quality Xilinx boards ? Your experience ?
                                127202: 07/12/13: ereader: Re: Poor quality Xilinx boards ? Your experience ?
        127135: 07/12/12: John_H: Re: Poor quality Xilinx boards ? Your experience ?
        127187: 07/12/13: John_H: Re: Poor quality Xilinx boards ? Your experience ?
        127196: 07/12/13: John_H: Re: Poor quality Xilinx boards ? Your experience ?
    127112: 07/12/11: ereader: Re: Poor quality Xilinx boards ? Your experience ?
    127130: 07/12/12: austin: Re: Poor quality Xilinx boards ? Your experience ?
        127132: 07/12/12: ereader: Re: Poor quality Xilinx boards ? Your experience ?
            127133: 07/12/12: austin: Re: Poor quality Xilinx boards ? Your experience ?
                127137: 07/12/12: ereader: Re: Poor quality Xilinx boards ? Your experience ?
                    127140: 07/12/12: austin: Re: Poor quality Xilinx boards ? Your experience ?
                        127144: 07/12/12: ereader: Re: Poor quality Xilinx boards ? Your experience ?
127101: 07/12/11: motty: Initializing Micron DDR2 Memory
    127113: 07/12/12: RCIngham: Re: Initializing Micron DDR2 Memory
    127122: 07/12/12: Joseph Samson: Re: Initializing Micron DDR2 Memory
    127124: 07/12/12: motty: Re: Initializing Micron DDR2 Memory
    127192: 07/12/13: Kevin Neilson: Re: Initializing Micron DDR2 Memory
127108: 07/12/11: dream_life_0102: I try to Tri-Mode Embedded EMAC
    127125: 07/12/12: Jim Wu: Re: I try to Tri-Mode Embedded EMAC
    127161: 07/12/12: dream_life_0102: Re: I try to Tri-Mode Embedded EMAC
127114: 07/12/12: John Adair: Drigmorn1 User Manual
127120: 07/12/12: John Stein: Xilinx RocketIO problems
    127134: 07/12/12: Duane Clark: Re: Xilinx RocketIO problems
        127147: 07/12/12: John Stein: Re: Xilinx RocketIO problems
            127153: 07/12/12: Ed McGettigan: Re: Xilinx RocketIO problems
                127179: 07/12/13: John Stein: Re: Xilinx RocketIO problems ->solved
                    148806: 10/08/27: santukms: Xilinx RocketIO problems
    127165: 07/12/12: Marc Randolph: Re: Xilinx RocketIO problems
127123: 07/12/12: Poonam: FPGA Board design basics
    127141: 07/12/12: John_H: Re: FPGA Board design basics
        127160: 07/12/12: Duane Clark: Re: FPGA Board design basics
    127143: 07/12/12: Poonam: Re: FPGA Board design basics
    127145: 07/12/12: Gabor: Re: FPGA Board design basics
    127146: 07/12/12: John Adair: Re: FPGA Board design basics
    127152: 07/12/12: Poonam: Re: FPGA Board design basics
    127162: 07/12/12: Poonam: Re: FPGA Board design basics
    127163: 07/12/12: Kris Vorwerk: Re: FPGA Board design basics
    127175: 07/12/13: Rob: Re: FPGA Board design basics
    127182: 07/12/13: Poonam: Re: FPGA Board design basics
    127197: 07/12/13: Dave Pollum: Re: FPGA Board design basics
    127212: 07/12/14: Andrew Burnside: Re: FPGA Board design basics
    127217: 07/12/14: <jcr_alr@xplornet.com>: Re: FPGA Board design basics
    127218: 07/12/14: Brian Drummond: Re: FPGA Board design basics
    127221: 07/12/14: Poonam: Re: FPGA Board design basics
    127235: 07/12/14: mng: Re: FPGA Board design basics
127127: 07/12/12: Paul: Debugging designs that are running on FPGA
    127131: 07/12/12: Kris Vorwerk: Re: Debugging designs that are running on FPGA
    127138: 07/12/12: Duane Clark: Re: Debugging designs that are running on FPGA
        127174: 07/12/13: Paul: Re: Debugging designs that are running on FPGA
            127189: 07/12/13: Duane Clark: Re: Debugging designs that are running on FPGA
            127201: 07/12/13: Duane Clark: Re: Debugging designs that are running on FPGA
        127190: 07/12/13: comp.arch.fpga: Re: Debugging designs that are running on FPGA
    127149: 07/12/12: Nico Coesel: Re: Debugging designs that are running on FPGA
    127150: 07/12/12: Thomas Stanka: Re: Debugging designs that are running on FPGA
127129: 07/12/12: ratemonotonic: Newbee Microblaze system BRAM utlization confusion
    127172: 07/12/13: Göran Bilski: Re: Newbee Microblaze system BRAM utlization confusion
        127204: 07/12/13: Eric Smith: Re: Newbee Microblaze system BRAM utlization confusion
    127176: 07/12/13: Brian Drummond: Re: Newbee Microblaze system BRAM utlization confusion
        127209: 07/12/14: =?iso-8859-1?Q?G=F6ran_Bilski?=: Re: Newbee Microblaze system BRAM utlization confusion
        127220: 07/12/14: Brian Drummond: Re: Newbee Microblaze system BRAM utlization confusion
    127184: 07/12/13: ratemonotonic: Re: Newbee Microblaze system BRAM utlization confusion
    127185: 07/12/13: ratemonotonic: Re: Newbee Microblaze system BRAM utlization confusion
    127186: 07/12/13: ratemonotonic: Re: Newbee Microblaze system BRAM utlization confusion
    127188: 07/12/13: John McCaskill: Re: Newbee Microblaze system BRAM utlization confusion
    127253: 07/12/15: ratemonotonic: Re: Newbee Microblaze system BRAM utlization confusion
127148: 07/12/12: kislo: Spartan 3e pin question
    127151: 07/12/12: John_H: Re: Spartan 3e pin question
    127181: 07/12/13: kislo: Re: Spartan 3e pin question
127154: 07/12/12: <Josh.OuterSpace@gmail.com>: spartan 3e VQ100 serious question
    127155: 07/12/12: <Josh.OuterSpace@gmail.com>: Re: spartan 3e VQ100 serious question
        127157: 07/12/12: Stef: Re: spartan 3e VQ100 serious question
    127164: 07/12/12: John Larkin: Re: spartan 3e VQ100 serious question
        127167: 07/12/13: Nico Coesel: Re: spartan 3e VQ100 serious question
        127178: 07/12/13: Brian Drummond: Re: spartan 3e VQ100 serious question
            127229: 07/12/14: John Larkin: Re: spartan 3e VQ100 serious question
                127239: 07/12/15: Brian Drummond: Re: spartan 3e VQ100 serious question
        127230: 07/12/14: John Larkin: Re: spartan 3e VQ100 serious question
    127166: 07/12/12: <Josh.OuterSpace@gmail.com>: Re: spartan 3e VQ100 serious question
    127169: 07/12/12: <Josh.OuterSpace@gmail.com>: Re: spartan 3e VQ100 serious question
127156: 07/12/12: Rk: VHDL code for component labeling
    127158: 07/12/12: Mike Treseler: Re: VHDL code for component labeling
127159: 07/12/12: <dteira@gmail.com>: WARNING:PAR:289 and bitgen error.
    127170: 07/12/12: mh: Re: WARNING:PAR:289 and bitgen error.
    127180: 07/12/13: Brian Drummond: Re: WARNING:PAR:289 and bitgen error.
127168: 07/12/13: David Hand: How do you initialize Xilinx ISOCM memory using DCR interface
    127198: 07/12/13: Peter Ryser: Re: How do you initialize Xilinx ISOCM memory using DCR interface
        127207: 07/12/14: David Hand: Re: How do you initialize Xilinx ISOCM memory using DCR interface
            127225: 07/12/14: Peter Ryser: Re: How do you initialize Xilinx ISOCM memory using DCR interface
                127277: 07/12/16: David Hand: Re: How do you initialize Xilinx ISOCM memory using DCR interface
                    127299: 07/12/17: Peter Ryser: Re: How do you initialize Xilinx ISOCM memory using DCR interface
127171: 07/12/13: sachin: ML505 board Compact Flash
    127191: 07/12/13: Ed McGettigan: Re: ML505 board Compact Flash
        127199: 07/12/13: PatC: Re: ML505 board Compact Flash
    127200: 07/12/13: self: Re: ML505 board Compact Flash
    127455: 07/12/27: sachin: Re: ML505 board Compact Flash
127173: 07/12/13: John Adair: Darnaw1 User Manual
127193: 07/12/13: Neil Steiner: `ifdef XST?
    127219: 07/12/14: johnp: Re: `ifdef XST?
127203: 07/12/13: ereader: Spartan 3E starter kit expansion boards - Gb ethernet & video
127210: 07/12/14: mynewlifever@yahoo.com.cn: xilinx v5 configeration problem
    127213: 07/12/14: bunty: Re: xilinx v5 configeration problem
        127226: 07/12/14: Ed McGettigan: Re: xilinx v5 configeration problem
    127652: 08/01/04: <richard_hein@shaw.ca>: Re: xilinx v5 configeration problem
127211: 07/12/14: Bathala: using fstream to access File on Compact Flash Card
    127223: 07/12/14: Thomas: Re: using fstream to access File on Compact Flash Card
127214: 07/12/14: Cagatay Kalelioglu: Chrontel 7010A
    127215: 07/12/14: Cagatay Kalelioglu: Re: Chrontel 7010A
127216: 07/12/14: <rinky.singh.86@gmail.com>: Connecting BRAM block to Self designed BRAM controller
127222: 07/12/14: cpope: serial ATA question
    127227: 07/12/14: Ed McGettigan: Re: serial ATA question
    127258: 07/12/15: ereader: Re: serial ATA question
        127259: 07/12/16: John_H: Re: serial ATA question
127224: 07/12/14: psihodelia@googlemail.com: Re: VHDL language is out of date! Why? I will explain.
127231: 07/12/14: psihodelia@googlemail.com: Re: VHDL language/MyHDL
127236: 07/12/14: <posedge52@yahoo.com>: Using LVDS_25 with 3.3V Vcco.
    127238: 07/12/15: <MikeShepherd564@btinternet.com>: Re: Using LVDS_25 with 3.3V Vcco.
        127242: 07/12/15: <MikeShepherd564@btinternet.com>: Re: Using LVDS_25 with 3.3V Vcco.
            127244: 07/12/15: John Larkin: Re: Using LVDS_25 with 3.3V Vcco.
    127241: 07/12/15: <posedge52@yahoo.com>: Re: Using LVDS_25 with 3.3V Vcco.
    127245: 07/12/15: austin: Re: Using LVDS_25 with 3.3V Vcco.
        127255: 07/12/15: John Larkin: Re: Using LVDS_25 with 3.3V Vcco.
        127256: 07/12/15: John_H: Re: Using LVDS_25 with 3.3V Vcco.
    127247: 07/12/15: John_H: Re: Using LVDS_25 with 3.3V Vcco.
    127250: 07/12/15: <posedge52@yahoo.com>: Re: Using LVDS_25 with 3.3V Vcco.
127240: 07/12/15: <posedge52@yahoo.com>: Spartan-3E starter kit, what's "J8" 6-pin for?
    127249: 07/12/15: John_H: Re: Spartan-3E starter kit, what's "J8" 6-pin for?
        127269: 07/12/16: John_H: Re: Spartan-3E starter kit, what's "J8" 6-pin for?
    127263: 07/12/16: <jcr_alr@xplornet.com>: Re: Spartan-3E starter kit, what's "J8" 6-pin for?
    127391: 07/12/19: HenktenBakker: Re: Spartan-3E starter kit, what's "J8" 6-pin for?
127243: 07/12/15: Michael: Getting started guide for Digilent Spartan 3E Starter Board?
    127246: 07/12/15: austin: Re: Getting started guide for Digilent Spartan 3E Starter Board?
    127248: 07/12/15: John_H: Re: Getting started guide for Digilent Spartan 3E Starter Board?
    127252: 07/12/15: John Adair: Re: Getting started guide for Digilent Spartan 3E Starter Board?
    127257: 07/12/15: ereader: Re: Getting started guide for Digilent Spartan 3E Starter Board?
        127270: 07/12/16: John_H: Re: Getting started guide for Digilent Spartan 3E Starter Board?
    127264: 07/12/16: Michael: Re: Getting started guide for Digilent Spartan 3E Starter Board?
127251: 07/12/15: Kshitij: System Generator Design examples for spartan3, virtex 2pro?
127254: 07/12/15: John Adair: LVDS on Drigmorn1
127260: 07/12/16: Rebecca: =?ISO-8859-1?Q?Why_the_core_dynamic_power_isn't_0_when_the_toggle?=
    127266: 07/12/16: austin: Re: Why the core dynamic power isn't 0 when the toggle =?ISO-8859-1?Q?_rate_is_0??=
    127273: 07/12/17: Jim Granville: Re: Why the core dynamic power isn't 0 when the toggle=?ISO-8859-1?Q?_rate_is_0??=
    127275: 07/12/16: Rebecca: Re: Why the core dynamic power isn't 0 when the toggle rate is 0
    127276: 07/12/16: Rebecca: Re: Why the core dynamic power isn't 0 when the toggle rate is 0
        127294: 07/12/17: austin: Re: Why the core dynamic power isn't 0 when the toggle rate is 0
            127322: 07/12/18: glen herrmannsfeldt: Re: Why the core dynamic power isn't 0 when the toggle rate is 0
    127295: 07/12/17: Rebecca: Re: Why the core dynamic power isn't 0 when the toggle rate is 0
127261: 07/12/16: sfaragnaus@gmail.com: Mico32 linux kernel git repository
127262: 07/12/16: fl: What timing constraint value should be set for input/output module?
    127272: 07/12/16: Mike Treseler: Re: What timing constraint value should be set for input/output module?
    127288: 07/12/17: KJ: Re: What timing constraint value should be set for input/output module?
127265: 07/12/16: <westspeed@gmail.com>: [help]SAS with FPGAs
    127267: 07/12/16: comp.arch.fpga: Re: SAS with FPGAs
        127268: 07/12/16: Rube Bumpkin: Re: SAS with FPGAs
    127271: 07/12/16: John_H: Re: [help]SAS with FPGAs
127274: 07/12/16: Jon Neerup Lassen: Generating a RPM in Xilinx floorplanner
127278: 07/12/16: <wxy0624@gmail.com>: sampling error between 2 clocks
    127284: 07/12/17: Symon: Re: sampling error between 2 clocks
        127325: 07/12/18: Sean Durkin: Re: sampling error between 2 clocks
        127341: 07/12/19: KJ: Re: sampling error between 2 clocks
            127352: 07/12/19: RCIngham: Re: sampling error between 2 clocks
            127358: 07/12/19: Brian Drummond: Re: sampling error between 2 clocks
            127364: 07/12/19: mk: Re: sampling error between 2 clocks
                127371: 07/12/19: mk: Re: sampling error between 2 clocks
                    127389: 07/12/20: mk: Re: sampling error between 2 clocks
                        127400: 07/12/20: Symon: Re: sampling error between 2 clocks
                            127405: 07/12/20: Mike Treseler: Re: sampling error between 2 clocks
                                127412: 07/12/21: Symon: Re: sampling error between 2 clocks
                                    127414: 07/12/21: Symon: Re: sampling error between 2 clocks
    127310: 07/12/17: <wxy0624@gmail.com>: Re: sampling error between 2 clocks
        127410: 07/12/21: <wxy0624@gmail.com>: Re: sampling error between 2 clocks
        127411: 07/12/21: <razzy2@gmail.com>: Re: sampling error between 2 clocks
        127413: 07/12/21: johnp: Re: sampling error between 2 clocks
    127344: 07/12/18: <wxy0624@gmail.com>: Re: sampling error between 2 clocks
    127357: 07/12/19: KJ: Re: sampling error between 2 clocks
    127360: 07/12/19: Andy: Re: sampling error between 2 clocks
    127365: 07/12/19: KJ: Re: sampling error between 2 clocks
    127367: 07/12/19: John_H: Re: sampling error between 2 clocks
    127373: 07/12/19: John_H: Re: sampling error between 2 clocks
    127374: 07/12/19: KJ: Re: sampling error between 2 clocks
127280: 07/12/16: tmpstr: Ethernet data rates using Spartan-3 FPGA
    127282: 07/12/17: comp.arch.fpga: Re: Ethernet data rates using Spartan-3 FPGA
        127308: 07/12/17: Alex Freed: Re: Ethernet data rates using Spartan-3 FPGA
    127296: 07/12/17: ereader: Re: Ethernet data rates using Spartan-3 FPGA
    127347: 07/12/18: tmpstr: Re: Ethernet data rates using Spartan-3 FPGA
127281: 07/12/17: Robert Lacoste: Xilinx MAC experience ?
    127283: 07/12/17: Robert Lacoste: Re: Xilinx MAC experience ?
    127291: 07/12/17: Teo: Re: Xilinx MAC experience ?
    127297: 07/12/17: John Aderseen: Re: Xilinx MAC experience ?
    127338: 07/12/18: Ben Jackson: Re: Xilinx MAC experience ?
        127348: 07/12/19: Robert Lacoste: Re: Xilinx MAC experience ?
127285: 07/12/17: Denkedran Joe: global clock (gclk) input at xilinx virtex4 fpga
    127289: 07/12/17: Marc Randolph: Re: global clock (gclk) input at xilinx virtex4 fpga
    127293: 07/12/17: Tim Wescott: Re: global clock (gclk) input at xilinx virtex4 fpga
127286: 07/12/17: Guru: Debugging EDK DDR interface
    127300: 07/12/17: <benradu@gmail.com>: Re: Debugging EDK DDR interface
127290: 07/12/17: Nicolas Matringe: How to use a generic memory with Xilinx ?
    127303: 07/12/17: sudhi: Re: How to use a generic memory with Xilinx ?
    127314: 07/12/17: Darol Klawetter: Re: How to use a generic memory with Xilinx ?
127301: 07/12/17: John Adair: Tarfessock1 - FPGA Cardbus Development Board
    127318: 07/12/18: HT-Lab: Re: Tarfessock1 - FPGA Cardbus Development Board
127302: 07/12/17: Anuja: multidimensional arrays in VHDL?
    127304: 07/12/17: sudhi: Re: multidimensional arrays in VHDL?
        127315: 07/12/18: RCIngham: Re: multidimensional arrays in VHDL?
            127324: 07/12/18: RCIngham: Re: multidimensional arrays in VHDL?
    127305: 07/12/17: Anuja: Re: multidimensional arrays in VHDL?
    127306: 07/12/17: Anuja: Re: multidimensional arrays in VHDL?
    127307: 07/12/17: sudhi: Re: multidimensional arrays in VHDL?
    127316: 07/12/18: comp.arch.fpga: Re: multidimensional arrays in VHDL?
    127317: 07/12/18: Anuja: Re: multidimensional arrays in VHDL?
    127328: 07/12/18: Anuja: Re: multidimensional arrays in VHDL?
    127342: 07/12/18: JK: Re: multidimensional arrays in VHDL?
127309: 07/12/17: John_H: Xilinx DCM outputs for DDR
    127311: 07/12/17: BobW: Re: Xilinx DCM outputs for DDR
        127326: 07/12/18: John_H: Re: Xilinx DCM outputs for DDR
    127339: 07/12/18: Gabor: Re: Xilinx DCM outputs for DDR
    127340: 07/12/18: John_H: Re: Xilinx DCM outputs for DDR
    127343: 07/12/18: Brian Davis: Re: Xilinx DCM outputs for DDR
        127368: 07/12/19: BobW: Re: Xilinx DCM outputs for DDR
    127366: 07/12/19: John_H: Re: Xilinx DCM outputs for DDR
    127372: 07/12/19: John_H: Re: Xilinx DCM outputs for DDR
    127376: 07/12/19: John_H: Re: Xilinx DCM outputs for DDR
    127379: 07/12/19: Brian Davis: Re: Xilinx DCM outputs for DDR
    127380: 07/12/19: John_H: Re: Xilinx DCM outputs for DDR
127312: 07/12/17: life.is.best: Xilinx Evaluation boad ISE sample project
127313: 07/12/17: aravind: Darnaw module
    127319: 07/12/18: John Adair: Re: Darnaw module
    127345: 07/12/18: aravind: Re: Darnaw module
    127349: 07/12/19: John Adair: Re: Darnaw module
127320: 07/12/18: Amontec, Larry: VCCIO issue on Xilinx Spartan3E !
    127321: 07/12/18: Amontec, Larry: Re: VCCIO issue on Xilinx Spartan3E !
    127327: 07/12/18: austin: Re: VCCIO issue on Xilinx Spartan3E !
        127361: 07/12/19: Amontec, Larry: Re: VCCIO issue on Xilinx Spartan3E !
    127334: 07/12/19: Jim Granville: Re: VCCIO issue on Xilinx Spartan3E !
127323: 07/12/18: <shakith.fernando@gmail.com>: MGT Transciever
    127329: 07/12/18: <shakith.fernando@gmail.com>: Re: MGT Transciever
        127330: 07/12/18: austin: Re: MGT Transciever
127331: 07/12/18: RK: Virtex BRAM Configuration
    127332: 07/12/18: John_H: Re: Virtex BRAM Configuration
    127333: 07/12/18: Eric Smith: Re: Virtex BRAM Configuration
127335: 07/12/18: hess: Altera USB-Blaster on RHEL 5?
127336: 07/12/18: kislo: BGA reflow soldering using vapor phase
    127354: 07/12/19: Antti: Re: BGA reflow soldering using vapor phase
    127355: 07/12/19: comp.arch.fpga: Re: BGA reflow soldering using vapor phase
    127363: 07/12/19: Antti: Re: BGA reflow soldering using vapor phase
    127370: 07/12/19: Ed McGettigan: Re: BGA reflow soldering using vapor phase
127337: 07/12/18: Sbreheny: Glitch warnings in Modelsim with Lattice ispLever 7.0
127346: 07/12/18: Alan Nishioka: Changes to use lwip 1.2.0 with Xilinx EDK 9.1 or earlier
127350: 07/12/19: taco: FPGA program cable suggestion
    127356: 07/12/19: taco: Re: FPGA program cable suggestion
127351: 07/12/19: John Aderseen: Xilinx's ML505
127353: 07/12/19: Petter Gustad: Emacs as GUI for NIOS-II
127359: 07/12/19: u_stadler@yahoo.de: Xilinx EDK PPC405+FSL
    127362: 07/12/19: John McCaskill: Re: Xilinx EDK PPC405+FSL
127369: 07/12/19: Rick North: Quartus and simulation libraries...
    127390: 07/12/19: HenktenBakker: Re: Quartus and simulation libraries...
127375: 07/12/19: Dwayne Dilbeck: ASIC verification job info request
    127377: 07/12/19: austin: Re: ASIC verification job info request
        127378: 07/12/19: Dwayne Dilbeck: Re: ASIC verification job info request
        127397: 07/12/20: HT-Lab: Re: ASIC verification job info request
            127404: 07/12/20: Dwayne Dilbeck: Re: ASIC verification job info request
127381: 07/12/19: fl: What is "4-state binary radix" in Modelsim
    127399: 07/12/20: RCIngham: Re: What is
127382: 07/12/19: Eric Smith: Routing Vccint on four-layer PCB
    127384: 07/12/19: John Larkin: Re: Routing Vccint on four-layer PCB
        127385: 07/12/19: Eric Smith: Re: Routing Vccint on four-layer PCB
            127387: 07/12/19: John Larkin: Re: Routing Vccint on four-layer PCB
            127401: 07/12/20: Symon: Re: Routing Vccint on four-layer PCB
        127395: 07/12/20: John Adair: Re: Routing Vccint on four-layer PCB
        127396: 07/12/20: colin: Re: Routing Vccint on four-layer PCB
        127421: 07/12/21: mng: Re: Routing Vccint on four-layer PCB
    127407: 07/12/20: Ben Jackson: Re: Routing Vccint on four-layer PCB
127383: 07/12/19: fpgaguy: help with rising edge matching
    127386: 07/12/19: Eric Smith: Re: help with rising edge matching
        127403: 07/12/20: fpgaguy: Re: help with rising edge matching
    127388: 07/12/20: John_H: Re: help with rising edge matching
127394: 07/12/20: Daniel O'Connor: Xilinx Spartan 3 JTAG issues
    127406: 07/12/20: Gabor: Re: Xilinx Spartan 3 JTAG issues
    127408: 07/12/20: Ben Jackson: Re: Xilinx Spartan 3 JTAG issues
        127409: 07/12/21: Daniel O'Connor: Re: Xilinx Spartan 3 JTAG issues
127415: 07/12/21: Jaime Andres Aranguren Cardona: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition
    127416: 07/12/21: austin: Re: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E
        127417: 07/12/21: Jaime Andres Aranguren Cardona: Re: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition
            127418: 07/12/21: austin: Re: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E
            127420: 07/12/21: Eric Smith: Re: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition
        127419: 07/12/21: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?=: Re: PowerPC & Spartan-3E Embedded Processing Development Kit -
127422: 07/12/23: Sebastien Bourdeauducq: DQS contention with ddr_sdr from Opencores
    127426: 07/12/24: KJ: Re: DQS contention with ddr_sdr from Opencores
    127427: 07/12/23: Eric Smith: Re: DQS contention with ddr_sdr from Opencores
    127430: 07/12/24: Nico Coesel: Re: DQS contention with ddr_sdr from Opencores
    127431: 07/12/24: Sebastien Bourdeauducq: Re: DQS contention with ddr_sdr from Opencores
127425: 07/12/23: recoder: video capturing+ filter + vga output
    127446: 07/12/26: mh: Re: video capturing+ filter + vga output
127428: 07/12/24: Antti: cable IV and platform USB cable API now officially public
    127920: 08/01/10: davide: Re: cable IV and platform USB cable API now officially public
    127941: 08/01/10: Antti: Re: cable IV and platform USB cable API now officially public
127429: 07/12/24: John Adair: Darnaw1 - PGA FPGA Module
127432: 07/12/24: BALAS009: FPGA Project Support
    127434: 07/12/24: John_H: Re: FPGA Project Support
        127437: 07/12/25: Nico Coesel: Re: FPGA Project Support
        127439: 07/12/25: <MikeShepherd564@btinternet.com>: Re: FPGA Project Support
        127440: 07/12/25: Rick C.: Re: FPGA Project Support
    127435: 07/12/24: Peter Alfke: Re: FPGA Project Support
    127438: 07/12/24: Bob Perlman: Re: FPGA Project Support
        127441: 07/12/25: Rube Bumpkin: Re: FPGA Project Support
    127442: 07/12/25: Rube Bumpkin: Re: FPGA Project Support
    127443: 07/12/25: PFC: Re: FPGA Project Support
127436: 07/12/24: root: Centos 5.1 linux, Xilinx 9.2, Spartan 3E-1600 board (USB)
127444: 07/12/26: maverick: Spartan 3 FPGA verification via readback
    127451: 07/12/26: Nathan Bialke: Re: Spartan 3 FPGA verification via readback
    127454: 07/12/26: Nico Coesel: Re: Spartan 3 FPGA verification via readback
127445: 07/12/26: Alain: TechXclusives from Xilinx
    127450: 07/12/26: johnp: Re: TechXclusives from Xilinx
        127459: 07/12/27: Symon: Re: TechXclusives from Xilinx
            127474: 07/12/27: Eric Smith: Re: TechXclusives from Xilinx
        127473: 07/12/27: Eric Smith: Re: TechXclusives from Xilinx
            127475: 07/12/27: <MikeShepherd564@btinternet.com>: Re: TechXclusives from Xilinx
                127477: 07/12/27: Eric Smith: Re: TechXclusives from Xilinx
                    127489: 07/12/28: Nico Coesel: Re: TechXclusives from Xilinx
    127452: 07/12/26: Peter Alfke: Re: TechXclusives from Xilinx
    127463: 07/12/27: Alain: Re: TechXclusives from Xilinx
    127465: 07/12/27: Peter Alfke: Re: TechXclusives from Xilinx
    127476: 07/12/27: Peter Alfke: Re: TechXclusives from Xilinx
    127486: 07/12/28: Peter Alfke: Re: TechXclusives from Xilinx
    127490: 07/12/28: johnp: Re: TechXclusives from Xilinx
    127491: 07/12/28: Peter Alfke: Re: TechXclusives from Xilinx
    127607: 08/01/03: Andy: Re: TechXclusives from Xilinx
127447: 07/12/26: <krc.1987@gmail.com>: Core Generators...
    127448: 07/12/26: KJ: Re: Core Generators...
        127457: 07/12/27: Brian Drummond: Re: Core Generators...
            127470: 07/12/27: Duane Clark: Re: Core Generators...
                127482: 07/12/28: Brian Drummond: Re: Core Generators...
                    127485: 07/12/28: KJ: Re: Core Generators...
                        127502: 07/12/29: Brian Drummond: Re: Core Generators...
                        127784: 08/01/08: Martin Thompson: Re: Core Generators...
                            127788: 08/01/08: KJ: Re: Core Generators...
    127449: 07/12/26: John Adair: Re: Core Generators...
    127453: 07/12/26: Mike Treseler: Re: Core Generators...
127456: 07/12/27: Uncle Noah: Xilinx XST questions
    127458: 07/12/27: Brian Drummond: Re: Xilinx XST questions
        127483: 07/12/28: Brian Drummond: Re: Xilinx XST questions
        127484: 07/12/28: Brian Drummond: Re: Xilinx XST questions
    127460: 07/12/27: Uncle Noah: Re: Xilinx XST questions
    127461: 07/12/27: Uncle Noah: Re: Xilinx XST questions
    127464: 07/12/27: Georg Acher: Re: Xilinx XST questions
    127466: 07/12/27: Tim Verstraete: Re: Xilinx XST questions
    127467: 07/12/27: Mike Treseler: Re: Xilinx XST questions
    127469: 07/12/27: John Adair: Re: Xilinx XST questions
    127478: 07/12/27: Uncle Noah: Re: Xilinx XST questions
    127479: 07/12/27: Uncle Noah: Re: Xilinx XST questions
    127480: 07/12/27: Uncle Noah: Re: Xilinx XST questions
127462: 07/12/27: Dolphin: Video processing courses
    127468: 07/12/27: Mike Treseler: Re: Video processing courses
127471: 07/12/27: root: Xilinx EDK 9.2 problems under Centos 5
    127472: 07/12/27: Duane Clark: Re: Xilinx EDK 9.2 problems under Centos 5
    127487: 07/12/28: root: Re: Xilinx EDK 9.2 problems under Centos 5
127481: 07/12/28: <posedge52@yahoo.com>: Initialization of arrays
127488: 07/12/28: root: Re: Initialization of arrays
    127494: 07/12/28: <posedge52@yahoo.com>: Re: Initialization of arrays
        127501: 07/12/29: Jonathan Bromley: Re: Initialization of arrays
    127497: 07/12/29: rsl: Re: Initialization of arrays
127492: 07/12/28: kislo: Spartan 3E 3.3V configuration reverse current situation
    127493: 07/12/28: Peter Alfke: Re: Spartan 3E 3.3V configuration reverse current situation
127495: 07/12/28: Koustav: Architectural level CMP simulators
    127503: 07/12/29: rponsard@gmail.com: Re: Architectural level CMP simulators
    127517: 07/12/31: Steven Guccione: Re: Architectural level CMP simulators
127498: 07/12/28: cationebox@gmail.com: what is the difference between system side XAUI and line side XAUI?
127499: 07/12/29: Mir: JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...
    127504: 07/12/30: MM: Re: JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...
        127511: 07/12/31: Allan Herriman: Re: JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...
    127505: 07/12/30: Mir: Re: JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...
    127520: 08/01/01: Mir: Re: JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...
127500: 07/12/29: nierveze: a newbie question
127506: 07/12/30: <MikeShepherd564@btinternet.com>: How to inhibit a timing warning
    127507: 07/12/30: Jon Beniston: Re: How to inhibit a timing warning
    127508: 07/12/30: Subroto Datta: Re: How to inhibit a timing warning
    127509: 07/12/30: <MikeShepherd564@btinternet.com>: Re: How to inhibit a timing warning
127510: 07/12/31: blisca: Can i verify RAM content with ISE simulator?
127512: 07/12/31: vits: xilinx PAR runtime and synplify synth runtime
    127514: 07/12/31: sudhi: Re: xilinx PAR runtime and synplify synth runtime
127513: 07/12/31: Wojciech Zabolotny: State machine with stack to implement "subroutines"
    127515: 07/12/31: Jonathan Bromley: Re: State machine with stack to implement "subroutines"
        127516: 07/12/31: <MikeShepherd564@btinternet.com>: Re: State machine with stack to implement "subroutines"
            127518: 08/01/01: Bob Smith: Sparkfun FPGA board ?
                127519: 08/01/01: RedskullDC: Re: Sparkfun FPGA board ?
                127522: 08/01/01: Petter Gustad: Re: Sparkfun FPGA board ?
        127521: 08/01/01: John Adair: Re: Sparkfun FPGA board ?
        127523: 08/01/01: Brian Drummond: Re: State machine with stack to implement "subroutines"
    127530: 08/01/01: Mike Treseler: Re: State machine with stack to implement "subroutines"


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