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On 1 d=E9c, 21:09, fl <rxjw...@gmail.com> wrote:
> Hi,
> I find a strange problem relating to Quartus 7.2 and Modelsim 6.1g,
> web edition. For functional simulation, all is OK. For timing
> simulation, the component cannot be recognized by the testbench
> routine. I notice that in the work lib of Modelsim, the path sign is
> "\", not the same with the other's "/".
> Such as:
>
> C:\altera\72\qdesigns\...
>
> It should be:
> C:/altera/72/qdesigns/...
>
> I cannot find any menu to change the option in both Quartus and
> Modelsim. Could you tell me that? Thanks a lot.
Hi,
Further infomation about the problem. When I recompile the file, the
result is correct. And its command is like the following:
vcom -93 -work work C:/altera/72/qdesigns/vhdlQadd/simulation/modelsim/
addp.vho
I find the .do file generated by Quartus 7.2 has the problem command
line:
vcom -93 -work work {addp.vho}
It does not give the full path of addp.vho. Could you tell me where to
set it correct, in Quartus or Modelsim? Thank you very much.
Article: 126776Hi I had to use version 7.1 because 9.2 looks too heavy for my old pc I tried to generate internal block memory,but i have the following message Customizing IP An error occurred during customization Downloading ip updates 3 does not solve the problem.Article: 126777
forgot to say thanks Diego > >Article: 126778
On Dec 2, 5:30 am, fl <rxjw...@gmail.com> wrote:
> On 1 d=E9c, 21:09, fl <rxjw...@gmail.com> wrote:
>
> > Hi,
> > I find a strange problem relating to Quartus 7.2 and Modelsim 6.1g,
> > web edition. For functional simulation, all is OK. For timing
> > simulation, the component cannot be recognized by the testbench
> > routine. I notice that in the work lib of Modelsim, the path sign is
> > "\", not the same with the other's "/".
> > Such as:
>
> > C:\altera\72\qdesigns\...
>
> > It should be:
> > C:/altera/72/qdesigns/...
>
> > I cannot find any menu to change the option in both Quartus and
> > Modelsim. Could you tell me that? Thanks a lot.
>
> Hi,
> Further infomation about the problem. When I recompile the file, the
> result is correct. And its command is like the following:
>
> vcom -93 -work work C:/altera/72/qdesigns/vhdlQadd/simulation/modelsim/
> addp.vho
>
> I find the .do file generated by Quartus 7.2 has the problem command
> line:
> vcom -93 -work work {addp.vho}
>
> It does not give the full path of addp.vho. Could you tell me where to
> set it correct, in Quartus or Modelsim? Thank you very much.
Article: 126779
On Dec 2, 5:30 am, fl <rxjw...@gmail.com> wrote:
"\" has caused a great deal of confusion :)
ModelSim uses Tcl Command Syntax there backslash "\" symbol means
backslash substitution. If you wanna got to path "C:\altera\72\qdesigns
\..."
you should type C:\\altera\\72\qdesigns\\... or C:/altera/72/
qdesigns/... or { C:\altera\72\qdesigns\... }.
Backslash substitution is not performed on words enclosed in braces,
except for backslash-newline.
RTFM: Tcl and Macros (DO Files) > Tcl Command Syntax
Digitally yours,
Michael Tsvetkov
Article: 126780"KJ" <kkjennings@sbcglobal.net> writted in message news:Fam4j.2769$NY.781@nlpi068.nbdc.sbc.com... > > "Bronathan Jimley" <Bronathan.Jimley@MYCOMPANY.com> writted in message > news:8ln3l3pdrhgq93k3qj5fj2u16ka5k6a7iq@4ax.com... >> On Sat, 01 Dec 2007 11:33:23 -0800, Trick Misseller writted: >> >>>farm_traffic takes it down to one. >>>http://groups.google.com/groups/search?q=farm_traffic >> >> Sorry Trick, it's two now - and this post will make it three :-) >> -- >> Bronathan Jimley, Consultant >> > > My gosh, you're right....it just keeps a growin, will it never end???? > > Can get it back down to 1 though by filtering out anything with the > following words > > Trick Misseller writted Bronathan Jimley > > http://groups.google.com/groups?as_q=farm_traffic&num=10&scoring=r&as_epq=&as_oq=&as_eq=Trick+Misseller+writted+Bronathan+Jimley& > > KJ > Not now. Myss.Article: 126781
It isin't right to applicate lossless algorithms to fixed-bandwidth systems. There is always dark case corner with fully uncorrerlated data set then compression ratio will be 1:1 (or even worse for prediction-based algorithms with not corresponding distribution model). Lossless algorithms are perfect in storage systems for space saving. But transport channel should be wide enough for the worst case. From my knowledge of life the robust solution in your case is the redesigning system with wide channel at the current stage. Don't play with thin air, force oneself now and eliminate great troubles in the future. Digitally yours, Michael Tsvetkov (JPEG-lossless IP Core developer) http://www.jpegls.comArticle: 126782
On Nov 29, 6:46 am, "liqi...@gmail.com" <liqi...@gmail.com> wrote: > How can i interface the cyclone III with 2.5v LVDS to 3.3v LVDS adc & > dac ? > > Thanks IMHO directly. I've connected 3.3V Stratix LVDS to 2.5V StratixII LVDS in both directions. "The Cyclone III device meets the ANSI/TIA/EIA-644 standard with the following exceptions: =94 The maximum voltage output differential (VOD) is increased to 600 mV. The maximum VOD for ANSI specification is 450 mV. =94 The input voltage range can be reduced to the range of 1.0 V to 1.6 V, 0.5 V to 1.85 V or 0 V to 1.8 V based on different frequency ranges. The ANSI/TIA/EIA-644 specification supports an input voltage range of 0V to 2.4V." See the Cyclone III Device Datasheet: DC and Switching Characteristics of Cyclone III Devices chapter in volume 2 of the Cyclone III Device Handbook for the LVDS I/O standard electrical specifications and check your DAC/ ADC specification for final proof. Digitally yours, Michael Tsvetkov http://www.jpegls.comArticle: 126783
cms wrote: > It isin't right to applicate lossless algorithms to fixed-bandwidth > systems. Depends on the algorithm. E.g. RLE will never cause an increase in size, what's sufficient even for use with fixed-bandwidth channels. DoDiArticle: 126784
Hans-Peter Diettrich wrote: > Depends on the algorithm. E.g. RLE will never cause an increase in size, Wrong. It's trivially easy to prove that *no* lossless compression algorithm can avoid to sometimes cause an increase in size, while still compressing at least some inputs: There are 2^N different inputs with N bits, and as long as one of them is compressed by at least 1 bit, that means you have only 2^N-2 possible outputs left to represent the remaining 2^N-1 inputs with --- impossible. [F'up2 comp.compression, which is the only place this could possibly be on-topic]Article: 126785
On 2007-12-02, Hans-Peter Diettrich <DrDiettrich1@aol.com> wrote: > Depends on the algorithm. E.g. RLE will never cause an increase in size Even RLE can increase the size. Two of the most used methods to incidate runs are 1) prefix byte, 2) two consequtive bytes are the same. For both of these methods you can construct (or the file sometimes happens to be) a file containing 1) the value of the prefix byte 2) exactly two equal bytes. Even if you use some other method of indicating the runs, you can always constuct the pathological file that increases in size after compression. This fact does not change depending on what the compression algorithm is. The best you can do is have one bit to select uncompressed/compressed. followups set to comp.compression -Pasi -- "You're the type of guy who doesn't like to give up control." -- Wade to Garibaldi in Babylon 5:"The Exercise of Vital Powers"Article: 126786
Dear all,
I am now trying to use XHwICAP_getClbBits() (and also setClbBits())
to change contents of LUTs on EDK.
But they do not work well.
My fpga board is XUP (Virtex2 Pro.)
I write a part of "user_logic.vhd" and C code below.
---(a part of) user_logic.vhd----------------------
attribute LOC : string;
attribute LOC of LUT4_inst_1 : label is "SLICE_X6Y6";
...........
LUT4_inst_1 : LUT4
generic map
( INIT => X"00F5" )
port map
(
O => tmpreg,
I0 => slv_reg0(28),
I1 => slv_reg0(29),
I2 => slv_reg0(30),
I3 => slv_reg0(31)
);
------------------------------------------------------------
---(a part of) main.c----------------------------------------------
#include <ctype.h>
#include"xparameters.h"
#include"xuartlite_l.h"
#include "xutil.h"
#include "xbasic_types.h"
// for ICAP
#include <xhwicap.h>
#include <xhwicap_clb_lut.h>
//====================================================
int main (void) {
XStatus status;
XHwIcap hwicap;
status = XHwIcap_Initialize (&hwicap, 0,
XHI_READ_DEVICEID_FROM_ICAP);
if (status == XST_DEVICE_IS_STARTED)
{
print ("ICAP is OK\r\n");
}
else if (status != XST_SUCCESS)
{
print ("ICAP ERROR\r\n");
exit(-1);
}
print("-- Exiting main() --\r\n");
// for ICAP functions
Xuint32 col = 6; // SLICE number
Xuint32 row = 6; // SLICE number
int i = 0;
Xuint32 clb_col;
Xuint32 clb_row;
Xuint32 slice;
Xuint8 getValue[16];
Xuint8 getValue_2[16];
///////////////////////////////////////////
// translate to use getClbBits function
///////////////////////////////////////////
clb_col = XHwIcap_mSliceX2Col(col);
clb_row = XHwIcap_mSliceY2Row(&hwicap,row);
slice = XHwIcap_mSliceXY2Slice(col, row);
status = XHwIcap_GetClbBits (&hwicap, clb_row, clb_col,
XHI_CLB_LUT.CONTENTS[slice][XHI_CLB_LUT_F],getValue, 16);
status = XHwIcap_GetClbBits (&hwicap, clb_row, clb_col,
XHI_CLB_LUT.CONTENTS[slice][XHI_CLB_LUT_G],getValue_2, 16);
if (status != XST_SUCCESS)
{
print ("error");
}
// Display got values
..................
------------------------------------------------------------
In this case, I think either GetClbBits function in main.c returns
"0000000011110101" because SLICE_X6Y6 has been initialized by
user_logic.vhd as "00F5" (see above).
But, 2 functions both return just "0000000000000000".
I have some mistakes?
By the way, if I use "setClbBits" function before "getClbBits",
"getClbBits" returns correct values set by "setClbBits".
But, in this case, an external LED is always same state (does not do
any action like blanking). So, I think changed values are not
reflected.
In addtion, I have checked floorplan of this design.
SLICE_X6Y6 is certainly reserved.
Please tell me if you have a solution.
Thank you.
Hiroyuki
Article: 126787Denkedran Joe a écrit : > So my idea was to put the question to all of you what to do in case of > uncompressibility? Any ideas? Hi, Generally, a compression algorithm may be optimized for a type of data, or for a "packet" of data (ie with dynamic table building huffman compression, with different algorithms for video, sound or exe files, etc). If you can find two (or more) complementary algorithms (or sets of fixed parameters for a single algo) that covers the whole flows, you can dynamically switch between them, without transmitting the parameters. The known of the data flow may help you. Ie, if you may have to transmit an already compressed packet, your problem may have not any solution.Article: 126788
Hans-Peter Diettrich wrote: > cms wrote: > >> It isin't right to applicate lossless algorithms to >> fixed-bandwidth systems. > > Depends on the algorithm. E.g. RLE will never cause an increase in > size, what's sufficient even for use with fixed-bandwidth channels. Nit. Depends on the data. You have to have something to separate a repetition count from a new value, which implies a lost char (or more) somewhere. However, any such expansion can be expected to be small. -- Chuck F (cbfalconer at maineline dot net) <http://cbfalconer.home.att.net> Try the download section. -- Posted via a free Usenet account from http://www.teranews.comArticle: 126789
CBFalconer <cbfalconer@yahoo.com> writes: > Hans-Peter Diettrich wrote: > > cms wrote: > > > >> It isin't right to applicate lossless algorithms to > >> fixed-bandwidth systems. > > > > Depends on the algorithm. E.g. RLE will never cause an increase in > > size, what's sufficient even for use with fixed-bandwidth channels. > > Nit. Depends on the data. You have to have something to separate > a repetition count from a new value, which implies a lost char (or > more) somewhere. However, any such expansion can be expected to be > small. Most RLEs can be caused to explode horribly, simply by peppering the file with the value used as the escape code(s). Packbits solves this problem, and it will never expand more than a small fraction, as it escapes both blocks of literals and runs. Phil -- Dear aunt, let's set so double the killer delete select all. -- Microsoft voice recognition live demonstrationArticle: 126790
blisca wrote: > Hi > I had to use version 7.1 because 9.2 looks too heavy for my old pc > > I tried to generate internal block memory,but i have the following message > > > Customizing IP > An error occurred during customization ISE sure seems to have a lot of "issues"... I have the same version (web edition 8.1) on two machines and the CoreGen simply refuses to cooperate on one of them. Does your path include spaces (e.g. "Program Files\Xilinx ISE"? If so, try reinstalling the ISE to e.g. "C:\Xilinx" (assuming that you're using Windows), maybe this will help. And then again, maybe not. Hope it does. RGArticle: 126791
On Dec 1, 10:49 am, tang <tarangpatel2elect...@gmail.com> wrote: > On Dec 1, 1:59 am, John Adair <g...@enterpoint.co.uk> wrote: > > > > > > > There are a large number of ways you could do this. Personally I'm not > > a get fan of next state, current state, style you use but it does have > > it's followers. > > > Staying with what you have I would check the asychronous > > (combinatorial) processes have complete sensativity lists. Your > > clocked processes I would make sure all statements lie with the clock > > and reset statements. > > > Personally I would have a counter that reloaded with values linked to > > the transitions of the state machine and taking a count value relevant > > to the state being entered. The counter then counts down to zero and > > then the next state transition. If you make your counter integer type > > you don't need extra numerical type libraries. > > > John Adair > > Enterpoint Ltd. - Home of Craignells The obsolete DIL solution. > > > On 30 Nov, 22:12, tang <tarangpatel2elect...@gmail.com> wrote: > > > > hey guys i hope u can help me out... i want to design a simple traffic > > > light controller according to the 4 states shown in the code below. my > > > only problem is that my signal state_reg is not changing form one > > > state to another. this is because the counter i included in the the > > > code as a process is not working. green to yellow time wait is 30 sec > > > and yellow to red is 5 sec. my clock period will be 5 sec. so can > > > anyone help me out > > > > -------------------------------------------------------------------------------------------------------------------------------------------------------------- > > > library ieee; > > > use ieee.std_logic_1164.all; > > > use ieee.std_logic_arith.all; > > > use IEEE.std_logic_unsigned.all; > > > > entity TLC is > > > port( > > > clk,reset, sa, sb:in std_logic; > > > Ga, Ya, Ra, Gb, Yb, Rb:out std_logic > > > ); > > > end TLC; > > > > architecture Behavioral of TLC is > > > > type state_type is (a, b, c, d); > > > signal state_reg, state_next: state_type; > > > signal Pre_Q, Q: std_logic_vector(3 downto 0); > > > signal count, clear: std_logic; > > > > begin > > > > -- behavior describe the counter > > > process(clk, count, clear) > > > begin > > > if (clear = '0') then > > > Pre_Q <= Pre_Q - Pre_Q; > > > elsif (clk='1' and clk'event) then > > > if (count = '1') then > > > Pre_Q <= Pre_Q + 1; > > > end if; > > > end if; > > > Q <= Pre_Q; > > > end process; > > > > -- state register > > > > process(clk,reset) > > > begin > > > if(reset='0') then > > > state_reg <= a; > > > elsif (clk'event and clk='1') then > > > state_reg <= state_next; > > > end if; > > > end process; > > > > -- next state logic > > > > process(state_reg,Q,sa,sb) > > > begin > > > > case state_reg is > > > when a => > > > if(sa = '1' and sb = '0')then > > > state_next <= a; > > > elsif (sa = '0' and sb = '1') then > > > count <= '1'; > > > if(Q = "0110") then > > > state_next <= b; > > > end if; > > > end if; > > > > when b => > > > > if(Q = "0111") then > > > state_next <= c; > > > count <= '0'; > > > elsif(sa = '1') then > > > state_next <= b; > > > end if; > > > > when c => > > > if(sa = '0' and sb = '1') then > > > state_next <= c; > > > elsif (sa = '1' and sb ='0') then > > > clear <= '0'; > > > count <= '1'; > > > if(Q = "0110") then > > > state_next <= d; > > > > end if; > > > end if; > > > > when d => > > > > if(Q = "0111") then > > > state_next <= a; > > > count <= '0'; > > > elsif(sb = '1') then > > > state_next <= d; > > > end if; > > > end case; > > > end process; > > > > process (state_reg) > > > begin > > > Ga <= '1'; Ya <= '0'; Ra <= '0'; > > > Gb <= '0'; Yb <= '0'; Rb <= '1'; > > > > case state_reg is > > > when a => > > > when b => > > > Ga <= '0'; > > > Ya <= '1'; > > > > when c => > > > Ya <= '0'; > > > Ra <= '1'; > > > Gb <= '1'; > > > > when d => > > > Gb <= '0'; > > > Yb <= '1'; > > > > end case; > > > > end process; > > > > end Behavioral; > > > ------------------------------------------------------------------------------------------------------------------------------------------------------------ > > Thanx for the solution. I was also thinking about making counter > integer. Can you please elaborate on that? will it be like adding for > loop till count reach to desired value and then perform the > transition? > thanx again- Hide quoted text - > > - Show quoted text - How many mega herzts will your red light controller run at ?Article: 126792
Hi, Thomas Feller wrote: > Michael Laajanen wrote: > >>Hi, >> >>I am trying to install ISE 9.2 on a Fedora 8 machine, but have numerous >>problems. >> >>Is there anyone that managed to do this? >> >>/michael > > > Hi Michael, > > perhaps it would help if you supply some error messages. Maybe someone > has had the same problems with another distro. > > regards > Thomas Thanks Thomas for the reply, sorry for beeing so late in respondig. First I did not pass the setup due to some libstd+.. something and I can not right now check what it was exactly due to I changed from Fedora 8 to CentOS which starts better but have other difficulties. Using CentOS I can install fine, ISE 9.2 SP3, but XST crashes with a internal error on a certain project. So I tried as along shoot to upgrade coregen to the latest(update #2) which fails with a CRC checksum error (: very annoying. The environment we have is strictly shell based and the same "Make" is working fine on Solaris(as always), so there must be some picky things that Xilinx have done which makes it need RedHat that bad. We are moving from a Solaris installation to Linux and I have been avoiding this just because of things like this, Solaris have always been rock solid, we even use XACT 5.2.1 still on Solaris 11 without any problems and XACT 5 is old very old :) Do you have experience in ISE on Linux? cheers MichaelArticle: 126793
On Nov 29, 11:29 pm, Mark McDougall <ma...@vl.com.au> wrote: > Tricky wrote: > > Have you checked to see if ISE hasnt optimised the logic connected to > > those signals away (like you said, often caused by an unconnected > > clock)? Use a post synthesis RTL and Technology veiw to have a look. > > Quartus has them, Im sure ISE must have them too. > > OK, now I am officially insane! > > I have 2 projects with a lot of common modules which I have been porting > to Xilinx. The 1st has no video output, the 2nd works perfectly. > > I was looking at the RTL viewer for the video controller (common to both) > for the 1st project with no video. It shows the X pixel output as being > tied to GND, and NO y pixel output at all! I can't explain why it has > decided to do this, but it would explain why there is no video. > > So I go to the working project, and view the RTL for the same controller. > It TOO shows X pixel output tied to GND and NO y pixel output!!!! Let me > reming you, this project works perfectly! > > So there you have it, I am certifiably insane! Either I have no clue what > I am looking at, or Xilinx RTL viewer is complete and utter garbage!?! I'm > willing to accept either hypothesis as being true at this point... > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 When ISE acts weird, clicking on PROJECT/Cleanup Project Files, and then re-synthesizing often works. -Dave PollumArticle: 126794
The Flancter circuit is described in an article by Rob Weinstein of
Memec in Xilinx Xcell Journal issue 37 page 54. The PDF of the entire
issue is on Xilinx' FTP server:
ftp://ftp.xilinx.com/pub/documentation/xcell/xcell37.pdf
The article makes mention of a Memec application note on the Flancter,
but the URL is stale and Google doesn't seem to find it. Does anyone
have a copy squirreled away?
Thanks!
Eric
Article: 126795Michael Laajanen wrote: > First I did not pass the setup due to some libstd+.. something and I > can not right now check what it was exactly due to I changed from > Fedora 8 to CentOS which starts better but have other difficulties. The Xilinx tools are compiled with a relatively old toolchain to support RHEL3 and 4. To run them on any of the last several Fedora releases, install the Fedora package compat-libstdc++-33. I've had good results on Fedora 7 but haven't yet tried them on Fedora 8. EricArticle: 126796
I've been looking into reconfigurable computing as a research topic for my final year project in Computer Science. I've pretty much settled on this topic but am struggling to figure out what exactly im going to do with it, I was thinking of my own implementation of a processor with some sort of custom function unit (in VHDL). I've read a few papers on various implementations (GARP, Molen, etc) but still don't really have a comfortable grounding. Other than asking for more information that anyone would feel is helpful on this topic, does anyone have any ideas on specific areas of reconfigurable computing I could possibly look at? I am tied to the Xilinx Virtex II Pro board (http://www.xilinx.com/ univ/xupv2p.html). Any ideas/suggestions would be helpful. Thanks!Article: 126797
On 2007-12-01, create <paraliczb@NO_SPAM_orange.pl> wrote: > > I have problem with write and read and I use 50Mhz clock.. > Especially BURST-MODE is wrong. > > Is problem too litle clock or only too fast? No. I didn't check that particular chip, but many of those have options for linear and interleaved bursting. Are you selecting the one you want? -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 126798
Eric Smith wrote: > Michael Laajanen wrote: >> First I did not pass the setup due to some libstd+.. something and I >> can not right now check what it was exactly due to I changed from >> Fedora 8 to CentOS which starts better but have other difficulties. > > The Xilinx tools are compiled with a relatively old toolchain to support > RHEL3 and 4. To run them on any of the last several Fedora releases, > install the Fedora package compat-libstdc++-33. I've had good results > on Fedora 7 but haven't yet tried them on Fedora 8. > > Eric I've had good luck installing ISE9.2 and Webpack under Ubuntu. In fact I have much better luck with everything under Ubuntu. RH and Fedora takes a lot of fiddling in my experience. Try Ubuntu. PeteArticle: 126799
Brian Davis wrote: > But only when: > - decode_field is an alias (signals work ok) > - the constant CS2_ADDRESS has the MSB set > - the old std_logic_signed package is used > ( numeric_std, or just std_logic_unsigned."+" is ok) Thanks for the tip Brian! This is certainly a possibility, as I'm a big fan of aliases... I'll look into it with this in mind! How you found that, I have no idea, but thanks again! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
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