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Threads Starting Mar 1997

5616: 97/03/01: Richard Schwarz: ACTEL RAM BASED FPGAs
    5740: 97/03/11: Jaap Mol: Re: ACTEL RAM BASED FPGAs
        5744: 97/03/11: Ray Andraka: Re: ACTEL RAM BASED FPGAs
        5751: 97/03/12: Petter Gustad: Re: ACTEL RAM BASED FPGAs
        5778: 97/03/14: Hans Tiggeler: Re: ACTEL RAM BASED FPGAs
            5784: 97/03/14: Steven K. Knapp: Re: ACTEL RAM BASED FPGAs
            5802: 97/03/16: Peter Alfke: Re: ACTEL RAM BASED FPGAs
                5805: 97/03/16: Richard Schwarz: Re: ACTEL RAM BASED FPGAs
5618: 97/03/01: 1997 International Symposium on Physical Design: ISPD-97 Advance Pgm & Registration: (April 14-16, Napa CA)
5619: 97/03/01: ACM/PDW Treasurer: ISPD-97 Advance Pgm & Registration: (April 14-16, Napa CA)
5620: 97/03/02: Peter Fenn: Printing VHDL source?
5624: 97/03/03: <orachat@imap2.asu.edu>: Using internal clock of XC4000
    5629: 97/03/03: Philip Freidin: Re: Using internal clock of XC4000
5625: 97/03/03: Chris Hart: Place and Route on Pentium Pro Benchmark?
    5630: 97/03/03: Paulo Dutra: Re: Place and Route on Pentium Pro Benchmark?
        5648: 97/03/04: Symon Brewer: Re: Place and Route on Pentium Pro Benchmark?
    5649: 97/03/04: Gerhard Hoffmann: Re: Place and Route on Pentium Pro Benchmark?
        5769: 97/03/13: Humberto Honda: Re: Place and Route on Pentium Pro Benchmark?
5626: 97/03/03: Andreas Kugel: JTAG config on ALTERA FLEX10K10: How?
    5633: 97/03/03: Daniel Lang: Re: JTAG config on ALTERA FLEX10K10: How?
    5636: 97/03/03: David Atkins: Re: JTAG config on ALTERA FLEX10K10: How?
    5637: 97/03/03: Steve Baldwin: Re: JTAG config on ALTERA FLEX10K10: How?
        5640: 97/03/04: Andreas Kugel: Re: JTAG config on ALTERA FLEX10K10: How?
        5641: 97/03/04: Andreas Kugel: Re: JTAG config on ALTERA FLEX10K10: How?
        5642: 97/03/04: Andreas Kugel: Re: JTAG config on ALTERA FLEX10K10: How?
        5643: 97/03/04: Andreas Kugel: Re: JTAG config on ALTERA FLEX10K10: How?
        5644: 97/03/04: Andreas Kugel: Re: JTAG config on ALTERA FLEX10K10: How?
        5646: 97/03/04: Andreas Kugel: Re: JTAG config on ALTERA FLEX10K10: How?
        5650: 97/03/04: Andreas Kugel: Re: JTAG config on ALTERA FLEX10K10: How?
            5678: 97/03/06: Jörgen Båth: Re: JTAG config on ALTERA FLEX10K10: How?
                5693: 97/03/07: Andreas Kugel: Re: JTAG config on ALTERA FLEX10K10: How? SUMMARY
5628: 97/03/03: Anders Kugler: XILINX xchecker drivers on HP
5632: 97/03/03: Don Wilkerson: Altera 10K50 Demo Board?
5638: 97/03/04: Larry Chen: Motorola 68HC16 background debugger
5647: 97/03/04: Henry Selvaraj: ICCIMA'98 Call for papers (includes a special session on Logic Synthesis and AI)
5651: 97/03/04: Fabio Somenzi: VIS 1.2 Released
5652: 97/03/04: Andreas Doering: ALTERA MAX9000 BSCAN
5655: 97/03/04: Henry Thomas: Timing simulator for Warp 4.1 that works under Win NT 4.0
    5671: 97/03/05: Steve Wiseman: Re: Timing simulator for Warp 4.1 that works under Win NT 4.0
    5690: 97/03/07: Daniel J. Morelli: Re: Timing simulator for Warp 4.1 that works under Win NT 4.0
        5727: 97/03/11: Henry Thomas: Re: Timing simulator for Warp 4.1 that works under Win NT 4.0
5657: 97/03/04: Rich K.: viewlogic ...
    5661: 97/03/05: Peter: Re: viewlogic ...
        5663: 97/03/05: Austin Franklin: Re: viewlogic ...
            5696: 97/03/07: Peter: Re: viewlogic ...
    5817: 97/03/18: David Pashley: Re: viewlogic ...
        5823: 97/03/18: Rich K.: Re: viewlogic ...
5662: 97/03/05: Nils Koehler: Altera LPM_MUX Function
    5682: 97/03/06: Woody Johnson: Re: Altera LPM_MUX Function
5665: 97/03/05: Willy: XILINX LIBRARY FOR VIEWLOGIC
    5668: 97/03/05: Philip Freidin: Re: XILINX LIBRARY FOR VIEWLOGIC
5667: 97/03/05: Wayne Turner: Re: Altera support better than Xilinx
    5674: 97/03/05: Rhondalee Rohleder: Re: Altera support better than Xilinx
        5706: 97/03/09: Wayne Turner: Re: Altera support better than Xilinx
5669: 97/03/05: David Lawrence Hoenig: Opinions on Cypress/PCI?
    5697: 97/03/07: Dan Dixon: Re: Opinions on Cypress/PCI?
5675: 97/03/05: Jeffrey M. Arnold: FCCM'97 Registration and Hotel Information
5677: 97/03/06: Gerhard Wiesinger: Problem with Synopsys/Altera interface
5679: 97/03/06: Louis Zhang: Xilinx 4002 RAM Question
    5686: 97/03/07: Steven K. Knapp: Re: Xilinx 4002 RAM Question
    5688: 97/03/07: Jan Gray: Re: Xilinx 4002 RAM Question
        5724: 97/03/11: Louis Zhang: Re: Xilinx 4002 RAM Question
            5789: 97/03/14: Peter Alfke: Re: Xilinx 4002 RAM Question
                5827: 97/03/19: Gavin Hurlbut: Re: Xilinx 4002 RAM Question
                    5842: 97/03/20: Gavin Hurlbut: Re: Xilinx 4002 RAM Question
                    5853: 97/03/20: Louis Zhang: Re: Xilinx 4002 RAM Question
    5700: 97/03/08: David R Brooks: Re: Xilinx 4002 RAM Question
5681: 97/03/06: Oleg Sheynin: Waveform files from Workview into WVOffice
5683: 97/03/07: Mark Osterud: FPGA Reliability
    5752: 97/03/12: Peter Alfke: Re: FPGA Reliability
        5770: 97/03/13: Rich K.: Re: FPGA Reliability
            5782: 97/03/14: Kardos, Botond: Re: FPGA Reliability - JTAG reset
5684: 97/03/07: Samir Marc Falaki: DEVICE SELECTION
    5694: 97/03/07: Keith D. Brown: Re: DEVICE SELECTION
    5719: 97/03/10: Ed Vogel: Re: DEVICE SELECTION
    5749: 97/03/12: Richard Schwarz: Re: DEVICE SELECTION
5685: 97/03/06: Renoir Support: Introducing Renoir
    5698: 97/03/07: Jim Mrowca: Re: Introducing Renoir
        5716: 97/03/10: suzanne M southworth: Re: Introducing Renoir
            5734: 97/03/11: Rudolf Simbuerger: Re: Introducing Renoir
        5720: 97/03/10: Renoir Support: Re: Introducing Renoir
    5709: 97/03/10: Don Husby: Galileo... Leonardo... Renoir... ?
        5726: 97/03/10: Thomas Rock: Re: Galileo... Leonardo... Renoir... ?
    5715: 97/03/10: Steve Bird: Re: Galileo... Leonardo... Renoir... ?
    5730: 97/03/11: Uwe Bonnes: Re: Introducing Renoir
        5731: 97/03/11: Nick Weavers: Re: Introducing Renoir
        5741: 97/03/11: Paolo Spazzini: Re: Introducing Renoir
    5747: 97/03/12: Don Husby: Re: Galileo... Leonardo... Renoir... ?
    5791: 97/03/14: jim granville: Re: Galileo... Leonardo... Renoir... ?
5689: 97/03/07: Andreas Wehr: Xilinx config pins M0..M2
    5699: 97/03/07: Ray Andraka: Re: Xilinx config pins M0..M2
    5714: 97/03/10: Steven K. Knapp: Re: Xilinx config pins M0..M2
5702: 97/03/08: 1997 International Symposium on Physical Design: ISPD-97 (final week for early registration)
5703: 97/03/08: ACM/PDW Treasurer: ISPD-97 (final week for early registration)
5704: 97/03/09: Stuart Summerville: Xil FPGA: Usage of Multi-purpose pins as I/O
    5707: 97/03/09: Tom Burgess: Re: Xil FPGA: Usage of Multi-purpose pins as I/O
    5718: 97/03/10: Brad Taylor: Re: Xil FPGA: Usage of Multi-purpose pins as I/O
    5745: 97/03/11: Peter Alfke: Re: Xil FPGA: Usage of Multi-purpose pins as I/O
        5765: 97/03/13: Alan Weir: Re: Xil FPGA: Usage of Multi-purpose pins as I/O
5712: 97/03/10: Christos Dimitrakakis: Xilinx FPGA & SIMMs
    5717: 97/03/10: Ray Andraka: Re: Xilinx FPGA & SIMMs
        5725: 97/03/10: Peter Alfke: Re: Xilinx FPGA & SIMMs
    5736: 97/03/11: John L. Smith: Re: Xilinx FPGA & SIMMs
    5787: 97/03/14: Andrew Papageorgiou: Re: Xilinx FPGA & SIMMs
5713: 97/03/10: Peter Wurbs: Accolade
    5786: 97/03/14: Joel Kolstad: Re: Accolade
        5790: 97/03/15: <c-d-symes@worldnet.att.net>: Re: Accolade
            5848: 97/03/20: Hans Tiggeler: Re: Accolade
                5890: 97/03/23: Richard Schwarz: Re: Accolade
        5800: 97/03/16: David Pellerin: Re: Accolade
5733: 97/03/11: Rich K.: viewoffice compatibility - dumb question
    5759: 97/03/13: bob elkind: Re: viewoffice compatibility - dumb question
        5812: 97/03/17: Rich K.: Re: viewoffice compatibility - dumb question
5735: 97/03/11: Daniel Alley: How to tell number of or name of Viewlogic users on PC network under site license?
5737: 97/03/11: Linda Boyd: COURSE: High Level Design Using VHDL, March 31 - April 4
5742: 97/03/11: Shantanu Tarafdar: Fatal exception under Win95 & XACT v6.0.1
    5746: 97/03/12: Paul Taylor: Re: Fatal exception under Win95 & XACT v6.0.1
        5775: 97/03/13: Peter: Re: Fatal exception under Win95 & XACT v6.0.1
5743: 97/03/11: Todd A. Kline: VHDL & ABEL synthesis tools on 95/NT
    5748: 97/03/12: Richard Schwarz: Re: VHDL & ABEL synthesis tools on 95/NT
    5757: 97/03/12: Andreas Kugel: Re: VHDL & ABEL synthesis tools on 95/NT
        5792: 97/03/15: Richard Schwarz: Re: VHDL & ABEL synthesis tools on 95/NT
        5801: 97/03/16: David Pellerin: Re: VHDL & ABEL synthesis tools on 95/NT
        5810: 97/03/17: Tom Bowns: Re: VHDL & ABEL synthesis tools on 95/NT
            5859: 97/03/20: Phil Ngai: Re: VHDL & ABEL synthesis tools on 95/NT
5750: 97/03/12: Steve Gross: Xilinx/NeoCAD software vs. XC4KE question
    5760: 97/03/13: bob elkind: Re: Xilinx/NeoCAD software vs. XC4KE question
        5806: 97/03/16: Richard Schwarz: Re: Xilinx/NeoCAD software vs. XC4KE question
5755: 97/03/12: Rod Leiting: Viewlogic/Xilinx questions
5756: 97/03/12: Hari Shankar: Development board with multiple FPGAs
    5758: 97/03/12: Stuart Clubb: Re: Development board with multiple FPGAs
        5779: 97/03/14: Richard Schwarz: Re: Development board with multiple FPGAs
            5860: 97/03/20: Steve Nordhauser: Re: Development board with multiple FPGAs
                5875: 97/03/21: Steven K. Knapp: Re: Development board with multiple FPGAs
                    5939: 97/03/27: Steven K. Knapp: Re: Development board with multiple FPGAs
    5819: 97/03/18: Kevin M. Olson: Re: Development board with multiple FPGAs
        5821: 97/03/18: Steven K. Knapp: Re: Development board with multiple FPGAs
        5824: 97/03/18: Martine Schlag: Re: Development board with multiple FPGAs
    5832: 97/03/19: Laurent Moll: Re: Development board with multiple FPGAs
5761: 97/03/13: <frank_xie@writeme.com>: How to count the total numbers of Product Term for Altera MaxPlusII compiler report?
    5783: 97/03/14: Kardos, Botond: Re: How to count the total numbers of Product Term for Altera MaxPlusII compiler report?
5762: 97/03/13: <frank_xie@writeme.com>: The Logic Level of design using Altera devices
5766: 97/03/13: Insight/Xilinx: VHDL Training Course, April 10 & 11
5767: 97/03/13: Insight/Xilinx: Xilinx Schematic Based Training, Rockville,MD April 7-9
5771: 97/03/13: <rcgipson@ix.netcom.com>: pld 74hc195 equiv
    5780: 97/03/14: Geoffrey Bostock: Re: pld 74hc195 equiv
    5811: 97/03/17: Peter Alfke: Re: pld 74hc195 equiv
5777: 97/03/14: <asa@lan.novsu.ac.ru>: PCI user_defined project on ALTERA FLEX chips. E-mail <rastr@lan.novsu.ac.ru>
5781: 97/03/14: Craig Slorach: EDIF Format Specification
5788: 97/03/14: Insight/Xilinx: Free Xilinx 9500 Seminar. Gaithersburg,MD March 19
5793: 97/03/15: Four D Electronics: Pentium 166 with AA type Keys
    5797: 97/03/16: Philip Freidin: Re: Pentium 166 with AA type Keys
5794: 97/03/16: 1997 International Symposium on Physical Design: ISPD-97 (Important Announcement RE Hotel & Registration)
5795: 97/03/16: ACM/PDW Treasurer: ISPD-97 (Important Announcement RE Hotel & Registration)
5796: 97/03/15: <takecards@answerme.com>: ACCEPT MAJOR CREDIT CARDS !!!!!!
5798: 97/03/16: Gabby Shpirer: PEEL16V8 with PALASM
    5799: 97/03/16: Steve Wiseman: Re: PEEL16V8 with PALASM
    5813: 97/03/17: Werner Dreher: Re: PEEL16V8 with PALASM
5807: 97/03/17: Apolonio B. Sanches: PLC
    5815: 97/03/17: Brad Taylor: Re: PLC
    5825: 97/03/18: Paul Jones: Re: PLC
        5838: 97/03/19: "Paul E. Bennett": Re: PLC
5808: 97/03/17: Kari Laiholuoto: Synopsys -> Altera (maxplus2) interface
    5814: 97/03/17: John C. Peck, Jr.: Re: Synopsys -> Altera (maxplus2) interface
5809: 97/03/17: Jon Saul: Reminder: Reed-Muller 97 -- Int. Workshop on Function Representations
5816: 97/03/18: CISCO SYSTEMS: Cisco's SIBU is looking for ASIC and Systems Engineers
5820: 97/03/18: David Gesswein: Multiple clocks in Xilinx
    5828: 97/03/18: Brad Taylor: Re: Multiple clocks in Xilinx
        5829: 97/03/18: Brad Taylor: Re: Multiple clocks in Xilinx
            5836: 97/03/19: Peter Alfke: Re: Multiple clocks in Xilinx
                5845: 97/03/20: Peter: Re: Multiple clocks in Xilinx
                    5861: 97/03/20: David R Brooks: Re: Multiple clocks in Xilinx
                    5871: 97/03/21: steve goodwin: Re: Multiple clocks in Xilinx
                        5880: 97/03/22: Peter: Re: Multiple clocks in Xilinx
                5852: 97/03/20: Brad Taylor: Re: Multiple clocks in Xilinx
5822: 97/03/18: Jeffrey M. Arnold: FCCM'97 Preliminary Program
    5833: 97/03/19: Peter Alfke: Re: FCCM'97 Preliminary Program
        5835: 97/03/19: Peter Alfke: Re: FCCM'97 Preliminary Program
5826: 97/03/18: Dirk Brandis: EDA tools
    5831: 97/03/19: <timolmst@cyberramp.net>: Re: EDA tools
5830: 97/03/19: Garnet Brace: Sole source
    5837: 97/03/19: Peter Alfke: Re: Sole source
        5846: 97/03/20: Andrew Morley: Re: Sole source
        5873: 97/03/21: Henry Spencer: Re: Sole source
            5889: 97/03/23: Richard Schwarz: Re: Sole source
    5841: 97/03/20: James West: Re: Sole source
    5930: 97/03/27: Andrew Metcalfe: Re: Sole source
        5945: 97/03/28: Peter: Re: Sole source
            5953: 97/03/30: Tom Burgess: Re: Sole source
                5961: 97/03/31: Peter Alfke: Re: Sole source
                    5982: 97/04/02: Steve Wiseman: Re: Sole source
                        6009: 97/04/04: Peter Alfke: Re: Sole source
                            6042: 97/04/07: Martin d'Anjou: Chip Temperature (was:Re: Sole source)
                                6050: 97/04/08: Martin d'Anjou: Re: Chip Temperature (was:Re: Sole source)
                                6052: 97/04/08: Henry Spencer: Re: Chip Temperature (was:Re: Sole source)
                                6054: 97/04/08: Jason T. Wright: Re: Chip Temperature (was:Re: Sole source)
                                    6070: 97/04/09: Steven K. Knapp: Re: Chip Temperature (was:Re: Sole source)
                                        6083: 97/04/10: Peter Alfke: Re: Chip Temperature (was:Re: Sole source)
                            6047: 97/04/07: Tom Burgess: Re: Sole source
                                6092: 97/04/11: jim granville: Re: Sole source
                                    6096: 97/04/11: Tom Burgess: Re: Sole source
                            6051: 97/04/08: Henry Spencer: temperature (was Re: Sole source)
                    6003: 97/04/03: Tom Burgess: Re: Sole source
                5963: 97/03/31: Peter: Re: Sole source
                    5964: 97/03/31: Thomas D. Tessier: Re: Sole source
    5994: 97/04/03: Gareth Baron: Re: Sole source
    6066: 97/04/09: Gareth Baron: Re: Chip Temperature (was:Re: Sole source)
5839: 97/03/20: Kent: Is this really possible?
    5843: 97/03/20: Nicholas C. Weaver: Re: Is this really possible?
        5857: 97/03/20: Peter Alfke: Re: Is this really possible?
    5850: 97/03/20: Ray Andraka: Re: Is this really possible?
        5856: 97/03/20: Roger Kinkead: Re: Is this really possible?
            5869: 97/03/21: Roger Kinkead: Re: Is this really possible?
            5881: 97/03/22: David R Brooks: Re: Is this really possible?
    5858: 97/03/20: David Buckley: Re: Is this really possible?
5840: 97/03/19: Gregory M. Haskins: Lattice software
5844: 97/03/20: Wolfram Seibold: PCI & Altera
5849: 97/03/20: Ian Page: Research Posts Available at Oxford
5851: 97/03/20: Stuart Summerville: Viewlogic Licensing delays?? Anyone?
    5910: 97/03/25: Austin Franklin: Re: Viewlogic Licensing delays?? Anyone?
5854: 97/03/20: Rick Filipkiewicz: Re: Sole source
    5878: 97/03/21: Peter Alfke: Re: Sole source
        5884: 97/03/23: Henry Spencer: Re: Sole source
            5898: 97/03/24: Peter Alfke: Re: Sole source
            5902: 97/03/25: Gerry Belanger: Re: Sole source
                5906: 97/03/25: Peter: Re: Sole source
                    5929: 97/03/27: Gerry Belanger: Re: Sole source
        5886: 97/03/23: Peter: Re: Sole source
        5887: 97/03/23: Tom Burgess: Re: Sole source
5855: 97/03/20: CISCO SYSTEMS: Cisco's SIBU is looking for ASIC and Systems Engineers
5862: 97/03/21: Alec Cosic: FPGA and PLL
5863: 97/03/20: Greg Quintana: FIFOs
    5877: 97/03/21: Peter Alfke: Re: FIFOs
    5883: 97/03/22: Brad and Renea Ree: Re: FIFOs
        5891: 97/03/23: Peter Alfke: Re: FIFOs
        5938: 97/03/27: Steven K. Knapp: Re: FIFOs
5864: 97/03/21: Samir Marc Falaki: FPGA CLB USAGE
5865: 97/03/21: Samir Marc Falaki: RENOIR DEMO CD
    5908: 97/03/25: Paolo Spazzini: Re: RENOIR DEMO CD
5866: 97/03/21: Samir Marc Falaki: BIT SERIAL MULTIPLY
    5867: 97/03/21: Andreas Kugel: Re: BIT SERIAL MULTIPLY
    5922: 97/03/26: R.W. DeHoedt: Re: BIT SERIAL MULTIPLY
5868: 97/03/21: Anthony Ellis: What tools for $8000?
    5888: 97/03/23: Richard Schwarz: Re: What tools for $8000?
    5897: 97/03/24: <timolmst@cyberramp.net>: Re: What tools for $8000?
    5936: 97/03/27: Steven K. Knapp: Re: What tools for $8000?
5870: 97/03/21: Johannes Soelhusvik: 8-bit divider in FPGA
    5874: 97/03/21: Pasquale Corsonello: Re: 8-bit divider in FPGA
    5879: 97/03/21: Tom Burgess: Re: 8-bit divider in FPGA
        5882: 97/03/22: Ray Andraka: Re: 8-bit divider in FPGA
        5895: 97/03/24: Johannes Soelhusvik: Re: 8-bit divider in FPGA
            5946: 97/03/28: Tom Burgess: Re: 8-bit divider in FPGA
            5970: 97/04/01: Robert M. Münch: Re: 8-bit divider in FPGA
        5900: 97/03/24: Andrew Papageorgiou: Re: 8-bit divider in FPGA
        5927: 97/03/26: Vitit Kantabutra: Re: 8-bit divider in FPGA
        5984: 97/04/02: Johannes Soelhusvik: Re: 8-bit divider in FPGA
5872: 97/03/21: FT/KD Patrik Eriksson: Problem loading XC4010E with XCHECKER!
    5899: 97/03/24: Wilfried Eisele: Re: Problem loading XC4010E with XCHECKER!
5876: 97/03/21: Mauro Fiorini: problem: my xc4003 don't work !!!!
    5892: 97/03/23: Peter Alfke: Re: problem: my xc4003 don't work !!!!
5893: 97/03/24: Henry Selvaraj: ICCIMA'98 Special Sessions - First CFP
5894: 97/03/24: Christos Dimitrakakis: fast resampling
    5960: 97/03/31: Peter Alfke: Re: fast resampling
5896: 97/03/24: Michael Niechziol: ZYCAD's 'browse'
5901: 97/03/25: Frank Xie: Is there anyone interested in FPGA or CPLD?
5903: 97/03/24: webmaster: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
    5904: 97/03/25: Dodderin' Ol' Don: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
        5914: 97/03/25: webmaster: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
            5926: 97/03/26: Henry Spencer: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
                5940: 97/03/27: Mark Zenier: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
    5905: 97/03/25: Chris Wright: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
    5915: 97/03/25: webmaster: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
    5917: 97/03/26: Chris Wright: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
    5920: 97/03/26: <rstevew@armory.butfukspam.com>: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
        5947: 97/03/28: Henry Davis: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
5907: 97/03/25: kwong lau hei: Xilinx 4013 cannot configuration
    5913: 97/03/26: Philip Freidin: Re: Xilinx 4013 cannot configuration
    5918: 97/03/26: Peter Alfke: Re: Xilinx 4013 cannot configuration
    5934: 97/03/27: Peter Alfke: Re: Xilinx 4013 cannot configuration
5909: 97/03/25: Rich K.: viewoffice <--> viewoffice compatibility
    5937: 97/03/27: Steven K. Knapp: Re: viewoffice <--> viewoffice compatibility
        5941: 97/03/27: Rich K.: Re: viewoffice <--> viewoffice compatibility
            5951: 97/03/29: Paul Surma: Re: viewoffice <--> viewoffice compatibility
                5952: 97/03/29: <who@is.this.com>: Re: viewoffice <--> viewoffice compatibility
            6080: 97/04/10: Scott Evans: Re: viewoffice <--> viewoffice compatibility
                6086: 97/04/10: Rich K.: Re: viewoffice <--> viewoffice compatibility
    5948: 97/03/28: Mark Woods: Re: viewoffice <--> viewoffice compatibility
5911: 97/03/25: CISCO SYSTEMS: Cisco's SIBU is looking for ASIC and Systems Engineers
5912: 97/03/25: Mike Butts: FCCM '96 Top Ten Predictions
5916: 97/03/26: Philip Freidin: Viewlogic, A company that listens
5921: 97/03/26: Rob Hurley: ANNOUNCE: New FREE Tip and Model of the Month
5923: 97/03/26: Tactics: Consulting Opportunity
5924: 97/03/26: Name Deleted: Looking for a Digital Design Job!
5925: 97/03/26: Justin Morgan: Software602, Inc.
5928: 97/03/27: Simon Bacon: Xilinx XC6200 -- any sightings?
    5935: 97/03/27: Steven K. Knapp: Re: Xilinx XC6200 -- any sightings?
        5944: 97/03/28: Steve Casselman: Re: Xilinx XC6200 -- any sightings?
5931: 97/03/27: lzh: verilog to VHDL tools needed!
    6013: 97/04/04: <sanjay@edadirect.com>: Re: verilog to VHDL tools needed!
5932: 97/03/27: Tore H. Larsen: Any FPGA with 6809 core?
    5950: 97/03/29: Steven K. Knapp: Re: Any FPGA with 6809 core?
    5959: 97/03/31: Eric Ryherd: Re: Any FPGA with 6809 core?
5933: 97/03/27: K. S. Venkatraman: Computer Architecture - IC design position wanted
5942: 97/03/27: Richard J. Auletta: Xilinx RAM & Synopsys BC
5943: 97/03/28: markn: HELP! - peel programming?
    5949: 97/03/28: Henry Spencer: Re: HELP! - peel programming?
5956: 97/03/31: Richard Schwarz: Free VHDL /FPGA newsletter
    5957: 97/03/31: Jian Shen: clock edge specification for Synopsys synthesis
        5969: 97/04/01: Brandon Azbell: Re: clock edge specification for Synopsys synthesis
        6007: 97/04/04: Andrew Hana: Re: clock edge specification for Synopsys synthesis
        6026: 97/04/06: Jaap Mol: Re: clock edge specification for Synopsys synthesis
5958: 97/03/30: Kayvon Irani: System Level Integration on Deep submicron FPGAs
    5965: 97/03/31: Thomas D. Tessier: Re: System Level Integration on Deep submicron FPGAs
    6195: 97/04/24: Kate Meilicke: Re: System Level Integration on Deep submicron FPGAs
5962: 97/03/31: CISCO SYSTEMS: Cisco's SIBU is looking for ASIC and Systems Engineers
5966: 97/03/31: Wim Vanderstraeten: XC2018
    5967: 97/04/01: Austin Franklin: Re: XC2018
    5972: 97/04/01: Rhondalee Rohleder: Re: XC2018
    5993: 97/04/03: Geoffrey Bostock: Re: XC2018
        5998: 97/04/03: Peter Alfke: Re: XC2018
    5997: 97/04/03: <timolmst@cyberramp.net>: Re: XC2018


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