Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Threads Starting Feb 2002

39136: 02/02/01: Harjo Otten: Dual ported RAM in SpartanII, output = ?????
    39138: 02/02/01: Harjo Otten: Re: Dual ported RAM in SpartanII, output = ?????
    39143: 02/02/01: Peter Alfke: Re: Dual ported RAM in SpartanII, output = ?????
    39237: 02/02/04: Jay: Re: Dual ported RAM in SpartanII, output = ?????
        39247: 02/02/04: Peter Alfke: Re: Dual ported RAM in SpartanII, output = ?????
39148: 02/02/01: Dave Brown: Read Only Register
    39156: 02/02/02: Falk Brunner: Re: Read Only Register
39160: 02/02/02: AMID GUBTA: PAR prediction
39162: 02/02/02: Hristo Stevic: BRAM, clka too short setup time
    39163: 02/02/02: Hristo Stevic: Re: BRAM, clka too short setup time
        39172: 02/02/03: Falk Brunner: Re: BRAM, clka too short setup time
            39173: 02/02/03: Hristo Stevic: Re: BRAM, clka too short setup time
    39375: 02/02/07: Jay: Re: BRAM, clka too short setup time
39164: 02/02/03: Dr. Michael D. Foegelle: LARGE ultra low power FPGA/CPLD recommendation
    39168: 02/02/03: Jim Granville: Re: LARGE ultra low power FPGA/CPLD recommendation
    39171: 02/02/03: Falk Brunner: Re: LARGE ultra low power FPGA/CPLD recommendation
        39174: 02/02/03: Falk Brunner: Re: LARGE ultra low power FPGA/CPLD recommendation
    39236: 02/02/04: Jay: Re: LARGE ultra low power FPGA/CPLD recommendation
        39245: 02/02/05: Jim Granville: Re: LARGE ultra low power FPGA/CPLD recommendation
39165: 02/02/02: ug: odd divider
    39170: 02/02/03: Falk Brunner: Re: odd divider
39166: 02/02/02: strut911: solutions manuals, and no they are not for school
    39180: 02/02/03: Rick Lyons: Re: solutions manuals, and no they are not for school
        39188: 02/02/03: strut911: Re: solutions manuals, and no they are not for school
            39189: 02/02/03: Jerry Avins: Re: solutions manuals, and no they are not for school
            39198: 02/02/04: Steve: Re: solutions manuals, and no they are not for school
                39205: 02/02/04: Ray Andraka: Re: solutions manuals, and no they are not for school
                    39233: 02/02/04: Rick Filipkiewicz: Re: solutions manuals, and no they are not for school
                    39249: 02/02/04: Steve: Re: solutions manuals, and no they are not for school
                        39250: 02/02/04: Bob Cain: Re: solutions manuals, and no they are not for school
                            39260: 02/02/05: Rick Lyons: Re: solutions manuals, and no they are not for school
                                39285: 02/02/05: Jerry Avins: Re: solutions manuals, and no they are not for school
                                    39317: 02/02/06: Rick Lyons: Re: solutions manuals, and no they are not for school
                                39344: 02/02/06: Bob Cain: Re: solutions manuals, and no they are not for school
                                    39380: 02/02/07: Jerry Avins: Re: solutions manuals, and no they are not for school
                                        39396: 02/02/08: strut911: Re: solutions manuals, and no they are not for school
                                            39432: 02/02/08: Bob Cain: Re: solutions manuals, and no they are not for school
                                        39398: 02/02/08: Rick Lyons: Re: solutions manuals, and no they are not for school
                                            39417: 02/02/08: Jerry Avins: Re: solutions manuals, and no they are not for school
                                                39435: 02/02/09: Rick Lyons: Re: solutions manuals, and no they are not for school
                                                    39436: 02/02/09: Eric Jacobsen: Re: solutions manuals, and no they are not for school
                                                        39437: 02/02/09: Jerry Avins: Re: solutions manuals, and no they are not for school
                                                            39441: 02/02/10: Dr A.P. Whichello: Re: solutions manuals, and no they are not for school
                                                                39514: 02/02/12: Anthony J Bybell: Re: solutions manuals, and no they are not for school
                                    39397: 02/02/08: Rick Lyons: Re: solutions manuals, and no they are not for school
    39246: 02/02/04: Anthony J Bybell: Re: solutions manuals, and no they are not for school
39167: 02/02/03: Hitesh Brahmbhatt: To Prevent Xilinx Mapper from Removing the RAMs in ISE 4.1i
    39169: 02/02/03: Falk Brunner: Re: To Prevent Xilinx Mapper from Removing the RAMs in ISE 4.1i
39175: 02/02/03: Nurit Eliram: DCM relationship question
    39179: 02/02/03: Peter Alfke: Re: DCM relationship question
        39199: 02/02/04: Nurit Eliram: Re: DCM relationship question
            39272: 02/02/05: newman: Re: DCM relationship question
                39275: 02/02/05: Austin Lesea: Re: DCM relationship question
39176: 02/02/03: rickman: JTAG Boundary Scan with the XDS510
    39183: 02/02/03: Mark D'Sylva: Re: JTAG Boundary Scan with the XDS510
        39192: 02/02/04: Darrell Grainger: Re: JTAG Boundary Scan with the XDS510
            39193: 02/02/03: rickman: Re: JTAG Boundary Scan with the XDS510
                39228: 02/02/04: Par Ligander: Re: JTAG Boundary Scan with the XDS510
            39203: 02/02/04: Mark D'Sylva: Re: JTAG Boundary Scan with the XDS510
39177: 02/02/03: Hristo Stevic: F3.3 SP8
    39264: 02/02/05: Alex Jumper: Re: F3.3 SP8
39184: 02/02/03: adetaylor: Using Refinate to compare EDIF files and verify/create BOM
39185: 02/02/03: Richard Aikman: VHDL-FPGA design survey
39186: 02/02/04: David Miller: can comparisons glitch?
    39191: 02/02/04: Peter Alfke: Re: can comparisons glitch?
        39212: 02/02/04: Bryan: Re: can comparisons glitch?
            39219: 02/02/04: Falk Brunner: Re: can comparisons glitch?
39187: 02/02/03: niv: Coregen & PAR
    39254: 02/02/05: <hamish@cloud.net.au>: Re: Coregen & PAR
39195: 02/02/03: Antonio: MUX seelction question
    39202: 02/02/04: newman: Re: MUX seelction question
        39251: 02/02/04: Antonio: Re: MUX seelction question
39196: 02/02/03: Antonio: ClkEnable vs gated clock
    39206: 02/02/04: Ray Andraka: Re: ClkEnable vs gated clock
    39308: 02/02/05: Nurit Eliram: Re: ClkEnable vs gated clock
    39313: 02/02/06: Ray Andraka: Re: ClkEnable vs gated clock
39197: 02/02/03: Antonio: RAM question
    39204: 02/02/04: MANDY & DOUGLAS: Re: RAM question
    39208: 02/02/04: Ray Andraka: Re: RAM question
        39216: 02/02/04: Peter Alfke: Re: RAM question
            39220: 02/02/04: Ray Andraka: Re: RAM question
                39235: 02/02/04: Peter Alfke: Re: RAM question
                    39255: 02/02/05: <hamish@cloud.net.au>: Re: RAM question
        40014: 02/02/24: Antonio: Re: RAM question
            40032: 02/02/25: Peter Alfke: Re: RAM question
                40042: 02/02/25: Falk Brunner: Re: RAM question
                    40062: 02/02/26: Martin Thompson: Re: RAM question
    39232: 02/02/04: Jay: Re: RAM question
        40023: 02/02/25: Xilinx FAE from Insight SANKET: Re: RAM question
            40033: 02/02/25: Antonio: Re: RAM question
                40035: 02/02/25: Peter Alfke: Re: RAM question
                    40061: 02/02/25: Antonio: Re: RAM question
                        40068: 02/02/26: Peter Alfke: Re: RAM question
                            40070: 02/02/26: Peter Alfke: Re: RAM question
                                40080: 02/02/26: Peter Ormsby: Re: RAM question
                                    40083: 02/02/27: Peter Alfke: Re: RAM question
                                        40110: 02/02/27: Falk Brunner: Re: RAM question
                                            40122: 02/02/28: Peter Ormsby: Re: RAM question
                                                40123: 02/02/28: Peter Alfke: Re: RAM question
                                                40143: 02/02/28: Falk Brunner: Re: RAM question
                        40069: 02/02/26: Antonio: Re: RAM question
                            40091: 02/02/26: Antonio: Re: RAM question
39200: 02/02/04: Venu: Virtex-II and SDRAM Controller at 133MHz
    39209: 02/02/04: Ray Andraka: Re: Virtex-II and SDRAM Controller at 133MHz
        39210: 02/02/04: Austin Lesea: Re: Virtex-II and SDRAM Controller at 133MHz
        39221: 02/02/04: Tim: Re: Virtex-II and SDRAM Controller at 133MHz
        39299: 02/02/05: Jay: Re: Virtex-II and SDRAM Controller at 133MHz
            39300: 02/02/06: Rick Filipkiewicz: Re: Virtex-II and SDRAM Controller at 133MHz
                39342: 02/02/07: Allan Herriman: Re: Virtex-II and SDRAM Controller at 133MHz
                    39346: 02/02/07: Rick Filipkiewicz: Re: Virtex-II and SDRAM Controller at 133MHz
                        39358: 02/02/07: Ray Andraka: Re: Virtex-II and SDRAM Controller at 133MHz
        39719: 02/02/17: rickman: Re: Virtex-II and SDRAM Controller at 133MHz
            39722: 02/02/17: Tim: Re: Virtex-II and SDRAM Controller at 133MHz
            39725: 02/02/17: Rick Filipkiewicz: Re: Virtex-II and SDRAM Controller at 133MHz
                39727: 02/02/17: rickman: Re: Virtex-II and SDRAM Controller at 133MHz
                    39822: 02/02/20: Ray Andraka: Re: Virtex-II and SDRAM Controller at 133MHz
                        40008: 02/02/24: rickman: Re: Virtex-II and SDRAM Controller at 133MHz
                            40034: 02/02/25: John_H: Re: Virtex-II and SDRAM Controller at 133MHz
                                40048: 02/02/25: Rick Filipkiewicz: Re: Virtex-II and SDRAM Controller at 133MHz
39211: 02/02/04: Assaf Sarfati: Destroying a CPLD by JTAG
    39222: 02/02/04: Marcin E. Hamerla: Re: Destroying a CPLD by JTAG
    39223: 02/02/04: Tim: Re: Destroying a CPLD by JTAG
        39225: 02/02/04: Austin Lesea: Re: Destroying a CPLD by JTAG
            39229: 02/02/04: Marcin E. Hamerla: Re: Destroying a CPLD by JTAG
            39231: 02/02/05: Jim Granville: Re: Destroying a CPLD by JTAG
            39242: 02/02/05: Tim: Re: Destroying a CPLD by JTAG
                39265: 02/02/05: Austin Lesea: Re: Destroying a CPLD by JTAG
                    39271: 02/02/05: Austin Lesea: Re: Destroying a CPLD by JTAG
    39230: 02/02/05: Jim Granville: Re: Destroying a CPLD by JTAG
    39256: 02/02/05: k.: Re: Destroying a CPLD by JTAG
39213: 02/02/04: Theron Hicks: par and carry chains not allowing manual floorplanning
    39218: 02/02/04: Falk Brunner: Re: par and carry chains not allowing manual floorplanning
        39226: 02/02/04: Ray Andraka: Re: par and carry chains not allowing manual floorplanning
        39227: 02/02/04: Theron Hicks: Re: par and carry chains not allowing manual floorplanning
            39243: 02/02/04: Theron Hicks (Terry): Re: par and carry chains not allowing manual floorplanning
    39460: 02/02/10: Ray Andraka: Re: par and carry chains not allowing manual floorplanning
        39461: 02/02/10: Theron Hicks (Terry): Re: par and carry chains not allowing manual floorplanning
            39463: 02/02/11: Ray Andraka: Re: par and carry chains not allowing manual floorplanning
            39493: 02/02/12: Ray Andraka: Re: par and carry chains not allowing manual floorplanning
                39552: 02/02/13: <hamish@cloud.net.au>: Re: par and carry chains not allowing manual floorplanning
        39551: 02/02/13: <hamish@cloud.net.au>: Re: par and carry chains not allowing manual floorplanning
            39562: 02/02/13: Ray Andraka: Re: par and carry chains not allowing manual floorplanning
                39643: 02/02/15: Utku Ozcan: Re: par and carry chains not allowing manual floorplanning
                    39657: 02/02/15: Ray Andraka: Re: par and carry chains not allowing manual floorplanning
39214: 02/02/04: Nurit Eliram: Terabit Networking Forum
39215: 02/02/04: madhu: Glitch detect
    39217: 02/02/04: Falk Brunner: Re: Glitch detect
39224: 02/02/04: Arvin Patel: Xilinx synthesis tools
    39252: 02/02/05: Thomas Stanka: Re: Xilinx synthesis tools
        39289: 02/02/05: Arvin Patel: Re: Xilinx synthesis tools
            39580: 02/02/13: Edwin Bland: Re: Xilinx synthesis tools
    39257: 02/02/05: Sanket Bandyopadhyay: Re: Xilinx synthesis tools
        39639: 02/02/15: Leon de Boer: Re: Xilinx synthesis tools
            39669: 02/02/15: Mike Treseler: Re: Xilinx synthesis tools
    39316: 02/02/06: John McCluskey: Re: Xilinx synthesis tools
        39443: 02/02/10: Tim: Re: Xilinx synthesis tools
            39456: 02/02/10: Phil Hays: Re: Xilinx synthesis tools
                39586: 02/02/13: David Dye: Re: Xilinx synthesis tools
39253: 02/02/05: starpanda: Core generator Asynchronous FIFO
    39267: 02/02/05: Brian Philofsky: Re: Core generator Asynchronous FIFO
39258: 02/02/05: Gamma Globulin: When is Xilinx going to have multi-gigabit serial PHY?
    39261: 02/02/05: sanketinsight.memec.co.in: Re: When is Xilinx going to have multi-gigabit serial PHY?
        39268: 02/02/05: Gamma Globulin: Re: When is Xilinx going to have multi-gigabit serial PHY?
            39269: 02/02/05: Austin Lesea: Re: When is Xilinx going to have multi-gigabit serial PHY?
    39266: 02/02/05: Austin Lesea: Re: When is Xilinx going to have multi-gigabit serial PHY?
39262: 02/02/05: Jeff Stout: I want pla2tdf.exe
    39274: 02/02/05: heyho: Re: I want pla2tdf.exe
39263: 02/02/05: Luigi: Adding internal JTAG chains on FPGA
    39309: 02/02/06: Marco Serafini: Re: Adding internal JTAG chains on FPGA
        39366: 02/02/07: Luigi: Re: Adding internal JTAG chains on FPGA
39276: 02/02/05: ls_user: FPGA vs GAL : Lattice
    39277: 02/02/05: John_H: Re: FPGA vs GAL : Lattice
    39278: 02/02/05: ls_user: Re: FPGA vs GAL : Lattice
        39280: 02/02/05: Falk Brunner: Re: FPGA vs GAL : Lattice
        39283: 02/02/05: Jan Pech: Re: FPGA vs GAL : Lattice
        39311: 02/02/06: <hamish@cloud.net.au>: Re: FPGA vs GAL : Lattice
    39279: 02/02/05: Antonio: Re: FPGA vs GAL : Lattice
        39281: 02/02/05: Falk Brunner: Re: FPGA vs GAL : Lattice
    39284: 02/02/05: ls_user: Re: FPGA vs GAL : Lattice
        39286: 02/02/05: Austin Lesea: Re: FPGA vs GAL : Lattice
        39290: 02/02/05: Przemyslaw Wegrzyn: Re: FPGA vs GAL : Lattice
        39303: 02/02/05: Keith R. Williams: Re: FPGA vs GAL : Lattice
    39288: 02/02/05: ls_user: Re: FPGA vs GAL : Lattice
        39291: 02/02/05: Philip Freidin: Re: FPGA vs GAL : Lattice Its a TROLL
            39301: 02/02/06: Rick Filipkiewicz: Re: FPGA vs GAL : Lattice Its a TROLL
                39320: 02/02/06: Davis Moore: Re: FPGA vs GAL : Lattice Its a TROLL
    39292: 02/02/05: ls_user: Re: FPGA vs GAL : Lattice
        39305: 02/02/06: Bob Perlman: Re: FPGA vs GAL : Lattice
    39297: 02/02/05: Paul: Re: FPGA vs GAL : Lattice
    39328: 02/02/06: whazzup: Re: FPGA vs GAL : Lattice
        39332: 02/02/06: Rick Filipkiewicz: Re: FPGA vs GAL : Lattice
            39378: 02/02/07: whazzup: Re: FPGA vs GAL : Lattice
                39391: 02/02/08: Rick Filipkiewicz: Re: FPGA vs GAL : Lattice
39287: 02/02/05: Daniel Davies: Development time query
39294: 02/02/05: rk: FPGA --> SDRAM & Groundbounce: Latchup Possible?
    39296: 02/02/05: Austin Lesea: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible?
        39302: 02/02/05: rk: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible?
            39318: 02/02/06: Martin Thompson: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible?
    39321: 02/02/06: Mike Treseler: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible?
        39336: 02/02/06: Austin Lesea: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible?
39295: 02/02/05: Paul: Making Altera development quicker
    39307: 02/02/06: z.karim: Re: Making Altera development quicker
    39319: 02/02/06: Martin Thompson: Re: Making Altera development quicker
    39327: 02/02/06: Jay: Re: Making Altera development quicker
        39329: 02/02/06: Paul: Re: Making Altera development quicker
            39338: 02/02/06: Jay: Re: Making Altera development quicker
                39352: 02/02/07: Paul: Re: Making Altera development quicker
    39501: 02/02/12: Julian Cox: Re: Making Altera development quicker
        39502: 02/02/12: Paul: Re: Making Altera development quicker
            39508: 02/02/12: Ray Andraka: Re: Making Altera development quicker
                39520: 02/02/12: Jay: Re: Making Altera development quicker
                    39523: 02/02/12: Paul: Re: Making Altera development quicker
                        39525: 02/02/12: Tim: Re: Making Altera development quicker
                        39587: 02/02/13: Vitaliy Tkachenko: Re: Making Altera development quicker
                    39543: 02/02/13: Ray Andraka: Re: Making Altera development quicker
                        39556: 02/02/13: newman: Re: Making Altera development quicker
                            39564: 02/02/13: Ray Andraka: Re: Making Altera development quicker
        39736: 02/02/18: Martin Thompson: Re: Making Altera development quicker
39298: 02/02/05: James: Programming Altera PGAs.
    39304: 02/02/06: Duane Hague: Re: Programming Altera PGAs.
    39306: 02/02/06: Jim Granville: Re: Programming Altera PGAs.
        39312: 02/02/06: Victor Schutte: Re: Programming Altera PGAs.
            39392: 02/02/08: James: Re: Programming Altera PGAs.
39310: 02/02/06: Yann: Virtex 2 rect->pol conversion
    39315: 02/02/06: Ray Andraka: Re: Virtex 2 rect->pol conversion
39314: 02/02/06: niv: RE Xilinx 3.3SP8, Beware!
    39335: 02/02/06: Austin Lesea: Re: RE Xilinx 3.3SP8, Beware!
39322: 02/02/06: strut911: designing a protocol analyzer for proprietary serial bus
    39339: 02/02/06: Jay: Re: designing a protocol analyzer for proprietary serial bus
39323: 02/02/06: Achim Gratz: Pseudorandom Bitstream
    39324: 02/02/06: Mike Treseler: Re: Pseudorandom Bitstream
    39326: 02/02/06: Ray Andraka: Re: Pseudorandom Bitstream
        39356: 02/02/07: Achim Gratz: Re: Pseudorandom Bitstream
            39357: 02/02/07: <vt313@comsys.ntu-kpi.kiev.ua>: Re: Pseudorandom Bitstream
                39368: 02/02/07: Ray Andraka: Re: Pseudorandom Bitstream
                    39372: 02/02/07: <vt313@comsys.ntu-kpi.kiev.ua>: Re: Pseudorandom Bitstream
                    39382: 02/02/07: jrc: Re: Pseudorandom Bitstream
                        39386: 02/02/07: Ray Andraka: Re: Pseudorandom Bitstream
                            39407: 02/02/08: Achim Gratz: Re: Pseudorandom Bitstream
                                39421: 02/02/08: Ray Andraka: Re: Pseudorandom Bitstream
                                39739: 02/02/18: Achim Gratz: Re: Pseudorandom Bitstream
                            39753: 02/02/18: Lasse Langwadt Christensen: Re: Pseudorandom Bitstream
                                39823: 02/02/20: Ray Andraka: Re: Pseudorandom Bitstream
            39359: 02/02/07: Ray Andraka: Re: Pseudorandom Bitstream
        39503: 02/02/12: Achim Gratz: Re: Pseudorandom Bitstream
            39504: 02/02/12: Tim: Re: Pseudorandom Bitstream
                39505: 02/02/12: Ray Andraka: Re: Pseudorandom Bitstream
                    39533: 02/02/12: Achim Gratz: Re: Pseudorandom Bitstream
                        39541: 02/02/13: Ray Andraka: Re: Pseudorandom Bitstream
                            39550: 02/02/13: Achim Gratz: Re: Pseudorandom Bitstream
                                39561: 02/02/13: Ray Andraka: Re: Pseudorandom Bitstream
                                    39583: 02/02/13: Achim Gratz: Re: Pseudorandom Bitstream
                                39570: 02/02/13: Mike Treseler: Re: Pseudorandom Bitstream
39325: 02/02/06: Antonio: CLKDLL x4 problem
    39330: 02/02/06: Falk Brunner: Re: CLKDLL x4 problem
        39348: 02/02/06: Antonio: Re: CLKDLL x4 problem
            39351: 02/02/07: Magnus Homann: Re: CLKDLL x4 problem
            39360: 02/02/07: Ray Andraka: Re: CLKDLL x4 problem
                39394: 02/02/07: Antonio: Re: CLKDLL x4 problem
                    39420: 02/02/08: Ray Andraka: Re: CLKDLL x4 problem
39334: 02/02/06: Igor Peker: Preliminary timing simulation (Leonardo SDF => ModelSim)
    39337: 02/02/06: Lewis: Re: Preliminary timing simulation (Leonardo SDF => ModelSim)
    39442: 02/02/09: Igor Peker: Re: Preliminary timing simulation (Leonardo SDF => ModelSim)
39341: 02/02/07: Haneef Mohammed: Announce: VHDL Simili 2.0 - Graphics, Windows, Linux, Affordable
    39345: 02/02/07: Srinivasan Venkataramanan: Re: Announce: VHDL Simili 2.0 - Graphics, Windows, Linux, Affordable
        39361: 02/02/07: Haneef Mohammed: Re: Announce: VHDL Simili 2.0 - Graphics, Windows, Linux, Affordable
        39388: 02/02/08: Haneef Mohammed: Re: Announce: VHDL Simili 2.0 - Graphics, Windows, Linux, Affordable
    39347: 02/02/07: Allan Herriman: Re: Announce: VHDL Simili 2.0 - Graphics, Windows, Linux, Affordable
39343: 02/02/06: Peter Jahnke: Altera MAX7000 PLD's
    39353: 02/02/07: Martin Thompson: Re: Altera MAX7000 PLD's
39349: 02/02/07: Srinivasan Venkataramanan: Looking for Free EDIF/Verilog netlist - Schematic Viewer
    39354: 02/02/07: Russell Shaw: Re: Looking for Free EDIF/Verilog netlist - Schematic Viewer
    39373: 02/02/07: Vikram Pasham: Re: Looking for Free EDIF/Verilog netlist - Schematic Viewer
    39467: 02/02/11: Shing-Fat Fred Ma: Re: Looking for Free EDIF/Verilog netlist - Schematic Viewer
39350: 02/02/07: Utku Ozcan: toolbox.xilinx.com
39355: 02/02/07: poste libre: MC6800 vhdl design
    39362: 02/02/07: Ray Andraka: Re: MC6800 vhdl design
    39364: 02/02/07: Paul: Re: MC6800 vhdl design
39363: 02/02/07: Richard Meester: Multiple clock domein synchronization.
    39370: 02/02/07: Ray Andraka: Re: Multiple clock domein synchronization.
        39381: 02/02/07: Arvin Patel: Re: Multiple clock domein synchronization.
            39393: 02/02/08: Richard Meester: Re: Multiple clock domein synchronization.
    39428: 02/02/08: Jay: Re: Multiple clock domein synchronization.
        39430: 02/02/08: Ray Andraka: Re: Multiple clock domein synchronization.
            39450: 02/02/11: Kobayashi,: Re: Multiple clock domein synchronization.
                39457: 02/02/10: Ray Andraka: Re: Multiple clock domein synchronization.
                    39458: 02/02/11: Jim Granville: Re: Multiple clock domein synchronization.
                        39459: 02/02/10: Ray Andraka: Re: Multiple clock domein synchronization.
                    39472: 02/02/12: Tadashi Kobayashi: Re: Multiple clock domein synchronization.
                        39480: 02/02/11: Ray Andraka: Re: Multiple clock domein synchronization.
                            39500: 02/02/11: Valeri Serebrianski: Re: Multiple clock domein synchronization.
                                39507: 02/02/12: Ray Andraka: Re: Multiple clock domein synchronization.
39365: 02/02/07: Stéphane: Which PC for ALTERA development tools ?
    39367: 02/02/07: Paul: Re: Which PC for ALTERA development tools ?
    39369: 02/02/07: Ray Andraka: Re: Which PC for ALTERA development tools ?
    39374: 02/02/07: Jay: Re: Which PC for ALTERA development tools ?
        39604: 02/02/14: gyp: Re: Which PC for ALTERA development tools ?
39371: 02/02/07: Antonio: Ptractical polyphase filter question
39379: 02/02/07: Josan Moreno: Design with Triscend E5
    39403: 02/02/08: S. Ramirez: Re: Design with Triscend E5
39383: 02/02/07: Jui Tan: Xilinx ISE 3.3 upgrade to 4.1
    39387: 02/02/08: Mike Johnson: Re: Xilinx ISE 3.3 upgrade to 4.1
        39401: 02/02/08: <hamish@cloud.net.au>: Re: Xilinx ISE 3.3 upgrade to 4.1
            39406: 02/02/08: Rick Filipkiewicz: Re: Xilinx ISE 3.3 upgrade to 4.1
                39412: 02/02/08: John_H: Re: Xilinx ISE 3.3 upgrade to 4.1
                    39425: 02/02/08: Rick Filipkiewicz: Re: Xilinx ISE 3.3 upgrade to 4.1
                        39429: 02/02/08: Ray Andraka: Re: Xilinx ISE 3.3 upgrade to 4.1
    39389: 02/02/07: Marc Klingelhofer: Re: Xilinx ISE 3.3 upgrade to 4.1
    39390: 02/02/08: Bob Perlman: Re: Xilinx ISE 3.3 upgrade to 4.1
    39400: 02/02/08: <hamish@cloud.net.au>: Re: Xilinx ISE 3.3 upgrade to 4.1
        39423: 02/02/08: Mike Johnson: Re: Xilinx ISE 3.3 upgrade to 4.1
        39572: 02/02/13: Rick Filipkiewicz: Re: Xilinx ISE 3.3 upgrade to 4.1
            39695: 02/02/16: <hamish@cloud.net.au>: Re: Xilinx ISE 3.3 upgrade to 4.1
                39705: 02/02/16: Rick Filipkiewicz: Re: Xilinx ISE 3.3 upgrade to 4.1
                    39801: 02/02/20: Ray Andraka: Re: Xilinx ISE 3.3 upgrade to 4.1
                    39824: 02/02/20: Ray Andraka: Re: Xilinx ISE 3.3 upgrade to 4.1
    40136: 02/02/28: Ian Smith: Re: Xilinx ISE 3.3 upgrade to 4.1
39384: 02/02/07: AP: Schema Schematic Capture/ C models
39395: 02/02/08: Tim Ottley: Xilinx DCM question anyone? (or Peter if he is there?)
    39399: 02/02/08: Philip Freidin: Re: Xilinx DCM question anyone? (or Peter if he is there?)
        39402: 02/02/08: Tim Ottley: Re: Xilinx DCM question anyone? (or Peter if he is there?)
            39411: 02/02/08: John_H: Re: Xilinx DCM question anyone? (or Peter if he is there?)
            39413: 02/02/08: Austin Lesea: Re: Xilinx DCM question anyone? (or Peter if he is there?)
                39414: 02/02/08: Austin Lesea: Re: Xilinx DCM question anyone? (or Peter if he is there?)
            39418: 02/02/08: Ray Andraka: Re: Xilinx DCM question anyone? (or Peter if he is there?)
39404: 02/02/08: ssy: the problem of post simulation
39408: 02/02/08: Rick Filipkiewicz: NT parallel port driver
    39410: 02/02/08: Dave Vanden Bout: Re: NT parallel port driver
        39415: 02/02/08: Theron Hicks: Re: NT parallel port driver ...Any serial NT drivers?
            39444: 02/02/10: Alex Sherstuk: Re: NT parallel port driver ...Any serial NT drivers?
                39462: 02/02/10: Theron Hicks (Terry): Re: NT parallel port driver ...Any serial NT drivers?
    39469: 02/02/11: Dan Oprisan: Re: NT parallel port driver
    39578: 02/02/13: Robert Abiad: Re: NT parallel port driver
    39594: 02/02/14: Hans Summers: Re: NT parallel port driver
39409: 02/02/08: Richard Meester: Help on bus interface needed.
    39426: 02/02/08: Jay: Re: Help on bus interface needed.
        39433: 02/02/09: Richard Meester: Re: Help on bus interface needed.
            39486: 02/02/11: Jay: Re: Help on bus interface needed.
                39499: 02/02/12: Richard Meester: Re: Help on bus interface needed.
                    39521: 02/02/12: Jay: Re: Help on bus interface needed.
                        39522: 02/02/12: Richard Meester: Re: Help on bus interface needed.
                            39542: 02/02/12: Jay: Re: Help on bus interface needed.
                                39547: 02/02/13: Richard Meester: Re: Help on bus interface needed.
                                    39573: 02/02/13: Jay: Re: Help on bus interface needed.
39416: 02/02/08: Theron Hicks: Modelsim questions
    39419: 02/02/08: Mike Treseler: Re: Modelsim questions
    39607: 02/02/14: Phil Connor: Re: Modelsim questions
        39621: 02/02/14: newman: Re: Modelsim questions
        39627: 02/02/14: Yury: Re: Modelsim questions
            39633: 02/02/14: Kevin Brace: Re: Modelsim questions
                39694: 02/02/16: <hamish@cloud.net.au>: Re: Modelsim questions
            39816: 02/02/20: Brian Philofsky: Re: Modelsim questions
39422: 02/02/08: Terry: Schematic Entry in Xilinx ISE 4.1i
39424: 02/02/08: Tim: Re: CLKDLL x4 problem
    39854: 02/02/21: David Bishop: Re: CLKDLL x4 problem
        39858: 02/02/21: Ray Andraka: Re: CLKDLL x4 problem
            39860: 02/02/21: Peter Alfke: Re: CLKDLL x4 problem
                39862: 02/02/21: Tim: Re: CLKDLL x4 problem
39434: 02/02/09: Terrence Mak: beside System Generator
39438: 02/02/09: Alberto Moreira: Help with getting started
    39439: 02/02/09: Dave Vanden Bout: Re: Help with getting started
    39446: 02/02/10: Falk Brunner: Re: Help with getting started
39440: 02/02/09: Johann Glaser: Xilinx EDIF to BIT transation
    39447: 02/02/10: Rick Filipkiewicz: Re: Xilinx EDIF to BIT transation
        39448: 02/02/10: Johann Glaser: Re: Xilinx EDIF to BIT transation
            39449: 02/02/10: Falk Brunner: Re: Xilinx EDIF to BIT transation
                39451: 02/02/10: Duane Clark: Re: Xilinx EDIF to BIT transation
                39452: 02/02/10: Rick Filipkiewicz: Re: Xilinx EDIF to BIT transation
                    39453: 02/02/10: Johann Glaser: Re: Xilinx EDIF to BIT transation
                    39454: 02/02/10: Falk Brunner: Re: Xilinx EDIF to BIT transation
        39490: 02/02/11: In Memory of tecNovia: Re: Xilinx EDIF to BIT transation
            39491: 02/02/12: Ray Andraka: Re: Xilinx EDIF to BIT transation
                39519: 02/02/12: In Memory of tecNovia: Re: Xilinx EDIF to BIT transation
                    39524: 02/02/12: Tim: Re: Xilinx EDIF to BIT transation
39455: 02/02/10: <shparekh@yahoo.com>: Xilinx XC2V6000 - cannot get anything out of jtag port
    39653: 02/02/15: David Hawke: Re: Xilinx XC2V6000 - cannot get anything out of jtag port
39464: 02/02/11: Tim: Re: I think it's a synthesis bug
    39489: 02/02/11: Ray Andraka: Re: I think it's a synthesis bug
39465: 02/02/10: chris: inconsistent results after place and route on xilinx XC2V3000
    39603: 02/02/14: Utku Ozcan: Re: inconsistent results after place and route on xilinx XC2V3000
39468: 02/02/11: Hartmut Schaefer: XILINX Webpack 4.1 beginners question
    39477: 02/02/11: Falk Brunner: Re: XILINX Webpack 4.1 beginners question
        39481: 02/02/11: Hartmut Schaefer: Re: XILINX Webpack 4.1 beginners question
            39483: 02/02/11: Falk Brunner: Re: XILINX Webpack 4.1 beginners question
    39482: 02/02/11: Kamal Patel: Re: XILINX Webpack 4.1 beginners question
39470: 02/02/11: Muzaffer Kal: Altera's new family Stratix
    39476: 02/02/11: Austin Lesea: Re: Altera's new family Stratix
        39479: 02/02/11: Ray Andraka: Re: Altera's new family Stratix
            39484: 02/02/11: John_H: Re: Altera's new family Stratix
            39485: 02/02/11: Eric Smith: Re: Altera's new family Stratix
                39487: 02/02/11: Tim: SRL/Logic - was Altera's new family Stratix
                39488: 02/02/11: Ray Andraka: Re: Altera's new family Stratix
        39492: 02/02/12: Peter Ormsby: Re: Altera's new family Stratix
        39495: 02/02/11: rickman: Re: Altera's new family Stratix
            39497: 02/02/12: Ray Andraka: Re: Altera's new family Stratix
            39512: 02/02/12: Austin Lesea: Re: Altera's new family Stratix
                39590: 02/02/13: rickman: Re: Altera's new family Stratix
                    39606: 02/02/14: Austin Lesea: Re: Altera's new family Stratix
                        39609: 02/02/14: Austin Lesea: Re: Altera's new family Stratix
                        39714: 02/02/17: rickman: Re: Altera's new family Stratix
                            40147: 02/02/28: Magnus Homann: Re: Altera's new family Stratix
                                40249: 02/03/03: rickman: Re: Altera's new family Stratix
        39506: 02/02/12: ls_user: Re: Altera's new family Stratix
            39530: 02/02/12: arpit.desai: Re: Altera's new family Stratix
                39537: 02/02/12: Austin Lesea: Re: Altera's new family Stratix
                39538: 02/02/12: John_H: Re: Altera's new family Stratix
            39536: 02/02/12: Austin Lesea: Re: Altera's new family Stratix
                39563: 02/02/13: jakab tanko: Re: Altera's new family Stratix
                    39568: 02/02/13: Austin Lesea: Re: Altera's new family Stratix
                39567: 02/02/13: gyp: Re: Altera's new family Stratix
                39575: 02/02/13: Falk Brunner: Re: Altera's new family Stratix
                    39581: 02/02/13: Jim Kearney: Re: Altera's new family Stratix
39471: 02/02/11: Michael Boehnel: Sequential commands in statemachine
    39475: 02/02/11: Michael Boehnel: Re: Sequential commands in statemachine
39473: 02/02/11: Aare Tali: Spartan Program/Verify
    39478: 02/02/11: Falk Brunner: Re: Spartan Program/Verify
    39494: 02/02/12: David Miller: Re: Spartan Program/Verify
        39513: 02/02/12: Aare Tali: Re: Spartan Program/Verify
            39516: 02/02/12: Jim Kearney: Re: Spartan Program/Verify
                39535: 02/02/12: Aare Tali: Re: Spartan Program/Verify
                    39539: 02/02/12: Ray Andraka: Re: Spartan Program/Verify
                        39540: 02/02/13: Jim Kearney: Re: Spartan Program/Verify
                        39544: 02/02/12: Brian Davis: Re: Spartan Program/Verify
                        39545: 02/02/13: Rick Filipkiewicz: Re: Spartan Program/Verify
39474: 02/02/11: Martin, Charles: Xilinx m1map vs map
    39613: 02/02/14: Martin, Charles: Re: Xilinx m1map vs map
39496: 02/02/12: David Miller: DONE goes high, but the device doesnt seem to "run"
39498: 02/02/11: Phil Curry: student F2.1i printing problem
    39555: 02/02/13: Stephen: Re: student F2.1i printing problem
    40276: 02/03/04: Paul Taylor: Re: student F2.1i printing problem
39509: 02/02/12: Theron Hicks: fifo in coregen? Xilinx (ise4.1) is screwed up!
    39515: 02/02/12: Bob Perlman: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
        39518: 02/02/12: Theron Hicks: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
            39527: 02/02/12: Bob Perlman: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
                39641: 02/02/15: G: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
                    39656: 02/02/15: Ray Andraka: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
    39599: 02/02/14: ZhengLin: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
    39646: 02/02/15: Jonas Weiss: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
        39767: 02/02/19: Theron Hicks: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
        39865: 02/02/21: Theron Hicks: Xilinx (ise4.1) is screwed up! SCREAM LOUD!!
            39934: 02/02/22: Jonas Weiss: Re: Xilinx (ise4.1) is screwed up! SCREAM LOUD!!
39510: 02/02/12: Dinesh: spi4-02.0
    39554: 02/02/13: <hamish@cloud.net.au>: Re: spi4-02.0
39517: 02/02/12: Tamar Poker: Power estimation for Virtex-2 device
    39532: 02/02/12: Ray Andraka: Re: Power estimation for Virtex-2 device
        39611: 02/02/14: Tamar Poker: Re: Power estimation for Virtex-2 device
            39619: 02/02/14: Ray Andraka: Re: Power estimation for Virtex-2 device
        39741: 02/02/18: Nate Goldshlag: Re: Power estimation for Virtex-2 device
            39742: 02/02/18: Phil Hays: Re: Power estimation for Virtex-2 device
    39614: 02/02/14: Me: Re: Power estimation for Virtex-2 device
        40096: 02/02/27: Mohamed Ismail: Re: Power estimation for Virtex-2 device
39526: 02/02/12: Jens Niemann: Newbie SpartanII Block Ram question
    39528: 02/02/12: Falk Brunner: Re: Newbie SpartanII Block Ram question
        39531: 02/02/12: Ray Andraka: Re: Newbie SpartanII Block Ram question
    39529: 02/02/12: John_H: Re: Newbie SpartanII Block Ram question
        39557: 02/02/13: Jens Niemann: Re: Newbie SpartanII Block Ram question
        39574: 02/02/13: Falk Brunner: Re: Newbie SpartanII Block Ram question
39546: 02/02/13: Nicholas Weaver: Suggestions on distributing a module...
    39559: 02/02/13: Ray Andraka: Re: Suggestions on distributing a module...
39548: 02/02/12: Antonio: RAM CORE settings for maximum speed
    39560: 02/02/13: Ray Andraka: Re: RAM CORE settings for maximum speed
        39576: 02/02/13: Falk Brunner: Re: RAM CORE settings for maximum speed
            39595: 02/02/13: Antonio: Re: RAM CORE settings for maximum speed
            39616: 02/02/14: Ray Andraka: Re: RAM CORE settings for maximum speed
                39671: 02/02/15: Falk Brunner: Re: RAM CORE settings for maximum speed
39549: 02/02/13: Noddy: Foundation 4.1 vs. ISE 4.1?
    39565: 02/02/13: Ray Andraka: Re: Foundation 4.1 vs. ISE 4.1?
        39596: 02/02/14: Noddy: Re: Foundation 4.1 vs. ISE 4.1?
    39597: 02/02/14: ZhengLin: Re: Foundation 4.1 vs. ISE 4.1?
        39620: 02/02/14: Ray Andraka: Re: Foundation 4.1 vs. ISE 4.1?
39553: 02/02/13: jeremy: CLKDLL doesn't work without BUFG ?
    39569: 02/02/13: Austin Lesea: Re: CLKDLL doesn't work without BUFG ?
39566: 02/02/13: Leon de Boer: Is Leonardo spectrum OEM version for Altera limited?
    39571: 02/02/13: Mike Treseler: Re: Is Leonardo spectrum OEM version for Altera limited?
        39577: 02/02/13: Paul: Re: Is Leonardo spectrum OEM version for Altera limited?
    39589: 02/02/13: Jay: Re: Is Leonardo spectrum OEM version for Altera limited?
        39636: 02/02/15: Leon de Boer: Re: Is Leonardo spectrum OEM version for Altera limited?
    39648: 02/02/15: Victor Schutte: Re: Is Leonardo spectrum OEM version for Altera limited?
39579: 02/02/13: Gunther May: Problem with Lattice Design Expert Starter
    39582: 02/02/13: Speedy Zero Two: Re: Problem with Lattice Design Expert Starter
        39588: 02/02/14: Mikeandmax: Re: Problem with Lattice Design Expert Starter
39584: 02/02/13: Colin O'Flynn: Atmel CPLD chip design software?
    39585: 02/02/14: Jim Granville: Re: Atmel CPLD chip design software?
39591: 02/02/13: Kevin Brace: What do the Spartan-II Global Clock delay binary values for 66MHz PCI
39592: 02/02/14: Paul Taylor: SpartanXL & VHDL -- free software?
    39602: 02/02/14: Achim Gratz: Re: SpartanXL & VHDL -- free software?
        39608: 02/02/14: Johann Glaser: Re: SpartanXL & VHDL -- free software?
        39623: 02/02/14: Paul Taylor: Re: SpartanXL & VHDL -- free software?
            39630: 02/02/14: Eric Smith: Re: SpartanXL & VHDL -- free software?
                39637: 02/02/15: Paul Taylor: Re: SpartanXL & VHDL -- free software?
                    39676: 02/02/15: Falk Brunner: Re: SpartanXL & VHDL -- free software?
                        39690: 02/02/16: Paul Taylor: Re: SpartanXL & VHDL -- free software?
                            39699: 02/02/16: Falk Brunner: Re: SpartanXL & VHDL -- free software?
                                39766: 02/02/19: Theron Hicks: Re: SpartanXL & VHDL -- free software?
                    39681: 02/02/15: Eric Smith: Re: SpartanXL & VHDL -- free software?
                39674: 02/02/15: Falk Brunner: Re: SpartanXL & VHDL -- free software?
                    39683: 02/02/15: Johann Glaser: Re: SpartanXL & VHDL -- free software?
                        39685: 02/02/15: Austin Lesea: Re: SpartanXL & VHDL -- free software?
                        39686: 02/02/15: Tim: Re: SpartanXL & VHDL -- free software?
                            39687: 02/02/15: Rick Filipkiewicz: Re: SpartanXL & VHDL -- free software?
39593: 02/02/14: Albert Wang: Does anybody have the Xilinx Foundation Series 2.1i newest not locked license.dat file?
    39610: 02/02/14: Eric Crabill: Re: Does anybody have the Xilinx Foundation Series 2.1i newest not
39598: 02/02/14: Bernhard Holzmayer: Trivial (?) problem with Xilinx - System Generator (tristate port pin)?
    39712: 02/02/16: sharat babu: Re: Trivial (?) problem with Xilinx - System Generator (tristate port pin)?
        39756: 02/02/19: Bernhard Holzmayer: Re: Trivial (?) problem with Xilinx - System Generator (tristate port pin)?
    39605: 02/02/14: Kevin Brace: Re: Spartan-II becomes Vertex.
        39615: 02/02/14: Ray Andraka: Re: Spartan-II becomes Vertex.
            39631: 02/02/14: Kevin Brace: Re: Spartan-II becomes Vertex.
                39632: 02/02/15: X. Q.: Re: Spartan-II becomes Vertex.
                    39634: 02/02/14: Kevin Brace: Re: Spartan-II becomes Vertex.
                        39635: 02/02/15: X. Q.: Re: Spartan-II becomes Vertex.
                            39654: 02/02/15: Ray Andraka: Re: Spartan-II becomes Vertex.
                39664: 02/02/15: Marc Baker: Re: Spartan-II becomes Vertex.
                    39675: 02/02/15: Ray Andraka: Re: Spartan-II becomes Vertex.
                    39713: 02/02/17: rickman: Re: Spartan-II becomes Vertex.
39601: 02/02/14: X. Q.: Spartan-II becomes Vertex.
    39649: 02/02/15: Dave Haynes: Re: Spartan-II becomes Vertex.
39617: 02/02/14: Aaron Eberhart: Create a bit stream (BIT file) from an NCD file?
    39629: 02/02/15: Tim: Re: Create a bit stream (BIT file) from an NCD file?
39618: 02/02/14: Aaron Eberhart: Logiblox cells not connected in ISE4.1 HDL project
    41425: 02/03/27: Aaron Eberhart: Re: Logiblox cells not connected in ISE4.1 HDL project
39622: 02/02/14: jetmarc: Lean serial communication processor
    39624: 02/02/15: Jim Granville: Re: Lean serial communication processor
        39625: 02/02/14: Mike Johnson: Re: Lean serial communication processor
            39628: 02/02/14: Goran Bilski: Re: Lean serial communication processor
    39672: 02/02/15: Falk Brunner: Re: Lean serial communication processor
39626: 02/02/14: Inder: Orca ngdbuild error: could not expand block
    39638: 02/02/14: rickman: Re: Orca ngdbuild error: could not expand block
        39647: 02/02/15: Inder: Re: Orca ngdbuild error: could not expand block
    39650: 02/02/15: Philip Freidin: Re: Orca ngdbuild error: could not expand block
        39689: 02/02/15: Inder: Re: Orca ngdbuild error: could not expand block
    39703: 02/02/16: Hal Murray: Speaking of ORCA...
        39709: 02/02/16: Kevin Brace: Re: Speaking of ORCA...
        39715: 02/02/17: rickman: Re: Speaking of ORCA...
39640: 02/02/14: rickman: Configuration in SelectMAP mode and CCLK
    39677: 02/02/15: Falk Brunner: Re: Configuration in SelectMAP mode and CCLK
39642: 02/02/15: Niv: Xilinx Virtex XCV300
    39682: 02/02/15: Salman Sheikh: Re: Xilinx Virtex XCV300
        39698: 02/02/16: z.karim: Re: Xilinx Virtex XCV300
        39700: 02/02/16: Falk Brunner: Re: Xilinx Virtex XCV300
    39697: 02/02/16: z.karim: Re: Xilinx Virtex XCV300
39644: 02/02/14: Antonio: RAM CORE result that I did not understand
    39661: 02/02/15: John_H: Re: RAM CORE result that I did not understand
39645: 02/02/14: Antonio: Some doubts on FIFO CORE v.4.0
39651: 02/02/15: Jock: Modelsim Logo
    39655: 02/02/15: Jonathan Bromley: Re: Modelsim Logo
    40043: 02/02/25: Arvind Kumar: Re: unisims simprims
39658: 02/02/15: Jon Schneider: Thingy has the property IOB=TRUE
    39662: 02/02/15: David Hawke: Re: Thingy has the property IOB=TRUE
        39667: 02/02/15: Jon Schneider: Re: Thingy has the property IOB=TRUE
    39668: 02/02/15: Bret Wade: Re: Thingy has the property IOB=TRUE
        39673: 02/02/15: Jon Schneider: Re: Thingy has the property IOB=TRUE
            39684: 02/02/15: Bret Wade: Re: Thingy has the property IOB=TRUE
39659: 02/02/15: Jens Niemann: Newbie question Synchronous RAM
    39660: 02/02/15: John_H: Re: Newbie question Synchronous RAM
39663: 02/02/15: Dani Guzman: FPGA choices and questions
    39666: 02/02/15: rickman: Re: FPGA choices and questions
        39693: 02/02/16: FPGA/IC: Re: FPGA choices and questions
            39696: 02/02/16: Ray Andraka: Re: FPGA choices and questions
            39716: 02/02/17: rickman: Re: FPGA choices and questions
    39680: 02/02/15: Ulf Samuelsson: Re: FPGA choices and questions
        39692: 02/02/16: FPGA/IC: Re: FPGA choices and questions
            39706: 02/02/16: ikauranen: Re: FPGA choices and questions
            39718: 02/02/17: rickman: Re: FPGA choices and questions
                39724: 02/02/17: S. Ramirez: Re: FPGA choices and questions
        39717: 02/02/17: rickman: Re: FPGA choices and questions
            39846: 02/02/21: Ulf Samuelsson: Re: FPGA choices and questions
                39908: 02/02/21: rickman: Re: FPGA choices and questions
    39704: 02/02/16: Hal Murray: Re: FPGA choices and questions
    39710: 02/02/16: Kevin Brace: Re: FPGA choices and questions
    39721: 02/02/16: ZhengLin: Re: FPGA choices and questions
        39805: 02/02/20: Leon Qin: Re: FPGA choices and questions
            40104: 02/02/27: Andy Main: Re: FPGA choices and questions
39665: 02/02/15: Hristo Stevic: oscillation
    39670: 02/02/15: Ray Andraka: Re: oscillation
        39688: 02/02/15: glen herrmannsfeldt: Re: oscillation
            39691: 02/02/16: Ray Andraka: Re: oscillation
    39679: 02/02/15: Falk Brunner: Re: oscillation
39678: 02/02/15: Robert VanRooyen: Clocking issues w/ CoolRunner & Webpack
    39798: 02/02/19: Jay: Re: Clocking issues w/ CoolRunner & Webpack
39701: 02/02/16: Frank Vorstenbosch: Re: wild teen sex scenes and CPLDs
39702: 02/02/16: Phil Hays: Handel-C, System-C, Formal verification ???
    39707: 02/02/17: glen herrmannsfeldt: Re: Handel-C, System-C, Formal verification ???
        39914: 02/02/22: Phil Hays: Re: Handel-C, System-C, Formal verification ???
    39708: 02/02/17: Kelly Hall: Re: Handel-C, System-C, Formal verification ???
        39915: 02/02/22: Phil Hays: Re: Handel-C, System-C, Formal verification ???
    39711: 02/02/17: z.karim: Re: Handel-C, System-C, Formal verification ???
        39726: 02/02/17: Seb: Re: Handel-C, System-C, Formal verification ???
        39919: 02/02/22: Phil Hays: Re: Handel-C, System-C, Formal verification ???
    39732: 02/02/18: Thomas Stanka: Re: Handel-C, System-C, Formal verification ???
        39920: 02/02/22: Phil Hays: Re: Handel-C, System-C, Formal verification ???
39728: 02/02/18: Craig Ward: Faster designs
    39783: 02/02/19: Nicholas Weaver: Re: Faster designs
    39789: 02/02/19: Falk Brunner: Re: Faster designs
    39792: 02/02/19: Jay: Re: Faster designs
    39793: 02/02/19: newman: Re: Faster designs
    39799: 02/02/20: Craig Ward: Re: Faster designs
    39803: 02/02/20: Phil Hays: Re: Faster designs
    39804: 02/02/19: Leon Qin: Re: Faster designs
    39981: 02/02/22: Arvind Kumar: Re: Faster designs
39729: 02/02/18: X. Q.: Do I need to install software in order to use Multilinx?
    39733: 02/02/18: ZhengLin: Re: Do I need to install software in order to use Multilinx?
        39748: 02/02/18: Falk Brunner: Re: Do I need to install software in order to use Multilinx?
            39838: 02/02/21: Ray Andraka: Re: Do I need to install software in order to use Multilinx?
                39839: 02/02/21: X. Q.: Re: Do I need to install software in order to use Multilinx?
                    39843: 02/02/21: Ray Andraka: Re: Do I need to install software in order to use Multilinx?
                39852: 02/02/21: Rick Filipkiewicz: Re: Do I need to install software in order to use Multilinx?
                    39856: 02/02/21: Ray Andraka: Re: Do I need to install software in order to use Multilinx?
                        39868: 02/02/21: Falk Brunner: Re: Do I need to install software in order to use Multilinx?
                            39882: 02/02/21: Ray Andraka: Re: Do I need to install software in order to use Multilinx?
                                39891: 02/02/21: Rick Filipkiewicz: Re: Do I need to install software in order to use Multilinx?
39730: 02/02/17: Antonio: Edge selection with RAM
    39749: 02/02/18: Falk Brunner: Re: Edge selection with RAM
        39776: 02/02/19: Jay: Re: Edge selection with RAM
39731: 02/02/17: Antonio: Some problem initializing a RAMB4S1
    39764: 02/02/19: David Hawke: Re: Some problem initializing a RAMB4S1
        39813: 02/02/20: Antonio: Re: Some problem initializing a RAMB4S1
            39818: 02/02/20: Brian Philofsky: Re: Some problem initializing a RAMB4S1
                39819: 02/02/20: Brian Philofsky: Re: Some problem initializing a RAMB4S1
                    39849: 02/02/21: Antonio: Re: Some problem initializing a RAMB4S1
39734: 02/02/18: shiva kumar: FPGA: JTAG CABLE
    39735: 02/02/18: Rick Filipkiewicz: Re: FPGA: JTAG CABLE
    39738: 02/02/18: MH: Re: JTAG CABLE
        39744: 02/02/18: Rick Filipkiewicz: Re: JTAG CABLE
    39746: 02/02/18: Eric Crabill: Re: FPGA: JTAG CABLE
        40052: 02/02/26: Steve Casselman: Re: FPGA: JTAG CABLE
    39778: 02/02/19: Jay: Re: FPGA: JTAG CABLE
        39787: 02/02/19: Neil: Re: FPGA: JTAG CABLE
            39880: 02/02/21: Ray Andraka: Re: FPGA: JTAG CABLE
                39895: 02/02/21: Aare Tali: Re: FPGA: JTAG CABLE
39737: 02/02/18: Paul: Altera library problems.
    39942: 02/02/22: Wolfgang Loewer: Re: Altera library problems.
39740: 02/02/18: Paul: Timing constraints
    39750: 02/02/18: Falk Brunner: Re: Timing constraints
    39752: 02/02/18: David Hawke: Re: Timing constraints
39743: 02/02/18: Unit Manager: Book Recommendation for Designing Complex System using HDL.
    39745: 02/02/18: Srinivasan Venkataramanan: Re: Book Recommendation for Designing Complex System using HDL.
    40313: 02/03/05: Khaled Nsaibia: Re: Book Recommendation for Designing Complex System using HDL.
39747: 02/02/18: Przemyslaw Wegrzyn: Xilinx IP Core multiplier performance
    39795: 02/02/19: Jay: Re: Xilinx IP Core multiplier performance
        39802: 02/02/20: Ray Andraka: Re: Xilinx IP Core multiplier performance
            39831: 02/02/21: Przemyslaw Wegrzyn: Re: Xilinx IP Core multiplier performance
                39840: 02/02/21: Ray Andraka: Re: Xilinx IP Core multiplier performance
39751: 02/02/18: Prashant: Multipliers in Altera FPGAs
    39777: 02/02/19: Jay: Re: Multipliers in Altera FPGAs
        39779: 02/02/19: C.Schlehaus: Re: Multipliers in Altera FPGAs
            39782: 02/02/19: Seb: Re: Multipliers in Altera FPGAs
39754: 02/02/19: Rick Filipkiewicz: Xilinx XDL documentation
    40082: 02/02/27: Steve Casselman: Re: Xilinx XDL documentation
        40089: 02/02/27: Rick Filipkiewicz: Re: Xilinx XDL documentation
39755: 02/02/19: X. Q.: Whether an FPGA & CPLD device has been spoiled.
    39781: 02/02/19: Seb: Re: Whether an FPGA & CPLD device has been spoiled.
    39786: 02/02/19: Eric Smith: Re: Whether an FPGA & CPLD device has been spoiled.
        39879: 02/02/21: Ray Andraka: Re: Whether an FPGA & CPLD device has been spoiled.
            39941: 02/02/22: Xilinx FAE from Insight SANKET: Re: Whether an FPGA & CPLD device has been spoiled.
39758: 02/02/19: starpanda: Maximum # of logic level
    39775: 02/02/19: Jay: Re: Maximum # of logic level
39759: 02/02/19: Markus Meng: I/O Type of the Xilinx CCLK pin ??
39760: 02/02/19: Carsten Heise: Orca FPSC synthesizing issue
    39770: 02/02/19: rickman: Re: Orca FPSC synthesizing issue
        39851: 02/02/21: Carsten: Re: Orca FPSC synthesizing issue
            39959: 02/02/22: rickman: Re: Orca FPSC synthesizing issue
    39980: 02/02/22: Arvind Kumar: Re: Orca FPSC synthesizing issue
        40093: 02/02/27: Carsten: Re: Orca FPSC synthesizing issue
39761: 02/02/19: Paul: "DONT TOUCH" with Xilinx XST?
    39762: 02/02/19: =?iso-8859-1?Q?St=E9phane?= Guyetant: Re: "DONT TOUCH" with Xilinx XST?
    39763: 02/02/19: David Hawke: Re: "DONT TOUCH" with Xilinx XST?
    39772: 02/02/19: Mike Treseler: Re: "DONT TOUCH" with Xilinx XST?
39765: 02/02/19: Salman Sheikh: Virtex II prototype/development boards
    39780: 02/02/19: Seb: Re: Virtex II prototype/development boards
39768: 02/02/19: Peter Alfke: Re: Virtex-E BRAM timing
39769: 02/02/19: rickman: Coolrunner and ISP
    39771: 02/02/19: Alan Nishioka: Re: Coolrunner and ISP
    39773: 02/02/19: David Hawke: Re: Coolrunner and ISP
        39794: 02/02/19: Jay: Re: Coolrunner and ISP
        39810: 02/02/20: rickman: Re: Coolrunner and ISP
            39817: 02/02/20: Alan Nishioka: Re: Coolrunner and ISP
                39906: 02/02/21: rickman: Re: Coolrunner and ISP
                    39910: 02/02/22: Jim Granville: Re: Coolrunner and ISP
                        39955: 02/02/22: rickman: Re: Coolrunner and ISP
                            39964: 02/02/23: Jim Granville: Re: Coolrunner and ISP
                                39983: 02/02/23: rickman: Re: Coolrunner and ISP
                            39982: 02/02/23: Hal Murray: Re: Coolrunner and ISP
                                39984: 02/02/23: rickman: Re: Coolrunner and ISP
                                    39986: 02/02/23: Jim Granville: Re: Coolrunner and ISP
                                        39989: 02/02/23: rickman: Re: Coolrunner and ISP
                                            39994: 02/02/23: Hal Murray: Re: Coolrunner and ISP
                                                39998: 02/02/24: Jim Granville: Re: Coolrunner and ISP
                                                40000: 02/02/24: rickman: Re: Coolrunner and ISP
                    39921: 02/02/22: Ray Andraka: Re: Coolrunner and ISP
                        39957: 02/02/22: rickman: Re: Coolrunner and ISP
                    39958: 02/02/22: Alan Nishioka: Re: Coolrunner and ISP
                        39985: 02/02/23: rickman: Re: Coolrunner and ISP
                            39996: 02/02/23: James Horn: Re: Coolrunner and ISP
                                39997: 02/02/24: Hal Murray: Re: Coolrunner and ISP
                                    40003: 02/02/24: Rick Filipkiewicz: Re: Coolrunner and ISP
39774: 02/02/19: Jay: Re: Virtex-E BRAM timing
    39857: 02/02/21: Ray Andraka: Re: Virtex-E BRAM timing
39784: 02/02/19: Theron Hicks: spartan2 clock input from LVPECL signals
    39809: 02/02/20: David Frith: Re: spartan2 clock input from LVPECL signals
39785: 02/02/19: H.L: Virtex-E BRAM timing
    39847: 02/02/21: H.L: Re: Virtex-E BRAM timing
39788: 02/02/19: Frank Vorstenbosch: Few pins but more gates
    39790: 02/02/20: Jim Granville: Re: Few pins but more gates
    39815: 02/02/20: svhb: Re: Few pins but more gates
        40006: 02/02/24: rickman: Re: Few pins but more gates
            40039: 02/02/25: Falk Brunner: Re: Few pins but more gates
39797: 02/02/19: Clark Pope: Virtex II multiplier pipeline
    39806: 02/02/20: David Hawke: Re: Virtex II multiplier pipeline
    39807: 02/02/20: MH: Re: Virtex II multiplier pipeline
    39825: 02/02/20: Seb: Re: Virtex II multiplier pipeline
39800: 02/02/19: Skept: Mux implemented as tristate
    39812: 02/02/20: Rick Filipkiewicz: Re: Mux implemented as tristate
39808: 02/02/20: Victor Levandovsky: Need good PCI book
    39821: 02/02/20: Steen Larsen: Re: Need good PCI book
        39826: 02/02/20: Keith R. Williams: Re: Need good PCI book
            39832: 02/02/20: Steen Larsen: Re: Need good PCI book
    39833: 02/02/20: Kevin Brace: Re: Need good PCI book
        39850: 02/02/21: Eric Smith: Re: Need good PCI book
            39972: 02/02/22: Kevin Brace: Re: Need good PCI book
39811: 02/02/20: svhb: gate array
    39830: 02/02/20: Jay: Re: gate array
39814: 02/02/20: Dan Oprisan: Counter does not fit CPLD?
    39820: 02/02/20: Rick Filipkiewicz: Re: Counter does not fit CPLD?
    39829: 02/02/20: Jay: Re: Counter does not fit CPLD?
39827: 02/02/20: Aare Tali: KEEP constraints on std_logic_vector
39828: 02/02/20: Jesus Molina: PCI/FPGA evaluation board
    39834: 02/02/20: Kevin Brace: Re: PCI/FPGA evaluation board
        39835: 02/02/20: Kevin Brace: Re: PCI/FPGA evaluation board
    39836: 02/02/20: Jesus Molina: Re: PCI/FPGA evaluation board
    39837: 02/02/20: Kevin Brace: Re: PCI/FPGA evaluation board
    39853: 02/02/21: Rick Filipkiewicz: Re: PCI/FPGA evaluation board
    40017: 02/02/25: Matthias Scheerer: Re: PCI/FPGA evaluation board
39842: 02/02/21: X. Q.: Need largest CPLD devices?
    39845: 02/02/21: Ulf Samuelsson: Re: Need largest CPLD devices?
        39875: 02/02/21: Jay: Re: Need largest CPLD devices?
    39869: 02/02/21: Falk Brunner: Re: Need largest CPLD devices?
        39903: 02/02/22: X. Q.: Re: Need largest CPLD devices?
            39905: 02/02/22: Jim Granville: Re: Need largest CPLD devices?
            39966: 02/02/22: Falk Brunner: Re: Need largest CPLD devices?
            39973: 02/02/22: Kevin Brace: Re: Need largest CPLD devices?
                39993: 02/02/23: Andy Main: Re: Need largest CPLD devices?
                    40057: 02/02/26: X. Q.: Re: Need largest CPLD devices?
                        40076: 02/02/26: Andy Main: Re: Need largest CPLD devices?
39844: 02/02/20: Kumar: Problem While Downloading to Spartan 2 FPGA using JTAG
    39870: 02/02/21: Falk Brunner: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
        39887: 02/02/21: Tim: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
            39918: 02/02/21: Kumar: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
        39912: 02/02/21: Kumar: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
            39965: 02/02/22: Falk Brunner: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
                40055: 02/02/25: Kumar: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
    39894: 02/02/21: Mark van de Belt: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
        39916: 02/02/21: Kumar: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
            39917: 02/02/22: Ray Andraka: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
                39931: 02/02/22: Rick Filipkiewicz: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
                39935: 02/02/22: Kumar: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
                    39938: 02/02/22: Tim: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
                39940: 02/02/22: Xilinx FAE from Insight SANKET: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
39848: 02/02/21: AT: SRL16E Initialization
    39859: 02/02/21: Ray Andraka: Re: SRL16E Initialization
39855: 02/02/21: Russell Tessier: FPGA'2002: JOIN US SUNDAY
39861: 02/02/21: Madhu: Here is an argument and can anyone help me out
    39863: 02/02/21: Peter Alfke: Re: Here is an argument and can anyone help me out
    39864: 02/02/21: Theron Hicks: Re: Here is an argument and can anyone help me out
        39867: 02/02/21: Christopher Saunter: Re: Here is an argument and can anyone help me out
            39872: 02/02/21: Theron Hicks: Re: Here is an argument and can anyone help me out
                39932: 02/02/22: Christopher Saunter: Re: Here is an argument and can anyone help me out
    39890: 02/02/21: Eric Pearson: Re: Here is an argument and can anyone help me out
    39893: 02/02/21: Bob Perlman: Re: Here is an argument and can anyone help me out
    39930: 02/02/22: Thomas Stanka: Re: Here is an argument and can anyone help me out
    40117: 02/02/28: Steve Casselman: Re: Here is an argument and can anyone help me out
39866: 02/02/21: Dave Brown: Using a CoreGen component
    39871: 02/02/21: Kamal Patel: Re: Using a CoreGen component
    39874: 02/02/21: Theron Hicks: Re: Using a CoreGen component
        39881: 02/02/21: Ray Andraka: Re: Using a CoreGen component
    39877: 02/02/21: Theron Hicks: Re: Using a CoreGen component
39873: 02/02/21: Theron Hicks: EDIF IN A VHDL PROJECT (kcpsm.edn) in ISE4.1
    39886: 02/02/21: Tim: Re: EDIF IN A VHDL PROJECT (kcpsm.edn) in ISE4.1
    39888: 02/02/21: Falk Brunner: Re: EDIF IN A VHDL PROJECT (kcpsm.edn) in ISE4.1
    40026: 02/02/25: Ken Chapman: Re: EDIF IN A VHDL PROJECT (kcpsm.edn) in ISE4.1
        40037: 02/02/25: Theron Hicks: Re: EDIF IN A VHDL PROJECT (kcpsm.edn) in ISE4.1
39876: 02/02/21: Alkos Nikos: IIR. convolution
    40010: 02/02/25: MANDY & DOUGLAS: Re: IIR. convolution
        40164: 02/03/01: Ray Andraka: Re: IIR. convolution
39878: 02/02/21: David Bishop: Floating point synthesis
39883: 02/02/21: Jason LaPenta: Problems : INOUT not allowed, alternatives
    39889: 02/02/21: Peter Alfke: Re: Problems : INOUT not allowed, alternatives
    39892: 02/02/21: Rick Filipkiewicz: Re: Problems : INOUT not allowed, alternatives
    39904: 02/02/22: Tim: Re: Problems : INOUT not allowed, alternatives
        39927: 02/02/22: Hal Murray: Tristate meets mux
    39907: 02/02/21: Muzaffer Kal: Re: Problems : INOUT not allowed, alternatives
39884: 02/02/21: Johann Glaser: EDIF to .bit file conversion for Xilinx Spartan XCS10
    39885: 02/02/21: Tim: Re: EDIF to .bit file conversion for Xilinx Spartan XCS10
        39898: 02/02/21: Eric Smith: Re: EDIF to .bit file conversion for Xilinx Spartan XCS10
    39899: 02/02/21: Eric Smith: Re: EDIF to .bit file conversion for Xilinx Spartan XCS10
        39901: 02/02/21: Johann Glaser: Re: EDIF to .bit file conversion for Xilinx Spartan XCS10
39896: 02/02/21: Mark van de Belt: INIT on XC2S30
    39900: 02/02/21: Peter Alfke: Re: INIT on XC2S30
        39928: 02/02/22: Mark van de Belt: Re: INIT on XC2S30
            39954: 02/02/22: rickman: Re: INIT on XC2S30
39897: 02/02/21: Kevin Brace: How can I do a Verilog/VHDL mixed language design in ISE WebPACK 4.1
    39902: 02/02/21: Rick Filipkiewicz: Re: How can I do a Verilog/VHDL mixed language design in ISE WebPACK 4.1
39911: 02/02/21: starpanda: cross clock domain signals
    39945: 02/02/22: Xilinx FAE from Insight SANKET: Re: cross clock domain signals
    39971: 02/02/22: Peter Alfke: Re: cross clock domain signals
        40210: 02/03/01: Paul Butler: Re: cross clock domain signals
39913: 02/02/22: rick: what's different between Foundation series and FPGA express
39922: 02/02/21: Al Williams: Beginner Altera Questions
    39923: 02/02/22: jerry1111: Re: Beginner Altera Questions
        39948: 02/02/22: Al Williams: Re: Beginner Altera Questions
    39947: 02/02/22: Peter Ormsby: Re: Beginner Altera Questions
        39962: 02/02/22: Al Williams: Re: Beginner Altera Questions
            39990: 02/02/23: Peter Ormsby: Re: Beginner Altera Questions
    40050: 02/02/25: Jay: Re: Beginner Altera Questions
        40066: 02/02/26: Al Williams: Re: Beginner Altera Questions
            40074: 02/02/26: Jay: Re: Beginner Altera Questions
                40079: 02/02/26: jerry1111: Re: Beginner Altera Questions
                    40108: 02/02/27: Jay: Re: Beginner Altera Questions
                        40129: 02/02/28: Martin Thompson: Re: Beginner Altera Questions
                            40132: 02/02/28: Al Williams: Re: Beginner Altera Questions
                                40169: 02/03/01: Martin Thompson: Re: Beginner Altera Questions
                        40184: 02/03/01: jerry1111: Re: Beginner Altera Questions
                            40204: 02/03/02: Jim Granville: Re: Beginner Altera Questions
39924: 02/02/22: Seb: init RAM in VirtexII
    39967: 02/02/22: Falk Brunner: Re: init RAM in VirtexII
        40009: 02/02/24: Seb: Re: init RAM in VirtexII
    40007: 02/02/24: newman: Re: init RAM in VirtexII
39925: 02/02/21: Antonio: QPRO questions
    39953: 02/02/22: Ray Andraka: Re: QPRO questions
39926: 02/02/22: Christopher Duncan: OT - Programmer war stories
39937: 02/02/22: JHL: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
    39968: 02/02/22: Peter Alfke: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation
    39969: 02/02/22: Falk Brunner: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
        39978: 02/02/22: Theron Hicks: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
            39979: 02/02/22: Falk Brunner: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
                40019: 02/02/25: Martin Thompson: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
        39999: 02/02/24: JHL: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
39943: 02/02/22: Luigi: Pin assignments in QUARTUS
    39949: 02/02/22: Jean-Baptiste Monnard: Re: Pin assignments in QUARTUS
    39952: 02/02/22: James Srinivasan: Re: Pin assignments in QUARTUS
        39956: 02/02/22: Paul: Re: Pin assignments in QUARTUS
            39961: 02/02/22: James Srinivasan: Re: Pin assignments in QUARTUS
                39991: 02/02/23: Luigi: Re: Pin assignments in QUARTUS
                    40038: 02/02/25: Paul: Re: Pin assignments in QUARTUS
    40063: 02/02/26: russell: Re: Pin assignments in QUARTUS
        40177: 02/03/01: Luigi: Re: Pin assignments in QUARTUS
            40201: 02/03/01: Mike Treseler: Re: Pin assignments in QUARTUS
            40213: 02/03/02: Russell Shaw: Re: Pin assignments in QUARTUS
39946: 02/02/22: Yoram Rovner: CPLD PROJECT
    39970: 02/02/22: Falk Brunner: Re: CPLD PROJECT
    39974: 02/02/22: Kevin Brace: Re: CPLD PROJECT
    39975: 02/02/22: Kevin Brace: Re: CPLD PROJECT
    39976: 02/02/22: Jay: Re: CPLD PROJECT
    40005: 02/02/24: Richard Erlacher: Re: CPLD PROJECT
39950: 02/02/22: Manfred Kraus: Replacing expensive configuration SPROM
    39951: 02/02/22: Keith R. Williams: Re: Replacing expensive configuration SPROM
    39960: 02/02/23: Tadashi Kobayashi: Re: Replacing expensive configuration SPROM
    39963: 02/02/22: stefaan vanheesbeke: Re: Replacing expensive configuration SPROM
    39995: 02/02/23: Mark van de Belt: Re: Replacing expensive configuration SPROM
39987: 02/02/23: LM: Implementing MD5 in hardware (Handel C, VHDL)
    40018: 02/02/25: Panu H: Re: Implementing MD5 in hardware (Handel C, VHDL)
39988: 02/02/23: jean-francois hasson: Question about multiple Virtex DLLs locking management after configuration
    40044: 02/02/25: Arvind Kumar: Re: Question about multiple Virtex DLLs locking management after configuration
40001: 02/02/23: strong: about EPLD Rules and FLEX Rules
40002: 02/02/24: strong: EPLD RULES AND FLEX RULES
    40004: 02/02/24: Frank Vorstenbosch: Re: EPLD RULES AND FLEX RULES
40011: 02/02/24: Alan J. Coppola: Announce: pdcodes-0.01 Beta Release: CRC code modeling
40012: 02/02/25: tyew: Altera FPGA MISC Pipeline
40013: 02/02/25: Kevin Brace: Is it possible to have an output FF in IOB, but a tri-state control FF
    40022: 02/02/25: Xilinx FAE from Insight SANKET: Re: Is it possible to have an output FF in IOB, but a tri-state control FF outside of IOB?
    40027: 02/02/25: Tim: Re: Is it possible to have an output FF in IOB, but a tri-state control FF outside of IOB?
    40041: 02/02/25: Falk Brunner: Re: Is it possible to have an output FF in IOB, but a tri-state control FF outside of IOB?
        40053: 02/02/25: Kevin Brace: Re: Is it possible to have an output FF in IOB, but a tri-state control
            40054: 02/02/25: Kevin Brace: Re: Is it possible to have an output FF in IOB, but a tri-state control
40015: 02/02/25: Antonio: Floorplanner and then ??
    40024: 02/02/25: Xilinx FAE from Insight SANKET: Re: Floorplanner and then ??
40016: 02/02/25: Antonio: Synplify warning that I don't understand
    40020: 02/02/25: Nicolas Matringe: Re: Synplify warning that I don't understand
    40025: 02/02/25: Francisco Camarero: Re: Synplify warning that I don't understand
        40040: 02/02/25: Arvind Kumar: Re: Synplify warning that I don't understand
40028: 02/02/25: king: Comparison between two FPGAs- what is decisive factor?
    40045: 02/02/25: Falk Brunner: Re: Comparison between two FPGAs- what is decisive factor?
    40047: 02/02/25: Neil Franklin: Re: Comparison between two FPGAs- what is decisive factor?
    40049: 02/02/25: Jay: Re: Comparison between two FPGAs- what is decisive factor?
    40058: 02/02/25: Assaf Sarfati: Re: Comparison between two FPGAs- what is decisive factor?
    40158: 02/03/01: Ray Andraka: Re: Comparison between two FPGAs- what is decisive factor?
        40170: 02/03/01: Tim: Re: Comparison between two FPGAs- what is decisive factor?
40029: 02/02/25: Charles Wagner: unisims simprims
40030: 02/02/25: J Kenens: Virtex-E,Spartan2 and cpld jtag chain problem
    40046: 02/02/25: Falk Brunner: Re: Virtex-E,Spartan2 and cpld jtag chain problem
        40095: 02/02/27: J Kenens: Re: Virtex-E,Spartan2 and cpld jtag chain problem
    40099: 02/02/27: Rick Filipkiewicz: Re: Virtex-E,Spartan2 and cpld jtag chain problem
40031: 02/02/25: Carsten: EDIF netlist in FPGA Express
    40077: 02/02/26: Philip Freidin: Re: EDIF netlist in FPGA Express
    40078: 02/02/26: Robert Abiad: Re: EDIF netlist in FPGA Express
40036: 02/02/25: Paul: Creation of FPGA tips and tricks forum - help required
    40081: 02/02/26: Philip Freidin: Re: Creation of FPGA tips and tricks forum - help required
        40097: 02/02/27: Paul: Re: Creation of FPGA tips and tricks forum - help required
    40112: 02/02/27: Hobson: Re: Creation of FPGA tips and tricks forum - help required
    40159: 02/03/01: Ray Andraka: Re: Creation of FPGA tips and tricks forum - help required
        40163: 02/02/28: Theron Hicks (Terry): Re: Creation of FPGA tips and tricks forum - help required
    40246: 02/03/03: Christopher Saunter: Re: Creation of FPGA tips and tricks forum - help required
40051: 02/02/25: Mik Kim: Spartan 2E JTAG
    40056: 02/02/25: Xilinx FAE from Insight SANKET: Re: Spartan 2E JTAG
        40101: 02/02/27: David Hawke: Re: Spartan 2E JTAG
40059: 02/02/26: Jonas Weiss: VIRTEX-II DCI Ref Pins
    40067: 02/02/26: Jonas Weiss: Re: VIRTEX-II DCI Ref Pins
40060: 02/02/26: X. Q.: Spartan-2 chip;
40064: 02/02/26: russell: Quartus (finding node)
    40075: 02/02/26: Jay: Re: Quartus (finding node)
        40131: 02/02/28: russell: Re: Quartus (finding node)
40065: 02/02/26: Jens Frauenschlaeger: readback by JTAG
40071: 02/02/26: Nicholas Weaver: Anyone have a delidded Spartan II?
40072: 02/02/26: emanuel stiebler: microblaze
    40109: 02/02/27: Victor Schutte: Re: microblaze
        40113: 02/02/27: emanuel stiebler: Re: microblaze
            40119: 02/02/27: Jesse Kempa: Re: microblaze
                40145: 02/02/28: Victor Schutte: Re: microblaze
                40149: 02/02/28: Goran Bilski: Re: microblaze
                    40192: 02/03/01: Jesse Kempa: Re: microblaze
                        40193: 02/03/01: emanuel stiebler: Re: microblaze
                        40195: 02/03/01: Goran Bilski: Re: microblaze
40073: 02/02/26: fre: Core generator2.1(FIR)
40085: 02/02/26: Johnny Wang: Implementation failed cause of sourceless signals
    40086: 02/02/26: Johnny Wang: Re: Implementation failed cause of sourceless signals
40087: 02/02/26: <voytov@ihpc.net>: EEPROM simulation
    40090: 02/02/27: z.karim: Re: EEPROM simulation
40088: 02/02/26: Johnny Wang: Is ISE3.1 a good one?
    40189: 02/03/01: Kamal: Re: Is ISE3.1 a good one?
40092: 02/02/27: X. Q.: Need comments on QuickWorks 9.1.
    40098: 02/02/27: Uwe Bonnes: Re: Need comments on QuickWorks 9.1.
40094: 02/02/27: Michal Kvasnicka: methods implementation
40100: 02/02/27: Yoram Rovner: Webpack symbol library
40102: 02/02/27: Ilko Iliev: PAL to JEDEC convertor
    40107: 02/02/28: Jim Granville: Re: PAL to JEDEC convertor
40103: 02/02/27: emanuel stiebler: scsi, ip, spartanII, vhdl
40105: 02/02/27: =?iso-8859-1?Q?St=E9phane?= Guyetant: SDRAM+FPGA
    40120: 02/02/27: Jay: Re: SDRAM+FPGA
40106: 02/02/27: Jan Gray: RAM32X1S, Virtex-II, 4.1i PAR travails
40111: 02/02/27: Warren Wisnewski: quicklogic parts request
40114: 02/02/27: Brady Gaughan: FPGAs with differential LVDS terminations?
    40144: 02/02/28: Falk Brunner: Re: FPGAs with differential LVDS terminations?
    40148: 02/02/28: Austin Lesea: Re: FPGAs with differential LVDS terminations?
40125: 02/02/28: Albert: share two months salary with you if you have job information
    40155: 02/02/28: Ryan Henderson: Re: share two months salary with you if you have job information
        40222: 02/03/02: Tom: Re: share two months salary with you if you have job information
            40223: 02/03/02: Lewin A.R.W. Edwards (Despammed): Re: share two months salary with you if you have job information
        40225: 02/03/02: S. Ramirez: Re: share two months salary with you if you have job information
    40289: 02/03/04: Jay: Re: share two months salary with you if you have job information
        40319: 02/03/05: Tom: Re: share two months salary with you if you have job information
            40329: 02/03/05: Jay: Re: share two months salary with you if you have job information
        40361: 02/03/06: Albert: Re: share two months salary with you if you have job information
            40405: 02/03/06: <istjohn@spamcop.net>: Re: share two months salary with you if you have job information
            40492: 02/03/07: Paul: Re: share two months salary with you if you have job information
40126: 02/02/28: John Williams: Simulation Question
    40127: 02/02/28: Muzaffer Kal: Re: Simulation Question
    40130: 02/02/28: Martin Thompson: Re: Simulation Question
        40154: 02/03/01: John Williams: Re: Simulation Question
40128: 02/02/28: dragomir milojevic: rloc for a flip flop
40133: 02/02/28: Ken Mac: stuck in state in Spartan-II!
    40137: 02/02/28: Phil Hays: Re: stuck in state in Spartan-II!
        40140: 02/02/28: Ken Mac: Re: stuck in state in Spartan-II!
        40142: 02/02/28: Phil Connor: Re: stuck in state in Spartan-II!
        40172: 02/03/01: Ken Mac: Re: stuck in state in Spartan-II!
            40179: 02/03/01: Xilinx FAE from Insight SANKET: Re: stuck in state in Spartan-II!
                40182: 02/03/01: Ken Mac: Re: stuck in state in Spartan-II!
                    40200: 02/03/01: Falk Brunner: Re: stuck in state in Spartan-II!
        40173: 02/03/01: Ken Mac: Re: stuck in state in Spartan-II!
            40196: 02/03/01: rickman: Re: stuck in state in Spartan-II!
                40208: 02/03/01: Peter Alfke: Re: stuck in state in Spartan-II!
            40218: 02/03/02: Phil Hays: Re: stuck in state in Spartan-II!
    40272: 02/03/04: Ken Mac: SOLVED Re: stuck in state in Spartan-II!
40135: 02/02/28: H.L: Rising and falling edge of a clk
    40141: 02/02/28: Peter Alfke: Re: Rising and falling edge of a clk
        40175: 02/03/01: H.L: Re: Rising and falling edge of a clk
            40199: 02/03/01: Ray Andraka: Re: Rising and falling edge of a clk
                40239: 02/03/03: H.L: Re: Rising and falling edge of a clk
                    40247: 02/03/03: Ray Andraka: Re: Rising and falling edge of a clk
                        40251: 02/03/03: Peter Alfke: Re: Rising and falling edge of a clk
                        40310: 02/03/05: H.L: Re: Rising and falling edge of a clk
                            40424: 02/03/07: Ray Andraka: Re: Rising and falling edge of a clk
                                40448: 02/03/07: Theron Hicks: Re: Rising and falling edge of a clk
                                    40457: 02/03/07: Ray Andraka: Re: Rising and falling edge of a clk
                                40462: 02/03/07: H.L: Re: Rising and falling edge of a clk
            40206: 02/03/01: Peter Alfke: Re: Rising and falling edge of a clk
                40240: 02/03/03: H.L: Re: Rising and falling edge of a clk
                    40245: 02/03/03: Peter Alfke: Re: Rising and falling edge of a clk
40138: 02/02/28: <news@prodigy.net>: Pacbell users - this group has been changed!
40139: 02/02/28: Matthias Scheerer: PCI book ... still confused
    40153: 02/02/28: Kevin Brace: Re: PCI book ... still confused
        40166: 02/03/01: Matthias Scheerer: Re: PCI book ... still confused
            40207: 02/03/01: Kevin Brace: Re: PCI book ... still confused
40146: 02/02/28: Jay: Synopsys Design Compiler
    40151: 02/02/28: Georg Acher: Re: Synopsys Design Compiler
        40209: 02/03/01: Jay: Re: Synopsys Design Compiler
            40214: 02/03/02: Georg Acher: Re: Synopsys Design Compiler
    40168: 02/03/01: Ansgar Bambynek: Re: Synopsys Design Compiler
        40528: 02/03/08: Mark Momcilovich: Re: Synopsys Design Compiler
    40171: 02/03/01: Tim: Re: Synopsys Design Compiler
        40613: 02/03/11: Jay: Re: Synopsys Design Compiler
40150: 02/02/28: Christof Paar: Call for Papers CHES 2002
40152: 02/02/28: Prashant: Altera FPGAs
    40156: 02/02/28: Peter Alfke: Re: Altera FPGAs
        40160: 02/02/28: Prashant: Re: Altera FPGAs
    40157: 02/03/01: Nicholas Weaver: Re: Altera FPGAs
        40161: 02/03/01: Ray Andraka: Re: Altera FPGAs
        40191: 02/03/01: John_H: Re: Altera FPGAs
    40162: 02/03/01: Peter Ormsby: Re: Altera FPGAs
        40178: 02/03/01: Xilinx FAE from Insight SANKET: Re: Altera FPGAs
        40203: 02/03/01: Prashant: Re: Altera FPGAs
    40180: 02/03/01: David Hawke: Re: Altera FPGAs
        40265: 02/03/04: Phil: Re: Altera FPGAs
            40273: 02/03/04: Ray Andraka: Re: Altera FPGAs
                40279: 02/03/04: phil: Re: Altera FPGAs
                    40296: 02/03/05: Ray Andraka: Re: Altera FPGAs
                        40326: 02/03/05: Falk Brunner: Re: Altera FPGAs
                            40341: 02/03/05: Ray Andraka: Re: Altera FPGAs
                                40351: 02/03/05: Falk Brunner: Re: Altera FPGAs
                                    40353: 02/03/05: Ray Andraka: Re: Altera FPGAs
            40307: 02/03/05: David Hawke: Re: Altera FPGAs
    40183: 02/03/01: Rene Tschaggelar: Re: Altera FPGAs


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search