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Authors (F)

F M:
    148139: 10/06/23: Re: Programming the Actel Smartfusion Eval Kit in Linux
    148142: 10/06/23: Re: Programming the Actel Smartfusion Eval Kit in Linux
    150235: 11/01/04: Re: Actel Designer: how to compile VHDL top & EDIF submodule together?
    150320: 11/01/10: Re: Low slewrate, abnormal current consumption.
    150346: 11/01/11: Re: Low slewrate, abnormal current consumption.
    152652: 11/09/23: Re: Browser-Based Timing Diagram Editor
    152774: 11/10/21: Re: Peter Alfke has passed away
F Tooned:
    1388: 95/06/13: Re: 80x51 in FPGA anyone ?
F. Arnold:
    12308: 98/10/08: Xilinx Foundation Base
    13005: 98/11/10: free Xilinx developer tools
F. Bertolazzi:
    150456: 11/01/23: Re: Xilinx news
    150461: 11/01/23: Re: Xilinx news
F. Modderkolk:
    40375: 02/03/06: FPGA or DSP
    40381: 02/03/06: FPGA or DSP in a power supply?
    40394: 02/03/06: Re: FPGA or DSP in a power supply?
    40433: 02/03/07: Re: FPGA or DSP in a power supply?
    40510: 02/03/08: Re: FPGA or DSP in a power supply?
    40520: 02/03/08: Re: FPGA or DSP in a power supply?
    40576: 02/03/11: Re: FPGA or DSP in a power supply?
    43836: 02/06/04: Problem with spartan2 vhdl code
F. Wirtz:
    4822: 96/12/18: Jedec file format definition?????
f.j.koons:
    1592: 95/07/23: Re: "Circuit Loops" in NeoCad??
    1641: 95/08/09: Re: AT&T ORCA: Using register input mux?
    1653: 95/08/10: Re: AT&T ORCA: Using register input mux?
    3262: 96/05/06: Re: FPGA leaders - Who are they? Xilinx, Altera, Actel?
F.M. Fontaine:
    29813: 01/03/12: Parallel Port EPP (again)
    43916: 02/06/06: Re: xc3042
F.Rodriguez:
    19270: 99/12/09: Re: CAN testing - Any CANbus cores out there?
<311f037@gmail.com>:
    88269: 05/08/13: Creating EDIF from VHDL
f5:
    51864: 03/01/24: Re: free x86 core ip
<faaizal@gmail.com>:
    89438: 05/09/14: Matched Filter
Fab:
    75969: 04/11/21: Altera chip identification
    75978: 04/11/21: Re: Altera chip identification
fab.:
    143385: 09/10/08: Re: image scalar in Spartan 3E
    143389: 09/10/08: xilinx ISE 11.1 and linux (Mint) - USB drivers problems with IMPACT
    143393: 09/10/09: Re: xilinx ISE 11.1 and linux (Mint) - USB drivers problems with
    143395: 09/10/09: Re: xilinx ISE 11.1 and linux (Mint) - USB drivers problems with
    143411: 09/10/10: Re: xilinx ISE 11.1 and linux (Mint) - USB drivers problems with
    143650: 09/10/20: Spartan-3A DSP and include a Digital Clock Manager (DCM_SP) - How to
    143689: 09/10/21: Re: Spartan-3A DSP and include a Digital Clock Manager (DCM_SP) - How
    144465: 09/12/09: Measure accurate time with a 50MHz FPGA - what are the limits?
    144497: 09/12/11: Re: Measure accurate time with a 50MHz FPGA - what are the limits?
    144591: 09/12/18: Re: How to add cores in XPS 9.1i ?
fabbl:
    64858: 04/01/15: Re: Port mapping a Verilog component in a VHDL design
    64863: 04/01/15: Re: What does nios-run do?
    64927: 04/01/16: Re: Spartan-3 VCCINT
    64933: 04/01/16: Re: yo, Mr. FPGA Engineer
    64936: 04/01/16: Re: Power-up input value detection
    65248: 04/01/22: Re: Why is router software not multi-threaded?
    65445: 04/01/29: Re: what is back annotation
    65446: 04/01/29: Re: Power extimation?
    65459: 04/01/29: Re: Where to get FPGA devices for testing?
    65872: 04/02/09: Re: Xilinx training
    66272: 04/02/16: Re: using fpga for sampling audio
    66277: 04/02/16: Re: using fpga for sampling audio
    66278: 04/02/16: Re: IOB's
    66280: 04/02/16: Re: Manual Partitioning to Multiple FPGAs
    66366: 04/02/18: Re: using fpga for sampling audio
    66692: 04/02/25: Re: An old FPGA paper back to 1986...
    66796: 04/02/26: Re: one more inquiry....fpga architecture
    67202: 04/03/08: Re: strange error
    71559: 04/07/22: Re: Cheap FPGA's
    117472: 07/04/01: Re: Static RAM implementation with VHDL
    118170: 07/04/18: Re: Back annotating to RTL
    120860: 07/06/19: Re: Graduate/Junior FPGA Designer concerns
fabble:
    74191: 04/10/06: PCI Transactor
Fabian:
    36994: 01/11/28: Re: an unespected clock
Fabian Schuh:
    142461: 09/08/12: Partial Reconfiguration - Pin access from within the module
    142491: 09/08/13: Re: Partial Reconfiguration - Pin access from within the module
    142492: 09/08/13: Re: Partial Reconfiguration - Pin access from within the module
    142669: 09/08/25: Re: [help]error from my own hard macro by FPGA edit
    143534: 09/10/15: [Partial reconfiguration] FSM-states after reconf.
    143558: 09/10/16: Re: FSM-states after reconf.
    143567: 09/10/16: Re: FSM-states after reconf.
    143622: 09/10/19: Re: FSM-states after reconf.
    143683: 09/10/21: Re: [Partial reconfiguration] FSM-states after reconf.
    143684: 09/10/21: Re: [Partial reconfiguration] FSM-states after reconf.
Fabian Schulte:
    122366: 07/07/26: ICAP in Virtex 4
Fabien Arrive:
    46613: 02/09/04: CLK DLL problem
Fabien Todescato:
    41216: 02/03/22: Re: Pipelined sorting algorithms...
fabien.goy@gmail.com:
    119896: 07/05/29: Microchip ICD on FPGA
    119911: 07/05/29: Re: Microchip ICD on FPGA
    120117: 07/06/01: using ICAP with the ML310
    120236: 07/06/04: Re: using ICAP with the ML310
    120262: 07/06/04: Re: using ICAP with the ML310
Fabio:
    27509: 00/11/26: fpga + live
    27636: 00/11/30: R: fpga + live
    32594: 01/07/01: About evolutionary circuit design
Fabio Bertone:
    36956: 01/11/27: Alliance
Fabio de Matos Gon?alves:
    65426: 04/01/28: Hot2 configuration
Fabio G.:
    43595: 02/05/25: Re: Synchronous Single Clock Designs
    43688: 02/05/29: Re: ALtera SOPC Builder
    43777: 02/06/02: Re: ALtera SOPC Builder
    44648: 02/06/25: Re: Quartus v/s Leonardo
    65686: 04/02/04: Dual clock FIFO with Atmel FPGA ??
    69475: 04/05/11: Looking for Synario 3.0 (Lattice)
    69512: 04/05/12: Re: Looking for Synario 3.0 (Lattice)
    69528: 04/05/13: Re: Looking for Synario 3.0 (Lattice)
    69556: 04/05/13: Re: Looking for Synario 3.0 (Lattice)
    69567: 04/05/14: Re: Looking for Synario 3.0 (Lattice)
    69630: 04/05/16: Re: Looking for Synario 3.0 (Lattice)
    70532: 04/06/19: Re: CPLD mistery. Help.
    85111: 05/06/04: Re: ispLSI1016
    85124: 05/06/05: Re: ispLSI1016
    85193: 05/06/06: Re: ispLSI1016
    85449: 05/06/09: Re: ispLSI1016
Fabio Rodrigues de la Rocha:
    97536: 06/02/23: Variables in VHDL and simulation
    97617: 06/02/24: Module-based partial reconfiguration in ISE Webpack
    98345: 06/03/08: Re: VHDL
    98481: 06/03/10: synthesis time with XST
    98487: 06/03/10: Re: synthesis time with XST
    98737: 06/03/15: Re: synthesis time with XST
    101261: 06/04/28: Bus macros compatible with ISE 8.1
    101603: 06/05/03: Re: How to open an ISE 8.1 project in ISE 7.1?
Fabio Somenzi:
    5651: 97/03/04: VIS 1.2 Released
    12052: 98/09/25: VIS 1.3 Released
<Fabio>:
    85184: 05/06/06: Obsoleto package - Part 1/3
Fabric:
    71603: 04/07/23: EDA software&IP core
Fabrice Hoffmann:
    20792: 00/02/22: ALTERA BitBlaster
    20821: 00/02/23: Re: ALTERA BitBlaster
Fabrice MONTEIRO:
    30481: 01/04/10: Obj: Handel-C
    30498: 01/04/11: Re: Handel-C
Fabrizio Mezzetti:
    54405: 03/04/10: ieee1284
    54464: 03/04/11: Re: ieee1284
    54482: 03/04/11: Re: ieee1284
<fabtn2012@gmail.com>:
    154937: 13/02/23: Re: add-compare-select
fad:
    91575: 05/11/08: Installing FPGA Advantage on Linux machine
    91717: 05/11/10: Re: Installing FPGA Advantage on Linux machine
    91839: 05/11/14: Re: ISE, JTAG and ChipScopePro.
    91933: 05/11/17: Re: Suggestions on good books
    92083: 05/11/22: Re: Uart core for a virtex-4
    92943: 05/12/09: Securing verilog source code
    92977: 05/12/10: Re: Securing verilog source code
Fadi J Kurdahi:
    15359: 99/03/19: ISSS99 Second Call for Papers
Fadi Sibai:
    14362: 99/01/27: Call for Papers - Workshop on Parallel Execution on Reconfigurable Hardware (PERH'99)
    14565: 99/02/04: Call for Papers - PERH'99
fahadislam2002:
    87095: 05/07/14: How to Interface External Ram with FPGA
    87103: 05/07/15: Plz send C compiler for picoblaze with manual
    88076: 05/08/08: can use bram for VGA
    88077: 05/08/08: how to reduce vga memory????????
    88078: 05/08/08: Can use SRAM instead of VRAM ......... how ???????????
    88103: 05/08/09: Re: can use bram for VGA
    88104: 05/08/09: Re: how to reduce vga memory????????
    88105: 05/08/09: Re: can use bram for VGA
    88124: 05/08/10: Re: can use bram for VGA
    88205: 05/08/11: Re: FPGA Programming using Block Design Files or Graphic Des
    89473: 05/09/15: SDRAM HOW?
    90376: 05/10/11: How to Reduce Interconnects (VDD and VSS)
    90686: 05/10/18: re:How to Reduce Interconnects (VDD and VSS)
    92987: 05/12/10: re:Job available... 2 projects
    92988: 05/12/10: MMC(MultiMedia Card) interfacing with FPGA
    93042: 05/12/12: re:MMC(MultiMedia Card) interfacing with FPGA
    93082: 05/12/13: re:MMC(MultiMedia Card) interfacing with FPGA
<fahmeed.zaheer47@gmail.com>:
    155980: 13/11/02: Re: Simulation of VHDL code for a vending machine
faidon:
    49090: 02/10/31: BLOCK RAM : FIFO implementation
    49125: 02/11/01: Re: BLOCK RAM : FIFO implementation
    49129: 02/11/01: Re: BLOCK RAM : FIFO implementation
    49535: 02/11/14: Re: BLOCK RAM : FIFO implementation
Fairbairn Family:
    26182: 00/10/08: Re: Altera Internal Error
faizal:
    81317: 05/03/21: Block RAM Initialization - RAMB16_S2
Falk:
    32495: 01/06/28: Re: clock speed in XC95288XL
    33430: 01/07/26: Re: Prom: Download problem
    33465: 01/07/27: Re: Q: dividing by 2 results in out-of-phase pulse sometimes
    33671: 01/08/01: Re: May I connect two pins to the same net?
    33672: 01/08/02: Re: finite defect statistics
    33733: 01/08/02: Re: May I connect two pins to the same net?
    33739: 01/08/03: Re: Clock skew with Xilinx DLLs...
    33745: 01/08/03: Re: 4 (8) bit Microporcessor Implementation
    34430: 01/08/24: Re: Spartan-II & clock
    34902: 01/09/13: Re: Counter problem
    35711: 01/10/15: Re: PLLs & DLLs
    39023: 02/01/30: Re: Real-world keyboard signals
    45732: 02/08/02: Re: Which device equivalent
    45733: 02/08/02: Re: Spartan II BlockRAM - inverting control signals
    45747: 02/08/03: Re: Spartan II BlockRAM - inverting control signals
Falk Brunner:
    28761: 01/01/23: Re: Virtex counter speed
    28792: 01/01/24: Re: Virtex counter speed
    28804: 01/01/24: Re: Virtex counter speed
    28826: 01/01/25: Re: Encryption is supported in new Virtex II but.....
    28937: 01/01/30: Spartan 2 DLL
    28975: 01/01/31: Re: Spartan 2 DLL
    29001: 01/02/01: Re: JTAG Programming with SpartanII demo card
    29002: 01/02/01: Re: More then 4 Clocks
    29063: 01/02/04: Re: More then 4 Clocks
    29064: 01/02/04: Re: Can Virtex-II be programmed with MultiLINX?
    29112: 01/02/06: Re: Xilinx Implementation Error! need help urgently
    29201: 01/02/09: Re: Low skew lines in Virtex-E
    29209: 01/02/09: Re: DLL jitter "bake-off" vs. PLL
    29234: 01/02/10: Re: any idea ?
    29237: 01/02/10: Re: any idea ?
    29258: 01/02/11: Re: any idea ?
    29331: 01/02/14: Re: Spartan II power
    29355: 01/02/15: Re: Configuration file of SpartanXL
    29420: 01/02/20: Re: Fine Phase Shift in VirtexII
    29443: 01/02/21: Re: to you sir Peter Alfke...
    29444: 01/02/21: Re: Clocks
    29500: 01/02/23: Re: ERROR on Xilinx fundation
    29535: 01/02/25: Re: Spartan II power
    29621: 01/03/01: Re: Virtex DLLs
    29693: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29732: 01/03/06: Again Spartan II power
    29805: 01/03/11: Re: Configuration devices
    29872: 01/03/14: Re: FPGA : Simple FD latch glitchs
    29915: 01/03/16: Re: RAM-based Shift Register
    29957: 01/03/19: Re: FFT in FPGAs
    30121: 01/03/23: Re: speech
    30142: 01/03/25: Re: No inputs on XC9536XL
    30144: 01/03/25: Re: No inputs on XC9536XL
    30157: 01/03/26: Re: hybrid design entry
    30158: 01/03/26: Re: Asynchronus Mashine States
    30574: 01/04/17: Re: Clean Frequency Division
    30711: 01/04/25: Re: SPARTAN vs VERTEX
    30712: 01/04/25: Re: Pin A1 on Spartan2 chips
    30732: 01/04/26: Re: bidirectional I/O
    30808: 01/04/30: Re: FPGA-CPLD
    30896: 01/05/02: Re: High resolution time measurement?
    31100: 01/05/11: Re: SpartanII: non clock pad drives clock net ?
    31117: 01/05/12: Re: Implementation Of LUT in Vertex-E
    31118: 01/05/12: Re: SRAM fpga cell
    31134: 01/05/12: Re: SRAM fpga cell
    31183: 01/05/14: Re: Implementation Of LUT in Vertex-E
    31197: 01/05/14: Re: Implementation Of LUT in Vertex-E
    31251: 01/05/16: Re: Comparator
    31254: 01/05/16: Re: PCI The Real Hardware
    31255: 01/05/16: Re: Ideas for Faster XILINX compilations ?
    31502: 01/05/28: Re: Fun with DLLs.
    31767: 01/06/05: Re: Download problems
    31815: 01/06/06: Re: one state machine
    31816: 01/06/06: Re: one state machine
    31818: 01/06/06: Re: one state machine
    31834: 01/06/06: Re: one state machine
    31835: 01/06/06: Re: one state machine
    31836: 01/06/06: Re: one state machine
    31839: 01/06/06: Re: one state machine
    31840: 01/06/06: Re: Xilinx Configuration Bitstream
    31878: 01/06/07: Re: Force tristate enable register into IOB
    32030: 01/06/11: Re: Help in FIFO design
    32031: 01/06/11: Re: Help in FIFO design
    32032: 01/06/11: Re: On the prices of the FPGA and how to buy it
    32036: 01/06/11: Re: On the prices of the FPGA and how to buy it
    32037: 01/06/11: Re: On the prices of the FPGA and how to buy it
    32090: 01/06/13: Re: Fifo Clock in SpartanII
    32115: 01/06/14: Re: Cores needed
    32321: 01/06/22: Re: Xilinx: Download times with Parallel/Multilinx cable
    32322: 01/06/22: Re: Clock Derivation
    32323: 01/06/22: clock speed in XC95288XL
    32357: 01/06/24: Re: Clock Derivation
    32383: 01/06/25: Re: Xilinx Spartan - Power Rail Related Timing Problem
    32428: 01/06/26: Re: clock speed in XC95288XL
    32471: 01/06/27: Re: clock speed in XC95288XL
    32472: 01/06/27: Re: clock speed in XC95288XL
    32508: 01/06/28: Re: Clock muxes
    32519: 01/06/28: Re: clock speed in XC95288XL
    32593: 01/07/01: Re: clock speed in XC95288XL
    32609: 01/07/02: Re: Closest Xilinx equivalent to Altera EPF10KE?
    32736: 01/07/06: Re: Glitch hunting.
    32796: 01/07/09: Re: Clock buffers
    32850: 01/07/10: Re: Spartan-II implementation woes
    32851: 01/07/10: Re: Pins state on Spartan XL before config.
    33012: 01/07/15: Re: Foundation2.1i
    33013: 01/07/15: Re: Which Chip Family?
    33014: 01/07/15: Re: Which Chip Family?
    33015: 01/07/15: Re: WebPack or Foundation?
    33046: 01/07/16: Re: Which Chip Family?
    33158: 01/07/18: Re: Which Chip Family?
    33159: 01/07/18: Re: processor core
    33173: 01/07/18: Re: regarding the constraints while writing VHDL code
    33276: 01/07/21: Measuring power consumption
    33310: 01/07/23: Re: Measuring power consumption
    33327: 01/07/23: Re: Altera ISP - JTAG
    33362: 01/07/24: Re: Measuring power consumption
    33412: 01/07/26: Re: Measuring power consumption
    33470: 01/07/27: Re: PCI-Interface
    33693: 01/08/02: DLL useage
    33694: 01/08/02: Re: May I connect two pins to the same net?
    33780: 01/08/04: Re: Clock skew with Xilinx DLLs...
    33817: 01/08/06: Re: May I connect two pins to the same net?
    34110: 01/08/14: Re: this code doesn't work properly
    34213: 01/08/16: Re: Internal clock skew when using DLL
    34254: 01/08/17: Re: DPLL frequency synthesis
    34255: 01/08/17: Re: Slowing PCI for FPGA
    34257: 01/08/17: Re: Internal clock skew when using DLL
    34317: 01/08/20: Re: Internal clock skew when using DLL
    34366: 01/08/22: Re: Slowing PCI for FPGA
    34396: 01/08/23: Re: Logic Emulation
    34401: 01/08/23: Re: FPGA MP3 decoder
    34827: 01/09/10: Re: Spartan II JTAG configuration
    34828: 01/09/10: Re: Level sensitive latches in Xilinx Virtex
    34908: 01/09/13: Re: Problems with Xilinx VirtexE (Newbie)
    35089: 01/09/20: Re: Digital PLL for implementing in FPGA
    35151: 01/09/24: Re: comp.arch.fpga : Unusual clock divider ckt
    35192: 01/09/25: Re: FPGA with embedded Memory
    35193: 01/09/25: Re: CLKDLL question
    35273: 01/09/27: Re: sensitivity list
    35284: 01/09/27: Re: sensitivity list
    35388: 01/10/02: Re: barrel shifter in Xilinx Virtex-E
    35389: 01/10/02: Re: Barrel Shifter
    35390: 01/10/02: Re: Which Cable for the Xilinx 3064XL ?
    35436: 01/10/04: Re: input signal frequency
    35477: 01/10/07: Re: ROM based FSMs
    35502: 01/10/08: Re: ROM based FSMs
    35558: 01/10/10: Re: Virtex-2 maximum clock speed
    35559: 01/10/10: Re: 155MHz to DLL in Spartan II
    35564: 01/10/10: Re: 155MHz to DLL in Spartan II
    35606: 01/10/11: Re: High level synthesis will never work well :)
    35607: 01/10/11: Re: High level synthesis will never work well :)
    35608: 01/10/11: Re: [Spartan-XL] Driving a BUFGS from a std. IO ...
    35610: 01/10/11: Re: Virtex-2 maximum clock speed
    35653: 01/10/12: Re: High level synthesis will never work well :)
    35701: 01/10/14: Re: how do I avoid glitches in this design?
    35702: 01/10/14: Re: High level synthesis will never work well :)
    35758: 01/10/16: Re: LUT Glitches
    35807: 01/10/18: Re: Phase noise of Xilinx/Altera DLL/PLL
    35815: 01/10/18: Glitch Hunting, a true story ;-)
    35833: 01/10/19: Re: Phase noise of Xilinx/Altera DLL/PLL
    35834: 01/10/19: Re: Career advice in fpga/asic design
    35835: 01/10/19: Re: unused I/O cell
    35884: 01/10/22: Re: Maser Serial Config Problem
    35983: 01/10/25: Re: S/PDIF interface for FPGA
    35984: 01/10/25: Re: Verilog vs. VHDL
    36030: 01/10/26: Re: S/PDIF interface for FPGA
    36037: 01/10/26: Re: S/PDIF interface for FPGA
    36120: 01/10/30: Re: Shift Registers with Xilinx Foundation 2.1
    36149: 01/10/31: Re: BRAM usage reduction in FIFO design: First Scenario
    36150: 01/10/31: Re: Second Scenario: BRAM usage reduction in FIFO design
    36151: 01/10/31: Re: Clock attribute problem
    36188: 01/11/01: Re: BRAM usage reduction in FIFO design: First Scenario
    36201: 01/11/01: Re: Help with a 1996 XC3064 design!!
    36246: 01/11/03: Re: Re: S/PDIF interface for FPGA
    36417: 01/11/08: Re: Can I enhance this Counter 4 and Counter 6 ???
    36418: 01/11/08: Re: Can Xilinx recognize the critical path in the design
    36431: 01/11/08: Re: FPGA Wish list
    36475: 01/11/09: Re: Decoupling capacitors on Virtex II
    36476: 01/11/09: Re: How to convert unsigned integer into std_logic_vector in VHDL design?
    36477: 01/11/09: Re: Unknown Timing Sim Warnings
    36478: 01/11/09: Re: Xilinx machine readable package info
    36482: 01/11/09: Re: Location constraint error message?
    36493: 01/11/09: Re: speed of HW JPEG implementations
    36514: 01/11/10: Re: XIlinx SLOW configuration option
    36568: 01/11/12: Re: Clock Divider or Multiplier ???
    36620: 01/11/13: Re: Xilinx s/w upgrade 4.1 problems
    36633: 01/11/13: Re: Clock Skew
    36725: 01/11/17: Re: Clock Divider or Multiplier ???
    36959: 01/11/27: Re: SPI implementation details
    37069: 01/11/29: Re: SpartanIIE
    37120: 01/11/30: Re: SpartanIIE
    37234: 01/12/04: Re: How to increase clock skew for Spartan-II
    37235: 01/12/04: Re: Installing ISE 4.1i
    37294: 01/12/06: Re: Newbie: FPGA or microcontroller for MPEG4 decoding?
    37295: 01/12/06: Re: ISP via JTAG
    37296: 01/12/06: Re: Timing Constraints Spartan, divided Clk
    37343: 01/12/07: Re: How to increase clock skew for Spartan-II
    37344: 01/12/07: Re: Parameters deciding Max. Clock Frequency supported in a Sequential Ckt
    37345: 01/12/07: Re: Translating....
    37346: 01/12/07: Re: Altera pin drivers
    37360: 01/12/08: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
    37369: 01/12/08: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
    37412: 01/12/10: Re: Altera pin drivers
    37413: 01/12/10: Re: SpartanIIE
    37414: 01/12/10: Re: Translating....
    37416: 01/12/10: Re: Michelangelo's Counter
    37526: 01/12/13: Re: Xilinx ISE4.1/FPGA express: specify pin loading
    37527: 01/12/13: Re: Crosstalk on clocks
    37528: 01/12/13: Fondation 4.1 and SpartanXL
    37548: 01/12/14: Re: Fondation 4.1 and SpartanXL
    37569: 01/12/15: Re: annoying problem
    37647: 01/12/18: Re: FGPA express bidir pins Xilinx, FPGA-pmap-18
    37648: 01/12/18: Re: Xilinx Foundation - Routing constraints/prohibit
    37735: 01/12/19: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
    37780: 01/12/20: Re: Clocks and Synplify
    37781: 01/12/20: Re: clk_dll general question
    37784: 01/12/20: Re: Kindergarten Stuff
    37785: 01/12/20: Re: Hardware FPGA questions
    37786: 01/12/20: Re: The speedest FPGA
    37878: 01/12/22: Re: Kindergarten Stuff
    37978: 01/12/28: Re: The speedest FPGA
    38082: 02/01/04: Re: ACTEL SX-A serie and ROM implementation ...
    38083: 02/01/04: Re: A Fast counter in VHDL?
    38089: 02/01/04: Re: Configuration Times of FPGAs
    38090: 02/01/04: Re: multiplexing a clock
    38123: 02/01/06: Re: how do i program a Spartan FPGA
    38158: 02/01/07: Re: Regarding frequency achieving in fpga design
    38187: 02/01/08: Re: Suitability of Atmel for project?
    38200: 02/01/08: Re: Repost: Should clock skew be included for setup time analysis?
    38201: 02/01/08: Re: ROM synthesis question
    38235: 02/01/09: Re: How can I relate Virtex2 pin names and Slice XY loc?
    38236: 02/01/09: Re: how do i program a Spartan FPGA
    38319: 02/01/11: Re: Xilinx High speed I/O
    38385: 02/01/13: Re: Homebrew computers using FPGA?
    38427: 02/01/14: Re: Falling edge in PLD
    38428: 02/01/14: Re: CLKDLL cascade questions
    38429: 02/01/14: Radiation Resistance
    38479: 02/01/15: Re: Falling edge in PLD
    38480: 02/01/15: Re: SDH Pointer generator and Pointer interpreter
    38484: 02/01/15: Re: Radiation Resistance
    38528: 02/01/16: Re: Audio time delay circuit
    38561: 02/01/17: Re: Signal processing using FPGAs
    38595: 02/01/18: Re: Audio time delay circuit
    38596: 02/01/18: Re: CoreGen question
    38803: 02/01/25: Re: Xilinx webpack
    38839: 02/01/26: Re: Peaks in smaller PLDs
    38840: 02/01/26: Re: Xilinx webpack
    38841: 02/01/26: Re: Xilinx webpack
    38879: 02/01/27: Re: fpga device utilization
    38927: 02/01/28: Re: Peaks in smaller PLDs
    38928: 02/01/28: Re: Xilinx webpack
    38946: 02/01/28: Re: Peaks in smaller PLDs
    38958: 02/01/29: The LUT puzzle, Iam on the way
    38994: 02/01/29: Re: The LUT puzzle, Iam on the way
    38995: 02/01/29: Dont care simulation
    39045: 02/01/30: Re: 9 or 8 bits for image processing ?
    39055: 02/01/30: Re: The LUT puzzle, Iam on the way
    39061: 02/01/30: Re: The LUT puzzle, Iam on the way
    39156: 02/02/02: Re: Read Only Register
    39169: 02/02/03: Re: To Prevent Xilinx Mapper from Removing the RAMs in ISE 4.1i
    39170: 02/02/03: Re: odd divider
    39171: 02/02/03: Re: LARGE ultra low power FPGA/CPLD recommendation
    39172: 02/02/03: Re: BRAM, clka too short setup time
    39174: 02/02/03: Re: LARGE ultra low power FPGA/CPLD recommendation
    39217: 02/02/04: Re: Glitch detect
    39218: 02/02/04: Re: par and carry chains not allowing manual floorplanning
    39219: 02/02/04: Re: can comparisons glitch?
    39280: 02/02/05: Re: FPGA vs GAL : Lattice
    39281: 02/02/05: Re: FPGA vs GAL : Lattice
    39330: 02/02/06: Re: CLKDLL x4 problem
    39446: 02/02/10: Re: Help with getting started
    39449: 02/02/10: Re: Xilinx EDIF to BIT transation
    39454: 02/02/10: Re: Xilinx EDIF to BIT transation
    39477: 02/02/11: Re: XILINX Webpack 4.1 beginners question
    39478: 02/02/11: Re: Spartan Program/Verify
    39483: 02/02/11: Re: XILINX Webpack 4.1 beginners question
    39528: 02/02/12: Re: Newbie SpartanII Block Ram question
    39574: 02/02/13: Re: Newbie SpartanII Block Ram question
    39575: 02/02/13: Re: Altera's new family Stratix
    39576: 02/02/13: Re: RAM CORE settings for maximum speed
    39671: 02/02/15: Re: RAM CORE settings for maximum speed
    39672: 02/02/15: Re: Lean serial communication processor
    39674: 02/02/15: Re: SpartanXL & VHDL -- free software?
    39676: 02/02/15: Re: SpartanXL & VHDL -- free software?
    39677: 02/02/15: Re: Configuration in SelectMAP mode and CCLK
    39679: 02/02/15: Re: oscillation
    39699: 02/02/16: Re: SpartanXL & VHDL -- free software?
    39700: 02/02/16: Re: Xilinx Virtex XCV300
    39748: 02/02/18: Re: Do I need to install software in order to use Multilinx?
    39749: 02/02/18: Re: Edge selection with RAM
    39750: 02/02/18: Re: Timing constraints
    39789: 02/02/19: Re: Faster designs
    39868: 02/02/21: Re: Do I need to install software in order to use Multilinx?
    39869: 02/02/21: Re: Need largest CPLD devices?
    39870: 02/02/21: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
    39888: 02/02/21: Re: EDIF IN A VHDL PROJECT (kcpsm.edn) in ISE4.1
    39965: 02/02/22: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
    39966: 02/02/22: Re: Need largest CPLD devices?
    39967: 02/02/22: Re: init RAM in VirtexII
    39969: 02/02/22: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
    39970: 02/02/22: Re: CPLD PROJECT
    39979: 02/02/22: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
    40039: 02/02/25: Re: Few pins but more gates
    40041: 02/02/25: Re: Is it possible to have an output FF in IOB, but a tri-state control FF outside of IOB?
    40042: 02/02/25: Re: RAM question
    40045: 02/02/25: Re: Comparison between two FPGAs- what is decisive factor?
    40046: 02/02/25: Re: Virtex-E,Spartan2 and cpld jtag chain problem
    40110: 02/02/27: Re: RAM question
    40143: 02/02/28: Re: RAM question
    40144: 02/02/28: Re: FPGAs with differential LVDS terminations?
    40200: 02/03/01: Re: stuck in state in Spartan-II!
    40284: 02/03/04: Re: Constraining help required for clk_enable
    40286: 02/03/04: Re: Asynchronous boundaries in FPGA
    40326: 02/03/05: Re: Altera FPGAs
    40328: 02/03/05: Re: digital video PLL
    40351: 02/03/05: Re: Altera FPGAs
    40463: 02/03/07: Re: Xilinx ISE 4.1
    40591: 02/03/11: Re: MP3 decoder.
    40592: 02/03/11: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
    40593: 02/03/11: Re: SPI interface
    40716: 02/03/13: Re: Universal FPGA Programmer
    40749: 02/03/14: Re: Difference between Virtex-II(E) und Virtex-E
    40750: 02/03/14: Re: Virtex BUFGDLL
    40751: 02/03/14: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
    40752: 02/03/14: Re: Xilinix FPGA width 5V IO
    40758: 02/03/14: Re: Xilinix FPGA width 5V IO
    40792: 02/03/15: Re: Xilinix FPGA with 5V IO
    40794: 02/03/15: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
    40795: 02/03/15: Re: PCI design in a Spartan II which crashes in some wintel PCs
    40796: 02/03/15: Re: High speed clock routing
    40805: 02/03/16: Re: High speed clock routing
    40837: 02/03/16: Re: High speed clock routing
    40839: 02/03/16: Re: Why do I want to do this ??
    40999: 02/03/19: Re: FIFO general question
    41018: 02/03/19: Re: A petition for Synplify's new fature (FPGA synthesis tool)
    41019: 02/03/19: Re: Unused I/Os + External Clock on Virtex II
    41076: 02/03/20: Re: Missing Timing by 30,000 ns
    41077: 02/03/20: Re: XPOWER accuracy?
    41078: 02/03/20: Re: Unused I/Os + External Clock on Virtex II + P-P Jitter
    41080: 02/03/20: Re: A petition for Synplify's new fature (FPGA synthesis tool)
    41143: 02/03/21: Re: High speed clock routing
    41144: 02/03/21: Re: XPOWER accuracy?
    41161: 02/03/21: Re: cpga : Converting PAL design
    41210: 02/03/22: Re: Altera Stratix compared to Xilinx Virtex
    41218: 02/03/22: Re: Poor availability problems on Coolrunner
    41272: 02/03/24: Re: Help with Xilinx CoolRunner Problem
    41358: 02/03/26: Re: clock source
    41360: 02/03/26: Re: Help with Xilinx CoolRunner Problem
    41516: 02/04/01: Re: FPGA config without boot PROM???
    41517: 02/04/01: Re: ALTERA Apex Device
    41572: 02/04/02: Re: how to synchronise asynchronous inputs?
    41655: 02/04/04: Re: powerpc in virtex2pro
    41657: 02/04/04: Re: powerpc in virtex2pro
    41717: 02/04/05: Re: Parallel cable IV schematic available???
    41740: 02/04/06: Re: How sensitive is the EPM7064?
    41744: 02/04/06: Re: Distributed ram
    41745: 02/04/06: Re: A learner of Modelsim
    41752: 02/04/06: Re: Distributed ram
    41761: 02/04/07: Re: Xilinx programmer
    41763: 02/04/07: Re: FPGA config without boot PROM???
    41807: 02/04/08: Re: XST Synthesis tool
    41808: 02/04/08: Re: Xilinx programmer
    41869: 02/04/09: Re: Xilinx programmer
    41901: 02/04/10: Re: Need help with Insight Spartan II demo board and the counter demo.
    41902: 02/04/10: Re: Low-cost FPGA + processor board?
    41903: 02/04/10: Re: [OT] Implement buffers in CPLD.
    41946: 02/04/11: Re: Need help with Insight Spartan II demo board and the counter demo.
    41947: 02/04/11: Re: Low-cost FPGA + processor board?
    41990: 02/04/12: Re: Price List ?
    42053: 02/04/14: Re: Xilinx JTAG C Source
    42054: 02/04/14: Re: FPGA eval/dev boards with *serial* interface?
    42055: 02/04/14: Re: DLL property control in UCF
    42090: 02/04/15: Re: DLL property control in UCF
    42128: 02/04/16: Re: Reconfiguring Spartan II after boot-up
    42129: 02/04/16: Re: Power supply pins
    42171: 02/04/17: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in ISE4.2.01
    42215: 02/04/18: Re: Bidirectionnal bus...multiple sources driving the same signal...
    42216: 02/04/18: Understanding clock routing (or not)
    42224: 02/04/18: Re: 8051 Core for Motor Electronics
    42225: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
    42290: 02/04/19: Re: 1000 I/O Pins -- What is cheapest FPGA?
    42304: 02/04/19: A new experiment
    42324: 02/04/20: Re: Xilinx Easypath- Selling parts with known defects
    42325: 02/04/20: Re: XC9500XL problem
    42341: 02/04/21: Re: clock management in Virtex-E (DLL)
    42371: 02/04/22: Re: clock management in Virtex-E (DLL)
    42418: 02/04/23: Re: Xilinx Easypath- Selling parts with known defects
    42459: 02/04/24: Re: Variable freq
    42460: 02/04/24: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
    42461: 02/04/24: Re: Spartan JTAG and pullups
    42496: 02/04/25: Re: SpartanII design considerations...
    42497: 02/04/25: Re: Newbie with signals
    42536: 02/04/26: Re: Spartan II configuration
    42537: 02/04/26: Re: webpack : how to generate a .sdf and .vhd for simulation
    42538: 02/04/26: Re: SpartanII design considerations...
    42629: 02/04/29: Re: High current I/O on SpartanXL
    42660: 02/04/30: Re: clock buffer infered on master reset in ISE for spartan2E
    42773: 02/05/02: Re: Availability of XC2S150E-6FG456I
    42776: 02/05/02: Re: Xilinx Download Cable III
    42821: 02/05/03: Re: Availability of XC2S150E-6FG456I
    42843: 02/05/04: Re: Setting max skew in Xilinx software...
    42844: 02/05/04: Re: Pointer processor
    42845: 02/05/04: Re: Frequency synthesiser
    42858: 02/05/05: Re: SelectRAM and DCM
    42859: 02/05/05: Re: PDH MUX (E2,E3) and frame (E1,T1,E2 ...) based device VHDL examples
    42865: 02/05/05: Re: Frequency synthesiser
    42897: 02/05/06: Re: Frequency synthesiser
    42903: 02/05/06: Re: clock multiplication in xilinx
    42904: 02/05/06: Re: virtex2: clk via clk buf to BRAM
    42928: 02/05/07: Re: clock multiplication in xilinx
    42934: 02/05/07: Re: clock multiplication in xilinx
    42952: 02/05/08: Re: JTAG 5V tollerance...?
    43043: 02/05/10: Re: power supply sequencer for Virtex II
    43062: 02/05/11: Re: dual port fifo
    43176: 02/05/15: Re: PCI Board Project
    43217: 02/05/16: Re: PCI Board Project
    43265: 02/05/17: Re: virtex 2 block rams
    43290: 02/05/18: P&R times
    43430: 02/05/21: Re: Shift register or state machine
    43456: 02/05/21: Re: Driving high speed external devices from an FPGA
    43575: 02/05/24: Re: Small FIFOs in Spartan
    43620: 02/05/27: Re: Small FIFOs in Spartan
    43650: 02/05/28: Re: Frequency synthesiser
    43689: 02/05/29: Re: Frequency synthesiser
    43707: 02/05/30: Re: about Configure FLEX10K10 with 89c51
    43708: 02/05/30: Re: Frequency synthesiser
    43709: 02/05/30: Re: Frequency synthesiser
    43710: 02/05/30: Re: place and route simulation time
    43736: 02/05/31: Re: LFSR with 2^n instead of (2^n)-1
    43737: 02/05/31: Re: place and route simulation time
    43743: 02/05/31: Re: How to add delay in fpga(spartan)?
    43773: 02/06/02: Re: Clock double trigger problem
    43804: 02/06/03: Re: FPGA destruction possible?
    43805: 02/06/03: Re: Interfacing B5 spartan FPGA with a Motorola 68HC11
    43806: 02/06/03: Re: Pipelining
    43859: 02/06/04: Re: FPGA destruction possible?
    43860: 02/06/04: Re: Interfacing B5 spartan FPGA with a Motorola 68HC11
    43861: 02/06/04: Re: place and route simulation time
    43862: 02/06/04: Re: VirtexE DLL Output clock phase
    43898: 02/06/05: Re: burning a design
    43899: 02/06/05: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
    43930: 02/06/06: Re: How design a 10 bits counter by using an XILINX FPGA
    43931: 02/06/06: Re: IOSTANDARD
    43932: 02/06/06: Re: Xilinx JTAG verification failed
    44071: 02/06/11: Re: 20,000 gates?
    44134: 02/06/12: Re: 20,000 gates?
    44199: 02/06/13: Re: Searching for high performance PLD
    44287: 02/06/16: Re: Which is greater?
    44306: 02/06/17: Re: Power supply caps on PCB
    44312: 02/06/17: Re: Power supply caps on PCB
    44364: 02/06/18: Re: Another stupid WebPack question
    44365: 02/06/18: Re: what's the use of BlockRAM
    44412: 02/06/19: Re: uart code using vhdl
    44414: 02/06/19: Re: Xilinx .bit file via jtag ?
    44423: 02/06/19: Re: Xilinx .bit file via jtag ?
    44424: 02/06/19: Re: uart code using vhdl
    44455: 02/06/20: Re: Xilinx Bel - how do I find the Bel nane?
    44457: 02/06/20: How to generate a valid EDIF netlist?
    44462: 02/06/20: Re: How to generate a valid EDIF netlist?
    44466: 02/06/20: Re: How to generate a valid EDIF netlist?
    44500: 02/06/21: Re: Multiply by 8 with DLL in Spaertan-II.
    44501: 02/06/21: Re: How to generate a valid EDIF netlist?
    44502: 02/06/21: Re: adding timing constraints
    44558: 02/06/23: Re: Xilinx's 4.1i's Lastest webpack
    44600: 02/06/24: Re: skew control between different signals ?
    44601: 02/06/24: Re: Will this clock divider be good on hardware?
    44641: 02/06/25: Re: Will this clock divider be good on hardware?
    44674: 02/06/26: Re: skew control between different signals ?
    44732: 02/06/28: Re: Silly questions about configuring Spartan 2's
    44735: 02/06/28: Re: Problem: Designing for older FPGAs
    44745: 02/06/28: Re: State machine and syncronous inputs
    44746: 02/06/28: Re: Silly questions about configuring Spartan 2's
    44754: 02/06/29: Re: Programming a Xilinx CPDL with a Microcontroller
    44765: 02/06/29: Re: virtex2 : 180 deg. phase clocks
    44792: 02/07/01: Re: Can Coolrunner's be daisy chained?
    44830: 02/07/02: Re: Communication between FPGA and PC
    45573: 02/07/27: Re: can 555 be used as clock input to cplds
    45671: 02/07/31: Re: lots of shift registers
    45816: 02/08/06: Re: How to use distributed ram/luts ?
    45817: 02/08/06: Re: New XILINX ISE not supporting 4000 series FPGAs?
    45878: 02/08/08: Re: Xilinx TIG
    45879: 02/08/08: Re: ... milk for free, Opencores?
    45985: 02/08/13: Re: Xilinx XST inferred Block-RAM Initialization
    46108: 02/08/19: Re: onboard reconfiguration of Xilinx FPGA
    46237: 02/08/22: Re: onboard reconfiguration of Xilinx FPGA
    46239: 02/08/22: Re: Want a most simple develop board's design example for Xilinx FPGA(SP-II)?
    46240: 02/08/22: Re: combinatorial clocks
    46245: 02/08/22: Re: Downloading bit streams in Xilinx
    46267: 02/08/23: Re: programming xc9536 xl
    46302: 02/08/25: Re: Can I directly connect XTAL to SpartanXL ?
    46431: 02/08/29: Re: Problem: Spartan 2 E CCLK
    46432: 02/08/29: Re: Any FSM optimizer?
    46460: 02/08/30: Re: Question on Fast CPLDs
    46461: 02/08/30: Re: gate the main FPGA clk
    46479: 02/08/31: Re: A little question
    46480: 02/08/31: Re: gate the main FPGA clk
    46522: 02/09/02: Re: Hardware Code Morphing?
    46523: 02/09/02: Re: Basic question: configuring IOBs ???
    46524: 02/09/02: Re: A little question
    46558: 02/09/03: Re: Question about IOB, BUFG, IBUF and IBUG.
    46716: 02/09/06: Re: question about quiescent current
    46717: 02/09/06: Re: new in fpga
    46718: 02/09/06: Re: Neural hardware containing many neurons but very simple computation
    46725: 02/09/06: Re: XCR3384XL availability
    46728: 02/09/06: Re: Measuring FPGA performance eg max clock speed
    46735: 02/09/06: Re: XCR3384XL availability
    46751: 02/09/07: Re: why the need for HIGH speed design?
    46752: 02/09/07: Re: XCR3384XL availability
    46804: 02/09/09: Re: Metastability numbers
    46979: 02/09/13: Re: Xilinx TBUFs
    46981: 02/09/13: Re: number of IOBs in Spartan IIE is fishy
    46996: 02/09/13: Re: number of IOBs in Spartan IIE is fishy
    47011: 02/09/14: Re: Xilinx TBUFs
    47017: 02/09/14: Re: number of IOBs in Spartan IIE is fishy
    47018: 02/09/14: Re: Clcok divison : Rational clock divider
    47023: 02/09/14: Re: number of IOBs in Spartan IIE is fishy
    47027: 02/09/15: Re: Clcok divison : Rational clock divider
    47056: 02/09/16: Re: number of IOBs in Spartan IIE is fishy
    47057: 02/09/16: Re: 1.8V regulator needed for Spartan IIE
    47276: 02/09/22: Re: VHDL : Lookup Table
    47277: 02/09/22: Re: GCLK pin used like an standard input
    47283: 02/09/22: Re: Spartan II JTAG reconfiguration bug - workaround
    47285: 02/09/22: Re: Timing accuracy with Modelsim
    47313: 02/09/23: Re: Fast serial interconnect bus using spartan-II
    47364: 02/09/24: Re: Question about IOB, BUFG, IBUF and IBUG.
    47478: 02/09/26: Re: writing across a column in an SDRAM
    47527: 02/09/27: Re: implementation of adaptive FIR with many input channels?
    47544: 02/09/28: Re: Block Ram maximum speed
    47654: 02/10/01: Re: design multiplier
    47655: 02/10/01: Re: Rounting of non-global IO pad to a GCLKIOB site.
    47656: 02/10/01: Re: Where can i buy xilinx fpga online?
    47712: 02/10/02: Re: Moving average filter
    47800: 02/10/04: Re: TCP/IP in FPGA
    47801: 02/10/04: Re: implementation of adaptive FIR with many input channels?
    47802: 02/10/04: Re: Low power design
    47803: 02/10/04: Re: Parallel asyncronous configuration of an Altera FPGA
    47804: 02/10/04: Re: FPGA with an EPROM on it?
    47825: 02/10/04: Re: FPGA with an EPROM on it?
    47910: 02/10/07: Re: FPGA with an EPROM on it?
    48064: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48065: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48066: 02/10/10: Re: fpgaarcade update
    48067: 02/10/10: Re: how do initialised signals really get set in Xilinx slices?
    48075: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48077: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48078: 02/10/10: Re: fpgaarcade update
    48127: 02/10/11: Re: HELP !/ How to mark (find) signals in VHDL simulation.
    48187: 02/10/13: Re: Notation for Xilinx *.UCF files
    48223: 02/10/14: Re: Clk Problem
    48269: 02/10/15: Re: GCK as normal IO ?
    48270: 02/10/15: Re: Xilinx microblaze vs. picoblaze
    48284: 02/10/15: Re: Xilinx microblaze vs. picoblaze
    48286: 02/10/15: Re: FPGA breadboard with a SmartMedia Card to store the bit file.
    48341: 02/10/16: Re: HELP about signal integrity, PLEASE!
    48346: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48428: 02/10/17: Re: Clk Problem
    48429: 02/10/17: Re: Hobbyist FPGA
    48432: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48433: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48436: 02/10/17: Re: DIY Xilinx Parallel Cable III
    48501: 02/10/18: Re: Hobbyist FPGA
    48502: 02/10/18: Re: Size of configuration bitstream for xcv50 (xilinx)
    48538: 02/10/19: Re: FPGA breadboard with a SmartMedia Card to store the bit file.
    48539: 02/10/19: Re: altera lpm_divide megafunction
    48541: 02/10/19: Re: Hobbyist FPGA
    48553: 02/10/20: Re: problems with Insight 2S100 demo board
    48666: 02/10/22: Re: CLK question for the VHDL daddy
    48667: 02/10/22: Re: slow slew rate signal...
    48726: 02/10/23: Re: slow slew rate signal...
    48864: 02/10/25: Re: Please recommend a FPGA chip!
    48865: 02/10/25: Re: Just some newbie ISE questions...
    48866: 02/10/25: Re: DCM and CLK on Virtex2 PCIX controller
    48898: 02/10/26: Re: Just some newbie ISE questions...
    48899: 02/10/26: Re: Crystal oscillator question
    48900: 02/10/26: Re: cpld I/O modes
    48902: 02/10/26: Re: A PCI Data Aqcuisition Card Design
    48925: 02/10/27: Re: Announce: FPGA Demo Board
    48926: 02/10/27: Re: Announce: FPGA Demo Board
    48930: 02/10/27: Re: How to interpret Xilinx synthesis report
    48938: 02/10/27: Re: How to interpret Xilinx synthesis report
    49012: 02/10/29: Re: Virtex-II, Clocking a register without any clock
    49015: 02/10/29: Re: Xilinx POS Power On Surge Current (... the Starbucks connection)
    49066: 02/10/31: Re: XST Constraint
    49175: 02/11/04: Re: Excessive heating on Xilinx XC9500XL
    49176: 02/11/04: Re: pc to fpga cpu commands
    49303: 02/11/08: Re: BUFT bus contention
    49313: 02/11/08: Re: Spartan I with ISE Webpack
    49353: 02/11/10: Re: CLB numbers for various ops?
    49356: 02/11/10: Re: CLB numbers for various ops?
    49452: 02/11/12: Re: Efficient implementation memory-mapped regisetrs
    49454: 02/11/12: Re: EDIF generation from XST of ISE 5.1i
    49493: 02/11/13: Re: EPP slave interface
    49545: 02/11/14: Re: Programming a Spartan2 via JTAG
    49570: 02/11/15: Re: Metastability in FPGAs
    49578: 02/11/15: Re: FPGA board random error
    49637: 02/11/18: Re: counter error no matching overload for "+"
    49638: 02/11/18: Re: problem with clkdll on spartan2
    49639: 02/11/18: Re: Asynchronous FIFOs using Handel-C?
    49708: 02/11/19: Re: Asynchronous FIFOs using Handel-C?
    49739: 02/11/20: Re: spartan-II Block RAM
    49740: 02/11/20: Re: Are block RAMs supported in simulation?
    49749: 02/11/20: Re: Cpld beginner
    49750: 02/11/20: Re: problem with clkdll on spartan2
    49768: 02/11/20: Re: Cpld beginner
    49769: 02/11/20: Re: Are block RAMs supported in simulation?
    49813: 02/11/21: Re: XCS-05-3PC84 and XCS10-3PC84 Question
    49815: 02/11/21: Re: Look up tables
    49860: 02/11/22: Re: XCS-05-3PC84 and XCS10-3PC84 Question
    49865: 02/11/22: Re: XCS-05-3PC84 and XCS10-3PC84 Question
    49989: 02/11/27: Re: question about PCB traces for FPGA board... ?
    50296: 02/12/08: Re: and vs. nand
    50297: 02/12/08: Re: Clocking in a Spartan IIE
    50298: 02/12/08: Re: How to assign pins in VHDL?
    50420: 02/12/10: Re: FPGA startup events
    50512: 02/12/12: Re: FPGA startup events
    50514: 02/12/12: Re: FPGA startup events
    50846: 02/12/20: Re: Async RAM on an FPGA board
    50918: 02/12/23: Re: FPGA Supercomputing opportunity
    51352: 03/01/11: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
    51373: 03/01/12: Re: Open FPGA please!
    51381: 03/01/12: Re: Open FPGA please!
    51382: 03/01/12: Re: State machine problem
    51383: 03/01/12: Re: Open FPGA please!
    51384: 03/01/12: Re: SChematic design approach compared to VHDL entry approach
    51428: 03/01/13: Re: State machine problem
    51573: 03/01/16: Re: Xilinx Constraint Problem
    51625: 03/01/17: Re: Booting Spartan IIE from SPI
    51626: 03/01/17: Re: SpartanII DLL lock issue
    51669: 03/01/18: Re: Booting Spartan IIE from SPI
    51684: 03/01/19: Re: Booting Spartan IIE from SPI
    51772: 03/01/21: Re: FPGA new bie question
    51850: 03/01/23: Re: Using unbonded CPLD IO Pads?
    51925: 03/01/26: Re: Extending a Virtex-II block RAM?
    52011: 03/01/28: Re: JTAG
    52104: 03/01/31: Re: STATE PROBLEM!
    52121: 03/02/01: Re: Spartan2E and parallel port
    52128: 03/02/02: Re: Analog display in modelsim
    52168: 03/02/03: Re: Spartan2E and parallel port
    52169: 03/02/03: Re: FPGA Overclocking
    52410: 03/02/08: Re: XC9536XL - ISP
    52760: 03/02/20: Re: spartan2: combinatorial logic -> clock buffer = problem
    52901: 03/02/25: Re: Unprogrammed XC9536XL is driving the databus high
    53306: 03/03/10: Re: Using divided clock
    53443: 03/03/13: Re: Homemade Xilinx Parallel JTAG Download Cable
    53444: 03/03/13: Re: [Xilinx] Looking for Parallel Cable III ...
    53494: 03/03/14: Re: ROM containing complex numbers
    53592: 03/03/17: Re: new XC95xx global clock
    53593: 03/03/17: Re: Using divided clock
    53608: 03/03/17: Re: new XC95xx global clock
    53642: 03/03/18: Re: TEMPERATURE constraint in UCF
    53669: 03/03/19: Re: spartan-2 clocking problem
    53719: 03/03/20: Re: spartan-2 clocking problem
    54839: 03/04/20: Re: Very low pin count FPGA
    54935: 03/04/22: Re: spartan-3 vs cyclone
    54982: 03/04/23: Re: Challenge: (n mod 3) in hardware???
    55017: 03/04/24: Re: ADC input
    55308: 03/05/03: Re: use of DRAM as massive FIFO
    55333: 03/05/04: Re: cable length on homemade Parallel Cable III
    55334: 03/05/04: Re: PLL chips
    55360: 03/05/05: Re: cable length on homemade Parallel Cable III
    55361: 03/05/05: Re: Output switching time
    55480: 03/05/09: Re: help on FPGA-programming tutorial for students
    55481: 03/05/09: Re: Price of CPLDs
    55500: 03/05/10: Re: Encrypted bitstream - battery lifetime solved
    55518: 03/05/11: Re: Encrypted bitstream - battery lifetime solved
    55727: 03/05/17: Re: Urgent: About ModelSim XEII Starter
    56024: 03/05/27: Re: Xilinx Spartan download with Parallel III cable
    56285: 03/06/02: Re: power consumption in CMOS..
    56389: 03/06/04: Re: Xilinx Spartan download with Parallel III cable
    56492: 03/06/06: Re: fifo or bram in spartan2e vs spartan3
    56521: 03/06/07: Re: Xilinx Spartan download with Parallel III cable
    56522: 03/06/07: Re: Xilinx Spartan download with Parallel III cable
    56523: 03/06/07: Re: Logical analyzer via USB or printer port
    56608: 03/06/10: Re: Pseudo random shift register - > DAC
    56808: 03/06/16: Re: Downloading bit-stream with a microprocessor.
    56809: 03/06/16: Re: spartan 2e dll locking
    56885: 03/06/18: Re: FPGA GPU (Spartan IIe 300K)
    56938: 03/06/19: Re: FPGA GPU (Spartan IIe 300K)
    56989: 03/06/20: Re: Multiple clock generation and maybe FIFO
    56990: 03/06/20: Re: Please help with clock signal
    57036: 03/06/21: Re: Please help with clock signal
    57075: 03/06/23: Re: Virtex-II's IO Level?
    57390: 03/06/29: Re: clock signals
    57467: 03/07/01: Re: 48bit adder won't fit
    57539: 03/07/02: Re: Regarding NRZ
    57635: 03/07/03: Re: Regarding NRZ
    57863: 03/07/08: Re: Rant mode ON
    58006: 03/07/11: Re: Fpga design with multiple audio rate (44, 48khz ...)
    74549: 04/10/13: Re: Tristate
    76167: 04/11/27: XST question
    76187: 04/11/28: Re: XST question
    76188: 04/11/28: Re: Disable Global Buffer
    76189: 04/11/28: Re: dual-write port BRAM with XST/Webpack
    76245: 04/11/29: Re: XST question
    76247: 04/11/29: Re: XST question
    76248: 04/11/29: Re: XST question
    76249: 04/11/29: Re: dual-write port BRAM with XST/Webpack
    76251: 04/11/29: Re: dual-write port BRAM with XST/Webpack
    76252: 04/11/29: Re: CPLD + CAN bus
    76253: 04/11/29: Re: CPLD + CAN bus
    76254: 04/11/29: Re: CPLD + CAN bus
    76269: 04/11/29: Re: XST question
    76270: 04/11/29: Re: XST question
    76271: 04/11/29: Re: dual-write port BRAM with XST/Webpack
    76344: 04/11/30: Re: Stupid tools question...
    76577: 04/12/06: Re: how to speed up my accumulator ??
    76635: 04/12/08: Re: how to speed up my accumulator ??
    76674: 04/12/08: Re: how to speed up my accumulator ??
    76788: 04/12/12: Re: Software controllable clock generator, Xilinx Virtex-II
    76921: 04/12/15: Re: Digital clock synthesis
    76979: 04/12/18: Re: Digital clock synthesis
    77198: 04/12/29: Re: BRAM timing problem
    77291: 05/01/03: Re: Skew between signals
    77384: 05/01/05: Re: Skew between signals
    77419: 05/01/06: Re: Counter
    77420: 05/01/06: Re: Utilisation of Xilinx FPGAs
    77421: 05/01/06: Re: How to change temperature in Xilnx Webpack with free starter Modelsim
    77430: 05/01/06: Re: xilinx as video processor?
    77469: 05/01/07: Re: Synthesis of more FSMs in one file using DC
    77511: 05/01/08: Re: a general question
    77543: 05/01/10: Re: Editing bitstream
    77579: 05/01/11: Re: Editing bitstream
    77618: 05/01/12: Re: Editing bitstream
    77665: 05/01/13: Re: Programming and copyright
    77666: 05/01/13: Re: Programming and copyright
    77674: 05/01/13: Re: Doubts in XCF01S Programming.txt
    77699: 05/01/14: Re: Questions from a beginner...
    77788: 05/01/17: Re: Creating a pyramid of shift registers
    78167: 05/01/25: Re: ADPLL I Think ?
    78234: 05/01/26: Re: ADPLL I Think ?
    78298: 05/01/28: Re: LVDS without termination
    78401: 05/01/31: Re: Init of BRAMs with ISE flow.
    78485: 05/02/01: Re: Oscillator for Digilent Spartan 3 Starter Kit
    79070: 05/02/13: Re: Fast counting in Spartan 3
    79107: 05/02/14: Re: clock division / multiplication in xilinx cpld
    79194: 05/02/15: Re: Cyclone clock
    79204: 05/02/15: Re: Xilinx Post Place and Route FIFO problems
    79205: 05/02/15: Re: Xilinx Post Place and Route FIFO problems
    79206: 05/02/15: Re: See the next high-wire act, this time on power consumption
    79351: 05/02/17: Re: binary constant divider theory
    79408: 05/02/18: Re: binary constant divider theory
    79409: 05/02/18: Re: Updated Stratix II Power Specs & Explanation
    79410: 05/02/18: Re: CRC-4 algorithm using in G.704(&G.706)
    79411: 05/02/18: Re: Xilinx: Pitfalls of chaining DLLs
    79502: 05/02/20: Re: Antti Lukats: all my past live projects to be published...
    79524: 05/02/20: Re: Antti Lukats: all my past live projects to be published...
    79527: 05/02/20: Re: difficult to build counter, some help please : (
    79544: 05/02/20: Re: Antti Lukats: all my past live projects to be published...
    79545: 05/02/21: Re: difficult to build counter, some help please : (
    79592: 05/02/21: Re: Sending information between VHDL modules from the top level module
    79653: 05/02/22: Re: Frequence max: many question from a beginner
    79705: 05/02/23: Re: Is there any compatibility difference between The parallel JTAG PC4 and JTAG III??
    79706: 05/02/23: Re: Hardcopy Vs ASIC
    79721: 05/02/23: Re: Hardcopy Vs ASIC
    79722: 05/02/23: Re: Spartan-3 partial reconfiguration trouble
    79737: 05/02/23: Re: Frequence max: many question from a beginner
    79738: 05/02/23: Re: The real performance leader: V4
    79807: 05/02/24: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
    79815: 05/02/24: Re: Multiple addition(2)
    79816: 05/02/24: Re: Multiple additions
    79879: 05/02/25: Re: pld macrocell usage
    79880: 05/02/25: Re: Fast 28x28 multiplier + adder in Virtex4
    79949: 05/02/26: Re: setup-hold time problems
    80026: 05/02/28: Re: difficult to build counter, some help please : (
    80033: 05/02/28: Re: difficult to build counter, some help please : (
    80094: 05/03/01: Re: FPGA interface to an asynchronous microcontroller memory bus
    80115: 05/03/01: Re: SR latches in Xilinx devices?
    80190: 05/03/02: Re: SR latches in Xilinx devices?
    80192: 05/03/02: Re: Resetting Virtex II BlockRAM
    80203: 05/03/02: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
    80302: 05/03/03: Re: making an fpga hot - addendum
    80303: 05/03/03: Re: V4 SI: The package is thrilling, but the Cin is bleak
    80304: 05/03/03: Re: PLL code
    80389: 05/03/04: Re: PLL code
    80390: 05/03/04: Re: 1,5Mhz Clock
    80391: 05/03/04: Re: SR latches in Xilinx devices?
    80392: 05/03/04: Re: Maximum Current utilized by Spartan-3
    80397: 05/03/04: Re: SR latches in Xilinx devices?
    80418: 05/03/05: Re: high fan out skew in v2pro
    80419: 05/03/05: Re: state encoding in FSM for simple cases ?
    80424: 05/03/05: Re: simulation and real world
    80803: 05/03/11: Re: Over-Sampling
    81164: 05/03/18: Re: Newbie: Slow FPGAs
    81203: 05/03/19: Re: rocketio
    81229: 05/03/19: Re: rocketio
    81251: 05/03/20: Re: Post-map simulation models
    81258: 05/03/20: Re: RS 232 receiver using spartan 3 board
    82212: 05/04/08: Re: Clock Jitter on Xilinx FPGA
    83099: 05/04/23: Re: Speed acceleration !!!
    83466: 05/04/30: Re: VGA sync signals
    84189: 05/05/13: Re: Whats going on here?
    84619: 05/05/23: CPLD Fitting problem
    84636: 05/05/23: Re: CPLD Fitting problem
    84993: 05/06/02: Re: Clock Generation : FPGA
    85051: 05/06/03: Re: Clock Generation : FPGA
    85052: 05/06/03: Re: Clock Generation : FPGA
    85053: 05/06/03: Re: PCI master clock trace
    85054: 05/06/03: Re: ispLSI1016
    85055: 05/06/03: Re: keypad scanner
    85056: 05/06/03: Re: keypad scanner
    85057: 05/06/03: Re: Clock Generation : FPGA
    85063: 05/06/03: Re: ispLSI1016
    85064: 05/06/03: Re: ispLSI1016
    85096: 05/06/04: Re: ispLSI1016
    85170: 05/06/06: Re: keypad scanner
    85293: 05/06/07: Re: Clock doubler to double an input 13.5 Mhz
    85295: 05/06/07: Re: Clock doubler to double an input 13.5 Mhz
    85296: 05/06/07: Re: Sch & Layout Free Program
    85297: 05/06/07: Re: Fast/low area Sorting hardware.
    85314: 05/06/07: Re: Fast/low area Sorting hardware.
    85318: 05/06/07: Re: faster Spartan III adder
    85369: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
    85370: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
    85379: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
    85439: 05/06/09: Re: faster Spartan III adder
    85441: 05/06/09: Re: Can I use a 18k ram as 2 single-port ram?
    85454: 05/06/09: Re: faster Spartan III adder
    85524: 05/06/10: Re: not clear about doing power estimation using xpower
    85525: 05/06/10: Re: pcb layers on BGAs Spartan-3
    85526: 05/06/10: Re: Gated clock question
    85532: 05/06/10: Re: fast universal compression scheme and its implementation in VHDL
    85534: 05/06/10: Re: FPGA : MAC FIR doubt--HELP ME PLEASE
    85539: 05/06/10: Re: pcb layers on BGAs Spartan-3
    85540: 05/06/10: Re: re:pcb layers on BGAs Spartan-3
    85544: 05/06/10: Re: computer upgrade time.
    85554: 05/06/10: Re: pcb layers on BGAs Spartan-3
    85580: 05/06/11: Re: pcb layers on BGAs Spartan-3
    85581: 05/06/11: Re: pcb layers on BGAs Spartan-3
    85612: 05/06/12: Re: Can I use a 18k ram as 2 single-port ram?
    85614: 05/06/12: Re: Can I use a 18k ram as 2 single-port ram?
    85626: 05/06/12: Re: Synplify vs XST...
    85658: 05/06/13: Re: Synplify vs XST...
    85707: 05/06/14: Re: Gated clock question
    85759: 05/06/15: Re: Stratix Kit EP1S25 Boot problem
    85760: 05/06/15: Re: Best Practices for Hardware Designers
    85761: 05/06/15: Re: Best Practices for Hardware Designers
    85907: 05/06/17: Re: Xlinix configuration: DONE pin too early?
    85980: 05/06/19: Re: Interesting question on CPLD
    86012: 05/06/20: Re: BIG PROBLEM : Configuration Boot Problem Stratix
    86015: 05/06/20: Re: Design tools comparison between Xilinx, Altera and Lattice for FPGA designs
    86072: 05/06/21: Re: BIG PROBLEM : Configuration Boot Problem Stratix
    86167: 05/06/22: Re: Area_Group
    86168: 05/06/22: Re: Frequency divisors
    86528: 05/06/29: Re: ADPLL for NRZ
    86529: 05/06/29: Re: ADPLL for NRZ
    86530: 05/06/29: Re: Small FPGA
    86532: 05/06/29: Re: Small FPGA
    86645: 05/07/01: Re: Foundation 3.1 in WinXP machine Problems!
    86787: 05/07/06: Re: fastest FPGA speed grade?
    86793: 05/07/06: Re: fastest FPGA speed grade?
    86899: 05/07/08: Re: fastest FPGA speed grade?
    86908: 05/07/08: Re: Timespec for DCM outputs (Spartan 3) ?
    86937: 05/07/10: Re: design does not fit in device
    87402: 05/07/22: Re: parallel optic availability
    88737: 05/08/26: Re: Phase Offset in Xilinx DDS Core
    88776: 05/08/28: Re: mails from Aman Mediratta
    89012: 05/09/02: Re: CPLD CoolRunner-II - IO current limited to 8mA?
    89013: 05/09/02: Re: I2C "SCL" line problem
    89014: 05/09/02: Re: LCD Interface
    89035: 05/09/03: Re: Spartan 3 Ram Instantiation
    89044: 05/09/03: Re: High baud rate chips for RS232 protocol
    89503: 05/09/16: Re: Is a CPLD appropriate for this triple PWM application?
    89513: 05/09/16: Re: Is a CPLD appropriate for this triple PWM application?
    89698: 05/09/22: Re: downlaoding bit files to Xilinx FPGA
    89721: 05/09/23: Re: downlaoding bit files to Xilinx FPGA
    89967: 05/09/30: Re: PCB Software....
    89969: 05/09/30: Re: PCB Software....
    91139: 05/10/31: Re: hex rep. in VHDL
    91404: 05/11/05: Re: Why Spartan-3e is the best
    96415: 06/02/03: Re: [map error] unable to pack a IBUF into the IOB
    96478: 06/02/04: Re: BGA central ground matrix
    96485: 06/02/04: Re: BGA central ground matrix
    97038: 06/02/15: Re: News from Embedded World in Nurnber
    97045: 06/02/15: Re: News from Embedded World in Nurnber
    97266: 06/02/20: Re: FPGA - software or hardware?
    97273: 06/02/20: Re: Cheating at homework (from "Re: FPGA - software or hardware?")
    97293: 06/02/20: Re: DDR SDRAM Controller
    97294: 06/02/20: Re: Is FPGA code called firmware?
    97303: 06/02/20: Re: Is FPGA code called firmware?
    97304: 06/02/20: Re: Is FPGA code called firmware?
    97315: 06/02/20: Re: Is FPGA code called firmware?
    97351: 06/02/21: Re: Is FPGA code called firmware?
    97358: 06/02/21: Re: Is FPGA code called firmware?
    97760: 06/02/27: Re: Combinatorial Division?
    99345: 06/03/23: Re: this JTAG thing is a joke
    99369: 06/03/23: Re: this JTAG thing is a joke
    99384: 06/03/23: Re: this JTAG thing is a joke
    99541: 06/03/26: Re: need help,test on Spartan3 starter kit
    99610: 06/03/27: Re: Clock multiplication without using the Xilinx DCM's
    99806: 06/03/29: Re: Stratum4E holdover
    99819: 06/03/29: Re: Stratum4E holdover
    99821: 06/03/30: Re: deglitching a clock
    99855: 06/03/30: Re: Stratum4E holdover
    99858: 06/03/30: Re: Stratum4E holdover
    99932: 06/03/31: Re: Picoblaze, UART: need help!!
    99933: 06/03/31: Re: Interface Problem
    99954: 06/03/31: Re: Interface Problem
    99956: 06/03/31: Re: deglitching a clock
    101784: 06/05/06: Re: FPGA-based hardware accelerator for PC
    101812: 06/05/07: Re: FPGA-based hardware accelerator for PC
    101813: 06/05/07: Re: flashing a led
    101884: 06/05/08: Re: Xilinx 3s8000?
    102081: 06/05/10: Re: CoolRunner XPLA3 getting axed?
    102088: 06/05/10: Re: CoolRunner XPLA3 getting axed?
    102090: 06/05/10: Re: CoolRunner XPLA3 getting axed?
    102091: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
    102094: 06/05/10: Re: CoolRunner XPLA3 getting axed?
    102179: 06/05/11: Re: CoolRunner XPLA3 getting axed?
    102320: 06/05/15: Re: difference of variable and signal
    102346: 06/05/15: Re: Make a signal free for glitches?
    102376: 06/05/15: Re: Virtex 5 announced and sampling
    102478: 06/05/16: Re: Virtex4 FX12 dynamic clock divider
    102479: 06/05/16: Re: Spartan 3E
    102515: 06/05/17: Re: Virtex4 FX12 dynamic clock divider
    102516: 06/05/17: Re: hy I need a code example for spartan 3 series in Xilinx regarding
    102519: 06/05/17: Re: Virtex4 FX12 dynamic clock divider
    102536: 06/05/17: Re: "disappointing" 550Mhz performance of V5 DSP slices
    102537: 06/05/17: Re: CoolRunner Pins during Programming
    102554: 06/05/17: Re: "disappointing" 550Mhz performance of V5 DSP slices
    102555: 06/05/17: Re: "disappointing" performance
    102563: 06/05/17: Re: DCM
    102640: 06/05/18: Re: FPGA Configuration Question
    102660: 06/05/19: Re: DCM and Clock
    102693: 06/05/19: Re: DCM and Clock
    102718: 06/05/19: Re: ADC implementation on FPGA ?
    102719: 06/05/19: Re: generate a square signal with a 3.8 ns
    102734: 06/05/19: Re: generate a square signal with a 3.8 ns
    102742: 06/05/19: Re: [Newbie] Suitable FPGA for my project
    102746: 06/05/19: Re: Suitable FPGA for my project
    102759: 06/05/19: Re: PLB clocking
    102765: 06/05/20: Re: CPLD (CoolRunner) failures.
    102780: 06/05/20: Re: Suitable FPGA for my project
    102804: 06/05/21: Re: CPLD (CoolRunner failures)
    102807: 06/05/21: Re: CPLD (CoolRunner failures)
    102947: 06/05/24: Re: I2C on Xilinx V4
    102991: 06/05/24: Re: Independent clock FIFOs
    102992: 06/05/24: Re: fpga debug
    102995: 06/05/24: Re: fpga debug
    103226: 06/05/29: Re: XC9572 Readback
    103299: 06/05/30: Re: fpga debug
    103330: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103387: 06/06/01: Re: clockless arbiters on fpgas?
    103388: 06/06/01: Re: Virtex4 FX12 - maximum frequency for Picoblaze
    103890: 06/06/14: Re: Current from FPGA pins to ADC
    104014: 06/06/16: Re: High speed differential to single ended
    104016: 06/06/16: Re: High speed differential to single ended
    104019: 06/06/16: Re: High speed differential to single ended
    104070: 06/06/18: Re: High speed differential to single ended
    104074: 06/06/18: Re: High speed differential to single ended
    104247: 06/06/21: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104273: 06/06/22: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104301: 06/06/23: Re: is picoblaze worth in my project?
    104320: 06/06/23: Re: Optimization of Multiplication in FPGA
    104349: 06/06/25: Re: Newbie to FPGA
    104386: 06/06/26: Re: PicoBlaze and DDR Ram
    104703: 06/07/04: Re: ADPLL (50Hz to 2kHz)
    105533: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105549: 06/07/25: Re: Issues w/ 8 lane Aurora sample design
    105575: 06/07/26: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105588: 06/07/26: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105590: 06/07/26: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105596: 06/07/26: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105714: 06/07/29: Re: Issues w/ 8 lane Aurora sample design
    105715: 06/07/29: Re: large data access to SDRAM at fixed frequency
    105716: 06/07/29: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
    105832: 06/08/01: Re: 100m JTAG cable
    107012: 06/08/23: Re: DQPs
    107063: 06/08/24: Re: Block RAM vs Flip Flop
    107068: 06/08/24: Re: Block RAM vs Flip Flop
    107361: 06/08/27: Re: FPGA -> SATA?
    107411: 06/08/28: Re: Spartan-4 ?
    107415: 06/08/28: Re: Spartan-4 ?
    107448: 06/08/28: Re: RocketIO over cable
    109291: 06/09/23: Re: DCM virtex II pro
    109468: 06/09/27: Re: Configuration of Spartan 3 devices
    109472: 06/09/27: Re: Configuration of Spartan 3 devices
    109604: 06/09/30: Re: DDR RAM
    109835: 06/10/06: Re: Design of a programmable delay line
    109840: 06/10/06: Re: Design of a programmable delay line
    109848: 06/10/06: Re: Design of a programmable delay line
    109883: 06/10/06: Re: Design of a programmable delay line
    110002: 06/10/09: Re: a clueless bloke tells Xilinx to get a move on
    110021: 06/10/09: Re: FPGA to SRAM port interface
    110060: 06/10/10: Re: FPGA to SRAM port interface
    110071: 06/10/10: Re: FPGA to SRAM port interface
    128236: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
    128239: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
    128457: 08/01/27: Re: FPGA decoupling calculation
    128458: 08/01/27: Re: FPGA decoupling calculation
    128462: 08/01/27: Re: FPGA decoupling calculation
    128466: 08/01/27: Re: FPGA decoupling calculation
    128565: 08/01/31: Re: Xilinx prom programming problem
    128621: 08/01/31: Re: FPGA in Telecommunications
    128660: 08/02/02: Re: Why use small resistor for Vcco voltage regulator
    128759: 08/02/06: Re: Possible CRC error on XC3S400 - now what?
    128784: 08/02/06: Re: Single Top FPGA Tips
    128816: 08/02/07: Re: Shutdown parts of core logic on FPGA
    129547: 08/02/27: Re: Interview questions
    129644: 08/03/01: Re: FPGA's be afraid, very afraid, of my wife!
    130681: 08/03/30: Re: async clk input, clock glitches
    147012: 10/04/09: Problems with data2mem
    147019: 10/04/09: Re: Problems with data2mem
    147023: 10/04/09: Re: Problems with data2mem
Falk Salewski:
    75205: 04/10/29: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
    75210: 04/10/29: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
    75327: 04/11/02: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
    75360: 04/11/03: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
    76213: 04/11/29: CPLD + CAN bus
    76216: 04/11/29: Re: CPLD + CAN bus
    76225: 04/11/29: Re: CPLD + CAN bus
    76226: 04/11/29: Re: CPLD + CAN bus
    83002: 05/04/21: low budget SystemC to VHDL Compiler?
    83004: 05/04/21: HDL in safety critical applications
    100876: 06/04/20: Reliability CPLD/FPGA vs Microcontroller
    100921: 06/04/21: Re: Reliability CPLD/FPGA vs Microcontroller
    101202: 06/04/27: Re: Reliability CPLD/FPGA vs Microcontroller
    101640: 06/05/04: Re: Reliability CPLD/FPGA vs Microcontroller
    102315: 06/05/15: safety critical applications with FPGAs/CPLDs
    102317: 06/05/15: Re: difference of variable and signal
    102427: 06/05/16: Re: safety critical applications with FPGAs/CPLDs
    102727: 06/05/19: Re: Multiple Independent Circuits on a Single FPGA
<falk.brunner@gmx.de>:
    133685: 08/07/09: Re: JTAG IR length detection
Falser Klaus:
    36408: 01/11/08: Re: Quadrature Encoder Sampling Time
    36823: 01/11/21: Re: jtag programming xilinx cpld
    37283: 01/12/06: Re: Installing ISE 4.1i
    50580: 02/12/13: Re: Can I use bus keeper like this?
    52920: 03/02/26: Re: Unprogrammed XC9536XL is driving the databus high
    53739: 03/03/21: Re: programmer adapter for Xilinx XC9572
    54701: 03/04/16: Impact : Using functional test
    55839: 03/05/21: Re: FPGA: Feasibility of Memory testing
    56071: 03/05/28: Re: Xilinx Spartan download with Parallel III cable
    56073: 03/05/28: Re: IL711 with LVDS
    56130: 03/05/29: Re: need help on sending 500Mbit/s data through 100 feet of cable, Giga-Ethernet?
    71488: 04/07/20: Re: Xilinx XC9500 CPLD internal pull-up??
<fancier.fpga@googlemail.com>:
    117786: 07/04/10: Ross Freeman - inventor of the FPGA
    117794: 07/04/10: Re: Ross Freeman - inventor of the FPGA
fanf:
    77028: 04/12/20: Access to SDRAM on Altera Cyclone dev kit - compactflash controller
FAQ:
    49453: 02/11/12: buffer ports on lower level VHDL modules
<faraz.khan@nssi.us>:
    99874: 06/03/30: Help needed
    99900: 06/03/30: Interface Problem
    99901: 06/03/30: Re: Help needed
    99905: 06/03/30: BlockRAM
    99947: 06/03/31: Re: Interface Problem
    99957: 06/03/31: FIFO Vs Shift Register
    99958: 06/03/31: Re: Interface Problem
    99979: 06/03/31: Discrete
Fargo:
    66890: 04/02/28: Pbl uploading code on a Spartan II board
    66899: 04/02/29: [solved] Pbl uploading code on a Spartan II board
Farhad A:
Farhad A.:
    77407: 05/01/06: Re: San Jose job offer - need advice
    77457: 05/01/07: Re: San Jose job offer - need advice
Farhad Abdolian:
    8353: 97/12/10: Re: Need a fast ADC
    12731: 98/10/26: Q: Configure FPGA from an ISA bus?
    12842: 98/11/01: Re: Q: Configure FPGA from an ISA bus?
    12967: 98/11/08: Re: FPGA VGA interface
    13144: 98/11/17: Atmel AT17C010?
    13175: 98/11/18: Re: Atmel AT17C010?
    14671: 99/02/10: Q: How to add contstraints in synopsys->Xilinx?
    18006: 99/09/22: Reset signal and Altera's FPGAs
    44325: 02/06/17: 12 years experience in Digital HW/ FPGA design, looking for job in the US
    44434: 02/06/19: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
    47222: 02/09/20: Re: Overheat with XCV-600E
    47471: 02/09/26: Re: Finding nets in hierarchy
    47557: 02/09/28: Re: Does it need any protection circuit for Interfacing FPGA device with PC ISA slot?
    47585: 02/09/30: Re: design multiplier
    47607: 02/09/30: Re: design multiplier
    147238: 10/04/20: Re: Developin tool for Xilinx XC2018
Farhan:
    64049: 03/12/13: WORK IN PROCESSOR BASED FPGAS - VERTEXII PRO
    64217: 03/12/20: WHAT APPLICATION WE CAN IMPLEMENT ON VERTEX II PRO
    64411: 04/01/02: Partitioning Problem in FPGA and Its Embedded PC Core
farhanakram:
    148785: 10/08/24: problem with using DCM of virtex 4
farnel:
    86933: 05/07/09: Altera QII WE Tutorials
FarseeR:
    144441: 09/12/08: Design a delay line from 10ns to 0.1s
FAS3:
    79301: 05/02/17: VGA core
    79556: 05/02/20: downloading program to external ram
    79960: 05/02/27: Platform Cable USB
fasf:
    149040: 10/09/23: Virtex6 quote
    149043: 10/09/23: Re: Virtex6 quote
    149353: 10/10/18: IO pin question
    149363: 10/10/18: Re: IO pin question
    149368: 10/10/19: Re: IO pin question
    149377: 10/10/20: Re: IO pin question
    149390: 10/10/21: Re: IO pin question
    149392: 10/10/21: Re: IO pin question
    150121: 10/12/15: Question about SOPC and SOF file
FaSt:
    67925: 04/03/22: all03 adapter
FastConnexion:
<fastgreen2000@yahoo.com>:
    83969: 05/05/10: Virtex4 running at 360Mhz DDR
    83971: 05/05/10: Re: Virtex4 running at 360Mhz DDR
    84102: 05/05/12: Re: Virtex4 running at 360Mhz DDR
    84319: 05/05/17: Re: Virtex4 running at 360Mhz DDR
    89937: 05/09/30: Testbench using Modelsim/VHDL - simple signal generation problem
    89942: 05/09/30: Re: Testbench using Modelsim/VHDL - simple signal generation problem
    89943: 05/09/30: Re: Testbench using Modelsim/VHDL - simple signal generation problem
    89960: 05/09/30: Re: Testbench using Modelsim/VHDL - simple signal generation problem
    91651: 05/11/10: Re: Can't pack into OLOGIC
    91652: 05/11/10: Re: Can't pack into OLOGIC
    119037: 07/05/09: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
    119063: 07/05/10: Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
    119072: 07/05/10: Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
    120978: 07/06/21: Modelsim simulation Q
    121086: 07/06/25: Re: Modelsim simulation Q
    124292: 07/09/17: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
    124313: 07/09/18: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
Fat Cat:
    77108: 04/12/23: Audio Codec '97...How big is the core size without pads with 0.18um?
    77906: 05/01/20: C programmer, what does this syntax mean?
fatalist:
    152811: 11/10/25: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152826: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152836: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152924: 11/11/01: Re: Fundamental DSP/speech processing patent for sale
    152946: 11/11/03: Re: Fundamental DSP/speech processing patent for sale
    152948: 11/11/03: Re: Fundamental DSP/speech processing patent for sale
    152975: 11/11/07: Re: Fundamental DSP/speech processing patent for sale
    152978: 11/11/07: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152990: 11/11/07: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152994: 11/11/08: Re: Fundamental DSP/speech processing patent for sale
    152996: 11/11/09: Re: Fundamental DSP/speech processing patent for sale
FatBoySlim:
    72596: 04/08/26: JTAG software
Fateh A. Tipu:
    968: 95/04/05: Re: Opinions on IBM PowerPC for Electronics CAD lab
fatfpga@googlemail.com:
    132467: 08/05/28: error when 'generating simulation hdl files' in xilinx xps
    132571: 08/05/31: Re: error when 'generating simulation hdl files' in xilinx xps
    132948: 08/06/11: Re: error when 'generating simulation hdl files' in xilinx xps
    133162: 08/06/19: DMA_BURST_SIZE in Xilinx EDK 9.1i
    133384: 08/06/26: How to start DMA from user_logic.vhdl (hardware side)
fath:
    111868: 06/11/11: SDRAM of Spartan 3E
fatima:
    128532: 08/01/29: define a new bust interface
<fatlad@my-dejanews.com>:
    11772: 98/09/08: Re: Altera 10K20 Register File Implementation??
Faycal Bensaali:
    49273: 02/11/07: Re: fir filter mit xilinx coregen
Fayette:
    77225: 04/12/31: SDRAM
    78048: 05/01/23: imported ip
    78049: 05/01/23: Re: imported ip
    78089: 05/01/24: Re: imported ip
    78369: 05/01/31: OPB IPIF user register interface
Fayette Sims:
    79074: 05/02/13: IPIF
faza:
    132681: 08/06/05: Re: FPGA clock frequency
    132700: 08/06/05: Re: FPGA clock frequency
    132706: 08/06/05: Re: FPGA clock frequency
    132761: 08/06/06: Re: FPGA clock frequency
    132841: 08/06/09: Re: FPGA clock frequency
    132848: 08/06/09: Re: FPGA clock frequency
    132858: 08/06/09: Re: FPGA clock frequency
    132894: 08/06/10: Re: FPGA clock frequency
    132905: 08/06/10: Re: FPGA clock frequency
    132906: 08/06/10: Re: FPGA clock frequency
    132987: 08/06/12: Re: FPGA clock frequency
    133046: 08/06/16: Re: FPGA clock frequency
    133063: 08/06/16: Re: FPGA clock frequency
    133075: 08/06/17: Re: FPGA clock frequency
    133094: 08/06/18: Fixed point number hardware implementation
    133111: 08/06/18: Re: Fixed point number hardware implementation
    133147: 08/06/19: Re: Fixed point number hardware implementation
    133191: 08/06/20: Re: Fixed point number hardware implementation
    133198: 08/06/20: Re: Fixed point number hardware implementation
fazulu deen:
    122010: 07/07/17: BD
    122083: 07/07/18: Re: BD
    122423: 07/07/27: doubts
    123224: 07/08/20: exe file in modelsim
    123557: 07/08/30: modelsim
    123562: 07/08/30: Re: modelsim
    123587: 07/08/30: Re: modelsim
    125719: 07/11/01: fpga based designs
    126031: 07/11/12: bidirectional in fpga
    126035: 07/11/12: Re: bidirectional in fpga
    126535: 07/11/27: Bidirectional open drain port
    126580: 07/11/27: device utilization
    126840: 07/12/03: calculation of clock cycle /instructions...
    126866: 07/12/05: clock cycle per Instructions
    132127: 08/05/14: FPGA imp
    132130: 08/05/15: Re: FPGA imp
    132137: 08/05/15: Re: FPGA imp
    132267: 08/05/19: synthesis...
    132312: 08/05/21: Re: synthesis...
    132330: 08/05/21: Re: synthesis...
    132397: 08/05/25: Re: FPGA Programing file
    132436: 08/05/27: FIR filter o/p width
    132510: 08/05/29: FIR in FPGA
    132517: 08/05/29: Re: FIR in FPGA
    132554: 08/05/31: cutoff frequency
    132558: 08/05/31: Re: cutoff frequency
    132562: 08/05/31: Re: cutoff frequency
    132572: 08/06/01: Re: cutoff frequency
    132670: 08/06/05: FPGA clock frequency
fb:
    51234: 03/01/08: USB OPENCORE IP usage
<FBergemann@web.de>:
    122669: 07/08/02: Re: Altera or Xilinx
fbob:
    137924: 09/02/02: auto reset / rs 232
<fbs.consulting@gmail.com>:
    105917: 06/08/02: MicroBlaze SPI interrupts
<fbv999@gmail.com>:
    128810: 08/02/06: beleive
<fcdup8k@yahoo.com>:
    129165: 08/02/16: Synthesis-Place-Route benchmark for i386-32bit
fczhao:
    32925: 01/07/11: How to view BlockRam contents generated by Xilinx Coregenerator in Active Hdl 4.2 ?
    32926: 01/07/11: View Blockram content generated by Xilinx Coregenerator
fe:
    62706: 03/11/05: Re: Tools Tree
    62907: 03/11/10: Re: Implementing a very fast counterin VirtexII
    69105: 04/04/27: Re: Simulating two clock domains
FE:
    56410: 03/06/04: Re: FPGA's an Flash
    58744: 03/07/31: Re: binary to BCD assistance
    58871: 03/08/03: Re: Showing my ignorance of VHDL again...
    58911: 03/08/04: Re: Showing my ignorance of VHDL again...
    58919: 03/08/04: Re: Gates Counting?
    61277: 03/10/01: Re: OT: spam poll
    61281: 03/10/01: Re: DP RAM infering
    61547: 03/10/06: Re: Should I worry about metastability
Fe:
    55165: 03/04/29: Re: ModelsimSE5.6/5.7 crashes with ISE5.1i
feather head:
    33497: 01/07/28: Laid-off worker needs software
fecs2:
    89618: 05/09/20: JTAG USB Circuit
    90635: 05/10/18: Simple PWM Spartan 3
Fed:
    119693: 07/05/24: How to code a bidirectional databus?
    119740: 07/05/25: Re: How to code a bidirectional databus?
fede:
    36612: 01/11/13: Elliptic Curves
federico:
    34325: 01/08/21: hardware(FPGA,DSP......) that it implements a function random or method of runge kutta?
Federico Silla:
    20640: 00/02/16: Logiblox and virtex
<federico.corradi@gmail.com>:
    156255: 14/01/25: Re: Prog3 - USB Programming Solution for Xilinx
feedcaseg:
    98266: 06/03/07: speed control ac motor in FPGA
    98291: 06/03/08: Re: speed control ac motor in FPGA
    98353: 06/03/08: Re: speed control ac motor in FPGA
Fei:
    56944: 03/06/19: Investment in FPGA
Fei Liu:
    129407: 08/02/22: newbie seeking help to use xilinx spart-3a starter kit
    129413: 08/02/22: Re: newbie seeking help to use xilinx spart-3a starter kit
    129417: 08/02/22: Problem with PINs XC3S700A-4FG484
    129446: 08/02/24: Re: Problem with PINs XC3S700A-4FG484
    129476: 08/02/25: Re: Problem with PINs XC3S700A-4FG484
    129499: 08/02/26: Re: Problem with PINs XC3S700A-4FG484
    129804: 08/03/05: question about verilog language constructs
    129810: 08/03/05: Re: question about verilog language constructs
    129850: 08/03/06: XC3S50-4VQ100C fpga chip
    129894: 08/03/08: Re: XC3S50-4VQ100C fpga chip
    130354: 08/03/20: verilog question, break while loop to avoid combinational feedback
    130366: 08/03/21: Re: verilog question, break while loop to avoid combinational feedback
    130401: 08/03/21: problem testing the serial interface code from fpga4fun
    130416: 08/03/22: Re: problem testing the serial interface code from fpga4fun
    130868: 08/04/03: problem with synthesis
    130937: 08/04/05: problem with synthesis of a state machine
    130938: 08/04/05: Re: problem with synthesis of a state machine
    130941: 08/04/05: Re: problem with synthesis of a state machine
    130975: 08/04/07: Re: Spartan3 JTAG flash In System Programming over Ethernet
    131052: 08/04/08: looking for critique for a spartan3a lcd controller verilog module
    131103: 08/04/10: Re: looking for critique for a spartan3a lcd controller verilog module
    131134: 08/04/11: high noise/signal in a simple serial to mono dac module
    131140: 08/04/11: Re: high noise/signal in a simple serial to mono dac module
    131150: 08/04/13: Re: high noise/signal in a simple serial to mono dac module
    131153: 08/04/13: Re: high noise/signal in a simple serial to mono dac module
    131214: 08/04/15: Re: Which to learn: Verilog vs. VHDL?
    131665: 08/04/28: what's next?
    132448: 08/05/27: Re: Downloading external data file to FPGA
Felicia:
    26105: 00/10/04: Xilinx FPGA Modules: Delays & Ha
Felip Vicedo Roman:
    9703: 98/03/31: Altera Bitblaster or Byteblaster??
    10533: 98/05/28: Altera FLEX8k configuration problem
Felipe Joffre Romano Renon:
    42422: 02/04/23: Input Frequence
    42504: 02/04/25: Re: Input Frequence
Felipe Naves:
    56764: 03/06/13: download svf to fpga
Felix Bertram:
    29485: 01/02/23: Re: Virtex USB solution
    29726: 01/03/06: Re: Virtex USB solution
    29861: 01/03/14: Re: how to use both edges of clock
    31800: 01/06/06: Re: problem: bahavior simulation of xilinx's coregen cores
    31913: 01/06/08: Re: FPGA & uC8031
    32067: 01/06/12: Re: USB for a new FPGA based product, which transciever ?
    32693: 01/07/05: Re: Downloading FPGA (XBN) bitstream to XCV50E
    33673: 01/08/02: Re: spartan & atmel eeproms
    33925: 01/08/08: Re: I NEED TO BUY A FPGA BOARD
    34502: 01/08/28: Re: FPGA : USB in an FPGA, has anyone done it before?
    34503: 01/08/28: Re: new to fpga
    34511: 01/08/28: Re: FPGA : USB in an FPGA, has anyone done it before?
    34539: 01/08/29: Re: FPGA : USB in an FPGA, has anyone done it before?
    34840: 01/09/11: Re: DSP design kit.
    34897: 01/09/13: Re: Block RAM initialization
    42066: 02/04/15: Re: FPGA eval/dev boards with *serial* interface?
    42214: 02/04/18: Re: 8051 Core for Motor Electronics
    42750: 02/05/02: Re: usb 2.0 on FPGAs
    42816: 02/05/03: Re: Newbie--Where to start learning?
    43414: 02/05/21: Ann: Spartan-IIE development board
    43606: 02/05/27: Re: evaluation boards for virtex
    43788: 02/06/03: Re: Looking for FPGA board with USB interface
    44048: 02/06/11: Re: Information about FPGA
    44332: 02/06/18: Re: Pls Recommend a Development Board
    44398: 02/06/19: Re: ISE Webpack Basics
    44439: 02/06/20: Re: Pls Recommend a Xilinx development Board
    45799: 02/08/06: MicroBlaze bus config 1
    51844: 03/01/23: Re: free x86 core ip
    53162: 03/03/05: Re: Mac Os X for FPGA design
    99341: 06/03/23: Re: this JTAG thing is a joke
    100252: 06/04/05: Re: USB Interface to Virtex-4
    100314: 06/04/06: Re: USB Interface to Virtex-4
    102525: 06/05/17: Re: IEEE-1394 (aka FireWire) Core
    102526: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
    102579: 06/05/17: Re: IEEE-1394 (aka FireWire) Core
    102583: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
    102997: 06/05/24: Re: I2C on Xilinx V4
    103143: 06/05/26: Re: I2C on Xilinx V4
    103463: 06/06/02: WebPack on Linux
    103500: 06/06/04: Re: WebPack on Linux
    103781: 06/06/11: Re: Xilinx ISE S/W Install kernel version "mismatch"
Felix Brack:
    34097: 01/08/14: Looking for MAXPLUS DOS Version
Felix Deutsch:
    20701: 00/02/18: Re: protocol implementations
Felix K.C. CHEN:
    1796: 95/09/04: Altera's Max+Plus2 vhdl output, bad!
    1941: 95/09/22: LFSR's solution
    3169: 96/04/18: high gate count FPGA for small volumn production?
    3188: 96/04/22: Inferring or design ware (modgen)?
    3296: 96/05/10: which coding style is better for synthesis?
    3346: 96/05/17: is high input number mutliplxer inferrable?
    3382: 96/05/23: impossible for Synthesizer to optimize FSM??!
    3406: 96/05/25: my earlier post about non-optimal VHDL FSM synthesis
    3428: 96/05/29: more about optimal synthesis of FSM
    3452: 96/06/01: specify fanout limit for individual net (input pin) with Exemplar
    3495: 96/06/11: troubles on the way from exemplar to Altera's MAX+PLUSII
    3535: 96/06/17: Re: troubles on the way from exemplar to Altera's MAX+PLUSII
    3536: 96/06/17: Re: synthesized VHDL output
    3619: 96/07/04: Re: FPGA Companies
    3620: 96/07/04: Re: FSM encoding in VHDL with MAX+plusII
    3640: 96/07/07: why? internal error in VSS when simulting
    3717: 96/07/21: What does the timing report from Synthesizer mean?
    4719: 96/12/06: what is "token chain"?
Felix Madlener:
    51766: 03/01/21: Re: Tristate vs. MUX
    57234: 03/06/26: Bitstream description for Virtex2 Pro
    57409: 03/06/30: Re: I need a commercial PCI FPGA board, please help
    61708: 03/10/09: Re: Installing Xilinx 6.1 under Linux
    69219: 04/04/30: Re: Xilinx ISE 6.2 on Debian
    88641: 05/08/24: fpga_editor and fvwm
Felix Pang:
    105563: 06/07/26: Re: EDK + Assembly Output Files + External Memory Usage
    105564: 06/07/26: Re: EDK Using External Ports to toggle FPGA pins
    105565: 06/07/26: Re: <EDK> PORT .... not found in MPD
    105937: 06/08/03: Re: MPD file option HDL
    106375: 06/08/12: Re: NgdBuild:604 error
    107476: 06/08/29: Re: FSL read/write problems
    107557: 06/08/30: Re: FSL read/write problems
Felix Stocker:
    136224: 08/11/07: Xilinx Floorplaner X,y Coordinates
Felix, Kuan-chih CHEN:
    3227: 96/04/30: S-modules and C-modules of Actel's FPGA
    3435: 96/05/30: Re: VHDL synthesis & style questions
    8506: 97/12/29: Re: how to instantiate an LCELL in VHDL source file
    10159: 98/04/30: Re: FPGA input data rate limitations?
<felix_bertram@my-deja.com>:
    22146: 00/04/27: Re: ? economical SPROM programmer for Xilinx
    22170: 00/04/28: Re: xilinx prom 2nd source.
    24028: 00/07/24: Re: Xilinx Core Generators.
    24085: 00/07/26: Re: Xilinx Core Generators.
    24119: 00/07/27: Re: Xilinx Core Generators.
    24163: 00/07/28: Re: implementation problem of Foundation 2.1i
    24961: 00/08/23: FPGA-Express 3.4: Problems with VHDL export
    26998: 00/11/07: Re: Coregen instantiation help!!
    28263: 01/01/04: Spartan-II DLL Usage
    28299: 01/01/05: Re: Spartan-II DLL Usage
    28337: 01/01/08: Re: Spartan-II DLL Usage
    28709: 01/01/22: Re: Designing fractional counters?
    28711: 01/01/22: Spartan-II CLKDLL Constraints
    28962: 01/01/31: Re: Spartan 2 DLL
FEMI:
    44309: 02/06/17: Pls Recommend a Development Board
    44310: 02/06/17: Advice on xilinx development board(kit)
    44363: 02/06/18: Pls Recommend a Xilinx development Board
    44675: 02/06/26: XESS / Digilent / Trenz Board Experience ? Help.
Feng-Chen Chang:
    1442: 95/06/23: The "InOut" Port mode in the Xilinx FPGA
    1461: 95/06/26: InOut Port in the Synopsys FPGA Compiler
FermiLab:
    48008: 02/10/09: Re: Booting a FPGA via USB
    49070: 02/10/31: Re: CLK4p in Nios board schematic
Fernandes Carlos /ECP:
    1312: 95/05/31: Re: FPGAs for PCI Interfaces
    1323: 95/06/01: VHDL->Exemplar->NeoCAD
Fernando:
    53733: 03/03/20: Re: Using FPGAs as coprocessors in a PC
    54583: 03/04/14: Re: Verilog to VHDL or vice-versa converters ??
    62805: 03/11/07: FPGAs and DRAM bandwidth
    62824: 03/11/08: Re: FPGAs and DRAM bandwidth
    62829: 03/11/09: Re: FPGAs and DRAM bandwidth
    62865: 03/11/10: Re: FPGAs and DRAM bandwidth
    62959: 03/11/11: Re: FPGAs and DRAM bandwidth
    62993: 03/11/12: Re: FPGAs and DRAM bandwidth
    67646: 04/03/16: Re: Which should I use, Floorplanner or PACE
    68531: 04/04/07: Re: XST -read_cores YES doesn't merge the NGC into the compiled file...
Fernando Pardo:
    3697: 96/07/17: Xilinx library for autologic
Fernando Peral:
    80261: 05/03/03: programming ATF750 in ABEL
    80415: 05/03/05: using atmel fit2500 fitter for a atf750
    80416: 05/03/05: Re: programming ATF750 in ABEL
    80734: 05/03/11: programing an ATF750 from VHDL
Fernley Boxall:
    15291: 99/03/17: Re: Problems with foundation
ferorcue:
    116080: 07/03/01: XPS (NGCBUILD) fails when creates netlist: "failed to copy to implementation"
    117888: 07/04/12: XPS behavioral simulation fails: the design is not loaded
    118127: 07/04/17: BFM simulation and number of Masters?
    118344: 07/04/24: Re: XPS behavioral simulation fails: the design is not loaded
    119545: 07/05/22: Problems to simulate (behavioural) in XPS
    119628: 07/05/24: Re: Problems to simulate (behavioural) in XPS
    119691: 07/05/24: Re: Problems to simulate (behavioural) in XPS
    120045: 07/05/31: Re: Problems to simulate (behavioural) in XPS
    120121: 07/06/01: Re: Problems to simulate (behavioural) in XPS
    120242: 07/06/04: Re: XPS behavioral simulation fails: the design is not loaded
    122854: 07/08/08: Write of 64 from PowerPC to my IP conected to the PLB?
    122917: 07/08/10: Re: Write of 64 from PowerPC to my IP conected to the PLB?
Feverish:
    77960: 05/01/21: Re: C programmer, what does this syntax mean?
feverlabs:
    156159: 13/12/29: Re: Interface Xilinx KC705 to BeagleBone?
feydo:
    7871: 97/10/26: Xilinx Adder Trees in Viewlogic
    8752: 98/01/23: Re: ALtera Devices.
    8753: 98/01/23: Xilinx M1.4 and Viewlogic
    8820: 98/01/28: Re: M1.4 problems
<ffa-list@chchpoly.ac.nz>:
    37945: 01/12/26: NEW: Subscribe To Newsletter
FFabio:
    15440: 99/03/24: Info about FPGA/PLD
    15466: 99/03/25: Info about VHDL syntesis
<fgherthj@yahoo.com>:
FGreen:
    73367: 04/09/20: Modelsim wave viewing in batch mode
    75198: 04/10/28: Random number generation in testbench
    74735: 04/10/17: Modelsim simulation problem
    74747: 04/10/18: Re: Modelsim simulation problem
<fhipvl@hotmail.com>:
    27455: 00/11/22: 10 Pcs. Of Paper Money From Around the World 5551
fhleung:
    69310: 04/05/05: bitgen progarm in ISE
    69316: 04/05/06: Re: bitgen progarm in ISE
    69382: 04/05/09: bitgen program in ISE generate readback bitstream
    69478: 04/05/11: reading bitstream in FPGA
fi:
    49327: 02/11/08: Xilinx LUT-based FPGAs
fibunacci:
    111569: 06/11/06: Re: Anyone who have succeeded with BPI configuration on the Spartan-3E Starter Kit
fictionalsam:
    49414: 02/11/11: Re: Compiling Altera Nios Designs
<fidonews2@my-deja.com>:
    17985: 99/09/21: FS: New Altera MAX+Plus II Magnum $1200
    18257: 99/10/10: Altera Max+Plus II for sale $1000 (new)
    18476: 99/10/26: FS: New Altera Max+Plus II $1000
    18737: 99/11/11: FS: New Altera Max+Plus II full VHDL $1K
    19093: 99/11/29: FS: New Altera MAX+Plus II 9.01 $1000
fifi:
    153122: 11/12/07: store data file in DDR2-SDRAM
FIFO_Luvr:
    41251: 02/03/22: FIFOs are just like magic
<FightingQuaker1@gmail.com>:
    118154: 07/04/18: Re: Embedding Altera SignalTap II on 1st synthesis/implementation pass
    118216: 07/04/19: Re: Embedding Altera SignalTap II on 1st synthesis/implementation pass
<figluufg@which.net>:
    18847: 99/11/18: ROLLER GARAGE DOORS
fili:
    151040: 11/03/01: S3E1600 Digilent drivers
    151045: 11/03/02: Re: S3E1600 Digilent drivers
Filip Atanassov:
    28748: 01/01/23: Atmel ATSTK40 starter kit
Filip Gielen:
    30543: 01/04/13: Re: Modlesim5.5
Filip Miletic:
    126233: 07/11/17: Re: VHDL language is out of date! Why? I will explain.
Filip S. Balan:
    18926: 99/11/22: Trouble with ATMEL's AT40K20
    18982: 99/11/23: Re: Trouble with ATMEL's AT40K20
    19011: 99/11/24: Re: Trouble with ATMEL's AT40K20
    19023: 99/11/24: Re: Trouble with ATMEL's AT40K20
    19040: 99/11/25: Re: Trouble with ATMEL's AT40K20
filippo:
    65773: 04/02/06: need desperate help!
    65822: 04/02/07: Re: need desperate help!
    65823: 04/02/07: Re: need desperate help!
    65824: 04/02/07: Re: need desperate help!
    65843: 04/02/07: Re: need desperate help!
    65938: 04/02/10: Re: need desperate help!
filox:
    103713: 06/06/09: Re: Good free or paid merge software that edits two similar files?
<filter001@desinformation.de>:
    128062: 08/01/14: Re: FPGA's as DSP's
    128139: 08/01/16: Re: FPGA's as DSP's
    128726: 08/02/05: Re: How to optimize my design area to fit?
    136271: 08/11/08: Re: Synplicity/Synplify and Systemverilog support?
    139361: 09/03/27: Re: FIFO controlled loop, PLL, FLL or something else?
    139496: 09/04/01: Re: DCM vs PLL
    139502: 09/04/01: Re: DCM vs PLL
    139617: 09/04/07: Re: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
    139821: 09/04/15: Re: What is the minimum acceptable slack on a signal
finish:
    31698: 01/06/03: one state machine
    31715: 01/06/04: Re: one state machine
    31754: 01/06/05: Re: one state machine
    32208: 01/06/19: Re: Flexlm license and windows 2000
    32209: 01/06/19: Pin-Put limit
    32247: 01/06/21: FFT limited size input
    32309: 01/06/22: Re: FFT limited size input
    32498: 01/06/28: Xc4k parallel-parallel multiplier
    32499: 01/06/28: Xc4K still alive?
    32746: 01/07/06: retiming possible with Schematic Entry
    36071: 01/10/27: FIR >14 taps
    36081: 01/10/28: automation caused exception
Finn M. Johansen:
    1299: 95/05/30: PCI ALTERA design
    1311: 95/05/31: Feb. article in ISD
Finn Nielsen:
    136489: 08/11/19: Re: IEEE 1394 interface for FPGA??
Finn S. Nielsen:
    70761: 04/06/26: Re: Family Photo Album
    86414: 05/06/27: Re: multiprocessing with microblaze ?
    89369: 05/09/13: Spartan-3 1000 -5 availability
    92942: 05/12/09: Re: XC4VFX12 -- availability?
    97476: 06/02/23: Truth about Spartan-3E DCM speed
    97626: 06/02/25: Re: Truth about Spartan-3E DCM speed
    112766: 06/11/29: Re: Mico32, how good is it?
    112768: 06/11/29: Re: Xilinx DDR2 IP core performance
    136509: 08/11/19: Re: USB JTAG
    136941: 08/12/15: Re: Looking for FPGA engineer for HD camera project
    138376: 09/02/18: Re: Recommended Xilinx USB JTAG cable?
    138466: 09/02/24: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be
    138560: 09/02/27: Re: FPGA Stamp
    140444: 09/05/13: Re: [newbie asking] I don't like Xilinx
    143206: 09/09/25: Re: HWICAP in virtex-5
    152713: 11/10/05: Spartan-6 PCI speed
    152714: 11/10/05: Xilinx EDK: XPS netlist combination error
    152750: 11/10/19: Re: Xilinx EDK: XPS netlist combination error
    153168: 11/12/23: Xilinx virtex-5 pitfalls
fire:
    77640: 05/01/12: Constraints to partial modules,modular design
    77951: 05/01/20: Constraints to partial modules,modular design
<fire4knight@mwlntyjq.fun>:
    12465: 98/10/13: LONELY?
fireball:
    49293: 02/11/08: LU-decomposition
    49351: 02/11/10: Re: LU-decomposition
    49371: 02/11/11: Re: LU-decomposition
    49534: 02/11/14: Re: LU-decomposition
firebird:
    111869: 06/11/12: SPI module in FPGA
    111897: 06/11/12: Re: SPI module in FPGA
firefly:
    154186: 12/08/31: Problem using virtex 4 and virtex 6 ibis models
<fireflyblue@gmail.com>:
    81055: 05/03/16: dma from pci device
firefox3107:
    148236: 10/06/30: Xilinx xapp175, empty + full flag really synchronous?
    148237: 10/06/30: Re: Xilinx xapp175, empty + full flag really synchronous?
    148239: 10/06/30: Re: Xilinx xapp175, empty + full flag really synchronous?
    148254: 10/07/02: Re: Xilinx xapp175, empty + full flag really synchronous?
    148477: 10/07/26: Re: Embedded Multipliers in Altera Cyclone
    148487: 10/07/27: Re: Problems with VHDL lookup table in Quartus
    148488: 10/07/27: RS-Latch
Firoz:
    149197: 10/10/07: Re: Add custom Ip to EDK - No result from sw registers
FirstLink Consulting Services:
    71760: 04/07/29: RPD File Format ?
FirstName LastName:
    860: 95/03/16: meeting others through personal ads (advertisement)
Fitz:
    10410: 98/05/17: Re: Minimal ALU instruction set.
Fizz:
    53110: 03/03/04: Re: SCSI SPI-4 interface
fizz:
    50167: 02/12/04: Where can i find a Harddisk behavior module, and a ATAPI CD-ROM behavior behavior module in Verilog?
    52961: 03/02/27: Re: Extend PCI slot to outside PC
Fizzy:
    100068: 06/04/02: Re: Discrete
    100069: 06/04/02: Xilinx Kernel
    100091: 06/04/03: Re: Discrete
    100236: 06/04/05: Data Validity and Freshness
    100246: 06/04/05: Re: Data Validity and Freshness
    100401: 06/04/07: Help needed
    100419: 06/04/08: Re: Help needed
    100490: 06/04/10: Very basic question
    100542: 06/04/11: SPI Problem
    101033: 06/04/24: PLB communication
    101142: 06/04/26: PLB
    101217: 06/04/27: CLock Issue
    101223: 06/04/27: Re: CLock Issue
    101224: 06/04/27: System Generator
    101374: 06/04/29: Reset
    101481: 06/05/01: BFM and ISE simulator
    101492: 06/05/02: Deadlock PLB
    101544: 06/05/02: EDK and SYSGEN
    101556: 06/05/02: Re: EDK and SYSGEN
    102477: 06/05/16: Shared Memory
    102480: 06/05/16: XilKernel and Budgeting
    102497: 06/05/16: SPI master
    102560: 06/05/17: DCM
    102655: 06/05/18: DCM and Clock
    102657: 06/05/18: Re: DCM and Clock
    102662: 06/05/18: Re: DCM and Clock
    102665: 06/05/18: Re: DCM and Clock
    102752: 06/05/19: PLB clocking
    103439: 06/06/01: Delay or latency
FJ.Perogil:
    134038: 08/07/22: Re: Strange behaviour with Xilkernel
fjh-mailbox-38@galois.com:
    91828: 05/11/14: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
    91830: 05/11/14: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
    91831: 05/11/14: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
    91832: 05/11/14: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
    92389: 05/11/29: Re: Memory in VHDL
    92391: 05/11/29: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
<fjz001@email.mot.com>:
    20635: 00/02/16: Re: coregen-bug produces bad blockram > 16 bit
    25302: 00/09/05: Re: Slow routing of PWR/GND (Virtex)
FK:
    42456: 02/04/24: Variable freq
fl:
    106436: 06/08/13: Problem of uninstall modelsim
    106437: 06/08/13: Re: Problem of uninstall modelsim
    106455: 06/08/13: How to attach module to the design source?
    106456: 06/08/13: Re: How to attach module to the design source?
    106836: 06/08/20: The warning of VCC and GND is normal in MAP file?
    106837: 06/08/20: Re: The warning of VCC and GND is normal in MAP file?
    107250: 06/08/25: How to change the font size in text editor of modelsim
    107372: 06/08/27: Question about library update in Modelsim
    107726: 06/08/31: How to active a disappeared HDL source file in the project of ISE webpack
    107917: 06/09/02: Qestion about the ability of synthesis
    107919: 06/09/02: Re: Qestion about the ability of synthesis
    107930: 06/09/02: Re: Qestion about the ability of synthesis
    107936: 06/09/02: Why does modelsim always look for another simulation model?
    108171: 06/09/06: How to bound a Cores generated output in Modelsim
    108185: 06/09/06: Re: How to bound a Cores generated output in Modelsim
    108194: 06/09/06: Re: How to bound a Cores generated output in Modelsim
    108195: 06/09/06: Re: How to bound a Cores generated output in Modelsim
    108218: 06/09/06: How to save preferences of modelsim
    110235: 06/10/12: How much function of FPGA Editor is open in webpack?
    110361: 06/10/14: Question about lib manual of Xilinx
    110770: 06/10/21: Where is the XORCY in the synthesised file?
    111062: 06/10/27: Question about generic usage?
    111893: 06/11/12: Question about Maxplus 2?
    111901: 06/11/12: Question about adder structure
    111983: 06/11/14: problem about license of Modelsim in Altera quartus webpack
    111984: 06/11/14: Re: problem about license of Modelsim in Altera quartus webpack
    111988: 06/11/14: Re: problem about license of Modelsim in Altera quartus webpack
    111995: 06/11/14: Why are there ModelSimAltera warning
    112347: 06/11/20: What's wrong with my tcl example in Quartus?
    112400: 06/11/21: Re: What's wrong with my tcl example in Quartus?
    112877: 06/11/30: Can I see the detail timing parameter by Quartus II tools?
    112886: 06/11/30: Re: Can I see the detail timing parameter by Quartus II tools?
    112906: 06/11/30: Re: Can I see the detail timing parameter by Quartus II tools?
    112923: 06/12/01: Re: Can I see the detail timing parameter by Quartus II tools?
    123504: 07/08/29: Question about xflow?
    123715: 07/09/02: Cannot pass par in tcl, Xilinx webpack 9.1.
    123869: 07/09/06: Question about timing of Xilinx Core generated counter
    126467: 07/11/23: How to simulate these example CORDIC code?
    126469: 07/11/23: Re: How to simulate these example CORDIC code?
    126470: 07/11/23: Re: How to simulate these example CORDIC code?
    126471: 07/11/23: Re: How to simulate these example CORDIC code?
    126507: 07/11/25: Re: How to simulate these example CORDIC code?
    126556: 07/11/27: What's the difference for VHDL code between simulation and synthesis?
    126773: 07/12/01: What option can change the path sign "\" in Quartus ?
    126775: 07/12/01: Re: What option can change the path sign "\" in Quartus ?
    127262: 07/12/16: What timing constraint value should be set for input/output module?
    127381: 07/12/19: What is "4-state binary radix" in Modelsim
    128296: 08/01/20: How FPGA downconvert Giga SPS ADC data?
    128297: 08/01/20: Re: How FPGA downconvert Giga SPS ADC data?
    128303: 08/01/20: Re: How FPGA downconvert Giga SPS ADC data?
    130339: 08/03/20: Is there a means to conditional synthesis in VHDL?
    130793: 08/04/01: Why does ISE 9.2 optimize out the logic
    131584: 08/04/25: How to arrange these SRL16 in a straight column
    132387: 08/05/24: Why this RLOC cannot be used two times?
    133041: 08/06/15: How to define the Dout width of DA FIR logic Core
    133118: 08/06/18: Question about coefficient padding
    134238: 08/07/31: Where is the package defined?
    136139: 08/11/03: Why does Nios cannot pass make?
    136141: 08/11/03: Re: Why does Nios cannot pass make?
    136146: 08/11/03: Re: Why does Nios cannot pass make?
    136159: 08/11/04: Re: Why does Nios cannot pass make?
    136374: 08/11/13: Why memory for this Nios II is still not enough
    136378: 08/11/13: Re: Why memory for this Nios II is still not enough
    136381: 08/11/13: Re: Why memory for this Nios II is still not enough
    136402: 08/11/14: How to generate downloadable Nios II cpu ?
    136403: 08/11/14: Re: How to generate downloadable Nios II cpu ?
    136499: 08/11/19: Is Atlantic Interface replaced by Avalon Streaming Interface?
    137491: 09/01/20: Where can I find the matlab file:gmsk_mod.mdl on Xilinx website
    137492: 09/01/20: Where can I find the matlab file:gmsk_mod.mdl on Xilinx website
    137580: 09/01/22: Problems when I download and install Xilinx ISE 10.1. Help please.
    139704: 09/04/09: How to understand the Nearest Even mode of Xilinx in quantization
    139708: 09/04/09: Re: How to understand the Nearest Even mode of Xilinx in quantization
    140968: 09/06/01: Xilinx DDS cannot pass simulation in Simulink
    140969: 09/06/01: Why Xilinx DDS cannot pass simulation in Simulink?
    140972: 09/06/01: Re: Why Xilinx DDS cannot pass simulation in Simulink?
    140973: 09/06/01: Re: Why Xilinx DDS cannot pass simulation in Simulink?
    141188: 09/06/10: What the switch of FFT implementation in FPGA for
    141340: 09/06/19: How to set environment to ModelsimXE
    141795: 09/07/09: How to implementa an FSM in block ram
    141812: 09/07/10: Re: How to implementa an FSM in block ram
    142658: 09/08/24: Why there is multi-source error in these VHDL code?
    143003: 09/09/14: Does Modelsim support Xilinx .mif file for Coregen generated
    147312: 10/04/22: How to over clock for DSP48
    147313: 10/04/22: Re: How to over clock for DSP48
    148136: 10/06/22: Question about Altera NIOS II, Eclipse, Quartus subscription try
    152665: 11/09/25: Modelsim cannot run its example tcl
    153578: 12/03/31: Could you explain these speed spec to me?
    154476: 12/11/10: What the advantages and disadvantages between distributed arithmetic
    154486: 12/11/16: Question about TCL command of modelsim
    154488: 12/11/17: question about verilog ?, :
    156805: 14/07/03: What use of Python, Perl in FPGA development?
    156816: 14/07/04: Re: What use of Python, Perl in FPGA development?
    156818: 14/07/04: Re: What use of Python, Perl in FPGA development?
    156819: 14/07/04: Re: What use of Python, Perl in FPGA development?
    156825: 14/07/05: Re: What use of Python, Perl in FPGA development?
    156827: 14/07/05: Re: What use of Python, Perl in FPGA development?
    156949: 14/08/02: Could you give me an example on synthesis techniques?
    156955: 14/08/05: How can Spartan-6 interface with 10/100 Mb/s Ethernet?
    156966: 14/08/08: What is the content of "High-speed SERDES interfacing such as PCIe,
flamarca:
    56461: 03/06/05: Modifing a Case Statement with a text file (looking for an Example)
Flash Gordon:
    118541: 07/04/29: Re: debounce state diagram FSM
    118594: 07/04/30: Re: debounce state diagram FSM
    118678: 07/05/02: Re: debounce state diagram FSM
    118679: 07/05/02: Re: debounce state diagram FSM
    118732: 07/05/02: Re: debounce state diagram FSM
    118735: 07/05/02: Re: debounce state diagram FSM - topical
    118738: 07/05/03: Re: debounce state diagram FSM
    118748: 07/05/03: Re: debounce state diagram FSM - topical
    118795: 07/05/03: Re: debounce state diagram FSM
<flatiron@libero.it>:
    135107: 08/09/16: Info request about Synplify and Foundation usage
    135175: 08/09/19: Re: Info request about Synplify and Foundation usage
Flavio Curti:
    68627: 04/04/11: Convert ispDS files to newer device
Flavio Miana de Paula:
    11154: 98/07/21: XC6200DS doubt/problem
<flavioas@my-deja.com>:
    18174: 99/10/05: Multiplierless FIR filters in FPGAs
    18201: 99/10/07: Re: Multiplierless FIR filters in FPGAs
    20543: 00/02/14: CIC Question
    20632: 00/02/16: Re: CIC Question
    27085: 00/11/10: Leonardo for Altera
    27186: 00/11/14: Re: Leonardo for Altera
Flemming JENSEN:
    10417: 98/05/18: Turbo bit in Altera 7000
Flemming@Sundance:
    140311: 09/05/08: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by
<flexlm666@my-deja.com>:
    18015: 99/09/23: Modelsim,synplify,Leonardo,MAX+plus, you name it!!
Flip Flippy:
    40454: 02/03/07: Re: Announcement: Freely available AES/Rijndael Core in Virtex FPGAs
flipoo:
    148029: 10/06/15: Simulation error
fliser3:
    18627: 99/11/04: Re: which is the maximum freqency?
flo:
    70559: 04/06/20: XC4010XL : parallel port access through data pin
    106396: 06/08/12: virtex II inner organisation
    107217: 06/08/25: Re: virtex II inner organisation
    107218: 06/08/25: Re: virtex II inner organisation
FLOOR MASTER:
    79849: 05/02/25: Digilent D2SB FPGA Boards
Flor Netsmar:
    11461: 98/08/17: Re: entry level ASIC salary question
    11981: 98/09/22: Re: fpga-asic
    12001: 98/09/23: Re: fpga-asic
flora:
    46622: 02/09/04: Virtex-2 BRAM
    51607: 03/01/17: copy of a project
Flora Cathy:
    40553: 02/03/10: 32-taps FIR !
    49600: 02/11/17: CLB logic function capabilities
<florent.peyrard@gmail.com>:
    112109: 06/11/16: use boundary scan in spartan-3
    112113: 06/11/16: Re: use boundary scan in spartan-3
    112114: 06/11/16: Re: use boundary scan in spartan-3
    112158: 06/11/17: Re: use boundary scan in spartan-3
    112581: 06/11/25: playing test SVF files for Spartan-3 Starter Board (using iMPACT ?)
    112659: 06/11/27: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
    112661: 06/11/27: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
    112663: 06/11/27: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
    112667: 06/11/27: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
    112669: 06/11/27: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
    113293: 06/12/10: How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?
Florian:
    51968: 03/01/28: Clock Feedback for DDR-SDRAM (XApp200)
    70110: 04/06/03: Partial Reconfiguration clock enable problem
    90034: 05/10/03: Re: Virtex-4 FX20 PPC405 Startup Issue
    93329: 05/12/20: Re: Problem with downloading elf file to ML403 using XMD
    97964: 06/03/02: Re: Virtex-4FX Mini Module TEMAC examples
    100776: 06/04/18: Re: RGMII mode on V4 Hard Tri-EMAC core
    100830: 06/04/18: Re: RGMII mode on V4 Hard Tri-EMAC core
    100862: 06/04/19: Re: RGMII mode on V4 Hard Tri-EMAC core
    126537: 07/11/27: Xilinx XChecker cable supported until which version?
    132410: 08/05/26: Downloading external data file to FPGA
    132414: 08/05/26: Re: Downloading external data file to FPGA
    142003: 09/07/21: Re: MPMC4.03 DDR1 question
    144490: 09/12/10: Re: Problems reading from PHY registers using plb_temac and
    147853: 10/05/27: Re: crc16 with 16 bit inputs
Florian Stock:
    125420: 07/10/25: Re: Paper about selecting fixed point bit widths?
    129983: 08/03/12: Re: Need info on systolic arrays in actual use
    137560: 09/01/22: Re: FPGA granularity
    137603: 09/01/23: Re: FPGA granularity
    140489: 09/05/14: Re: EMACS VHDL mode: how to rescan project so that makefile generates correctly?
    140834: 09/05/27: Re: Architecture of FPGA
    142603: 09/08/20: Re: Emulation of highly complex superscaler processor using FPGAs
    143364: 09/10/06: Re: fpga custom cpu VS. cuda
    151115: 11/03/08: Re: Re: ISE 12.4
Florian Student:
    69012: 04/04/25: Byteblaster Download cable schematics not available from altera site
    69064: 04/04/26: Re: Byteblaster Download cable schematics not available from altera
    69243: 04/05/02: Cheap SRAM?
    69571: 04/05/14: Quartus II Web Edition
    69631: 04/05/17: drive multiple outputs with the same value on EPM3064?
Florian-Wolfgang Stock:
    49624: 02/11/18: Jbits and DLLs
    51556: 03/01/16: Re: Virtex II pro architecture question
    52182: 03/02/04: Routing in JBits
    52386: 03/02/07: Re: blockram initialization
    52412: 03/02/08: Re: Multicontext FPGA
    54008: 03/03/31: JBits & Tristate
    66360: 04/02/18: Re: GZIP algorithm in FPGA
    66389: 04/02/18: Re: GZIP algorithm in FPGA
    66495: 04/02/20: Re: GZIP algorithm in FPGA
    66503: 04/02/20: Re: GZIP algorithm in FPGA
    66752: 04/02/26: Re: FSM in fpga's
FlorianB82:
    149791: 10/11/24: xilinx bitstream reading library & tool - legal issues?
    149847: 10/11/28: Re: xilinx bitstream reading library & tool - legal issues?
    149852: 10/11/28: Re: xilinx bitstream reading library & tool - legal issues?
Florin Franovici:
    51253: 03/01/08: Re: Newbie question
    51778: 03/01/21: ISE 5.1 help
    52263: 03/02/05: Help needed
    52267: 03/02/05: Re: Help needed
    52467: 03/02/10: Directions needed
Florindo Santoro:
    22120: 00/04/26: Buy FPGA
<floris.bala@gmail.com>:
    119646: 07/05/24: How can i command bit Inputs in an FPGA board?
Floyd Miller:
    2140: 95/10/19: PC Silos and DOS/16M
FlusH:
    8294: 97/12/05: !!! README NOW !!!
fluxgate:
    118523: 07/04/28: Interconnect architectures : Aurora and SPI-S
FlyingPenguin:
    106795: 06/08/19: Speed vs Area Optimisation
    106817: 06/08/20: Re: Speed vs Area Optimisation
flz47655:
    154351: 12/10/12: My First CPU but.. one problem
    154363: 12/10/15: Re: My First CPU but.. one problem
FMF:
    112968: 06/12/03: Re: problems with verilog SDRAM models
    112969: 06/12/03: Re: problems with verilog SDRAM models
fmostafa:
    132116: 08/05/14: problem in using ICAP
    132365: 08/05/23: HWICAP and BRAM
    132438: 08/05/27: HWICAP initialization
    133344: 08/06/25: RAM and shift register constraints
    133346: 08/06/25: Re: RAM and shift register constraints
    133347: 08/06/25: Re: RAM and shift register constraints
    133383: 08/06/26: mapping error
    133404: 08/06/27: Re: mapping error
    133454: 08/06/30: EDK question
    133526: 08/07/02: Re: EDK question
    133544: 08/07/03: C problem
    134176: 08/07/29: HWICAP in virtex-5
    134177: 08/07/29: Re: HWICAP initialization
    134248: 08/08/01: question about fifo
    134328: 08/08/06: processor clk and bus clk in edk
    134348: 08/08/07: how to change the system clk in EDK project
    134352: 08/08/07: Re: how to change the system clk in EDK project
    134862: 08/09/04: EDK frequency problem
fname lname:
    11565: 98/08/24: 8B/10B coding
<foag@iti.uni-luebeck.de>:
    94417: 06/01/11: UCF-File problem
    94421: 06/01/11: Re: UCF-File problem
    97705: 06/02/26: Coregen ISE 6.1
fogh:
    78627: 05/02/04: Re: Exportability of EDA industry from North America?
<foidsajoi@yahoo.com>:
Folkert Rienstra:
    88660: 05/08/24: Re: Drive startup mode - PIO write problems from FPGA
    88713: 05/08/26: Re: Drive startup mode - PIO write problems from FPGA
folnar:
    103597: 06/06/06: Propagation delay sensitivity to temperature, voltage, and manufacturing
Fong Chii Biao:
    38759: 02/01/24: Dynamic Reconfiguration of single Xilinx FPGA
    38767: 02/01/25: Re: Dynamic Reconfiguration of single Xilinx FPGA
    38770: 02/01/25: Re: Dynamic Reconfiguration of single Xilinx FPGA
    38783: 02/01/25: Re: Dynamic Reconfiguration of single Xilinx FPGA
    38784: 02/01/25: Re: Dynamic Reconfiguration of single Xilinx FPGA
Foolish:
    33785: 01/08/04: Re: Virtex-II prototyping board
FoolsGold:
    128455: 08/01/27: Synplicy and Xilinx - no PAR
    128481: 08/01/28: Re: Synplicy and Xilinx - no PAR
<fopisarr@hotmail.com>:
    88043: 05/08/07: if you or your friend have design experience about USB2.0 OTG and 10G Ethernet,plz contact us:
    88381: 05/08/16: Re: if you or your friend have design experience about USB2.0 OTG and 10G Ethernet,plz contact us:
forks dude:
    149352: 10/10/18: Re: ZIGBEE with FPGA
forrestoff:
    133804: 08/07/15: Re: EDK speed issue
fortiz80@gmail.com:
    86310: 05/06/24: V4 and DDR2 666
    89778: 05/09/26: Re: C-to-gates experiences
Fouad:
    59991: 03/09/03: Newbie CAN Core question - Student
    66086: 04/02/12: ISE 6.1.03i Linux...
Four D Electronics:
    5793: 97/03/15: Pentium 166 with AA type Keys
<fourbeans@gmail.com>:
    94083: 06/01/05: Do you name your FPGA?
    94158: 06/01/06: Re: Do you name your FPGA?
fouRmi:
    117227: 07/03/26: No results show up after "dow" and "con" in hypertrm
    117355: 07/03/29: Some errors i dont know in XMD
foxchip:
    137064: 08/12/21: Re: Bit width in CPU cores
foxclab01:
    152355: 11/08/11: Help needed to emulate a microcontroller.
fp:
    105359: 06/07/20: Re: Hardware book like "Code Complete"?
    105427: 06/07/22: Why 8 clock trees in Xilinx Spartan-3 device?
    105452: 06/07/23: Re: Why 8 clock trees in Xilinx Spartan-3 device?
    105467: 06/07/24: Re: Why 8 clock trees in Xilinx Spartan-3 device?
    110123: 06/10/11: Re: Quartus II 6.0: System clock has been set back
    110124: 06/10/11: Re: Quartus II 6.0: System clock has been set back
    111313: 06/11/01: De-serializer using Xilinx DCM
    111320: 06/11/01: Re: De-serializer using Xilinx DCM
    111333: 06/11/01: Re: De-serializer using Xilinx DCM
    111347: 06/11/01: Re: De-serializer using Xilinx DCM
    115085: 07/01/30: Help with Xilinx i/o constracint for ps/2 port
    118474: 07/04/27: a question about DDFS
    118499: 07/04/27: Re: a question about DDFS
    124430: 07/09/21: baord for learning softcore processor
    134303: 08/08/05: Re: Schematic Capture tutorials/books?
FP:
    131128: 08/04/11: case statements- verilog to vhdl
    131180: 08/04/14: Re: case statements- verilog to vhdl
    131187: 08/04/14: Re: case statements- verilog to vhdl
    131800: 08/05/02: quick question
    131807: 08/05/02: Re: quick question
    131808: 08/05/02: Re: quick question
    131819: 08/05/02: Re: quick question
    131821: 08/05/02: Re: quick question
    132583: 08/06/02: Help with $setuphold
    132590: 08/06/02: clock divider
    132688: 08/06/05: Spartan3 interface with DDR SDRAM
    132855: 08/06/09: SDRAM controller
    135424: 08/10/01: Xilinx device not listed
    135427: 08/10/01: Re: Xilinx device not listed
    135494: 08/10/05: Xilinx cores with license
    135495: 08/10/05: Re: Xilinx device not listed
    135676: 08/10/12: DDR FLOP?
    135677: 08/10/12: Re: DDR FLOP?
    135709: 08/10/13: Re: DDR FLOP?
    135739: 08/10/14: PRBS generator of Aurora core?
    135963: 08/10/24: quick question
    136213: 08/11/06: TCP/IP 3 way handshake
    136549: 08/11/21: Quartus error
    136674: 08/11/30: Jitter Management
    137376: 09/01/12: PCIe endpoint instantiation - beginner
    137377: 09/01/12: Single Lane Aurora Core Instantiation help - beginner
    137510: 09/01/21: Translate error
    137512: 09/01/21: Re: Translate error
    137647: 09/01/26: ERROR:MapLib:979
<fpbankroll@hotmail.com>:
    90288: 05/10/08: Opal help please
fpga:
    87740: 05/07/29: question about use SRAM on annapolis wildstarII board
    96914: 06/02/13: Question about using LMB to connect BRAM in MicroBlaze
    96918: 06/02/13: Re: Question about using LMB to connect BRAM in MicroBlaze
    97396: 06/02/21: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
    97461: 06/02/22: Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
    97520: 06/02/23: Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
    97546: 06/02/23: Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
    97547: 06/02/23: Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
    97568: 06/02/23: Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
    97569: 06/02/23: Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
    98545: 06/03/12: Question about multi write ports RAM in FPGA?
    98550: 06/03/12: Re: Question about multi write ports RAM in FPGA?
    98555: 06/03/12: Re: Question about multi write ports RAM in FPGA?
    98560: 06/03/12: Re: Question about multi write ports RAM in FPGA?
    98595: 06/03/13: Re: Question about multi write ports RAM in FPGA?
    98599: 06/03/13: Re: Question about multi write ports RAM in FPGA?
    98621: 06/03/13: Re: Question about multi write ports RAM in FPGA?
    98679: 06/03/14: Re: Question about multi write ports RAM in FPGA?
    98692: 06/03/14: Re: Question about multi write ports RAM in FPGA?
    98695: 06/03/14: Re: Question about multi write ports RAM in FPGA?
    98727: 06/03/15: Re: Question about multi write ports RAM in FPGA?
    98784: 06/03/16: Re: Question about multi write ports RAM in FPGA?
FPGA:
    50912: 02/12/23: serdes
    109071: 06/09/20: Audio interface in Spartan 3E Starter kit
    117995: 07/04/16: Xilinx LogiCore FFT 3.2
    118332: 07/04/24: How to add customer peripheral with IP core to EDK?
    118333: 07/04/24: Re: Take verilog code from Xilinx Core generator
    118369: 07/04/25: Re: Take verilog code from Xilinx Core generator
    127629: 08/01/04: simulation problems
    127631: 08/01/04: Re: simulation problems
    127638: 08/01/04: Re: simulation problems
    127645: 08/01/04: question on AND
    127648: 08/01/04: converting floating point number to integer and vice versa
    127650: 08/01/04: Re: converting floating point number to integer and vice versa
    127680: 08/01/05: Re: question on AND
    127681: 08/01/05: integer to binary conversion
    127689: 08/01/05: Re: integer to binary conversion
    127690: 08/01/05: Re: question on AND
    127697: 08/01/05: conversion problem
    127703: 08/01/05: Re: question on AND
    127735: 08/01/06: Re: conversion problem
    128043: 08/01/14: sine and cosine wave generation
    128047: 08/01/14: Re: sine and cosine wave generation
    128068: 08/01/14: ieee_ proposed library
    128070: 08/01/14: Re: Complex Multiply
    128071: 08/01/14: Re: sine and cosine wave generation
    128072: 08/01/14: Re: FPGA's as DSP's
    128101: 08/01/15: Re: ieee_ proposed library
    128383: 08/01/23: Re: ieee_ proposed library
    128385: 08/01/23: Re: ieee_ proposed library
    128396: 08/01/24: Re: ieee_ proposed library
    128397: 08/01/24: Random Number Generation in VHDL
    128449: 08/01/26: Re: Random Number Generation in VHDL
    128552: 08/01/30: question on record types
    128679: 08/02/03: Scaling data
    128744: 08/02/05: Modelsim Warning
    128751: 08/02/05: Re: Modelsim Warning
    128754: 08/02/05: simulator options
    128756: 08/02/05: Re: Modelsim Warning
    128798: 08/02/06: function/process to generate sine and cosine wave
    128799: 08/02/06: Re: function/process to generate sine and cosine wave
    128807: 08/02/06: Re: function/process to generate sine and cosine wave
    128809: 08/02/06: Re: function/process to generate sine and cosine wave
    128880: 08/02/08: Re: function/process to generate sine and cosine wave
    128906: 08/02/09: Re: function/process to generate sine and cosine wave
    129139: 08/02/15: distorted sine wave
    129152: 08/02/15: Re: distorted sine wave
    129174: 08/02/17: Re: distorted sine wave
    129459: 08/02/25: Seed Values
    129469: 08/02/25: Re: Seed Values
    129470: 08/02/25: Re: Seed Values
    129471: 08/02/25: Re: Seed Values
    129481: 08/02/25: Synthesis of functions in Quartus
    129490: 08/02/26: Re: Seed Values
    129501: 08/02/26: Re: Synthesis of functions in Quartus
    129502: 08/02/26: Re: Seed Values
    129579: 08/02/27: DSP newbie
    129580: 08/02/27: DSP newbie
    129581: 08/02/27: Re: DSP newbie
    129593: 08/02/28: Re: DSP newbie
    129597: 08/02/28: Re: DSP newbie
    129601: 08/02/28: Re: DSP newbie
    129624: 08/02/29: real to signed
    129632: 08/02/29: Re: real to signed
    129633: 08/02/29: Re: real to signed
    129712: 08/03/03: verifying UNIFORM using matlab
    129738: 08/03/04: Re: real to signed
    129739: 08/03/04: Re: verifying UNIFORM using matlab
    129741: 08/03/04: Re: verifying UNIFORM using matlab
    129753: 08/03/04: Re: verifying UNIFORM using matlab
    130038: 08/03/13: simulating Xilinx cores
    130181: 08/03/17: dual clock fifo
    130183: 08/03/17: Re: dual clock fifo
    130192: 08/03/17: Re: dual clock fifo
    130338: 08/03/20: Re: dual clock fifo
    130619: 08/03/28: quick question
    130738: 08/03/31: Re: quick question
    131061: 08/04/09: Task in verilog
    148651: 10/08/12: Re: DMA operation to 64-bits PC platform
    148652: 10/08/12: XC5VTX240T-2FF1759I4177
FPGA ACE, LLC:
    152594: 11/09/16: Re: LFSR in xilinx 13.2
fpga admirer:
    48959: 02/10/28: Re: GlobalReset hogging routing resources
FPGA admirer:
    48805: 02/10/24: GlobalReset hogging routing resources
FPGA Design / Logicblock:
    49684: 02/11/19: Altera Byteblaster
    49735: 02/11/20: Altera Byteblaster-compatible FPGA programmer
FPGA EXpert:
    52659: 03/02/18: Re: Synopsys FC2 version 3.7.2 best so far
FPGA geek:
    73137: 04/09/14: Xilinx RocketPHY Development Kit (HWK-RPHY-DVLP)
FPGA Guy:
    120708: 07/06/14: problems with FSL and Microblaze
    120819: 07/06/18: Re: problems with FSL and Microblaze
fpga kid:
    77443: 05/01/06: Re: VHDL Test Bench + Help
Fpga Newbie:
    155824: 13/09/20: FPGA Synthesis to LUT: Looking for papers/algorithms
FPGA Newsgroups:
    52055: 03/01/29: Re: problem with JTAG downloading
FPGA User:
FPGA user:
    55337: 03/05/04: LPM_ROM problem with Altera EP1K50 parts
    55431: 03/05/07: Re: LPM_ROM problem with Altera EP1K50 parts
FPGA Wonderkid:
    49979: 02/11/27: Re: 5.1i and Win-NT
    50012: 02/11/28: Re: Frequency multiplier with digital h/w
    50536: 02/12/12: Distributed RAM in cyclone
    50588: 02/12/13: Re: Distributed RAM in cyclone
    51109: 03/01/01: Re: Xilinx Gate Counts
<fpga-dev@web.de>:
    126538: 07/11/27: yet another Altera Cyclone II EP2C35 dev. board
    126555: 07/11/27: Re: yet another Altera Cyclone II EP2C35 dev. board
    126622: 07/11/28: Re: yet another Altera Cyclone II EP2C35 dev. board
Fpga.Dev69:
    152205: 11/07/20: Speed attained by virtex 6
<FPGA.unknown@gmail.com>:
    127612: 08/01/03: Re: round,fix and floor algortihms
<fpga.vhdl.designer@gmail.com>:
    120508: 07/06/08: Pin Capacitance Quartus 6.0
FPGA/IC:
    39692: 02/02/16: Re: FPGA choices and questions
    39693: 02/02/16: Re: FPGA choices and questions
<fpga00@gmail.com>:
    82764: 05/04/17: Microblaze Functions (Xilinx Specific)
    84237: 05/05/15: Microblaze interrupt problem
    84332: 05/05/17: Help needed!!interrupt handling in microblaze system
    84998: 05/06/02: UARTlite problem..!!!
    85371: 05/06/08: Memory management : microblaze system
FPGA05@gmail.com:
    80982: 05/03/15: Tri-Stae Bus
<FPGA23@gmail.com>:
    127576: 08/01/03: round,fix and floor algortihms
    127594: 08/01/03: Re: round,fix and floor algortihms
    127599: 08/01/03: Re: round,fix and floor algortihms
    127601: 08/01/03: Re: round,fix and floor algortihms
<fpga@iee.org>:
    29651: 01/03/03: Help : Testing a Ethernet Repeater
Fpga_Beginner:
    154933: 13/02/20: Spartan 3E Output Verification
FPGA_com:
    73226: 04/09/16: Re: Xilinx DCMs
    74462: 04/10/12: Re: multiplexing clocks
    77529: 05/01/10: Re: Clock Domains with PLL
Fpga_Designer:
    88278: 05/08/14: Modular design flow
    88344: 05/08/15: Re: Modular design flow
    88755: 05/08/27: Re: Issues with Synplify Pro 7.7 synthesis
    88756: 05/08/27: Re: Problem with ModelSim XE
    88759: 05/08/27: Re: Problem with ModelSim XE
    88763: 05/08/27: Re: Problem with ModelSim XE
fpga_engineer:
    122871: 07/08/09: Xilinx Webpack 9.1: How do I export a netlist to another project?
fpga_me:
    152462: 11/08/26: ISE and detecting flowthrus
    152464: 11/08/26: Re: ISE and detecting flowthrus
    152576: 11/09/15: Re: FPGA acceleration v.s. GPU acceleration
    152577: 11/09/15: Re: reduce EDK synthesis time
<fpga_toys@yahoo.com>:
    94921: 06/01/19: Re: FPGA Journal Article
    94923: 06/01/19: Re: FPGA Journal Article
    94924: 06/01/19: Re: FPGA Journal Article
    94936: 06/01/19: Re: FPGA Journal Article
    94925: 06/01/19: Re: FPGA Journal Article
    94933: 06/01/19: Re: FPGA Journal Article
    94934: 06/01/19: Re: FPGA Journal Article
    94926: 06/01/19: Re: FPGA Journal Article
    95421: 06/01/23: Re: Xilinx padding LC numbers, how do you feel about it?
    94962: 06/01/19: Re: Xilinx padding LC numbers, how do you feel about it?
    95168: 06/01/20: Re: Sorting large amounts of floats
    95564: 06/01/24: Re: need for a group FAQ?
    95548: 06/01/23: Re: working with XDL
    95551: 06/01/23: Re: working with XDL
    95165: 06/01/20: Re: Irrelevant, stupid, racist, and worse.
    95415: 06/01/23: Re: Irrelevant, stupid, racist, and worse.
    95567: 06/01/24: Re: Irrelevant, stupid, racist, and worse.
    95565: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    95592: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    95603: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    95608: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
    95663: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
    95664: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
    95694: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
    95715: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
    95742: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
    95788: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
    95719: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
    95540: 06/01/23: Re: Xilinx padding LC numbers, how do you really feel about it?
    95697: 06/01/25: Re: Newbie: xilinx vs arm
    95610: 06/01/24: Re: Xilinx package/PDS
    95790: 06/01/26: Re: How to handle the "gate count" issue?
    95713: 06/01/25: Re: porting linux on ml403
    95785: 06/01/25: Re: porting linux on ml403
    95673: 06/01/25: Re: So what happened to JHDLBits?
    95710: 06/01/25: Re: So what happened to JHDLBits?
    95781: 06/01/25: Re: So what happened to JHDLBits?
    95782: 06/01/25: Re: So what happened to JHDLBits?
    95783: 06/01/25: Re: So what happened to JHDLBits?
    95808: 06/01/26: Re: So what happened to JHDLBits?
    95816: 06/01/26: Re: So what happened to JHDLBits?
    95820: 06/01/26: Re: So what happened to JHDLBits?
    95825: 06/01/26: Re: So what happened to JHDLBits?
    95930: 06/01/27: Re: So what happened to JHDLBits?
    95991: 06/01/27: Re: So what happened to JHDLBits?
    95929: 06/01/27: Re: So what happened to JHDLBits?
    95693: 06/01/25: Re: open source fpga programmer programs
    95704: 06/01/25: Re: open source fpga programmer programs
    95722: 06/01/25: Re: open source fpga programmer programs
    95837: 06/01/26: Re: open source fpga programmer programs
    95812: 06/01/26: Re: open source fpga programmer programs
    95821: 06/01/26: Re: open source fpga programmer programs
    95828: 06/01/26: Re: open source fpga programmer programs
    96033: 06/01/28: Re: open source fpga programmer programs
    95833: 06/01/26: Re: open source fpga programmer programs
    95786: 06/01/25: Re: Xilinx padding LC numbers, how do you reeeeellly feel about it?
    95824: 06/01/26: Re: Xilinx padding LC numbers, how do you reeeeellly feel about it?
    95840: 06/01/26: Re: Xilinx padding LC numbers, how do you reeeeellly feel about it?
    95793: 06/01/26: Re: Stop. Go. Yield.
    95834: 06/01/26: So Xilinx, is XDL and related libraries an available open source interface?
    95855: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95861: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95877: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95890: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95902: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95899: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95887: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95906: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
    96047: 06/01/28: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95969: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95971: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95972: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source interface?
    96035: 06/01/28: Re: So Xilinx, is XDL and related libraries an available open source interface?
    96063: 06/01/29: Re: So Xilinx, is XDL and related libraries an available open source interface?
    96064: 06/01/29: Re: So Xilinx, is XDL and related libraries an available open source interface?
    96068: 06/01/29: Re: So Xilinx, is XDL and related libraries an available open source interface?
    96036: 06/01/28: Re: So Xilinx, is XDL and related libraries an available open source interface?
    96038: 06/01/28: Re: So Xilinx, is XDL and related libraries an available open source interface?
    96123: 06/01/30: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95849: 06/01/26: Re: Xilinx ....
    95876: 06/01/26: Re: Xilinx ....
    95885: 06/01/26: Re: Xilinx ....
    96000: 06/01/27: Re: C to FPGA Tools (Impulse C and others) and necessary trig IP
    96034: 06/01/28: Re: C to FPGA Tools (Impulse C and others) and necessary trig IP
    96065: 06/01/29: Re: C to FPGA Tools (Impulse C and others) and necessary trig IP
    95986: 06/01/27: Re: This is ended - there is no excuse for the false and sometimes malicious posts
    95989: 06/01/27: Re: This is ended - hardly ...
    96006: 06/01/27: Re: Lattice high end FPGAs to be announced soon
    96094: 06/01/30: Re: Digilent FPGA & Handel-C
    96196: 06/01/31: Re: Digilent FPGA & Handel-C
    96212: 06/01/31: Re: Digilent FPGA & Handel-C
    96224: 06/01/31: Re: Digilent FPGA & Handel-C
    96213: 06/01/31: Re: Digilent FPGA & Handel-C
    96109: 06/01/30: Re: XDL Tools wiki site
    96117: 06/01/30: Re: XDL Tools wiki site
    96130: 06/01/30: Re: XDL Tools wiki site
    96148: 06/01/30: Re: XDL Tools wiki site
    96132: 06/01/30: Re: XDL Tools wiki site
    96104: 06/01/30: Re: Xilinx Legal
    96111: 06/01/30: Re: Xilinx Legal
    96122: 06/01/30: Re: Xilinx Legal
    96128: 06/01/30: Re: Xilinx Legal
    96134: 06/01/30: Re: Xilinx Legal
    96147: 06/01/30: Re: Xilinx Legal
    96194: 06/01/31: Re: Xilinx Legal
    96187: 06/01/31: Re: Xilinx Legal
    96125: 06/01/30: Open source access to generate netlists into Altera tools? Others?
    96174: 06/01/31: Re: Open source access to generate netlists into Altera tools? Others?
    96180: 06/01/31: Re: Open source access to generate netlists into Altera tools? Others?
    96150: 06/01/30: Re: Xilinx Legal - topic beat to death
    96177: 06/01/31: Re: High-Level Languages for FPGAs
    96216: 06/01/31: Re: Wanted Help on All Digital PLL
    96218: 06/01/31: Back to max thermal and power for XC4VLX200's
    96262: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96268: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96271: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96276: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96280: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96285: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96290: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96304: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96314: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96306: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96307: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96313: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96297: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    96329: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
    94978: 06/01/19: Re: OT:Shooting Ourselves in the Foot
    94980: 06/01/19: Re: OT:Shooting Ourselves in the Foot
    95067: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95161: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95164: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95188: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    96438: 06/02/03: Re: why such fast placement?
    96440: 06/02/03: Re: BGA central ground matrix
    96441: 06/02/03: Re: why such fast placement?
    96491: 06/02/04: Re: High-density logic with simple, documented architecture ?
    96644: 06/02/08: Re: why such fast placement?
    96668: 06/02/08: Re: vhdl to edif
    96692: 06/02/08: Re: Async Processors
    96693: 06/02/08: Re: BGA central ground matrix
    96701: 06/02/08: Re: BGA central ground matrix
    96742: 06/02/09: Re: Async Processors
    96751: 06/02/09: Re: Async Processors
    96767: 06/02/09: Re: Async Processors
    96807: 06/02/10: Re: Async Processors
    96809: 06/02/10: Re: Async Processors
    96811: 06/02/10: Re: Async Processors
    96814: 06/02/10: Re: Async Processors
    96821: 06/02/10: Re: Async Processors
    96826: 06/02/10: Re: Async Processors
    96845: 06/02/11: Re: Async Processors
    96847: 06/02/11: Re: which one among the available FPGAs is best for a fresher?
    96849: 06/02/11: Re: using FPGA in control field
    96890: 06/02/12: Re: Async Processors
    96891: 06/02/12: Re: Async Processors
    96893: 06/02/13: Re: Async Processors
    96909: 06/02/13: Re: Async Processors
    96917: 06/02/13: Re: Async Processors
    97319: 06/02/20: Re: WebPACK license (and Quartus Web Edition too).
    97320: 06/02/20: Re: Is FPGA code called firmware?
    97321: 06/02/20: Re: Is FPGA code called firmware?
    97322: 06/02/20: Re: Is FPGA code called firmware?
    97329: 06/02/20: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
    97331: 06/02/20: Re: FPGA - software or hardware -2-
    97342: 06/02/21: Re: FPGA - software or hardware -2-
    97388: 06/02/21: Re: FPGA - software or hardware -2-
    97389: 06/02/21: Re: Is FPGA code called gateware?
    97394: 06/02/21: Re: Is FPGA code called gateware?
    97399: 06/02/21: Re: FPGA - software or hardware -2-
    97401: 06/02/21: Re: Is FPGA code called gateware?
    97410: 06/02/21: Re: Is FPGA code called gateware?
    97413: 06/02/21: Re: Is FPGA code called gateware?
    97419: 06/02/21: Re: Is FPGA code called gateware?
    97433: 06/02/22: Re: FPGA - software or hardware -2-
    97437: 06/02/22: Re: Is FPGA code called gateware?
    97441: 06/02/22: Re: Is FPGA code called gateware?
    97542: 06/02/23: Re: Is FPGA code called gateware?
    97612: 06/02/24: Re: Is FPGA code called gateware?
    97657: 06/02/25: Re: Combinatorial Division?
    97660: 06/02/25: Re: Combinatorial Division?
    97663: 06/02/25: Re: Combinatorial Division?
    97669: 06/02/25: Re: Combinatorial Division?
    97672: 06/02/25: Re: Combinatorial Division?
    97677: 06/02/25: Re: Combinatorial Division?
    97719: 06/02/26: Re: fpga to 5v ttl logic
    97736: 06/02/26: Re: Combinatorial Division?
    97815: 06/02/28: Re: Is FPGA code called gateware?
    97934: 06/03/01: Re: Is FPGA code called gateware?
    97939: 06/03/01: Re: Combinatorial Division?
    97994: 06/03/02: Re: Is FPGA code called gateware?
    97996: 06/03/02: Re: Is FPGA code called gateware?
    98046: 06/03/03: Re: Is FPGA code called gateware?
    98048: 06/03/03: Re: VirtexII routing data widths (further query)
    98049: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98054: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98055: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98056: 06/03/03: Re: VirtexII routing data widths (further query)
    98058: 06/03/03: Re: VirtexII routing data widths (further query)
    98066: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98068: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98070: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98074: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98090: 06/03/04: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98098: 06/03/04: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98099: 06/03/04: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98110: 06/03/05: FpgaC Beta-2 release on sourceforge.net today
    98208: 06/03/07: Re: A few questions about FPGAs
    98258: 06/03/07: Re: for all those who believe in ASICs....
    98260: 06/03/07: Re: for all those who believe in ASICs....
    98261: 06/03/07: Re: for all those who believe in ASICs....
    98268: 06/03/07: Re: for all those who believe in ASICs....
    98278: 06/03/08: Re: for all those who believe in ASICs....
    98279: 06/03/08: Re: for all those who believe in ASICs....
    98297: 06/03/08: using handles
    98305: 06/03/08: Re: for all those who believe in ASICs....
    98348: 06/03/08: Re: for all those who believe in ASICs....
    98364: 06/03/08: Re: for all those who believe in ASICs....
    98394: 06/03/09: Re: FPGA imple. of aes
    98439: 06/03/10: Re: FPGA imple. of aes
    98492: 06/03/10: Re: FPGA imple. of aes
    98497: 06/03/10: Re: for all those who believe in ASICs....
    98507: 06/03/11: Re: FPGA imple. of aes
    98508: 06/03/11: Re: FPGA imple. of aes
    98606: 06/03/13: Re: Soldering SMT/BGA
    98706: 06/03/14: Re: FPGA imple. of aes
    98710: 06/03/14: Re: FPGA imple. of aes
    98712: 06/03/14: Re: for all those who believe in ASICs....
    98717: 06/03/15: Re: FPGA imple. of aes
    98725: 06/03/15: Re: FPGA imple. of aes
    98774: 06/03/16: Re: for all those who believe in ASICs....
    98785: 06/03/16: Re: for all those who believe in ASICs....
    98803: 06/03/16: Re: for all those who believe in ASICs....
    98835: 06/03/16: Re: for all those who believe in ASICs....
    98836: 06/03/16: Re: for all those who believe in ASICs....
    98843: 06/03/17: Re: for all those who believe in ASICs....
    98848: 06/03/17: Re: for all those who believe in ASICs....
    98849: 06/03/17: Re: for all those who believe in ASICs....
    98852: 06/03/17: Re: for all those who believe in ASICs....
    98858: 06/03/17: Re: for all those who believe in ASICs....
    98880: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
    98881: 06/03/17: Re: for all those who believe in ASICs....
    98888: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
    98890: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
    98891: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
    98895: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
    98904: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
    98913: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
    98916: 06/03/17: Re: for all those who believe in ASICs....and can't stop ranting
    98919: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
    98928: 06/03/17: Re: for all those who believe in ASICs....
    98930: 06/03/17: Re: for all those who believe in ASICs....and can't stop ranting
    98931: 06/03/17: Re: for all those who believe in ASICs....and can't stop ranting
    98933: 06/03/17: Re: for all those who believe in ASICs....and can't stop ranting
    98944: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
    98945: 06/03/17: Re: for all those who believe in ASICs....and can't stop ranting
    98957: 06/03/17: Re: for all those who believe in ASICs....and can't stop ranting
    98965: 06/03/17: Re: Re:Disk/LCD defect tolerant models for FPGA sales
    98966: 06/03/17: Re: for all those who believe
    98987: 06/03/18: Historical Fpga Resources
    98988: 06/03/18: Re: Disk/LCD defect tolerant models for FPGA sales
    99033: 06/03/19: Re: for all those who have stopped listening, and are ranting now...
    99059: 06/03/19: Re: for all those who have stopped listening, and are ranting now...
    99079: 06/03/20: Re: Urgent Help Needed!!!!!
    99083: 06/03/20: Re: for all those who believe...
    99085: 06/03/20: Re: for all those who believe in ASICs....
    99087: 06/03/20: Re: Disk/LCD defect tolerant models for FPGA sales
    99089: 06/03/20: Re: Disk/LCD defect tolerant models for FPGA sales
    99090: 06/03/20: Re: for all those who believe
    99091: 06/03/20: Re: for all those who believe in ASICs....and can't stop ranting
    99093: 06/03/20: Re: Urgent Help Needed!!!!!
    99105: 06/03/20: Re: Urgent Help Needed!!!!!
    99106: 06/03/20: Re: Urgent Help Needed!!!!! Tech Speak
    99119: 06/03/20: Re: ignore thread
    99134: 06/03/20: Re: Urgent Help Needed!!!!!
    99140: 06/03/20: Re: for all those who have stopped listening, and are ranting now...
    99143: 06/03/20: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
    99163: 06/03/20: Re: Disk/LCD defect tolerant models for FPGA sales
    99164: 06/03/20: Re: Disk/LCD defect tolerant models for FPGA sales
    99172: 06/03/20: Re: Disk/LCD defect tolerant models for FPGA sales
    99173: 06/03/20: Re: Disk/LCD defect tolerant models for FPGA sales
    99198: 06/03/21: Re: Disk/LCD defect tolerant models for FPGA sales
    99199: 06/03/21: Re: for all those who believe in ASICs....
    99201: 06/03/21: Re: for all those who believe in ASICs....
    99204: 06/03/21: Re: An Open Letter to Mr. John Bass (was: Urgent Help Needed!!!!!)
    99215: 06/03/21: Re: for all those who believe in ASICs....
    99216: 06/03/21: Re: for all those who believe in ASICs....
    99224: 06/03/21: Re: for all those who believe in ASICs....
    99225: 06/03/21: Re: for all those who believe in ASICs....
    99230: 06/03/21: Re: Urgent Help Needed!!!!!
    99231: 06/03/21: Re: Disk/LCD defect tolerant models for FPGA sales
    99242: 06/03/21: Re: Smarter Power supplies arrive
    99247: 06/03/21: Re: An Open Letter to Mr. John Bass (was: Urgent Help Needed!!!!!)
    99301: 06/03/22: Re: Are Quad-processors advantageous?
    99307: 06/03/22: Re: Are Quad-processors advantageous?
    99321: 06/03/22: Re: Urgent Help Needed!!!!!
    99356: 06/03/23: Re: for all those who believe in ASICs....
    99551: 06/03/26: Re: chip reverse engineering
    99552: 06/03/26: Re: C-based FPGA programming/mixed languages
    99706: 06/03/28: Re: C-based FPGA programming/mixed languages
    99730: 06/03/28: Re: C-based FPGA programming/mixed languages
    99836: 06/03/29: FpgaC developers wanted :)
    99841: 06/03/29: Re: FpgaC developers wanted :)
    99863: 06/03/30: Re: FpgaC developers wanted :)
    99864: 06/03/30: Re: FpgaC developers wanted :)
    99888: 06/03/30: Re: FpgaC developers wanted :)
    99908: 06/03/30: Re: FpgaC developers wanted :)
    99926: 06/03/30: Re: FpgaC developers wanted :)
    100120: 06/04/03: Re: Want HiSpeed USB on your FPGA ?
    100193: 06/04/04: interesting note -- altera C to hardware :)
    100199: 06/04/04: Re: interesting note -- altera C to hardware :)
    100253: 06/04/05: Re: interesting note -- altera C to hardware :)
    101050: 06/04/24: Re: comp.arch.reconfig
    101099: 06/04/25: Re: comp.arch.reconfig
    101153: 06/04/26: Re: Async FPGA ~2GHz
    101158: 06/04/26: Re: Async FPGA ~2GHz
    101162: 06/04/26: Re: Async FPGA ~2GHz
    101163: 06/04/26: Re: Async FPGA ~2GHz
    101168: 06/04/26: Re: Async FPGA ~2GHz
    101169: 06/04/26: Re: Async FPGA ~2GHz
    101174: 06/04/26: Re: Async FPGA ~2GHz
    101242: 06/04/27: Re: Async FPGA ~2GHz
    101244: 06/04/27: Re: Async FPGA ~2GHz
    101250: 06/04/28: Re: Async FPGA ~2GHz
    101303: 06/04/28: Re: Async FPGA ~2GHz
    101696: 06/05/04: Re: Xilinx 3s8000?
    101774: 06/05/06: Re: Xilinx 3s8000?
    101775: 06/05/06: Re: Xilinx 3s8000?
    101806: 06/05/07: Re: Xilinx 3s8000?
    101835: 06/05/07: Re: Xilinx 3s8000?
    101841: 06/05/07: Re: Xilinx 3s8000?
    101844: 06/05/07: Re: Funky experiment on a Spartan II FPGA
    101860: 06/05/07: Re: Xilinx 3s8000?
    101867: 06/05/08: Re: FPGA-based hardware accelerator for PC
    101878: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
    101916: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
    102011: 06/05/09: Re: Can an FPGA be operated reliably in a car wheel?
    102068: 06/05/10: Re: FPGA-based hardware accelerator for PC
    102116: 06/05/10: Re: Xilinx 3s8000?
    102139: 06/05/10: Re: reverse engineering ?
    102187: 06/05/11: Re: reverse engineering ?
    102189: 06/05/11: Re: reverse engineering ?
    102190: 06/05/11: Re: reverse engineering ?
    102193: 06/05/11: Re: reverse engineering ?
    102197: 06/05/11: Re: reverse engineering ?
    102206: 06/05/11: Re: reverse engineering ?
    102209: 06/05/11: Re: reverse engineering ?
    102211: 06/05/11: Re: reverse engineering ?
    102216: 06/05/11: Re: reverse engineering ?
    102221: 06/05/11: Re: reverse engineering ?
    102226: 06/05/12: Re: reverse engineering ?
    102280: 06/05/13: Re: reverse engineering ?
    102302: 06/05/14: Re: reverse engineering ?
    102593: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102606: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102607: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102610: 06/05/17: Re: reverse engineering ?
    102612: 06/05/17: Re: Make a signal free for glitches?
    102617: 06/05/18: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102619: 06/05/18: Re: "disappointing" performance
    102652: 06/05/18: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102671: 06/05/18: Re: V5 and carry lookahead
    102683: 06/05/19: Re: "disappointing" performance
    102714: 06/05/19: Re: V5 and carry lookahead
    102753: 06/05/19: Re: "disappointing" performance
    102757: 06/05/19: Re: "disappointing" performance
    102763: 06/05/19: Re: V5 and carry lookahead
    102766: 06/05/19: Re: "disappointing" performance
    102771: 06/05/19: Re: "disappointing" performance
    102776: 06/05/20: Re: ispLEVER Starter 6.0 FPGA Design Software Available
    102890: 06/05/22: Re: "disappointing" performance
    102892: 06/05/22: Re: xilinx pricing discrepancy
    102921: 06/05/23: Re: xilinx pricing discrepancy
    102923: 06/05/23: Re: xilinx pricing discrepancy
    102952: 06/05/23: Re: xilinx pricing discrepancy
    102957: 06/05/23: Re: xilinx pricing discrepancy
    103165: 06/05/26: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
    103490: 06/06/04: Re: PCI Design
    103654: 06/06/07: Re: FlipChip BGA Conformal Coating
    103937: 06/06/15: Re: Time for a new "Largest FPGA with free tool support"?
    104027: 06/06/16: Re: anybody doing self-timed/asynchronous on post-jbits xilinx parts?
    104257: 06/06/22: Re: FSM State Minimization on FPGAs
    104389: 06/06/26: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
    105837: 06/08/01: Re: Sorting algorithm for FPGA availlable?
    106031: 06/08/06: Re: verilog versus vhdl
    106121: 06/08/07: Re: verilog versus vhdl
    106145: 06/08/08: Re: verilog versus vhdl
    106148: 06/08/08: Re: verilog versus vhdl
    106149: 06/08/08: Re: verilog versus vhdl
    106150: 06/08/08: Re: verilog versus vhdl
    106156: 06/08/08: Re: verilog versus vhdl
    106177: 06/08/08: Re: verilog versus vhdl
    106192: 06/08/08: Re: verilog versus vhdl
    106417: 06/08/12: Re: Maximum Current Draw of FPGA
    106418: 06/08/12: Re: Virtex 4 could not work correct,is it damaged?
    107167: 06/08/24: Re: high level languages for synthesis
    107169: 06/08/24: Re: high level languages for synthesis
    107172: 06/08/25: Re: Why No Process Shrink On Prior FPGA Devices ?
    107212: 06/08/25: Re: fastest FPGA
    107219: 06/08/25: Re: fastest FPGA
    107222: 06/08/25: Re: fastest FPGA
    107230: 06/08/25: Re: fastest FPGA
    107237: 06/08/25: Re: high level languages for synthesis
    107238: 06/08/25: Re: high level languages for synthesis
    107242: 06/08/25: Re: fastest FPGA
    107247: 06/08/25: Re: fastest FPGA
    107249: 06/08/25: Re: high level languages for synthesis
    107252: 06/08/25: Re: fastest FPGA
    107257: 06/08/25: Re: high level languages for synthesis
    107260: 06/08/25: Re: high level languages for synthesis
    107266: 06/08/25: Re: fastest FPGA
    107269: 06/08/25: Re: FPGA -> SATA?
    107271: 06/08/25: Re: fastest FPGA
    107273: 06/08/25: Re: fastest FPGA
    107277: 06/08/25: Re: fastest FPGA
    107281: 06/08/25: Re: fastest FPGA
    107284: 06/08/25: Re: FPGA -> SATA?
    107305: 06/08/26: Re: FPGA -> SATA?
    107312: 06/08/26: Re: FPGA -> SATA?
    107314: 06/08/26: Re: fastest FPGA
    107315: 06/08/26: Re: FPGA -> SATA?
    107316: 06/08/26: Re: FPGA -> SATA?
    107322: 06/08/26: Re: FPGA -> SATA?
    107324: 06/08/26: Re: fastest FPGA
    107330: 06/08/26: Re: high level languages for synthesis
    107333: 06/08/26: Re: high level languages for synthesis
    107338: 06/08/26: Re: FPGA -> SATA?
    107341: 06/08/26: Re: FPGA -> SATA?
    107342: 06/08/26: Re: FPGA -> SATA?
    107347: 06/08/26: Re: FPGA -> SATA?
    107367: 06/08/27: Re: FPGA -> SATA?
    107368: 06/08/27: Re: FPGA -> SATA?
    107369: 06/08/27: Re: FPGA -> SATA?
    107376: 06/08/27: Re: placing addiional caps across existing caps to reduce noise
    107387: 06/08/27: Re: placing addiional caps across existing caps to reduce noise
    107390: 06/08/27: Re: placing addiional caps across existing caps to reduce noise
    107391: 06/08/27: Re: placing addiional caps across existing caps to reduce noise
    107396: 06/08/28: Re: FPGA -> SATA?
    107402: 06/08/28: Re: FPGA -> SATA?
    107434: 06/08/28: Re: high level languages for synthesis
    107436: 06/08/28: Re: placing addiional caps across existing caps to reduce noise
    107439: 06/08/28: Re: high level languages for synthesis
    107470: 06/08/28: Re: FPGA -> SATA?
    107471: 06/08/28: Re: FPGA -> SATA?
    107474: 06/08/28: Re: placing addiional caps across existing caps to reduce noise
    107541: 06/08/29: Re: placing addiional caps across existing caps to reduce noise
    107546: 06/08/29: Re: FPGA -> SATA?
    107547: 06/08/29: Re: high level languages for synthesis
    107560: 06/08/29: Re: placing addiional caps across existing caps to reduce noise
    107597: 06/08/30: Re: high level languages for synthesis
    107612: 06/08/30: Re: placing addiional caps across existing caps to reduce noise
    107619: 06/08/30: Re: placing addiional caps across existing caps to reduce noise
    107632: 06/08/30: Re: Performance Appraisals
    107643: 06/08/30: Re: Performance Appraisals
    107651: 06/08/30: Re: Performance Appraisals
    107668: 06/08/30: Re: Performance Appraisals
    107677: 06/08/30: Re: Bypass Caps : XAPP623 vs Spartan-3 Starter Kit Board
    107697: 06/08/31: Re: Performance Appraisals
    107702: 06/08/31: Re: Performance Appraisals
    107703: 06/08/31: Re: Performance Appraisals
    107704: 06/08/31: Re: Bypass Caps : XAPP623 vs Spartan-3 Starter Kit Board
    107707: 06/08/31: Re: Performance Appraisals
    107724: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
    107728: 06/08/31: Re: Open-source CableServer for Impact (no more need for Jungo driver on Linux)
    107737: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
    107755: 06/08/31: Re: Performance Appraisals
    107806: 06/09/01: Re: placing addiional caps across existing caps to reduce noise
    107810: 06/09/01: Re: Performance Appraisals
    107814: 06/09/01: Re: Performance Appraisals
    107834: 06/09/01: Re: Performance Appraisals
    107836: 06/09/01: Re: Performance Appraisals
    107841: 06/09/01: Re: Performance Appraisals
    107843: 06/09/01: Re: Performance Appraisals
    107849: 06/09/01: Re: Performance Appraisals
    107852: 06/09/01: Re: Performance Appraisals
    107859: 06/09/01: Re: Performance Appraisals
    107860: 06/09/01: Re: Performance Appraisals
    107872: 06/09/01: Re: Performance Appraisals
    107975: 06/09/03: Re: wiring resource utilization?
    109342: 06/09/24: Re: MicroFpga = program an FPGA as it would be a MCU !
    109890: 06/10/06: Re: a clueless bloke tells Xilinx to get a move on
    110070: 06/10/10: Re: a clueless bloke tells Xilinx to get a move on
    110109: 06/10/11: Re: a clueless bloke tells Xilinx to get a move on
    110122: 06/10/11: Re: a clueless bloke tells Xilinx to get a move on
    110183: 06/10/11: Re: a clueless bloke tells Xilinx to get a move on
    110188: 06/10/12: Re: Functional Languages in Hardware
    110241: 06/10/12: Re: SPAM -- FPGA image processing camera
    110642: 06/10/19: Re: Cheapest FPGA board to study VHDL on
    110701: 06/10/19: Re: Cheapest FPGA board to study VHDL on
    110747: 06/10/20: Re: How many clocks are needed for a fastest ADD instruction of latest Intel CPU
    110751: 06/10/21: Re: i486 FPGA replacement
    111637: 06/11/07: Re: Scientific Computing on FPGA
    111639: 06/11/07: Re: Scientific Computing on FPGA
    112507: 06/11/23: Re: Protecting netlist for Xilinx
    113228: 06/12/08: Xilinx platform flash data sheet confusion (ds123) for clocking
    113239: 06/12/08: Re: Xilinx platform flash data sheet confusion (ds123) for clocking
    117947: 07/04/13: Re: No login in uClinux (Petalinux)
    117948: 07/04/13: Re: Where is Open Source for FPGA development?
    117950: 07/04/14: Re: Where is Open Source for FPGA development?
    117959: 07/04/14: Re: picoblaze C compiler download wanted
    118043: 07/04/16: Re: picoblaze C compiler download wanted
    118501: 07/04/27: Re: one extra slipway board from fccm
    118671: 07/05/01: Re: Xilinx software quality - how low can it go ?!
    118886: 07/05/05: Re: Xilinx software quality - how low can it go ?!
    118888: 07/05/06: Re: picoblaze C compiler download wanted
    119013: 07/05/09: Re: Xilinx software quality - how low can it go ?!
    119024: 07/05/09: Re: Open Source (was: Xilinx software quality - how low can it go ?!)
    119030: 07/05/09: Re: An Open-Source suggestion for Xilinx
    119109: 07/05/11: Re: how to choose the perfect fpga support
    119114: 07/05/11: Re: how to choose the perfect fpga support
    119115: 07/05/11: Re: how to choose the perfect fpga support
    119117: 07/05/11: Re: how to choose the perfect fpga support
    119118: 07/05/11: Re: how to choose the perfect fpga support
    119129: 07/05/12: Re: how to choose the perfect fpga support
    119131: 07/05/12: Re: how to choose the perfect fpga support
    119132: 07/05/12: Re: how to choose the perfect fpga support
    119175: 07/05/14: Re: An Open-Source suggestion for Xilinx
    119178: 07/05/14: Re: An Open-Source suggestion for Xilinx
    119182: 07/05/14: Re: An Open-Source suggestion for Xilinx
    119192: 07/05/14: Re: How to Ask a Question
    119202: 07/05/15: Re: An Open-Source suggestion for Xilinx
    119203: 07/05/15: Re: An Open-Source suggestion for Xilinx
    119252: 07/05/15: Re: how to choose the perfect fpga support
    119266: 07/05/15: Re: Power Consumption near Timing Failure Point
    119380: 07/05/17: Re: Power Consumption near Timing Failure Point
    119395: 07/05/17: Re: Power Consumption near Timing Failure Point
    119397: 07/05/17: Re: Power Consumption near Timing Failure Point
    119398: 07/05/17: Re: Power Consumption near Timing Failure Point
    119405: 07/05/17: Re: Power Consumption near Timing Failure Point
    119435: 07/05/18: Re: Power Consumption near Timing Failure Point
    121699: 07/07/11: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    122503: 07/07/29: Re: completely open source fpga toolchain
    122504: 07/07/29: Re: completely open source fpga toolchain
    122700: 07/08/03: Re: Altera or Xilinx
    122712: 07/08/04: Re: How to choose FPGA for a huge computation?
    123770: 07/09/04: Re: FPGA CPU
    123778: 07/09/04: Re: FPGA CPU
    123792: 07/09/04: Re: FPGA CPU
    123794: 07/09/04: Re: FPGA CPU
    123797: 07/09/04: Re: FPGA CPU
fpgaace:
    151417: 11/04/05: Re: Ideal FPGA Development Kit
    152207: 11/07/20: source synchronous DDR bus with non-continuous clock
    152209: 11/07/21: Re: source synchronous DDR bus with non-continuous clock
    152219: 11/07/22: Re: source synchronous DDR bus with non-continuous clock
fpgaarcade:
    94665: 06/01/16: Re: FPGA Journal Article
    94663: 06/01/16: Re: FPGA Altair Advice
<fpgaasicdesigner@gmail.com>:
    128527: 08/01/29: BPSK CORDIC tracking
    133062: 08/06/16: Rocket IO alignment, clocks
    139748: 09/04/11: Decimation clock
    139751: 09/04/11: Re: Decimation clock
fpgabuilder:
    78899: 05/02/09: second flop in asyn reset distribution
    79031: 05/02/11: Re: second flop in asyn reset distribution
    79052: 05/02/11: Re: second flop in asyn reset distribution
    79071: 05/02/13: Re: second flop in asyn reset distribution
    79110: 05/02/14: Re: second flop in asyn reset distribution
    84092: 05/05/12: initializing fifo pointers to simulate overflow
    84192: 05/05/13: Re: initializing fifo pointers to simulate overflow
    85592: 05/06/11: Re: initializing fifo pointers to simulate overflow
    90779: 05/10/20: low power design and unused i/os
    90815: 05/10/21: Re: low power design and unused i/os
    90879: 05/10/24: Re: low power design and unused i/os
    90931: 05/10/25: Re: a few questions
    90932: 05/10/25: Re: verilog code
    90934: 05/10/25: Re: a few questions
    90953: 05/10/25: Re: a few questions
    93160: 05/12/14: consensus theorem and power
    93420: 05/12/21: Re: consensus theorem and power
    97799: 06/02/27: Why wouldn't this infer a flop with async reset and sync enable
    97800: 06/02/27: Re: Why wouldn't this infer a flop with async reset and sync enable
    97806: 06/02/27: Re: Why wouldn't this infer a flop with async reset and sync enable
    100970: 06/04/21: altera async fifo with different read/write port widths?
    102967: 06/05/24: Re: PCI 64/66 fpga eval boards
    103052: 06/05/25: Re: PCI 64/66 fpga eval boards
    103055: 06/05/25: Re: PCI 64/66 fpga eval boards
    103095: 06/05/25: Re: PCI 64/66 fpga eval boards
    103111: 06/05/25: Re: PCI 64/66 fpga eval boards
    112929: 06/12/01: Re: Can I see the detail timing parameter by Quartus II tools?
    112974: 06/12/03: Re: Video Mux using FPGA
    115482: 07/02/12: Re: substracting a whole array of values at once
    115545: 07/02/13: Re: substracting a whole array of values at once
    116907: 07/03/20: 1.8V config proms for Cyclone 2s
    117163: 07/03/25: Re: Austin the Altera Mole
    117198: 07/03/26: Re: Austin the Altera Mole
    117200: 07/03/26: Re: Austin the Altera Mole
    117714: 07/04/08: Re: A new way to define systems of systems?
    117781: 07/04/10: Re: A new way to define systems of systems?
    117867: 07/04/11: Re: A new way to define systems of systems?
    117868: 07/04/11: Re: A new way to define systems of systems?
    119379: 07/05/17: Re: DDR 2 Memory controller own implementattion
    119382: 07/05/17: Mobile DDR vs DDR2
    120063: 07/05/31: Cyclone 3 Starter Board Question
    120091: 07/06/01: Re: Cyclone 3 Starter Board Question
    120122: 07/06/01: Re: Cyclone 3 Starter Board Question
    120189: 07/06/02: Re: Cyclone 3 Starter Board Question
    120550: 07/06/09: Re: FPGA with ARM+CAN+USB+ethernet+ADC
    120788: 07/06/16: Re: what is the correct way to capture ADC using fpga
    120789: 07/06/16: Re: Using LogicLock in Altera Quartus II
    120802: 07/06/17: Re: what is the correct way to capture ADC using fpga
    120876: 07/06/19: Re: what is the correct way to capture ADC using fpga
    122042: 07/07/18: DDR SDRAM in extended military applications
    122872: 07/08/09: secure interfacing between an fpga and a connected device
    122886: 07/08/09: Re: secure interfacing between an fpga and a connected device
    123192: 07/08/19: Re: DDR controller - best device to perform
    123307: 07/08/23: Re: Need to force all signals in a design to a known value at start of simulation
    123326: 07/08/23: Altera DDR Controller, Modelsim and Verilog
    123416: 07/08/27: PLL Power and m/n ratio
    123521: 07/08/29: Re: PLL Power and m/n ratio
    123583: 07/08/30: Re: modelsim
    123586: 07/08/30: Re: Registered output for Altera on-chip memory
    123614: 07/08/31: Re: modelsim
    123668: 07/09/01: Re: An FPGA startup is seeking testcase from potential customers
    123670: 07/09/01: Re: PLL Power and m/n ratio
    124554: 07/09/26: Altera PowerPlay Early Power Estimator Spreadsheet and MXCOMCT2.OCX
    124555: 07/09/26: Re: Very basic clock questions.
    124558: 07/09/26: Re: Never buy Altera!!!!
    124941: 07/10/11: Re: HELP, how to time constraint part of a design?
    124958: 07/10/12: Re: HELP, how to time constraint part of a design?
    125483: 07/10/26: Re: is Quartus 7.1 really that S*** !?
    125486: 07/10/26: FPGA vs ASIC
    125487: 07/10/26: Re: is Quartus 7.1 really that S*** !?
    125498: 07/10/26: Re: FPGA vs ASIC
    142566: 09/08/17: Operating same logic at two frequencies
    142570: 09/08/17: Re: Operating same logic at two frequencies
    142575: 09/08/17: Re: Operating same logic at two frequencies
    145081: 10/01/25: Re: SystemVerilog Verification Example using Quartus and ModelSim
    145959: 10/03/01: LVDS i/o in a SystemVerilog Interface block
    145980: 10/03/02: Re: LVDS i/o in a SystemVerilog Interface block
    146202: 10/03/08: Re: Using the SignalTap Logic Analyzer
    146426: 10/03/17: Re: Why doesn't this situation generate a latch?
    146474: 10/03/19: Re: Why doesn't this situation generate a latch?
    147060: 10/04/12: Re: I'd rather switch than fight!
<fpgabuilder-groups@yahoo.com>:
    102930: 06/05/23: PCI 64/66 fpga eval boards
<FPGADebug@gmail.com>:
    121541: 07/07/07: Re: Xilinx V4/V5 FPGA SATA GTP
fpgaengineer:
    116537: 07/03/12: Re: Multiple devices within one ISE project
FPGAEngineer@gmail.com:
    116987: 07/03/21: Looking for resources on timing analysis
    117013: 07/03/21: Re: Looking for resources on timing analysis
<fpgaer@my-deja.com>:
    20417: 00/02/09: launching a FPGA cores start-up
    20426: 00/02/10: Re: launching a FPGA cores start-up
    20539: 00/02/14: Re: launching a FPGA cores start-up
    20576: 00/02/15: Re: launching a FPGA cores start-up
    20620: 00/02/16: Re: launching a FPGA cores start-up
<fpgagrp@gmail.com>:
    90023: 05/10/02: Weird problem in Xilinx WebPack ISE PACE 7.1SP4
fpgaguy:
    104465: 06/06/27: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
    127383: 07/12/19: help with rising edge matching
    127403: 07/12/20: Re: help with rising edge matching
<fpgaguy@aedinc.net>:
    84808: 05/05/27: Re: Async FIFO coregen wizard
    86316: 05/06/24: Re: ISE 7.1 Service Pack 2 - Ready yet?
fpgahobbyist:
    147780: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
    147788: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
fpgaiua:
    152674: 11/09/26: PCI core with expansion ROM support
fpgakid@gmail.com:
    92883: 05/12/08: Replace fast ethernet with VDSL2
    106115: 06/08/07: Open source Xilinx JTAG programmer with Digilent USB support
    106959: 06/08/22: Open source Xilinx JTAG Programmer released on sourceforge.net
fpgalover:
    150875: 11/02/18: Power nets in Xilinx FPGAs
fpgaman:
    114123: 07/01/04: Re: LatticeMico32 Problem
<fpgamax@my-deja.com>:
    27477: 00/11/23: Re: Virtex-PCI-Boards
FPGANewbie:
    72249: 04/08/12: 95108 doesnt program
fpganovice:
    106700: 06/08/17: EDK vs. ISE for image processing
    106707: 06/08/17: Re: EDK vs. ISE for image processing
    106764: 06/08/18: Re: EDK vs. ISE for image processing
    106765: 06/08/18: Re: EDK vs. ISE for image processing
    106778: 06/08/18: Re: EDK vs. ISE for image processing
fpganut:
    131854: 08/05/04: need recommendation for PCB fab & BGA assembly vendor, I'm in SF bay area
    131974: 08/05/08: Anyway to secure a Xilinx NGC file ?
    132020: 08/05/09: Re: Anyway to secure a Xilinx NGC file ?
<fpgar@my-dejanews.com>:
    15199: 99/03/12: Spartan, delaying a clock.
    15203: 99/03/12: Re: Spartan, delaying a clock.
fpgasm:
    154318: 12/09/27: Re: edge matching
fpgauser:
    113853: 06/12/25: moving from xlinx 8.1 to 8.2 or better wait ?
    114186: 07/01/06: email protection in the list
    114274: 07/01/10: VHDL Model of a stepper motor
    114275: 07/01/10: Re: email protection in the list
    114484: 07/01/17: Re: VHDL Model of a stepper motor
    122679: 07/08/02: Spartan 3E starter kit DDR SDRAM
    122716: 07/08/04: Re: Spartan 3E starter kit DDR SDRAM
    122724: 07/08/04: Re: Spartan 3E starter kit DDR SDRAM
    122729: 07/08/05: Re: Download the contents of the FPGA's RAM block
    122730: 07/08/05: bare bone PCI cards with FPGAs
    125839: 07/11/06: Re: Why dynamic partial reconfiguration is still not there?
    125840: 07/11/06: Re: Fast Sampling of digital signals
    128406: 08/01/24: Virtex-4 driving a 5V CMOS
    139523: 09/04/02: Can I capture the jtag TDO pin of a Spartan3AN
fpgavhdl@gmail.com:
    80254: 05/03/02: Genlock
    80293: 05/03/03: Re: Genlock
    80388: 05/03/04: Re: Genlock
    80519: 05/03/07: Re: Genlock
    80923: 05/03/14: Re: Genlock
    82019: 05/04/05: FPGA with 2 JTAG ports
    82074: 05/04/06: Re: FPGA with 2 JTAG ports
    82082: 05/04/06: Re: FPGA with 2 JTAG ports
fpgawizz:
    79084: 05/02/13: Using the 7 segment displays on Xilinx Spartan 3 kit
    79087: 05/02/14: Xilinx Spartan 3 kit - displaying unique numbers
    79106: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
    79172: 05/02/15: Xilinx Spartan 3 kit - VHDL design question
    79192: 05/02/15: Re: Xilinx Spartan 3 kit - VHDL design question
    79484: 05/02/19: Re: Xilinx Spartan 3 kit - VHDL design question
    79487: 05/02/19: VHDL State Machine - Literature
    79559: 05/02/21: Sending information between VHDL modules from the top level module
    79942: 05/02/26: programming 2 pulses using VHDL
    80262: 05/03/03: bad synchronous description error
    80426: 05/03/05: spartan 3 design projects
    80427: 05/03/05: SRAM on spartan3 board
    81255: 05/03/20: RS 232 receiver using spartan 3 board
    81268: 05/03/20: Re: RS 232 receiver using spartan 3 board
    81569: 05/03/27: Block RAM in Xilinx Spartan 3
<fpgazone@gmail.com>:
    125259: 07/10/18: mess around with supply voltage to cyclone III
Frai:
    111145: 06/10/30: PC configuration for best Xilinx ISE performance
    114353: 07/01/12: Too many warnings in Modelsim?
    114355: 07/01/12: Re: Too many warnings in Modelsim?
    114411: 07/01/15: How to ensure Select signal arrives after Input signals changed
    114413: 07/01/15: Re: How to ensure Select signal arrives after Input signals changed
    114862: 07/01/25: Simulation of DCM with Xilinx 8.2 and Modelsim 6.1
    116677: 07/03/15: Re: Xilinx FPGA, OFFSET OUT AFTER
    116678: 07/03/15: Re: Does anybody work with Sundance Module (smt338vp30-> Virtex II Pro 30)
    116680: 07/03/15: Xilinx Xplorer misfunction
    119520: 07/05/21: Xilinx doesn't detect setup/hold violations on synchronous reset
    119522: 07/05/21: Re: Xilinx doesn't detect setup/hold violations on synchronous reset
    119544: 07/05/22: Re: Xilinx doesn't detect setup/hold violations on synchronous reset
    123623: 07/08/31: Xilinx blockram FIFO async reset annoys me (and Modelsim)
    129750: 08/03/04: AES Bitstream Encryption in Virtex-4. How safe it is?
    129769: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
Francesco:
    94529: 06/01/13: Re: FPGA Journal Article
    95968: 06/01/27: EDK 8.1 ... delay
    96233: 06/02/01: Re: Ethernet : MAC vs PHY
    96263: 06/02/01: Re: For our Study We need STM1, 4 , 16 Block diagram where to get it
    98714: 06/03/15: Re: Spartan 3 DCM
    100531: 06/04/11: Re: C-Compiler for free VHDL controller core ?
    101144: 06/04/26: Picoblaze C Compiler
    101189: 06/04/27: Re: Picoblaze C Compiler
    101190: 06/04/27: Re: Picoblaze C Compiler
    101490: 06/05/02: Re: Picoblaze C Compiler
    103385: 06/06/01: Re: Virtex4 FX12 - maximum frequency for Picoblaze
    103841: 06/06/13: Re: How to get lowest price for a ModelSim license?
    108341: 06/09/08: Virtex4FX12 and Spartan3 lead time
    110675: 06/10/19: Microblaze uclinux Kernel panic
    110785: 06/10/23: Re: Microblaze uclinux Kernel panic
    110786: 06/10/23: Re: Microblaze uclinux Kernel panic
    110826: 06/10/24: Re: Microblaze uclinux Kernel panic
    110839: 06/10/24: microblaze uclinux ping delay
    110884: 06/10/25: Re: Survey on Quartus SOPC/Nios-II
    110886: 06/10/25: Re: Microblaze uclinux Kernel panic
    115186: 07/02/02: Re: Webpack 9.1 problems with Impact on parallel cable
    115196: 07/02/02: ISE 9.1 SAY YOURS OPINION
    115264: 07/02/05: Re: ISE 9.1 SAY YOURS OPINION
    115326: 07/02/07: Re: Compile uCLinux for Spartan 3e
    116324: 07/03/07: Re: A Very good VLSI Chip design website
    118428: 07/04/26: Re: picoblaze C compiler download wanted
    118821: 07/05/04: Re: picoblaze C compiler download wanted
    121349: 07/07/03: Xilinx PCI Express solutions
    146444: 10/03/18: Xilinx only on Avnet now
    146445: 10/03/18: Re: FPGA Board and a adc working between 20MHz and 100MHz
Francesco Da Riva:
    150304: 11/01/09: Strange issue wih a very simple VHDL code and Spartan 3A Starter kit board
    150308: 11/01/09: Re: Strange issue wih a very simple VHDL code and Spartan 3A Starter
    150313: 11/01/09: Re: Strange issue wih a very simple VHDL code and Spartan 3A Starter
    150321: 11/01/10: Re: Strange issue wih a very simple VHDL code and Spartan 3A Starter
FRANCESCO IOVINE:
    4742: 96/12/10: GAL STARTER KIT
francesco l spadini:
    14959: 99/02/27: newbie questions
Francesco Micale, X4438:
    2147: 95/10/20: Re: Xilinx Configuration Memory Hacking
    2189: 95/10/29: Re: Xilinx Configuration Memory Hacking
    2689: 96/01/24: Re: HowTo access a SRAM with a XC4000
Francesco Poderico:
    56460: 03/06/05: Re: SONET/SDH chipset on FPGA
    75555: 04/11/09: C Compiler for Picoblaze !!!!!
    75642: 04/11/11: Re: C Compiler for Picoblaze !!!!!
    78634: 05/02/04: C compiler for Picoblaze
Francesco Verdicchio:
    105514: 06/07/25: Calculate CRC in Virtex-Spartan II bitstream
<francesco.poderico@trendcomms.com>:
    88177: 05/08/11: XILINX POWERPC <-> Embedded tri-mode-MAC connection
    88178: 05/08/11: Re: ASIC suggestions
francesco_pincio:
    151048: 11/03/02: iir filter
    151099: 11/03/06: Re: iir filter
    151556: 11/04/19: Re: iir filter
    151559: 11/04/19: Re: iir filter
<francesco_poderico@yahoo.com>:
    89679: 05/09/22: Re: picoblaze IDE for Linux
    89808: 05/09/27: Re: lwip sockets on spartan 3 microblaze? Any examples?
    89843: 05/09/28: Small C Compiler for Picoblaze
    89888: 05/09/29: Re: Small C Compiler for Picoblaze
    89916: 05/09/30: Re: best SPI flash configuration solution for Xilinx FPGA's
    90634: 05/10/18: Re: Rosetta Results
    90798: 05/10/21: Re: EDK on Virtex4 FX using embedded ethernet MAC
    91461: 05/11/07: Re: xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine
    91817: 05/11/14: Re: Viretx4 FX chip availability
    91965: 05/11/18: Re: Setting the environment variable in ISE 7.1?
    92159: 05/11/23: XST vs Synplify
    92224: 05/11/24: Re: XST vs Synplify
    92615: 05/12/02: Re: Virtex-4 FX60 based products are already shipping now !
    93730: 05/12/29: Re: FSM goes into invalid state after reset...
    94246: 06/01/09: Re: CRC error correction
<francescopoderico@googlemail.com>:
    119526: 07/05/22: Re: DDR Controller Blue
    119582: 07/05/23: Re: DDR Controller Blue
    140681: 09/05/21: JTAG problem
<francesjaynetaylor@gmail.com>:
    155702: 13/08/10: Re: [cross-post] vlib, vmap, vcom, how it all works...
    155703: 13/08/10: Re: [cross-post] vlib, vmap, vcom, how it all works...
Francis:
    12675: 98/10/23: Fast multiplier, FPGA & ASIC
    33254: 01/07/20: Schematic libraries in webpack ?
    89977: 05/09/30: ISE does not initialize the bitstream of a EDK project
    90205: 05/10/06: Re: More than one embedded system in ISE
    90217: 05/10/06: Re: ISE does not initialize the bitstream of a EDK project
    91583: 05/11/09: Multilinx, where do I get 3.3V power?
Francis St-Pierre:
    89978: 05/09/30: More than one embedded system in ISE
Francisco Barat Quesada:
    16212: 99/05/10: Re: FPGA, PLD, EPLD, CPLD differences
Francisco Camarero:
    32890: 01/07/11: Re: How do I distribute cores?
    32895: 01/07/11: Re: Need to speed up VHDL accumulator on Xilinx
    36407: 01/11/08: ITU G.273.1 Codec in Virtex XCV400E ?
    36678: 01/11/15: Re: High Speed PWM?
    40025: 02/02/25: Re: Synplify warning that I don't understand
    67626: 04/03/16: Schematic Edition Tool : Suggestions
Francisco José Blasco Abril:
    13289: 98/11/24: Re: How to use port in Altera Max+II (7xxx)
    13309: 98/11/25: Re: Which parts are fastest for 3-state enables?
    13308: 98/11/25: Re: Which parts are fastest for 3-state enables?
    13319: 98/11/25: Re: PCI for Xilinx Virtex
    13335: 98/11/26: Re: Which parts are fastest for 3-state enables?
    15081: 99/03/05: Re: ALTERA pin assignment
    15896: 99/04/20: Re: EEPROM for XC4010XL
Francisco Rodriguez:
    32294: 01/06/22: Re: Two's Complement conversion for FIR coefficients
    48511: 02/10/18: Floorplanner RPM. How to use it?
    48575: 02/10/21: Re: Floorplanner RPM. How to use it?
    48653: 02/10/22: Re: Using MXE II starter as a restricted user
    50152: 02/12/03: Weird problem with RPM
    50259: 02/12/06: Re: Weird problem with RPM
    55562: 03/05/12: How do I know of Xilinx connectivity restrictions?
    55591: 03/05/13: Re: How do I know of Xilinx connectivity restrictions?
    55910: 03/05/23: Re: Using Desigin Constraints in VHDL for Xilinx Spartan-II
    56941: 03/06/19: Re: bidirectional bus (tristate issue)
    56952: 03/06/19: Re: Xilinx ISE is putting this signal assignment in the wrong timing constraint group...
    62758: 03/11/06: Re: Arithmetics with carry
    62807: 03/11/07: Re: Arithmetics with carry
    62970: 03/11/11: Re: Implementing a very fast counterin VirtexII
    63326: 03/11/19: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
    66021: 04/02/11: Re: attribute +generate statement
    67328: 04/03/10: Re: Very strange Xilinx timing report.
    69451: 04/05/11: Constraints interaction report
<francisontheweb@yahoo.com>:
    89742: 05/09/23: 10G serial port with no FEC?
Franck:
    125605: 07/10/30: IDE to Flash memory
    125649: 07/10/31: Re: IDE to Flash memory
    125691: 07/11/01: Re: IDE to Flash memory
Franck Brault:
    3313: 96/05/13: New Web page (links on companies Webs, databooks, FAQs, etc...)
Franck Pissotte:
    29825: 01/03/12: Re: Spartan-II Evaluation Board
    38854: 02/01/26: Re: Homebrew computers using FPGA?
    38855: 02/01/26: Re: Homebrew computers using FPGA?
Franck Thierry:
    19030: 99/11/24: UTOPIA Interface on FPGA
Franck Y:
    131045: 08/04/08: Disable optimisation - Ring oscillator
    131050: 08/04/08: Re: Disable optimisation - Ring oscillator
    131051: 08/04/08: Re: Disable optimisation - Ring oscillator
Franco Tiratore:
    101814: 06/05/07: FPGA implementation of an OFDM-based modem
    102076: 06/05/10: [Newbie] 64-point complex FFT with 32 bit floating-point representation
    102151: 06/05/11: Re: 64-point complex FFT with 32 bit floating-point representation
    102163: 06/05/11: Re: 64-point complex FFT with 32 bit floating-point representation
    102165: 06/05/11: Re: 64-point complex FFT with 32 bit floating-point representation
    102224: 06/05/12: Re: 64-point complex FFT with 32 bit floating-point representation
    102249: 06/05/12: Re: 64-point complex FFT with 32 bit floating-point representation
    102739: 06/05/19: [Newbie] Suitable FPGA for my project
    102745: 06/05/19: Re: Suitable FPGA for my project
    102779: 06/05/20: Re: Suitable FPGA for my project
    102815: 06/05/21: Re: Suitable FPGA for my project
Francois Choquette:
    44683: 02/06/26: Multiple XC_PROPS attributes
    44711: 02/06/27: Re: Foundation ISE 4.2i SP3 release notes
    44730: 02/06/28: Re: Multiple XC_PROPS attributes
    45843: 02/08/07: Re: parameterized / variable ucf
    45871: 02/08/08: Re: xilinx: map -k
    59466: 03/08/19: Re: Which software from Xilinx
    113141: 06/12/06: Registers initial values with Altera Stratix II
    136260: 08/11/07: Re: face recognition
Francois DUSSAUGEY:
    25611: 00/09/15: Re: Xilinx PCI interface: buy the LogiCORE or do it yourself?
francois.hamon:
    23251: 00/06/19: Recherche =?iso-8859-1?Q?ing=E9nieur?= telecom/FPGA
frank:
    47231: 02/09/20: SDRAM<--->FPGA<--->IDE interface
    47416: 02/09/25: Re: SDRAM<--->FPGA<--->IDE interface
    51723: 03/01/20: frequency matching of ring oscillators
    51783: 03/01/21: Re: frequency matching of ring oscillators
    55240: 03/05/01: programmable oscillators
    101882: 06/05/08: Re: Xilinx 3s8000?
Frank:
    8491: 97/12/23: PCI-AT bridge
    8684: 98/01/20: UART Spec
    9097: 98/02/20: buft and bufe
    43228: 02/05/16: Circuit design for Altera ACEX development board
    48850: 02/10/25: Xilinx Webpack 4.2WP3 Question
    55988: 03/05/26: New Architectures
    60575: 03/09/16: Making hard macros in Xilinx FPGA Editor
    62259: 03/10/23: OPB write actions
    62367: 03/10/28: Re: OPB write actions
    62380: 03/10/28: Re: OPB write actions
    62695: 03/11/05: microblaze exceptions
    63213: 03/11/18: microblaze as submodule
    63222: 03/11/18: Re: microblaze as submodule
    63284: 03/11/19: interrupt handler for microblaze system
    63503: 03/11/24: MDD file
    63548: 03/11/25: using xilkernel
    63549: 03/11/25: running from external memory (microblaze)
    63608: 03/11/26: Re: running from external memory (microblaze)
    63707: 03/12/01: debugging microblaze with xmd
    63784: 03/12/04: Re: debugging microblaze with xmd
    63804: 03/12/04: process table for XMK
    63832: 03/12/05: Re: process table for XMK
    63893: 03/12/08: Re: process table for XMK
    63919: 03/12/09: Re: process table for XMK
    63996: 03/12/11: stopping XMK (at microblaze)
    64017: 03/12/12: Re: stopping XMK (at microblaze)
    64018: 03/12/12: 16-bit sdram and 32-bit opb bus
    64027: 03/12/12: Re: EDK, reset module, interrupts
    64028: 03/12/12: byte order microblaze
    64056: 03/12/15: Re: byte order microblaze
    89546: 05/09/19: Modelsim XE, what's the latest version?
    89547: 05/09/19: Re: Modelsim XE, what's the latest version?
    89581: 05/09/20: Re: Modelsim XE, what's the latest version?
    89585: 05/09/20: Re: Modelsim XE, what's the latest version?
    91619: 05/11/10: In Xilinx, how do I delay a signal by a fraction of a clock cycle?
    91622: 05/11/10: Re: Multilinx, where do I get 3.3V power?
    91624: 05/11/10: Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?
    92080: 05/11/22: How do I find the datasheet of this device "TIOPA 690 3BZL9"?
    92332: 05/11/28: ADC keeps outputting negative numbers, how?
    92333: 05/11/28: AD9218, what will the negative values be in binary mode?
    92345: 05/11/28: Re: AD9218, what will the negative values be in binary mode?
    92346: 05/11/28: Re: AD9218, what will the negative values be in binary mode?
    92372: 05/11/29: Re: ADC keeps outputting negative numbers, how?
    92376: 05/11/29: Why does two channels of ADC give different outputs?
    92377: 05/11/29: Re: Why does two channels of ADC give different outputs?
    92383: 05/11/29: Looking for manual for logic analyzer module 16750A.
    92384: 05/11/29: Re: Why does two channels of ADC give different outputs?
    92440: 05/11/30: Re: Looking for manual for logic analyzer module 16750A.
    92453: 05/11/30: Re: Why does two channels of ADC give different outputs?
    92455: 05/11/30: Re: Why does two channels of ADC give different outputs?
    92472: 05/11/30: Re: Why does two channels of ADC give different outputs?
    92527: 05/12/01: Re: Looking for manual for logic analyzer module 16750A.
    92528: 05/12/01: Re: Why does two channels of ADC give different outputs?
    92585: 05/12/02: Quick question, how do I supply +-5V?
    92591: 05/12/02: Re: Quick question, how do I supply +-5V?
    92904: 05/12/09: How do I find the signature of PROM bitstreams?
    93005: 05/12/12: When read back bitstreams from Xilinx PROMs, how to verify?
    93009: 05/12/12: Re: who can help me? i want to know the bitsream format of Virtex-II
    93011: 05/12/12: Re: Why does two channels of ADC give different outputs?
    93053: 05/12/13: How can I surpress noise in an ADC board?
    93054: 05/12/13: Re: who can help me? i want to know the bitsream format of Virtex-II
    93108: 05/12/14: Re: How can I surpress noise in an ADC board?
    93120: 05/12/14: Can ISE 4.2 program Virtex 2 6000K devices?
    93166: 05/12/15: Re: Can ISE 4.2 program Virtex 2 6000K devices?
    95001: 06/01/20: How in Design Compiler disable writing out "Assign" statement into the netlist?
    96318: 06/02/02: How will synthesizers handle these statements?
    97865: 06/03/01: Anyone with Insight DS-V2LC Board Rev. 2 datasheet?
    97929: 06/03/02: Re: How do I make dual-port RAM from single port RAM?
    97930: 06/03/02: Re: How do I make dual-port RAM from single port RAM?
    97940: 06/03/02: Re: How do I make dual-port RAM from single port RAM?
    97941: 06/03/02: Re: Anyone with Insight DS-V2LC Board Rev. 2 datasheet?
    97954: 06/03/02: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    97955: 06/03/02: Re: Anyone with Insight DS-V2LC Board Rev. 2 datasheet?
    98120: 06/03/06: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    99681: 06/03/28: Please recomend textbook with AES encryption.
    99826: 06/03/30: Re: Please recomend textbook with AES encryption.
    114154: 07/01/05: WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs
    120499: 07/06/07: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
    120500: 07/06/07: HELP with Asynch RAM
    146163: 10/03/07: Question in verilog testbench
    146171: 10/03/07: Re: Question in verilog testbench
Frank @ CN:
    97817: 06/02/28: How do I make dual-port RAM from single port RAM?
    97855: 06/03/01: Re: How do I make dual-port RAM from single port RAM?
    97856: 06/03/01: Re: How do I make dual-port RAM from single port RAM?
Frank A. Vorstenbosch:
    47: 94/08/04: Pierce oscillator using FPGA gates?
    14881: 99/02/22: Re: Altera freecore library ?
    17282: 99/07/16: Components for sale (London, UK)
Frank Adalater:
    47251: 02/09/21: Cheap development package for beginner?
Frank Adlam:
    4183: 96/09/23: Re: *** finding datasheets and chipmakers on the web ***
Frank Andreas de Groot:
    46483: 02/08/31: Re: Webpack 4.2 Schematic
    46505: 02/09/02: Re: Webpack 4.2 Schematic
    46535: 02/09/02: C/C++ to Verilog/VHDL ?!
    46536: 02/09/02: Re: C/C++ to Verilog/VHDL ?!
    46542: 02/09/03: Re: C/C++ to Verilog/VHDL ?!
    46566: 02/09/03: Re: C/C++ to Verilog/VHDL ?!
    46571: 02/09/03: Re: C/C++ to Verilog/VHDL ?!
    46595: 02/09/04: Re: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
    46639: 02/09/04: Re: why the need for HIGH speed design?
    46686: 02/09/05: Re: why the need for HIGH speed design?
    46764: 02/09/08: Re: Fault tolerant FPGA design
    46772: 02/09/08: Re: Fault tolerant FPGA design
    46819: 02/09/09: Re: C/C++ to Verilog/VHDL ?!
    46876: 02/09/10: Re: C/C++ to Verilog/VHDL ?!
    46904: 02/09/11: Re: C/C++ to Verilog/VHDL ?!
    59393: 03/08/18: Re: Never used FPGA board for sale
Frank Bemelman:
    13902: 99/01/01: Re: Can a cross coupled latch "oscillate"? was Re: ..........
    14055: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    14073: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    14090: 99/01/12: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    23916: 00/07/14: Re: Dual Port RAM
    24799: 00/08/18: Re: Non-disclosures in job interviews, Round One
    87901: 05/08/03: Re: System Engineering in the R/D World
    95384: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95405: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95437: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95438: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95498: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95523: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    95524: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    107781: 06/09/01: Re: Performance Appraisals
    107913: 06/09/02: Re: Performance Appraisals
Frank Benoit:
    70316: 04/06/12: Costs of IPs
    70318: 04/06/12: Re: Costs of IPs
    70331: 04/06/13: Re: Costs of IPs
    70389: 04/06/15: Starter Kit for Linux in Virtex?
    70540: 04/06/19: Re: compressing Xilinx bitstreams, some test data
    70541: 04/06/19: Re: Xilinx XST synthesis removes input pin even though it's LOCed
    72256: 04/08/12: Problem instantiating xilinx blockram ramb4_s1_s16
    72268: 04/08/12: Re: Problem instantiating xilinx blockram ramb4_s1_s16
    72273: 04/08/12: Re: Problem instantiating xilinx blockram ramb4_s1_s16
    72303: 04/08/14: Re: Problem instantiating xilinx blockram ramb4_s1_s16
frank bergmann:
    32955: 01/07/12: Re: Xilinx makefile under RedHat
Frank Bures:
    3314: 96/05/13: Re: Anyone use Orcad PLD tools ?
    3315: 96/05/13: Re: Anyone use Orcad PLD tools ?
Frank Buss:
    103070: 06/05/25: Re: LISP Workshop at ECOOP06
    104599: 06/07/01: Problem with SLL: "sll can not have such operands in this context" and bit-testing
    105080: 06/07/13: Spartan 3E starter kit DDR SDRAM code
    105087: 06/07/13: Re: Spartan 3E starter kit DDR SDRAM code
    105164: 06/07/16: Re: An idea for a product (FPGA/ASIC based)
    105283: 06/07/19: Re: VHDL Data Buffer on Spartan-3E
    105317: 06/07/20: Re: Virtex-5: SoftCore processors at 200MHz !
    105720: 06/07/29: Re: Can I get 840HZ from a Xilinx Spartan-3's DCM? Phase locked?
    105727: 06/07/30: Re: "This design element is inferred rather than instantiated" (newbie)
    105750: 06/07/31: Re: Problems compiling with ISE Webpack 8.2.01i
    105769: 06/07/31: Re: Problems compiling with ISE Webpack 8.2.01i
    106036: 06/08/06: Xilinx Impact USB speed problem
    106038: 06/08/06: clock problems with Spartan 3E starter kit
    106048: 06/08/07: Re: Counter status flags don't stay asserted not sure why?
    106185: 06/08/09: Re: Xilinx Impact USB speed problem
    106202: 06/08/09: Re: Simple code to check out Spartan3 starter kit?
    106301: 06/08/11: Re: clock problems with Spartan 3E starter kit
    106327: 06/08/11: Re: Embedded clocks
    106330: 06/08/11: Re: Embedded clocks
    106360: 06/08/12: Re: Embedded clocks
    106361: 06/08/12: Re: Embedded clocks
    106363: 06/08/12: Re: Embedded clocks
    106401: 06/08/12: Re: Embedded clocks
    106428: 06/08/13: Re: Gaisler on a Spartan 3E Starter Kit?
    106479: 06/08/14: Re: Gaisler on a Spartan 3E Starter Kit?
    106481: 06/08/14: how to declare a Wishbone interface with 4 bit port size and granularity?
    106531: 06/08/15: Re: Crystal input for FPGA
    106553: 06/08/15: Re: Crystal input for FPGA
    106556: 06/08/15: Re: IIR filter example ?
    106739: 06/08/18: Re: Using an FPGA as USB HOST without PHY
    106818: 06/08/20: CPU design
    106821: 06/08/20: Re: CPU design
    106830: 06/08/20: Re: CPU design
    106840: 06/08/21: Re: CPU design
    106864: 06/08/21: Re: CPU design
    106875: 06/08/22: Re: CPU design
    106890: 06/08/22: Re: CPU design
    106893: 06/08/22: Re: CPU design
    106898: 06/08/22: Re: CPU design
    106940: 06/08/23: Re: CPU design
    106947: 06/08/23: Re: CPU design
    106969: 06/08/23: Re: CPU design
    107041: 06/08/24: Re: esoteric hardware?
    107057: 06/08/24: Re: CPU design
    107058: 06/08/24: Re: esoteric hardware?
    107311: 06/08/26: adiabatic and reversible computing with FPGAs?
    107585: 06/08/30: Re: Xilinx - one secret less, or how to use the PMV primitive
    107883: 06/09/01: Re: Impossible to download WebPACK?
    107920: 06/09/02: Re: Impossible to download WebPACK?
    107924: 06/09/02: Re: I do not know this !
    107938: 06/09/03: Forth-CPU design
    107950: 06/09/03: Re: Forth-CPU design
    107951: 06/09/03: Re: Forth-CPU design
    107952: 06/09/03: Re: Forth-CPU design
    107961: 06/09/03: Re: Here are the URLs (was Re: Impossible to download WebPACK?)
    108892: 06/09/19: Re: regarding 4 bit multiplier
    110623: 06/10/19: Re: Cheapest FPGA board to study VHDL on
    111073: 06/10/28: Re: FPGA-based music synthesizer (with MyHDL)
    111108: 06/10/29: Re: A pre-emptive strike against blaming the chip
    111114: 06/10/29: Re: Survey: simulator usage
    111115: 06/10/29: Re: A pre-emptive strike against blaming the chip
    111133: 06/10/30: Re: Stratix to PC communication
    111459: 06/11/03: Re: Scientific Computing on FPGA
    111825: 06/11/10: Re: Code for Verilog 8bit * 8bit pipelined multiplier
    111829: 06/11/10: using FPGAs for synthesizing?
    111852: 06/11/11: Re: Virtex-5 Webpack?
    111871: 06/11/12: Re: SDRAM of Spartan 3E
    112070: 06/11/15: how to filter glitches and mutliple transitions?
    112084: 06/11/16: Re: how to filter glitches and mutliple transitions?
    112127: 06/11/16: Re: how to filter glitches and mutliple transitions?
    112200: 06/11/17: state problems with Quartus II 6
    112206: 06/11/17: Re: state problems with Quartus II 6
    112399: 06/11/21: Re: 8080 FSGA model in an FPGA
    112404: 06/11/21: Re: Spartan 3E-Kit
    112423: 06/11/22: Re: Spartan 3E-Kit
    112478: 06/11/23: Re: Spartan 3E-Kit
    112519: 06/11/23: Re: Spartan 3E-Kit
    112655: 06/11/27: Re: tips for P&R in FPGA(quartus)
    112958: 06/12/02: Re: Opencores DDR SDRAM controller
    113009: 06/12/05: Re: Opencores DDR SDRAM controller
    113101: 06/12/06: Re: Clock phase shift
    113361: 06/12/12: Re: Opencores DDR SDRAM controller
    113498: 06/12/15: Re: Opencores DDR SDRAM controller
    118094: 07/04/17: Re: 80000 Bit Shift Register
    118097: 07/04/17: Re: 80000 Bit Shift Register - The Code
    118769: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
    118774: 07/05/03: Re: Xilinx software quality - how low can it go ?!
    119119: 07/05/12: Re: how to choose the perfect fpga support
    119631: 07/05/24: 6502 and CPU licences in general
    119640: 07/05/24: Re: Binary to BCD
    119642: 07/05/24: Re: 6502 and CPU licences in general
    119643: 07/05/24: Re: 6502 and CPU licences in general
    119706: 07/05/25: Re: 6502 and CPU licences in general
    119808: 07/05/26: Re: 6502 and CPU licences in general
    119819: 07/05/27: 6502 FPGA core
    119825: 07/05/27: Re: 6502 FPGA core
    119836: 07/05/27: Re: 6502 FPGA core
    119929: 07/05/29: Re: 6502 FPGA core
    120417: 07/06/07: Re: asynchronous circuit design
    120482: 07/06/08: another Forth CPU design
    120801: 07/06/17: Re: anyone know a FPGA designer?
    120992: 07/06/21: Nios II problem
    120994: 07/06/21: Re: Nios II problem
    120995: 07/06/21: Re: Nios II problem
    121071: 07/06/25: Re: How to choose FPGA for a huge computation?
    121173: 07/06/27: Re: another Forth CPU design
    121200: 07/06/28: Re: another Forth CPU design
    122437: 07/07/27: Re: Best CPU platform(s) for FPGA synthesis
    122924: 07/08/10: Re: Amount of wire and logic
    122927: 07/08/10: Re: Amount of wire and logic
    123312: 07/08/23: Re: comparison with embedded processor
    123788: 07/09/04: Re: FPGA CPU
    125543: 07/10/28: Re: Power supply filter capacitors
    125544: 07/10/28: Re: Power supply filter capacitors
    125693: 07/11/01: Re: can i use dual edge or two clocks?
    125706: 07/11/01: Re: can i use dual edge or two clocks?
    127001: 07/12/08: DDS generator with interpolated samples for Spartan3E development board
    127037: 07/12/10: Re: DDS generator with interpolated samples for Spartan3E development board
    127064: 07/12/11: Re: DDS generator with interpolated samples for Spartan3E development board
    127065: 07/12/11: Re: DDS generator with interpolated samples for Spartan3E development board
    127067: 07/12/11: Re: DDS generator with interpolated samples for Spartan3E development board
    127070: 07/12/11: Re: DDS generator with interpolated samples for Spartan3E development board
    127103: 07/12/12: Re: DDS generator with interpolated samples for Spartan3E development board
    127105: 07/12/12: Re: DDS generator with interpolated samples for Spartan3E development board
    127111: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
    127208: 07/12/14: Re: DDS generator with interpolated samples for Spartan3E development board
    127528: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
    127534: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
    127577: 08/01/03: Re: Where are the LCD or OLED bitmapped displays?
    127610: 08/01/03: Re: Where are the LCD or OLED bitmapped displays?
    128279: 08/01/20: Re: Source of accurate frequency
    128280: 08/01/20: Re: Source of accurate frequency
    128791: 08/02/06: Re: 1-Wire and Dallas DS1WM in Spartan
    129097: 08/02/14: Cyclone flash configuration data
    129102: 08/02/14: Re: Rom Implementation in a CPLD
    129121: 08/02/14: Re: Spartan 3 configuration download error
    129167: 08/02/17: Re: Over utilization of FPGA resources
    129188: 08/02/18: Re: Interface on board ADC to Spartan 3E startkit
    129258: 08/02/19: Re: Cyclone flash configuration data
    129408: 08/02/22: Re: newbie seeking help to use xilinx spart-3a starter kit
    129426: 08/02/23: Re: FPGA Editor Tutorial based on examples
    129429: 08/02/23: Re: FPGA Editor Tutorial based on examples
    129896: 08/03/08: Re: Cyclone III and Quartus 7.2sp2
    130305: 08/03/20: Re: A Challenge for serialized processor design and implementation
    130349: 08/03/20: Re: A Challenge for serialized processor design and implementation
    130372: 08/03/21: Re: Designing CPU
    130644: 08/03/29: Re: async clk input, clock glitches
    130650: 08/03/29: Re: ISE 10.1 - Initial experience
    130797: 08/04/02: Re: now I can talk about it...
    130922: 08/04/05: Re: Project Ideas
    130949: 08/04/06: Re: Xilinx inferred FIFOs
    130958: 08/04/07: Re: Xilinx inferred FIFOs
    131338: 08/04/20: Re: Very simple VHDL problem
    131344: 08/04/20: Re: Very simple VHDL problem
    131360: 08/04/21: Re: Problem writing quadrature decoder
    132047: 08/05/11: Re: Problem writing quadrature decoder
    132060: 08/05/12: Re: value of the weak pull up resistor on IOBs of Virtex5
    132062: 08/05/12: Re: How to input an analog signal to FPGA board for processing?
    132326: 08/05/22: Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
    132561: 08/05/31: Re: cutoff frequency
    132563: 08/05/31: Re: cutoff frequency
    132689: 08/06/05: Re: Xilinx cuts 250 jobs.
    132703: 08/06/05: Re: Xilinx cuts 250 jobs.
    132998: 08/06/12: Re: Altera Quartus Web Edition 8.0 available
    133474: 08/07/01: Re: Design of a BFSK transmitter/receiver using Xilinx System Generator
    133517: 08/07/02: Re: VHDL code for RCOM message
    133518: 08/07/02: Re: real time FIR implementation in FPGA
    133522: 08/07/02: Re: real time FIR implementation in FPGA
    133523: 08/07/02: Re: real time FIR implementation in FPGA
    133696: 08/07/10: Re: Can I store the output of my FPGA logic inside FPGA memory for debug data values?
    133707: 08/07/10: Re: Can I store the output of my FPGA logic inside FPGA memory for debug data values?
    134030: 08/07/22: Re: powering fpga with lm317
    134053: 08/07/23: Re: Any good forum devoted to digital systems design?
    134115: 08/07/26: Re: Creating new operators
    134122: 08/07/26: Re: Creating new operators
    134124: 08/07/26: Re: Creating new operators
    134125: 08/07/26: Re: The littlest CPU
    134137: 08/07/27: Re: vhdl code for debouncing push button
    134649: 08/08/24: Re: Digital-to-Analog Converter LTC 2624, Spartan-3A
    134933: 08/09/07: Re: Spartan 3E evaluation board manufacturers
    134934: 08/09/07: Re: Spartan 3E evaluation board manufacturers
    134937: 08/09/07: Re: Spartan 3E evaluation board manufacturers
    134939: 08/09/07: Re: Spartan 3E evaluation board manufacturers
    135060: 08/09/12: Re: Ultra low power FPGAs
    135499: 08/10/05: Re: A question about the use of FPGA
    135535: 08/10/06: Re: A question about the use of FPGA
    135611: 08/10/09: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    135612: 08/10/09: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    135615: 08/10/10: Re: Newbie question
    135707: 08/10/13: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    135802: 08/10/16: Re: A couple of CPLD design challenges for the group
    135968: 08/10/24: again: statemachine bug in Quartus II Web Edition Software v8.0 SP1
    135970: 08/10/24: Re: again: statemachine bug in Quartus II Web Edition Software v8.0 SP1
    135994: 08/10/26: Re: how to program virtex 4?
    136379: 08/11/13: Re: Why memory for this Nios II is still not enough
    136382: 08/11/13: Re: Why memory for this Nios II is still not enough
    137188: 08/12/31: Re: One-channel >> multi-channel serial DAC
    137294: 09/01/08: problems with symbols and how to debug Quartus block diagrams with Modelsim?
    137296: 09/01/08: Re: problems with symbols and how to debug Quartus block diagrams with Modelsim?
    137299: 09/01/08: Re: problems with symbols and how to debug Quartus block diagrams with Modelsim?
    138200: 09/02/09: Re: Learning backend stuff
    138443: 09/02/23: Re: Cyclone2 4-phase clock generation
    138514: 09/02/25: Re: Converting state machine encoding to std_logic_vector
    138517: 09/02/25: Re: Converting state machine encoding to std_logic_vector
    139926: 09/04/19: Re: Atari VCS 2600 FPGA Cartridge
    139939: 09/04/20: Re: Atari VCS 2600 FPGA Cartridge
    140333: 09/05/09: Re: Dual Port RAM Inference
    140762: 09/05/25: passing data from fast to slow time domain
    140765: 09/05/25: Re: passing data from fast to slow time domain
    140825: 09/05/27: Re: passing data from fast to slow time domain
    141036: 09/06/03: Re: BRAM/LUT Comparison
    142070: 09/07/23: Re: FPGA development tools for FreeBSD?
    142121: 09/07/25: Re: How to implementa an FSM in block ram
    142122: 09/07/25: advanced clock divider generator
    142129: 09/07/26: Re: How to implementa an FSM in block ram
    142131: 09/07/26: Re: How to implementa an FSM in block ram
    142132: 09/07/26: Re: How to implementa an FSM in block ram
    142220: 09/07/29: Re: How to implementa an FSM in block ram
    142228: 09/07/29: Re: Implementing VHDL code in an embedded processor design and readout to computer.
    142237: 09/07/30: Re: How to implementa an FSM in block ram
    142253: 09/07/30: Re: Implementing VHDL code in an embedded processor design and readout to computer.
    142457: 09/08/12: Re: Spartan-6 Boards - Your Wish List
    142483: 09/08/12: Re: Spartan-6 Boards - Your Wish List
    142484: 09/08/12: Re: Spartan-6 Boards - Your Wish List
    142537: 09/08/16: Re: Soft Processor IP core report
    142554: 09/08/17: Re: Soft Processor IP core report
    142598: 09/08/20: Re: Emulation of highly complex superscaler processor using FPGAs
    142633: 09/08/23: Yet Another Graphics Controller
    142635: 09/08/23: Re: Yet Another Graphics Controller
    142637: 09/08/23: Re: Suitable starter kit for learning VHDL
    142652: 09/08/24: Re: Yet Another Graphics Controller
    142654: 09/08/24: Re: Yet Another Graphics Controller
    142671: 09/08/25: Re: Timing properties of FPGA devices at sub-clock frequencies
    142675: 09/08/25: Re: Timing properties of FPGA devices at sub-clock frequencies
    142681: 09/08/26: Re: Reading from ADC and writing to DAC at same time
    142691: 09/08/26: Re: Reading from ADC and writing to DAC at same time
    142692: 09/08/26: Re: Reading from ADC and writing to DAC at same time
    142698: 09/08/27: Re: Reading from ADC and writing to DAC at same time
    142699: 09/08/27: Re: Reading from ADC and writing to DAC at same time
    142706: 09/08/27: Re: Reading from ADC and writing to DAC at same time
    142751: 09/08/30: Re: program spartan3 under linux
    142790: 09/09/01: Re: Wants an update on FPGA development IDE/toolchains
    142881: 09/09/05: Re: Interfacing variable-speed functional units
    143014: 09/09/15: Re: To Xilinx: Regarding the download manager
    143181: 09/09/24: Re: Virtex 4 configruation frame internal details
    143222: 09/09/27: Re: ChipScope Pro, storing stimuli in ILA core
    143638: 09/10/19: Re: where can price list of FPGA be found?
    143892: 09/11/02: Re: 50+ pages fresh from Antti's brain
    143893: 09/11/02: Re: 50+ pages fresh from Antti's brain
    143902: 09/11/02: Re: 50+ pages fresh from Antti's brain
    144665: 09/12/22: Re: H.264 on Spartan3A DSP
    144725: 09/12/29: Re: How to protect my Virtex5 design without battery?
    144729: 09/12/29: Re: How to protect my Virtex5 design without battery?
    144735: 09/12/30: Re: Seeking some advice
    144742: 09/12/30: Re: How to protect my Virtex5 design without battery?
    144795: 10/01/04: Re: Digital-to-Analog Converter LTC 2624, Spartan-3A
    147546: 10/05/01: Re: Cheap FPGAs for tutorial
    148198: 10/06/27: Re: Free bitmap font
    148281: 10/07/04: Re: xilinx leadtimes
    148300: 10/07/06: Re: Q: Standard Programming Idiom
    148491: 10/07/27: Re: temporal logic folding
    148758: 10/08/19: Re: FPGA PCI BOARD .. Few Questions
    148813: 10/08/28: Re: Stratix iv PLLs ref clock
    148999: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
    149116: 10/10/02: Re: FPGA design not working!
    149136: 10/10/04: Re: FPGA design not working!
    149344: 10/10/18: Re: FPGA or CPLD?
    150394: 11/01/16: Re: Location constraints questions
    150396: 11/01/16: Re: Location constraints questions
    151264: 11/03/19: NIOS II license?
    151283: 11/03/20: Re: NIOS II license?
    151449: 11/04/10: Re: Altium Limited closing up shop - Altium Designer discontinued
    152082: 11/07/02: Re: Delta-Sigma in an FPGA
    152842: 11/10/26: Re: Peter Alfke has passed away
    152949: 11/11/04: Re: draw lines, circles, squares on FPGA by mouse and display on
    153038: 11/11/19: Re: Production Programming of Flash for FPGAs and MCUs
    153178: 12/01/04: Re: slimming down ISE install
    153190: 12/01/05: Re: Trying to select a development board, can somebody help me make
    153531: 12/03/25: Re: Digital Tachometer VHDL
    153626: 12/04/06: Re: Mandelbrot set on Spartan3
    153642: 12/04/09: Re: Best FPGA for algorithmic acceleration
    153674: 12/04/15: Re: recomendation on a processor core
    153676: 12/04/15: Re: recomendation on a processor core
    153714: 12/04/29: Re: FPGA acceleration v.s. GPU acceleration
    153719: 12/04/30: Re: Smallest GPL UART
    153725: 12/05/01: Re: Smallest GPL UART
    153727: 12/05/02: Re: Smallest GPL UART
    153731: 12/05/02: Re: Smallest GPL UART
    154082: 12/08/01: how much costs the Artix 7 devices?
    154088: 12/08/01: Re: how much costs the Artix 7 devices?
    154091: 12/08/02: Re: how much costs the Artix 7 devices?
    154095: 12/08/03: Re: how much costs the Artix 7 devices?
    154097: 12/08/05: Re: how much costs the Artix 7 devices?
    154208: 12/09/09: Re: Looking for an extremely cheap FPGA board (in quantity, academic
    154215: 12/09/10: Re: Looking for an extremely cheap FPGA board (in quantity, academic
    154218: 12/09/10: Re: Looking for an extremely cheap FPGA board (in quantity, academic
    154327: 12/09/28: Re: JTAG access from user design in Altera FPGAs
    154356: 12/10/14: Re: My First CPU but.. one problem
    154365: 12/10/15: Re: My First CPU but.. one problem
    155192: 13/05/25: Re: Cubic Spline Interpolator
    155200: 13/05/31: Re: Cubic Spline Interpolator
    155922: 13/10/16: Re: Zynq devices, boards and suppliers
    156252: 14/01/25: Re: my first microZed board
    156958: 14/08/07: strange effect with tristate output
    156961: 14/08/07: Re: strange effect with tristate output
Frank Ch. Eigler:
    29873: 01/03/14: Re: NIOS 16-Bit
Frank Chee (Remove the dots):
    83125: 05/04/24: Re: What is the cause of a "can not see clock" problem in logic analyser?
    85919: 05/06/18: Re: Xilinx
Frank Costantini:
    892: 95/03/22: Help: BCH Coding/Decoding in FPGA
Frank D. Cringle:
    5246: 97/02/01: Re: Steven K. Knapp - no such article
Frank de Groot:
    41816: 02/04/08: Low-cost FPGA + processor board?
    41828: 02/04/09: Re: Low-cost FPGA + processor board?
    41860: 02/04/09: Re: Low-cost FPGA + processor board?
    41868: 02/04/09: Re: Low-cost FPGA + processor board?
    41888: 02/04/10: Re: Low-cost FPGA + processor board?
    41909: 02/04/10: Re: Low-cost FPGA + processor board?
    41910: 02/04/10: Re: Low-cost FPGA + processor board?
    41951: 02/04/11: Re: Low-cost FPGA + processor board?
    42011: 02/04/12: Re: Low-cost FPGA + processor board?
    83491: 05/05/01: Cheap PowerPC G4 PCI coprocessor board for the PC
Frank Dresig:
    1174: 95/05/11: Workshop "Anwenderprogrammierbare Schaltungen"
    6217: 97/04/29: New Lattice (is)pLSI Resynthesis Server now online
frank fu:
    84958: 05/06/01: using 8051 and converted XSVF to download Spartan3
    84959: 05/06/01: file differece for two xsvf files
Frank Gilbert:
    6827: 97/07/01: Re: EDIF for Xilinx tools
    7156: 97/08/07: Problems with SDF Backannotation XACTStep6000
    7643: 97/09/30: Re: fifos design for fpga
    7720: 97/10/07: Re: Need help for Xilinx Demo Board
    8649: 98/01/16: Re: XC6200 Questions
    9982: 98/04/21: Re: Could you help me save CLB's?
    10810: 98/06/22: Re: Problems with XILINX 1.4
Frank GOENNINGER:
    150447: 11/01/22: Re: I Give Up!
Frank Guerino:
    2711: 96/01/27: Re: VHDL/Verilog training
    2712: 96/01/27: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
    2721: 96/01/30: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
    2763: 96/02/03: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
    2764: 96/02/03: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
Frank Hoffmann:
    51516: 03/01/15: Re: Short FIFO in Verilog / Spartan IIE
    54966: 03/04/23: Problem : Simulating SRL16 with webpack 5.2 and modelsim 5.6e starter
    54971: 03/04/23: Re: Problem : Simulating SRL16 with webpack 5.2 and modelsim 5.6e
frank johson:
    27202: 00/11/15: test test just test
    27228: 00/11/16: mailing list for this newsgroup ?
    27642: 00/12/01: jtag for fpga
Frank Kneepkens:
    8017: 97/11/07: How to program Altera EPC1213 from hex file?
Frank Leischnig:
    110125: 06/10/11: Virtex 4 RAMB16 Clock: optional inverter missing
    110193: 06/10/12: Re: Virtex 4 RAMB16 Clock: optional inverter missing
Frank Madison:
    22997: 00/06/08: Deficiencies in Actel 40mx tools?
    23050: 00/06/11: Re: math help needed
    27514: 00/11/26: Re: Fifo design problem
Frank Martinez:
    55408: 03/05/06: Xilinx XC4000 slave serial programming Q
Frank Miles:
    6832: 97/07/01: Re: fast scopes: how?
Frank Papendorf:
    16005: 99/04/27: Storage of 32Bit-Vectors
    16762: 99/06/07: FPGA interface SDRAM
Frank Papenfuss:
    37840: 01/12/21: CE on XILINX FFs and Metastability
Frank Poppen:
    20819: 00/02/23: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
Frank Quakernack:
    82395: 05/04/12: Re: Altera and VHDL library
Frank Raffaeli:
    63613: 03/11/26: Re: Reverse engineering an EDIF file?
Frank Scherler:
    16489: 99/05/25: JOB WANTED
    16491: 99/05/25: JOB WANTED
    43559: 02/05/23: JTAG ICE or programmer
Frank Schreiber:
    93613: 05/12/26: Download to board with RS232
    94226: 06/01/08: newbie question about Xillinx JTAG cable
    95338: 06/01/22: Starting with LVDS
    95385: 06/01/23: Re: Starting with LVDS
    95388: 06/01/23: Re: Starting with LVDS
    95382: 06/01/23: Re: Starting with LVDS
Frank Soehnge:
    2261: 95/11/14: Industry Trends
    2283: 95/11/17: Re: Industry Trends
Frank Tripp:
    24337: 00/08/04: Hardware for Sparse Matrix x Vector multiplication
Frank Van de Sande:
    22595: 00/05/12: foundation
    25234: 00/08/31: Re: Accessing internal signals and ports for writing to a file using testbench
    27138: 00/11/12: Leon processor core
    34802: 01/09/08: synplify device configuration settings
Frank van Eijkelenburg:
    64062: 03/12/15: .elf to .bin file for microblaze
    64098: 03/12/16: Re: .elf to .bin file for microblaze
    65393: 04/01/27: pjcli commandline tool
    66013: 04/02/11: debug with opb mdm for microblaze system
    66014: 04/02/11: debug application in sdram (microblaze system)
    66068: 04/02/12: debug sdram application with use of xmdstub (microblaze)
    66078: 04/02/12: Re: debug sdram application with use of xmdstub (microblaze)
    66087: 04/02/12: Re: debug application in sdram (microblaze system)
    66922: 04/03/01: Re: embedded powerpc in VirtexII-pro
    68182: 04/03/29: simalation of gigabit ethernet fails
    68204: 04/03/30: Re: ISE and EDK Incompatible?
    68250: 04/03/31: simulation
    68307: 04/04/01: Re: simulation
    68308: 04/04/01: Re: simalation of gigabit ethernet fails
    68369: 04/04/02: signal names in modelsim
    68370: 04/04/02: vcom in modelsim
    69245: 04/05/03: Re: EDK 3.2
    69255: 04/05/03: timing constraints
    69273: 04/05/04: Re: timing constraints
    75176: 04/10/28: OPB versus PLB
    82190: 05/04/08: running microblaze from bram through OPB-bus
    82385: 05/04/12: Re: running microblaze from bram through OPB-bus
    82417: 05/04/12: Re: How do I disable Microblaze on-chip hw debug
    82471: 05/04/13: Re: How do I disable Microblaze on-chip hw debug
    82784: 05/04/18: debugging source code for PowerPC
    82864: 05/04/19: Re: EDK:input to microblaze
    84149: 05/05/13: PowerPC and application in external RAM
    84305: 05/05/17: Re: PowerPC and application in external RAM
    84613: 05/05/23: using less brams for powerpc code
    84732: 05/05/25: powerpc startup
    84757: 05/05/26: Re: powerpc startup
    84784: 05/05/27: Re: powerpc startup
    85038: 05/06/03: Re: powerpc startup
    85435: 05/06/09: execute ppc code from external ram
    85438: 05/06/09: Re: Mapping Dual Port Ram into Microblaze address space
    85502: 05/06/10: Re: execute ppc code from external ram
    85503: 05/06/10: Re: Building a MicroBlaze from scratch, unable to run.
    85637: 05/06/13: Re: linker script!!!
    89545: 05/09/19: Using two PowerPCs
    89847: 05/09/28: IPIF interface not fast enough
    89853: 05/09/28: Re: IPIF interface not fast enough
    98013: 06/03/03: Re: Device ID of GPIO
    98021: 06/03/03: bscan_virtex4 device
    98223: 06/03/07: Re: bscan_virtex4 device
    98228: 06/03/07: Re: bscan_virtex4 device
    105462: 06/07/24: chipscope opb monitor
    105510: 06/07/25: Re: chipscope opb monitor
    105513: 06/07/25: Re: chipscope opb monitor
    105525: 06/07/25: Re: version control of ISE+EDK projects with CVS and/or SVN
    109768: 06/10/05: Nios II interrupt
    109961: 06/10/09: Quartus II 6.0
    110017: 06/10/09: Re: Quartus II 6.0
    110020: 06/10/09: Re: EDK / ISE versionning and interoperability
    110051: 06/10/10: boundary scan
    110055: 06/10/10: Nios software IDE
    110099: 06/10/11: Re: Nios software IDE
    110102: 06/10/11: Re: Nios software IDE
    110129: 06/10/11: Re: Two instances of Microblaze ...
    110213: 06/10/12: Re: EDK speed optimisation
    110451: 06/10/16: User peripherals within a Nios system
    110586: 06/10/18: Re: New IP with EDK : how connect external NET ?
    110781: 06/10/23: Re: EDK - XPS 8.1i segmentation
    111220: 06/10/31: Nios 2 application running from external ram
    111291: 06/11/01: Re: Nios 2 application running from external ram
    111304: 06/11/01: Re: Nios 2 application running from external ram
    111653: 06/11/07: avalon tristate slave address
    115636: 07/02/15: using shared vhdl code in customer ipif block
    116144: 07/03/02: Re: How to connect an IP to OPB bus??
    140001: 09/04/23: Variable phase shift in a DCM_SP -> MAX_STEPS
    148242: 10/07/01: DMA operation to 64-bits PC platform
    148249: 10/07/02: Re: DMA operation to 64-bits PC platform
    148259: 10/07/02: Re: DMA operation to 64-bits PC platform
    148302: 10/07/06: Re: DMA operation to 64-bits PC platform
    148303: 10/07/06: Re: DMA operation to 64-bits PC platform
    148565: 10/08/02: DMA operation to 64-bits PC platform (continued)
    148571: 10/08/03: Re: DMA operation to 64-bits PC platform (continued)
    148644: 10/08/11: Re: DMA operation to 64-bits PC platform (continued)
    148645: 10/08/11: Re: DMA operation to 64-bits PC platform
Frank Vorstenbosch:
    39701: 02/02/16: Re: wild teen sex scenes and CPLDs
    39788: 02/02/19: Few pins but more gates
    40004: 02/02/24: Re: EPLD RULES AND FLEX RULES
    40717: 02/03/13: Re: digital video PLL
    40719: 02/03/13: Re: digital video PLL
    40877: 02/03/17: Re: just bought... -- wildly OT
Frank Wang:
    75158: 04/10/27: Newbie: Read from Compact Flash using System ACE
Frank Wirtz:
    30487: 01/04/10: Re: Why FPGA/CPLDs draw a lot current?
    43589: 02/05/24: Re: Building a relaxation oscillator with a Xilinx 9536XL
Frank Xie:
    5901: 97/03/25: Is there anyone interested in FPGA or CPLD?
    7412: 97/09/08: Re: Which FPGA ?
frank yuan (rogers):
    49718: 02/11/19: need Actel programmer adaptor
Frank Z.F Xie:
    26662: 00/10/24: How to reduce Tco?
    27023: 00/11/08: Anything wrong with Xilinx website?
    27440: 00/11/22: Free Z80 ip core
    27471: 00/11/23: How to reduce the Tco
Frank Zampa:
    41609: 02/04/03: Signals pollution.
    41614: 02/04/03: Re: Signals pollution.
    41634: 02/04/04: Re: Signals pollution.
    41894: 02/04/10: [OT] Implement buffers in CPLD.
    42074: 02/04/15: Configuring XIlinx XL Fpga with no XL PROM.
    42605: 02/04/29: High current I/O on SpartanXL
    56981: 03/06/20: Output signal problem.
Frank Zhifeng Yuan:
    45036: 02/07/10: DPLL
    45111: 02/07/12: Actel 3.3v to 5v
Frank, Frank:
    92265: 05/11/25: Speed of programming for xc18v04?
    92266: 05/11/25: Re: Speed of programming for xc18v04?
<frank.frankli@gmail.com>:
    104711: 06/07/04: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
<frank_logic@yahoo.com>:
    115793: 07/02/20: Re: Selecting device in Project Properties : no XC2V1000?
<frank_mckenney@mindspring.com>:
    24978: 00/08/23: Re: Non-disclosures in job interviews, Round One
<frank_xie@writeme.com>:
    5761: 97/03/13: How to count the total numbers of Product Term for Altera MaxPlusII compiler report?
    5762: 97/03/13: The Logic Level of design using Altera devices
<frankgerlach@gmail.com>:
    104341: 06/06/24: newbie wants to do VHDL on an FPGA
    104346: 06/06/25: Re: newbie wants to do VHDL on an FPGA
    104347: 06/06/25: Re: Newbie to FPGA
    104355: 06/06/25: Re: newbie wants to do VHDL on an FPGA
    104356: 06/06/25: Re: newbie wants to do VHDL on an FPGA
Frankie Chung:
    1844: 95/09/09: QuickLogic SpDE 5.0
Franklin:
    87437: 05/07/23: Re: parallel optic availability
    87604: 05/07/26: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
FrankV.:
    33172: 01/07/18: FPGA / TDM Opportunity
Franky Deley:
    8727: 98/01/22: Re: XC4000E CLB utilization
<frankzhangee@gmail.com>:
    123974: 07/09/08: Anyway to stop Altera Stratix II SignalTap data acquisition
<frannhagen@my-dejanews.com>:
    14842: 99/02/19: Re: multiple clock domain problem
Franz Hollerer:
    23837: 00/07/12: Boundary-Scan Tests with JTAG Technologies Tools
    23859: 00/07/13: Re: Boundary-Scan Tests with JTAG Technologies Tools
    23889: 00/07/14: Re: Boundary-Scan Tests with JTAG Technologies Tools
    24168: 00/07/28: JTAG Technologies Boundary-Scan Test
    26365: 00/10/13: VHDL synthesis with synopsys
    26488: 00/10/18: Q: Xilinx unified libraries and synthesis
    26669: 00/10/24: timing simulation with Xilinx and Fusion/SpeedWave
    26754: 00/10/27: Re: timing simulation with Xilinx and Fusion/SpeedWave
    26755: 00/10/27: Re: timing simulation with Xilinx and Fusion/SpeedWave
    27878: 00/12/13: Programming Altera and Xilinx FPGAs with JTAG
    53749: 03/03/21: EPXA1 Development Kit Getting Started
    53838: 03/03/25: Re: EPXA1 Development Kit Getting Started
    53839: 03/03/25: Altera EPXA1 Development Kit - problems with the GNUPro Insight Debugger
    53841: 03/03/25: Re: Altera EPXA1 Development Kit - problems with the GNUPro Insight
    53910: 03/03/27: Re: Altera EPXA1 Development Kit - problems with the GNUPro Insight
    54959: 03/04/23: Q: Altera EPXA1 Development Board getting started - linking sequence
    121502: 07/07/06: Xilinx ISE, EDK and some ground roules in software development
    121522: 07/07/06: Re: Xilinx ISE, EDK and some ground roules in software development
    122557: 07/07/31: Re: Xint64 ?
Franz Pucher:
    18141: 99/10/03: Re: Xilinx XC4005E
frapa:
    154188: 12/08/31: Unconnected Done pin Virtex 6
Frater:
    128102: 08/01/15: speed... CORDIC vs. pure arithmetic expression
    128108: 08/01/15: Re: speed... CORDIC vs. pure arithmetic expression
    128134: 08/01/16: Re: speed... CORDIC vs. pure arithmetic expression
    128137: 08/01/16: Re: speed... CORDIC vs. pure arithmetic expression
    128138: 08/01/16: Re: speed... CORDIC vs. pure arithmetic expression
fre:
    36158: 01/10/31: Implementing Filter
    40073: 02/02/26: Core generator2.1(FIR)
Fred:
    23522: 00/06/28: Re: Tech: looking for Allpro programming software
    34465: 01/08/26: Help needed: simulation OK, synthesis OK, but doesnt work :-<
    34505: 01/08/28: Re: Help needed: simulation OK, synthesis OK, but doesnt work :-<
    34506: 01/08/28: Re: download bitstream to FPGA
    62997: 03/11/12: Need to verify an ATA/ATAPI-6 device
    63431: 03/11/21: Xlilinx (xc2vp30-5fg676)
    63433: 03/11/21: New ASCII-figure
    63434: 03/11/21: Re: New ASCII-figure
    67636: 04/03/16: Re: Schematic Edition Tool : Suggestions
    76088: 04/11/24: SDRAM Concurrent auto precharge
    76239: 04/11/29: Re: SDRAM Concurrent auto precharge
    76428: 04/12/02: Re: SDRAM Concurrent auto precharge
    80485: 05/03/07: Cheap alternatives to Mach 210s
    80488: 05/03/07: Re: Cheap alternatives to Mach 210s
    80981: 05/03/15: Lattice ispLEVER
    81024: 05/03/16: Re: Lattice ispLEVER
    82476: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
    83889: 05/05/09: Altera: Maxplus rules!
    83942: 05/05/10: Re: Altera: Maxplus rules!
    83943: 05/05/10: Re: Altera: Maxplus rules!
    83944: 05/05/10: Re: Altera: Maxplus rules!
    83945: 05/05/10: Re: Altera: Maxplus rules!
    84091: 05/05/12: Re: 8051 IP core
    84256: 05/05/16: Re: 8051 IP core
    85173: 05/06/06: Pissed off with Xilinx - Spartan 3
    85223: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
    85224: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
    85247: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
    85248: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
    85253: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
    92044: 05/11/21: Sounds or other means to indicate end of compilation in Xilinx ISE
    92049: 05/11/21: Re: Sounds or other means to indicate end of compilation in Xilinx ISE
    92162: 05/11/23: Case expression?
    92168: 05/11/23: Re: Case expression?
    92169: 05/11/23: Re: Case expression?
    92179: 05/11/23: Re: Case expression?
    92399: 05/11/29: ISE question on whats a "X_LUT3"?
    92412: 05/11/29: Re: ISE question on whats a "X_LUT3"?
    94763: 06/01/17: Re: FIFO in SDRAM
    94778: 06/01/17: Re: FIFO in SDRAM
    99036: 06/03/19: Progress bar in ISE 8.1
    100926: 06/04/21: Video circle generator
    100992: 06/04/24: Re: Video circle generator
    101439: 06/05/01: Re: Question about the ip I developed
    101442: 06/05/01: Re: Question about the ip I developed
    101523: 06/05/02: Re: Question about the ip I developed
    104149: 06/06/20: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
    104154: 06/06/20: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
    104160: 06/06/20: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
    108457: 06/09/11: Re: VHDL or Verilog or SystemC?
    114009: 07/01/02: ISE Simulator radix question
    114014: 07/01/02: Re: ISE Simulator radix question
    114261: 07/01/09: Re: ISE Simulator radix question
    114262: 07/01/09: Re: ISE Simulator radix question
    114263: 07/01/09: PCI-Express TLP example
    114292: 07/01/11: Re: PCI-Express TLP example
    115193: 07/02/02: Re: PCI Express user group
    116091: 07/03/01: Re: PCI-E TS1s
    117109: 07/03/23: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
    120781: 07/06/16: EDK - Microblaze question
    120943: 07/06/20: Re: EDK - Microblaze question
    121642: 07/07/10: EDK and ecncrpted .bit, .nky, .mcs files
    122904: 07/08/10: EDK speed issue
    122928: 07/08/10: Re: EDK speed issue
    122930: 07/08/10: Re: EDK speed issue
    131995: 08/05/09: ISE 9.2 - how do I extract component/slice placements for locking
    132025: 08/05/10: Re: ISE 9.2 - how do I extract component/slice placements for locking down a design?
    132341: 08/05/22: Xilinx XCF Flash ROMs - does a datasheet for erase and programming
    132935: 08/06/11: Re: Trouble programming V4FX40
    134143: 08/07/28: Re: vhdl code for debouncing push button
    134181: 08/07/29: Re: vhdl code for debouncing push button
    134190: 08/07/30: Re: vhdl code for debouncing push button
    135371: 08/09/29: Sending UDP packets over Ethernet
    135375: 08/09/29: Re: Sending UDP packets over Ethernet
    135558: 08/10/08: Packet sniffer help
    135587: 08/10/09: Re: Packet sniffer help
    135741: 08/10/14: Literature on 100Base-TX request
    135818: 08/10/16: Re: Literature on 100Base-TX request
    135836: 08/10/17: Re: Literature on 100Base-TX request
    135842: 08/10/17: Re: Literature on 100Base-TX request
    135864: 08/10/18: Re: Literature on 100Base-TX request
    135914: 08/10/21: Re: Literature on 100Base-TX request
    135938: 08/10/22: Re: Literature on 100Base-TX request
    147052: 10/04/12: MPEG Reading material
    147135: 10/04/15: Re: MPEG Reading material
    147207: 10/04/19: Re: MPEG Reading material
    147210: 10/04/19: Re: MPEG Reading material
    148287: 10/07/05: Difference between DDR and DDR2
    148293: 10/07/05: Re: Difference between DDR and DDR2
    148307: 10/07/06: Re: Difference between DDR and DDR2
    151883: 11/05/30: Package constants (VHDL)
    151885: 11/05/30: Re: Package constants (VHDL)
fred:
    26887: 00/11/02: Re: OT: Xilinx T-Shirt
    27080: 00/11/10: Re: Non routable design
    27146: 00/11/13: Re: Non routable design
    27148: 00/11/13: Re: Spartan-II with 5V ISA bus
    27490: 00/11/24: Re: Clock Skew : Does Xilinx know what they're doing?
    27516: 00/11/27: Re: Clock Skew : Does Xilinx know what they're doing?
    27648: 00/12/01: Re: 150MHz LVDS vs. 75MHz TTL
    27649: 00/12/01: Re: 150MHz LVDS vs. 75MHz TTL
    27824: 00/12/11: Re: Altera free development tools
    28057: 00/12/20: Re: Question about Xilinx pins at high-frequency
    28065: 00/12/20: Re: Methods to speed up timings by hdl?
    31599: 01/05/31: Re: PAD to PAD Timing Constraints. (Xilinx)
    31911: 01/06/08: Re: Force tristate enable register into IOB
    32110: 01/06/14: Re: Force tristate enable register into IOB
    32898: 01/07/11: Re: Need to speed up VHDL accumulator on Xilinx
    34201: 01/08/16: Re: Internal clock skew when using DLL
    34326: 01/08/21: Re: Need help: CLKDLLE.v does not work in simulation.
    34932: 01/09/14: Re: Foundation 3.1i REINSTALLATION
    35586: 01/10/11: Re: Timing constraints for unrelated clocks?
    35712: 01/10/15: Re: Timing constraints for unrelated clocks?
    35727: 01/10/15: Re: Timing constraints for unrelated clocks?
    35963: 01/10/25: Re: How to make an implementable big counter?
    35964: 01/10/25: Re: How to make an implementable big counter?
    45979: 02/08/13: Re: "flip flop" and "register"
    47755: 02/10/03: Re: Xilinx Cordic Core and Square Root...help
    55776: 03/05/19: Re: a (PC) workstation for FPGA development
    63157: 03/11/17: Re: Active-HDL 6.1 pricing
    83688: 05/05/05: Re: Does this group allow JobPostings?
    84596: 05/05/22: Re: Looking for core that does a vector product
    86660: 05/07/03: Re: Foundation 3.1 in WinXP machine Problems!
    86821: 05/07/07: Re: SELV - power supply specification
    86845: 05/07/07: Re: SELV - power supply specification
    105670: 06/07/28: Re: OT (2nd try): do you get paid for your travel time?
Fred Abse:
    88028: 05/08/06: Re: System Engineering in the R/D World
    95343: 06/01/22: Re: OT:Shooting Ourselves in the Foot
Fred Bartoli:
    68444: 04/04/05: ATMEL support / Are they serious ?
    68455: 04/04/05: Re: ATMEL support / Are they serious ?
    76667: 04/12/08: Chained signal propagation pb.
    76872: 04/12/15: Is it me or quartus ?
    99820: 06/03/30: Re: deglitching a clock
    100005: 06/04/01: Re: deglitching a clock
    156222: 14/01/18: Re: Math is hard
    156461: 14/04/08: Re: on-chip bypass caps
    156462: 14/04/08: Re: on-chip bypass caps
Fred Bloggs:
    61563: 03/10/07: Re: How To: 3-input NAND gate using ACTEL ACT 1 logic module
    61583: 03/10/07: Re: How To: 3-input NAND gate using ACTEL ACT 1 logic module
    84929: 05/06/01: Re: need a book: Hilbert transform
    95131: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95141: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95145: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95229: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95231: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95242: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95323: 06/01/22: Re: OT:Shooting Ourselves in the Foot
    95330: 06/01/22: Re: OT:Shooting Ourselves in the Foot
    95335: 06/01/22: Re: OT:Shooting Ourselves in the Foot
    97489: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
    103467: 06/06/03: Re: Adding a USB interface to Linksys WRT54G wifi router
    115474: 07/02/12: Re: Building Coaxial transmission line on PCB?
    115479: 07/02/12: Re: Building Coaxial transmission line on PCB?
    118544: 07/04/29: Re: debounce state diagram FSM
    118876: 07/05/05: Re: debounce state diagram FSM
    118878: 07/05/05: Re: debounce state diagram FSM
Fred C:
    84357: 05/05/18: About back annotated simulations...
    84394: 05/05/18: Re: About back annotated simulations...
fred cezilly:
    20786: 00/02/22: Signal visualization debug
Fred Fierling:
    2864: 96/02/19: Verilog vs. VHDL comparison
    2894: 96/02/25: Re: Verilog vs. VHDL comparison
Fred Ganong:
    15145: 99/03/09: Xilinx Foundation Timing
    15161: 99/03/10: Re: Xilinx Foundation Timing
Fred Giorgi:
    4242: 96/10/03: Altera Checksums
    4267: 96/10/08: Re: Altera Checksums
Fred H:
    63793: 03/12/04: Need a few tips working with an Xilinx FPGA
    63796: 03/12/04: Re: Need a few tips working with an Xilinx FPGA
    63800: 03/12/04: Re: Need a few tips working with an Xilinx FPGA
    63805: 03/12/04: Using FPGA Editor to introduce PULLUP and PULLDOWN
Fred Hamilton:
    3829: 96/08/07: BIDIR/TRI-STATE busses in Altera AHDL
Fred Ma:
    69565: 04/05/14: Simple way to generate random netlists of ALU cells
    69588: 04/05/14: Re: Simple way to generate random netlists of ALU cells
    69601: 04/05/15: Re: Simple way to generate random netlists of ALU cells
    69602: 04/05/15: Re: Simple way to generate random netlists of ALU cells
    69609: 04/05/15: MCNC benchmarks (was: Simple way to generate random netlists of ALU
    69613: 04/05/15: Re: Simple way to generate random netlists of ALU cells
    69681: 04/05/18: Re: Simple way to generate random netlists of ALU cells
    69830: 04/05/21: Seeking Chameleon Systems white paper
    71152: 04/07/09: Info on FPGA routing algorithms?
    71172: 04/07/10: Re: Info on FPGA routing algorithms?
    71249: 04/07/13: Re: Info on FPGA routing algorithms?
    71250: 04/07/13: Re: Info on FPGA routing algorithms?
    71277: 04/07/13: Re: Info on FPGA routing algorithms?
Fred Marshall:
    20810: 00/02/22: Re: MRP systems
    87354: 05/07/21: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87422: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87436: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87438: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87439: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87468: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87532: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87535: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87603: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87916: 05/08/03: Re: System Engineering in the R/D World
    87997: 05/08/04: Re: System Engineering in the R/D World
    92592: 05/12/01: Re: Quick question, how do I supply +-5V?
    148816: 10/08/28: Re: Plotting sampled data in Matlab
    149735: 10/11/21: Re: [O.T.] Audio DAC as AWG (test source)?
Fred Moses:
    13775: 98/12/24: Re: Version 8 of Verilog FAQ released
Fred Rose:
    565: 95/01/05: Re: What's Up At ViewLogic?
Fred Schimmel:
    2467: 95/12/08: Re: CRC-32 implementation
    2471: 95/12/11: CRC-32 implementation
Fred SKalka:
    24443: 00/08/08: Re: Fast (> 100Mb) serial link to PC
Fred Skalka:
    24060: 00/07/25: Re: phase lock different frequencies
    24061: 00/07/25: Category : Fndtn 3.1 compatability
Fred U. Rosenberger:
    13858: 98/12/29: Re: 22V10 Metastability - help please
Fred Viles:
    56125: 03/05/29: Re: JTAG madness
    56172: 03/05/29: Re: JTAG madness
fred_best:
    23879: 00/07/13: Re: Anyone tried the Virtex dev. board from Avnet?
Frederic:
    116089: 07/03/01: looking for the source VHDL for Jpeg 2000
    116123: 07/03/01: Re: looking for the source VHDL for Jpeg 2000
Frederic Antonin:
    31728: 01/06/04: Re: Pentium 4 or AMD ?
    34163: 01/08/15: Major performance problem with Modelsim
frederic Bastenaire:
    51459: 03/01/14: Re: How to coerce a list of discrete signals to an array in VHDL
Frederic Bastenaire:
    50079: 02/11/30: ModelSim XE vcom 5.6a #ERROR: cannot read output
    50099: 02/12/02: Re: ModelSim XE vcom 5.6a #ERROR: cannot read output
    50333: 02/12/09: Re: How to assign pins in VHDL?
    51243: 03/01/08: Re: USB OPENCORE IP usage
    51274: 03/01/09: Re: USB OPENCORE IP usage
    51308: 03/01/10: Re: USB OPENCORE IP usage
    51345: 03/01/11: Re: USB OPENCORE IP usage
    51347: 03/01/11: Re: USB OPENCORE IP usage
    51446: 03/01/13: How to coerce a list of discrete signals to an array in VHDL
    51544: 03/01/16: Re: Student development board
    51807: 03/01/22: Conditional signal assignment
    51808: 03/01/22: Re: ISE 5.1 help
    52535: 03/02/12: Causing Modelsim to break using VHDL code
    52586: 03/02/14: Re: Causing Modelsim to break using VHDL code
    52611: 03/02/16: JTAG and SVF
    52634: 03/02/17: Re: PCMCIA + FPGA/CPLD
    52667: 03/02/18: Communicating with a configured FPGA through the JTAG interface
    52763: 03/02/20: Re: Communicating with a configured FPGA through the JTAG interface
    52927: 03/02/26: New release of Xilinx ISE tools (5.2)
    54987: 03/04/23: Re: How to configure USER1 and USER2 of JTAG on Xilinx Virtex2!!
Frederic Darre:
    30206: 01/03/28: Please help a poor student with virtexe
    30336: 01/04/03: Re: Please help a poor student with virtexe
    31361: 01/05/21: Need A little prog?
    31364: 01/05/21: Re: Need A little prog?
    31369: 01/05/21: Re: Interfacing with serial port
    31561: 01/05/30: Help with vhd
    31601: 01/05/31: Re: Help with vhd
    31603: 01/05/31: Re: Help with vhd
    31648: 01/06/01: Re: Help with vhd
Frederic GOFFIN:
    3833: 96/08/08: Xact 6.0.1: memgen
Frederic Gruau:
    4295: 96/10/11: Next conf
Frederic Magniette:
    22097: 00/04/21: which pci board?
Frederic RIVOALLON:
    28140: 00/12/22: Re: Synplicity and multiple input IOB flops...how to specify which one
Frederic Rivoallon:
    37802: 01/12/20: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
    55172: 03/04/29: Re: Virtex-II DCM frequency synthesizer
frederik:
    29840: 01/03/13: Re: Questions about Xilinx Web Pack ISE
    31362: 01/05/21: Re: Need A little prog?
FredInAShed:
    36584: 01/11/12: Re: Interleaver and Reed Solomon Encoder example
Fredj Rouatbi:
    13199: 98/11/19: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
    13059: 98/11/13: Xilinx Core generator
    13060: 98/11/13: Re: hard macros design flow for XILINX Foundation Express
    13063: 98/11/13: Re: Xilinx Core generator
    13227: 98/11/20: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
    13254: 98/11/22: Re: XNF issue
    13253: 98/11/22: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
    13257: 98/11/22: Re: Combining busses Xilinx
    13258: 98/11/22: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
    32710: 01/07/05: Arc Tangente and Square Root algorithms
Fredk:
    66237: 04/02/15: 74ls193 in coolrunner
    66247: 04/02/16: Re: 74ls193 in coolrunner
    66287: 04/02/16: Re: 74ls193 in coolrunner
    66299: 04/02/16: Re: 74ls193 in coolrunner
Fredrik:
    48969: 02/10/28: Re: High Performance FPGA's - Xilinx and ??????
    48970: 02/10/28: Re: Porting from Xilinx to Altera?
    49026: 02/10/29: Re: Porting from Xilinx to Altera?
    49561: 02/11/15: Re: configuration with Altera EPC16?
    51262: 03/01/09: Re: can maxplusII use the result produced by other synthesize tool ,for axample synplify ?
    52151: 03/02/03: Re: Ip core pricing info
    52729: 03/02/20: Re: Should I choose Xilink or Altera for a small project
    53210: 03/03/06: Re: Multi cpu Nios processor through SoPC Builder
    53211: 03/03/06: Re: questions about RS232 IN Altera FPGA
    54399: 03/04/10: Re: Cheap(er) FPGA configuration?
    54703: 03/04/16: Re: NIOS 3.0 Fmax and other Issues
    54743: 03/04/17: Re: spartan2e vs cyclone
    55043: 03/04/25: Re: Low pin count SOC
    55834: 03/05/21: Re: Using GERMS monitor with NIOS CPU on non-Altera board
    55911: 03/05/23: Re: Using GERMS monitor with NIOS CPU on non-Altera board
    56744: 03/06/13: Re: FPGA CPU Development Board
    57404: 03/06/30: Re: Can Altera NIOS processor be syntheized on a Flex FPGA
    57479: 03/07/01: Re: Can Altera NIOS processor be syntheized on a Flex FPGA
    61922: 03/10/15: Re: ByteBlasterII
    63799: 03/12/04: Re: increase NIOS processor clock speed on APEX20K200E device
    65652: 04/02/04: Re: Stratix II NIOS sizes ?
    65705: 04/02/05: Re: Stratix II NIOS sizes ?
    65945: 04/02/10: Re: [Altera/Quartus] Tools to regenerate block schematics from .vhd files
    67457: 04/03/11: Re: Altera, Cyclone: pin not connected warning
    67586: 04/03/15: Re: Altera, Cyclone: pin not connected warning
    70900: 04/07/01: Re: Compact FPGA Board?
    71023: 04/07/05: Re: new Lattice FPGAs vs Cyclone and SpartanIII
    71058: 04/07/07: Re: new Lattice FPGAs vs Cyclone and SpartanIII
    97027: 06/02/15: Re: Altera RoHS Irony
    100832: 06/04/18: Re: FPGA availability & distribution options.
    101194: 06/04/27: Re: FPGA + MAC board?
    105262: 06/07/19: Re: Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
    123250: 07/08/21: Re: Spartan-3A DSP vs. Cyclone III Power-wise
    123494: 07/08/29: Re: altera's USB byteblaster cable: anyone has the mindford one?
    132301: 08/05/20: Re: Stratix IV Announced
Fredrik Andersson:
    69048: 04/04/26: Re: SDRAM's dqm
Fredrik Theander:
    30278: 01/03/30: Anadigms FPAA
    30340: 01/04/03: Analog programable devices
    30583: 01/04/18: testing
<fredrik_he_lang@hotmail.com>:
    136856: 08/12/09: Re: Can DDR2 work with Xilinx Virtex-5 at 400 MHz?
    136857: 08/12/09: Re: Can DDR2 work with Xilinx Virtex-5 at 400 MHz?
FredrikH:
    137874: 09/02/01: MPEG-1 Layer 3 (Mp3) Encoder and Decoder
    137925: 09/02/02: Re: MPEG-1 Layer 3 (Mp3) Encoder and Decoder
    138199: 09/02/09: Re: MPEG-1 Layer 3 (Mp3) Encoder and Decoder
    138215: 09/02/09: Re: MPEG-1 Layer 3 (Mp3) Encoder and Decoder
Fredxx:
    140569: 09/05/18: OT: Google vs Yahoo
    140652: 09/05/21: Re: Are all these claims in VHDL correct?
    140654: 09/05/21: Re: Are all these claims in VHDL correct?
    140696: 09/05/22: Re: ISIM and CONV_INTEGER warnings
    140870: 09/05/28: Re: Old School Altera MAX 7000
    140908: 09/05/29: Re: phase locking a slow (2Mhz) signal.
    140942: 09/05/30: Re: patent free ARM cores
    141144: 09/06/08: Re: Xilinx Block RAM Sim
    141425: 09/06/24: Re: True dual-port RAM in VHDL: XST question
    141427: 09/06/24: Re: True dual-port RAM in VHDL: XST question
    141429: 09/06/24: Re: True dual-port RAM in VHDL: XST question
    141432: 09/06/24: Re: True dual-port RAM in VHDL: XST question
    141436: 09/06/24: Re: True dual-port RAM in VHDL: XST question
    141437: 09/06/24: Re: True dual-port RAM in VHDL: XST question
    141451: 09/06/24: Re: True dual-port RAM in VHDL: XST question
    141457: 09/06/24: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141514: 09/06/26: Re: True dual-port RAM in VHDL: XST question
    141564: 09/06/28: Re: True dual-port RAM in VHDL: XST question
    141576: 09/06/28: Re: True dual-port RAM in VHDL: XST question
    141993: 09/07/21: Re: Strange FPGA behavior
    142002: 09/07/21: Re: Strange FPGA behavior
    142360: 09/08/06: Re: What would be the best method to terminate GTX_CLK signal in Gigabit Ethernet PHY
    142974: 09/09/11: Re: Behavior of crystal oscillator?
    147006: 10/04/09: ISE Timing Constraints
    147014: 10/04/09: Re: ISE Timing Constraints
    147041: 10/04/11: Re: ISE Timing Constraints
    147601: 10/05/06: Re: Xilinx project failed timing constraints
    147829: 10/05/26: Re: Software bloat (Larkin was right)
    147854: 10/05/27: Re: Software bloat (Larkin was right)
    147857: 10/05/27: Re: crc16 with 16 bit inputs
    148629: 10/08/10: Instantiating non-global clock buffers (Xilinx ISE)
    148631: 10/08/10: Re: Instantiating non-global clock buffers (Xilinx ISE)
    148638: 10/08/10: Re: Instantiating non-global clock buffers (Xilinx ISE)
    148715: 10/08/18: CE compliance testing
    148747: 10/08/19: Re: CE compliance testing
    148748: 10/08/19: Re: CE compliance testing
    148749: 10/08/19: Re: CE compliance testing
    148755: 10/08/19: Re: CE compliance testing
    148756: 10/08/19: Re: CE compliance testing
    149339: 10/10/17: Re: Combined Microprocessor and FPGA
    149361: 10/10/18: Re: Combined Microprocessor and FPGA
    149432: 10/10/25: Re: 0x80000000 Integer not supported??
    149578: 10/11/07: Re: Statemachine debugging with Chipscope
    150120: 10/12/15: Re: spartan 3 xc3s4000 JTAG pins not pulled up
    150265: 11/01/07: Re: Cheap Altera dev board with LVDS-compatible connector?
free quick reference cards for linux:
Free Spirit:
    19281: 99/12/10: Re: JTAG programming problem with multiple Altera MAX7000A devices
    19587: 00/01/03: Re: PCI slot 3.3V pins.
    20038: 00/01/25: Re: How to access standard sdram ?
<"FREE"free@free-email9.com>:
    7590: 97/09/24: ¤ ¤ ¤ F R E E V A C A T I O N S !!! ¤ ¤ ¤
<freeagent.20.oracle@xoxy.net>:
    120530: 07/06/08: Newbie Question: Using Includes in Verilog
    120533: 07/06/08: Re: Newbie Question: Using Includes in Verilog
    131666: 08/04/28: How to embed time and date in Xilinx FPGA?
freechip:
    97515: 06/02/23: High Speed Development Board
    97581: 06/02/24: Re: High Speed Development Board
    97590: 06/02/24: Need a SPI 4?
    97603: 06/02/24: implement IP TCP Layer in FPGA
    97605: 06/02/24: System Packet Interface?
    100948: 06/04/21: CAM, TCAM in Stratix
    101005: 06/04/24: Re: CAM, TCAM in Stratix
    101008: 06/04/24: Re: CAM, TCAM in Stratix
    101076: 06/04/25: Re: CAM, TCAM in Stratix
freeplatypus:
    120807: 07/06/17: Graduate/Junior FPGA Designer concerns
    120919: 07/06/20: Re: Graduate/Junior FPGA Designer concerns
FreeRTOS.org:
    113701: 06/12/19: Re: interrupt handling using microblaze with XPS
    124735: 07/10/02: Re: Basic VHDL Development kit
    131686: 08/04/29: Virtex4 PPC405 - FPU problem
freespace@gmail.com:
    136803: 08/12/05: Invalid devices when initialising scan chain with Nexys2
    136805: 08/12/05: Re: Invalid devices when initialising scan chain with Nexys2
    136806: 08/12/05: Re: Invalid devices when initialising scan chain with Nexys2
    136810: 08/12/06: Re: Invalid devices when initialising scan chain with Nexys2
    136830: 08/12/08: Re: Invalid devices when initialising scan chain with Nexys2
    136831: 08/12/08: Re: Invalid devices when initialising scan chain with Nexys2
    137976: 09/02/03: Re: Digilent Nexys 2 Issue
    138005: 09/02/03: Re: Digilent Nexys 2 Issue
    138006: 09/02/03: Re: Invalid devices when initialising scan chain with Nexys2
FreeWheel:
    135610: 08/10/09: Lattice vs Altera (Mico32 / NIOS)....or?
Freiberger Wolfgang:
    11145: 98/07/21: EEPROM <> XC1700 ?
<Fremont>:
    14744: 99/02/14: EEProm erasing?
frendy:
    67510: 04/03/12: ML300 : Write to ddr
freny:
    37886: 01/12/23: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
    37887: 01/12/23: no net attached to set reset cell
    37911: 01/12/24: Re: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
    37927: 01/12/25: Re: Where could I get a signal waveform editor?
    37992: 01/12/28: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
    41760: 02/04/06: Re: How to probe internal signals from Xilinx netlist?
    52103: 03/01/31: STATE PROBLEM!
Freund Laurent:
    17573: 99/08/11: Java and XS40 board
Frey:
    53860: 03/03/25: Problems with Altera Max Plus II software
    53882: 03/03/26: Re: Problems with Altera Max Plus II software
Fridolin:
    88099: 05/08/09: Linux driver for Embedded TEMAC in Virtex4
    88112: 05/08/09: Re: Linux driver for Embedded TEMAC in Virtex4
    141884: 09/07/15: Re: Problem with System ACE, can't get it to work with partitioned
    141990: 09/07/21: Re: Problem with System ACE, can't get it to work with partitioned
    141991: 09/07/21: Re: Problem with System ACE, can't get it to work with partitioned
Friedhelm Rünz:
    17356: 99/07/22: Workstation with Synopsys license server
Friedrich Beckmann:
    4979: 97/01/08: Re: ASICs Vs. FPGA in Safety Critical Apps.
Friedrich Kiesel:
    113661: 06/12/19: Integrating Atera =?UTF-8?B?4oCcRkZUIE1lZ2FDb3JlIEZ1bmN0aW9u4oCd?=
friedt jean-michel:
    29469: 01/02/22: fpga from linux/hc11
Fristot V.:
    9938: 98/04/15: MAXPLUS II ver7.1 & EPM 7128LC84,7160LC84
Frithiof Andreas Jensen:
    95422: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95561: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    107694: 06/08/31: Re: Performance Appraisals
    107787: 06/09/01: Re: Performance Appraisals
    108329: 06/09/08: Re: Performance Appraisals
    108332: 06/09/08: Re: Performance Appraisals
    115108: 07/01/31: Re: 1 Gbps - state of the art?
Frithiof Jensen:
    3323: 96/05/13: Re: Anyone use Orcad PLD tools ?
Frits Wester:
    8912: 98/02/06: Simple questions; please answer
Fritz:
    51799: 03/01/22: Re: Xilinx Foundation and ISE compatibility
    52936: 03/02/26: Re: FPGA arch.
    54706: 03/04/16: Re: XST and Makefile
frka:
    109407: 06/09/26: LCD(STN) controller
<frle@hrz.tu-chemnitz.de>:
    70979: 04/07/03: MAP: what are route-through look up tables
Frode Undseth:
    33459: 01/07/27: Too low output voltage on Altera 7000S??
Frode Vatvedt Fjeld:
    29440: 01/02/21: Clocks
    29445: 01/02/21: Re: Clocks
    29940: 01/03/19: video coding
    30563: 01/04/17: compression
    30589: 01/04/18: Re: compression
    30618: 01/04/19: Re: compression
Froilan P Montenegro:
    13393: 98/11/30: Re: Will XILINX survive?
From Sweden:
    132288: 08/05/20: How do I optimize filter coefficient bit length and signal bit length?
From_ASIC_2_FPGA:
    117652: 07/04/05: Transition from ASIC to FPGA
    117667: 07/04/06: Re: Transition from ASIC to FPGA
    117678: 07/04/06: Re: Transition from ASIC to FPGA
    117681: 07/04/06: Re: Transition from ASIC to FPGA
    117686: 07/04/06: Re: Transition from ASIC to FPGA
    117687: 07/04/06: Re: Transition from ASIC to FPGA
    117690: 07/04/06: Re: Transition from ASIC to FPGA
from_faa:
    146926: 10/04/02: Re: Xilinx XPS crash on Linux
<frouatbi@my-deja.com>:
    28859: 01/01/26: Re: CORDIC ALGORITHM
    28999: 01/02/01: It's time to make a little dance
    29075: 01/02/05: who wants to work in France ????
<frouatbi@my-dejanews.com>:
    16231: 99/05/11: Virtual fabs ...
frozen001:
    150515: 11/01/25: tft lcd with xilinx fpga
    150525: 11/01/25: Re: Zero Padding Circuit Design
    150526: 11/01/25: Re: Zero Padding Circuit Design
<fsdgsdf@spone.com>:
    110789: 06/10/23: Re: Spartan 3 Configuration Questions
    110805: 06/10/23: Re: Spartan 3 Configuration Questions
    118206: 07/04/19: Spartan 3 IOSTANDARD vs VCCO
    118226: 07/04/20: Re: Spartan 3 IOSTANDARD vs VCCO
FSI HUNTER:
    2535: 95/12/28: JOB> Sr. Digital Design Engineer
    2623: 96/01/12: JOB- Linecard FPGA/ASIC Designer
    2624: 96/01/12: CA-ATM/MUX Linecard FPGA/ASIC Designer
fskalka:
    71110: 04/07/08: programming to simulatin
fslearner:
    103993: 06/06/16: Floppy to FPGA?
    104071: 06/06/18: Re: Floppy to FPGA?
FT/KD Patrik Eriksson:
    5872: 97/03/21: Problem loading XC4010E with XCHECKER!
ftls1@uaf.edu:
    69822: 04/05/20: FREQUENCY DOUBOULER BY MAX PLUS......
    69897: 04/05/23: Re: FREQUENCY DOUBOULER BY MAX PLUS......
<ftorg@hotmail.com>:
    9005: 98/02/13: Development Board for ARM/FPGA
Fu-Chiung Cheng:
    775: 95/02/27: Questions of implementing asynchronous circuits using FPGAs.
    1416: 95/06/19: VHDL synthesis in ViewLogic.
    2154: 95/10/20: My own hard macro in VHDL?
Fuchs Gottfried:
    70852: 04/06/30: FPGA with fully asynchronous RAM
    70889: 04/07/01: Re: FPGA with fully asynchronous RAM
<fujiki@elf.coara.or.jp>:
    45892: 02/08/09: ia32 compatible IP core
Full Name:
    24436: 00/08/08: Re: Circuit Drawing
<fulvs@my-deja.com>:
    21746: 00/03/30: What's so good about antifuse???
funkrhythm:
    108461: 06/09/11: Re: Trying to get plb_temac working
    108615: 06/09/13: Re: Trying to get plb_temac working
    109267: 06/09/22: Re: MV4.0.1 and Avnet Mini-Module
    109510: 06/09/27: Re: Trying to get plb_temac working
    110243: 06/10/12: Re: Trying to get plb_temac working
    111965: 06/11/13: Re: opb_ddr
    112133: 06/11/16: Re: Compiling Linux Kernel for ML405
    112203: 06/11/17: Re: Compiling Linux Kernel for ML405
funky jim:
    20035: 00/01/24: actel desktop uniinstall?
    20258: 00/02/02: Can hobbyist buy altera in uk?
    20259: 00/02/02: Re: Foundation
    20260: 00/02/02: Re: part time
    20287: 00/02/04: Re: Can hobbyist buy altera in uk?
    20602: 00/02/16: synopsys, vhdl, verilog specs free?
Funstore:
    7397: 97/09/06: FREE PICS THROUGH E-MAIL
furia:
    138778: 09/03/10: Re: Finding aligned clock transitions with state machine
    143779: 09/10/25: Re: Teammates, interested?
<furia1024@news.secom.com.pl>:
    45867: 02/08/08: Modelsim in ISE pack
Furio Pettarin:
    3447: 96/05/31: Xilinx - OrCAD users
    3462: 96/06/03: Re: Xilinx - OrCAD OHDL language
fuseda:
    4017: 96/09/03: XACT STEP 6.0.1 SETUP PROBLEM
Future Intergrated Chips:
    181: 94/09/14: Need General Ptr's on FPGA's
-*Future-Net*-:
    6482: 97/05/27: FreeNetAccessWorldwide
futurebots:
    27951: 00/12/16: WTB: SAB82258, or R82258 in a PLCC package or PGA package
<futzy.r@gmail.com>:
    118681: 07/05/02: How to Black Box my IP using Quartus II
    119709: 07/05/24: How can I perform Boundary Scan Testing on Altera Cyclone II FPGAs using JTAG?
    119937: 07/05/29: Re: How can I perform Boundary Scan Testing on Altera Cyclone II FPGAs using JTAG?
    125602: 07/10/30: Re: builing a SPI interface in vhdl
Fuzesi Arnold:
    18304: 99/10/13: Re: ISP-Cable again
    20800: 00/02/23: Xchecker schematic?
    20858: 00/02/24: Re: Xchecker schematic?
    20799: 00/02/23: Re: Lattice Download Cable
    30387: 01/04/05: URGENT: Using SpartanII DLL to multiply clock freq
<fuzzyyt@my-deja.com>:
    18962: 99/11/23: Re: [Q] End-goal: porting ISA design to PCI. Which PLD to learn?
    18963: 99/11/23: Re: VHDL vs. schematic entry
fvnktion:
    149683: 10/11/17: fpga quickstart - best learning resource recommendations
<fwallac@nswc.navy.mil>:
    10768: 98/06/17: speed of xilinx par tools
fwj_733:
    76866: 04/12/14: algorithm: square operation
    76887: 04/12/15: Re: algorithm: square operation
    76928: 04/12/15: Re: algorithm: square operation
    77129: 04/12/24: Timing simulation : BRAM simulation proble
FyberOptic:
    135013: 08/09/10: WinCupl Problem(s)


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