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Messages from 105650

Article: 105650
Subject: Re: Guided MAP/PAR in ISE
From: "Eric Crabill" <eric.crabill@xilinx.com>
Date: Thu, 27 Jul 2006 16:49:20 -0700
Links: << >>  << T >>  << A >>
Hello Mikhail,

> I can't believe you need webcases for this.

Filing a webcase is one way to make sure the issue is recorded, so that
action may be taken on it.  There are, of course, other avenues; FAEs,
distributors, or direct contact with Xilinx employees.  However, in all
routes, the end result is the filing of a software change request.  These
are prioritized and dispatched to developers.  I'm sure this is standard
practice for people working on large systems with many software developers,
such as the ISE tool set.

I'm sorry to hear you have experienced some trouble.  Certainly, it is never
our intent to frustrate customers -- the intent of my request was to help us
keep other customers from experiencing the same trouble by letting us know
about it, so that we may have the opportunity to correct it.

Eric



Article: 105651
Subject: Re: Guided MAP/PAR in ISE
From: Ray Andraka <ray@andraka.com>
Date: Thu, 27 Jul 2006 20:12:02 -0400
Links: << >>  << T >>  << A >>
Eric Crabill wrote:

> Hello Mikhail,
> 
> 
>>I can't believe you need webcases for this.
> 
> 
> Filing a webcase is one way to make sure the issue is recorded, so that
> action may be taken on it.  There are, of course, other avenues; FAEs,
> distributors, or direct contact with Xilinx employees.  However, in all
> routes, the end result is the filing of a software change request.  These
> are prioritized and dispatched to developers.  I'm sure this is standard
> practice for people working on large systems with many software developers,
> such as the ISE tool set.
> 
> I'm sorry to hear you have experienced some trouble.  Certainly, it is never
> our intent to frustrate customers -- the intent of my request was to help us
> keep other customers from experiencing the same trouble by letting us know
> about it, so that we may have the opportunity to correct it.
> 
> Eric
> 
> 


Eric,

I also wait until I've debugged an issue as far as I can before filing a 
case.  More often than not, I'm asked to submit a test case that shows 
the problem.  Most of the time, it means preparing a test case and then 
convincing the hotline engineer that there is a problem.  I've had runs 
in the past where fully 1/3rd of my time over a month is spent 
developing and testing a test case for someone on the hotline that is 
either too lazy or not bright enough to write his own test case once I 
describe the issue.  It is frustrating, and frankly many times it is 
more effort than it is worth.

Article: 105652
Subject: Re: Hardware book like "Code Complete"?
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 27 Jul 2006 17:36:42 -0700
Links: << >>  << T >>  << A >>
Hi Andy,
I would like to ask a question:
> process (clk) is
> begin
>   if rising_edge(clk) then
>     var := (var - 1) mod var_limit;
>     out1 <= var = 0; -- registered comparison of combinatorial var
> (i.e. var - 1) with 0
>   end if;
>   out2 <= var = 0; -- combinatorial comparison of registered var with 0
> end process;
>
In the following statement:
  var := (var - 1) mod var_limit;
var is not assigned any value before it is used. var_limit is a
constant, of course.
Anything is wrong?

Weng

Andy wrote:
> Yes, but...
>
> Assuming the signals that those concurrent assignments depend on are
> driven from clocked processes, they do not update until after the
> clock, which means they are the registered (delayed) values.
>
> Also, see below:
>
> process (clk) is
> begin
>   if rising_edge(clk) then
>     var := (var - 1) mod var_limit;
>     out1 <= var = 0; -- registered comparison of combinatorial var
> (i.e. var - 1) with 0
>   end if;
>   out2 <= var = 0; -- combinatorial comparison of registered var with 0
> end process;
>
> Note that both out1 and out2 have the same cycle-accurate behavior.
> Note also that if both out1 and out2 exist, Synplify will combine them
> and use out1 for both.
>
> Andy
>
> KJ wrote:
> > Andy wrote:
> > > With variables, you don't have to wait an extra clock in single process
> > > descriptions.
> > >
> > With concurrent signal assignments that are outside of the process you
> > don't have to wait an extra clock either.
> > 
> > KJ


Article: 105653
Subject: Re: Guided MAP/PAR in ISE
From: "johnp" <johnp3+nospam@probo.com>
Date: 27 Jul 2006 17:38:50 -0700
Links: << >>  << T >>  << A >>
Ray -

And then after you submit the problem with the test case, the
support person doesn't bother to look at it.

I submitted a web case recently complaining about XST (not)
using the output-enable flip flops in the IOB.  I created
a test case that showed the issue, submitted it, and then had
a Xilinx support person tell me she couldn't re-produce the problem.

I don't think she even tried my simple test code.

Web cases are very frustrating and I seldom get any reasonable
solution.  I now just submit them so they can be in the Xilinx
system so that their s/w engineers can at least know about
the problems.

John Providenza


Ray Andraka wrote:
> Eric Crabill wrote:
>
> > Hello Mikhail,
> >
> >
> >>I can't believe you need webcases for this.
> >
> >
> > Filing a webcase is one way to make sure the issue is recorded, so that
> > action may be taken on it.  There are, of course, other avenues; FAEs,
> > distributors, or direct contact with Xilinx employees.  However, in all
> > routes, the end result is the filing of a software change request.  These
> > are prioritized and dispatched to developers.  I'm sure this is standard
> > practice for people working on large systems with many software developers,
> > such as the ISE tool set.
> >
> > I'm sorry to hear you have experienced some trouble.  Certainly, it is never
> > our intent to frustrate customers -- the intent of my request was to help us
> > keep other customers from experiencing the same trouble by letting us know
> > about it, so that we may have the opportunity to correct it.
> >
> > Eric
> >
> >
>
>
> Eric,
>
> I also wait until I've debugged an issue as far as I can before filing a
> case.  More often than not, I'm asked to submit a test case that shows
> the problem.  Most of the time, it means preparing a test case and then
> convincing the hotline engineer that there is a problem.  I've had runs
> in the past where fully 1/3rd of my time over a month is spent
> developing and testing a test case for someone on the hotline that is
> either too lazy or not bright enough to write his own test case once I
> describe the issue.  It is frustrating, and frankly many times it is
> more effort than it is worth.


Article: 105654
Subject: Does MAC FIR filter need special care?
From: "Sophi" <joy.li@student.adelaide.edu.au>
Date: 27 Jul 2006 18:03:21 -0700
Links: << >>  << T >>  << A >>
Hi everyone,

I am currently trying to implement a polyphase decimation filter by
using core generator in ISE 7.1

The filter has been both implemented by using DA FIR and MAC. The DA
FIR filter is working as it supposes to be, but MAC doesn't. I can't
really see why.

All the inputs and control signals feeding into these filters are the
same. They are running in exactly the same environment. The only
difference between these two filters that I know is that the output of
DA FIR is 28 bits and the output of MAC is 29 bits.

My question is does the MAC filter requires special care compare with
DA FIR.

Please help me. Any information will be appreciated. 

Sophi


Article: 105655
Subject: Re: Wanted: CPU config register code generator
From: pmaupin@gmail.com
Date: 27 Jul 2006 18:17:59 -0700
Links: << >>  << T >>  << A >>

Paul Urbanus wrote:
> I would create a table of registers, where the following parameters can
> be specified for each register.
>
> REGISTER NAME
> WIDTH
> OFFSET FROM BASE ADDRESS
> ACCESS TYPE:  R, W, R/W
> INTERNAL CLOCK NAME (assume bus I/F is async to this clock)
> WRITE STROBE GEN (sync'd to INTERNAL clock)
> READ STROBE GEN (sync'd to INTERNAL clock)
>
> These register table would be the input to a code generator
> script/program which would output a VHDL file that has the bus interface
> on one side and the register in/out/sync signals on the back side.
>

I also did something like this fairly recently (but in Python, not
Perl).  Where I workd, we generated Verilog, C headers, C testcases,
Framemaker .mif and HTML from home-grown XML register specifications.
But if I were doing something like this now, I would first check out
this nifty fairly new spec:

http://www.spiritconsortium.org/

Some background info is available here:

http://www.eetimes.com/showArticle.jhtml?articleID=159906802

Regards,
Pat


Article: 105656
Subject: Re: Guided MAP/PAR in ISE
From: Ray Andraka <ray@andraka.com>
Date: Thu, 27 Jul 2006 21:32:47 -0400
Links: << >>  << T >>  << A >>
johnp wrote:

> Ray -
> 
> And then after you submit the problem with the test case, the
> support person doesn't bother to look at it.
> 
> I submitted a web case recently complaining about XST (not)
> using the output-enable flip flops in the IOB.  I created
> a test case that showed the issue, submitted it, and then had
> a Xilinx support person tell me she couldn't re-produce the problem.
> 
> I don't think she even tried my simple test code.
> 
> Web cases are very frustrating and I seldom get any reasonable
> solution.  I now just submit them so they can be in the Xilinx
> system so that their s/w engineers can at least know about
> the problems.
> 
> John Providenza
> 
>
True enough.  The solution is usually something to the effect of issuing 
a CR number and a statement that it will be fixed in the next release 
(and it often is not).  I've got floorplanner issues that have been 
around for several major releases.

Article: 105657
Subject: Re: OT (2nd try): do you get paid for your travel time?
From: Tim Wescott <tim@seemywebsite.com>
Date: Thu, 27 Jul 2006 19:48:21 -0700
Links: << >>  << T >>  << A >>
Dave Pollum wrote:

> I recently traveled to another company to try to debug the company's
> hardware that they were building for us.  The hardware consists of a
> CPU and a large CPLD, etc. I wrote all of the firmware code and much of
> the test code, and had identified hardware failures on earlier boards.
> Anyway, I didn't have to pay a thing for the airline flights, hotel, or
> rental car.  However, when I asked if I was getting paid for my time
> spent traveling (~ 12 hours in airports/airplanes). I was told that was
> not normally done.
> BTW I eventually did get my company to pay for my travel time, so I am
> content.  But, is paying for travel time standard practice or not?
> 
> -Dave P
> 
My standard contract has travel time written into it, and if a company 
contracts with their standard contract I put the travel time clause in. 
  When I was a salaried employee I just took the travel as being part of 
the job (but they never asked me to travel on weekends).

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html

Article: 105658
Subject: Re: OT (2nd try): do you get paid for your travel time?
From: "Anonymous" <someone@microsoft.com>
Date: Fri, 28 Jul 2006 02:53:23 GMT
Links: << >>  << T >>  << A >>

"Dave Pollum" <vze24h5m@verizon.net> wrote in message
news:1154031435.955245.100680@b28g2000cwb.googlegroups.com...
> I recently traveled to another company to try to debug the company's
> hardware that they were building for us.  The hardware consists of a
> CPU and a large CPLD, etc. I wrote all of the firmware code and much of
> the test code, and had identified hardware failures on earlier boards.
> Anyway, I didn't have to pay a thing for the airline flights, hotel, or
> rental car.  However, when I asked if I was getting paid for my time
> spent traveling (~ 12 hours in airports/airplanes). I was told that was
> not normally done.
> BTW I eventually did get my company to pay for my travel time, so I am
> content.  But, is paying for travel time standard practice or not?
>
> -Dave P
>

Personally, I would be annoyed if I hired you and you held me up for 12
hours travel time. (a) no regular employees get paid for the hour a day they
spend in traffic jams (b) I have no way of knowing how long it really took
you to travel and (c) I'm probably already dropping a boat load of money on
you. I would suggest you bump your rate or pad you work hour report until
you feel compensated rather than ask me to pay you a bunch of money for
sitting on an airplane watching a DVD.

Don't forget that regular employees already resent contractors to start with
(for several reasons) so I would keep my head down if I wanted to be hired
again the next time.

-Clark



Article: 105659
Subject: Re: Guided MAP/PAR in ISE
From: "mh" <moazzamhussain@gmail.com>
Date: 27 Jul 2006 21:14:45 -0700
Links: << >>  << T >>  << A >>
dear MM
using guide file might not save time but makes placement and routing is
replicated for the new design.

1---try to built incrementally and then see the results in terms of
synthesis time.
2-- use tool like PlanAhead with hierarchical design. Its menu (FILE-->
UPDATE NETLIST) and then running PAR on the design in ExploreAhead will
definitely reduce PAR time exponentially.

regards
MH







MM wrote:
> Hi all,
>
> I was wondering if anyone had succeded in saving time by using guided
> MAP/PAR. I personally find that every time I want to use it, even in the
> most obvious cases when 99.9% of design hasn't changed,  I then have to
> re-run everything from scratch anyway...
> 
> 
> Thanks,
> /Mikhail


Article: 105660
Subject: Re: OT (2nd try): do you get paid for your travel time?
From: "RobJ" <rob@abc.net>
Date: Fri, 28 Jul 2006 04:38:27 GMT
Links: << >>  << T >>  << A >>
"Anonymous" <someone@microsoft.com> wrote in message 
news:D_eyg.12448$4c7.3273@tornado.southeast.rr.com...
>
> Personally, I would be annoyed if I hired you and you held me up for 12
> hours travel time. (a) no regular employees get paid for the hour a day 
> they
> spend in traffic jams (b) I have no way of knowing how long it really took
> you to travel and (c) I'm probably already dropping a boat load of money 
> on
> you. I would suggest you bump your rate or pad you work hour report until
> you feel compensated rather than ask me to pay you a bunch of money for
> sitting on an airplane watching a DVD.
>
> Don't forget that regular employees already resent contractors to start 
> with
> (for several reasons) so I would keep my head down if I wanted to be hired
> again the next time.
>
> -Clark
>
I disagree completely. It would be naive of a hiring manager to expect a 
contractor's travel time to be a freebie. And it would be stupid and 
dishonest for a contractor to recoup unbilled travel time by padding rate or 
hours billed. Like any contract, everything should be out in the open and 
agreed upon up front in writing.

Rob 



Article: 105661
Subject: Re: IOBDELAY and DCM
From: "Bob" <nimby1_NEEDSPAM@earthlink.net>
Date: Fri, 28 Jul 2006 04:58:21 GMT
Links: << >>  << T >>  << A >>

"RobertP." <r_p_u_d_l_i_k@poczta.onet.pl> wrote in message 
news:eaaeon$ho3$1@atlantis.news.tpi.pl...
> Gabor wrote:
>> Also note that the clock to output timing when measured
>> from the clock input pin and not the internal global net can be quite
>> long, so meeting hold time may not be as much problem as you
>> might think from reading the IOB timing numbers in the data sheet.
>>
>
> Why clock to output would be longer than specified in the datasheet 
> (TICKOFDCM - pin-to-pin clock to output)?
> Also there is no Min TICKOFDCM specified - I found some info about how to 
> estimate it (25% of worst case, but some people think it is not 
> conservative enough).
>
> -- 
> Regards
> RobertP.
>

I have the same gripe, with Xilinx. They expect you to use a tool, rather 
than the datasheet, to predict if your design will work. This makes it very 
difficult for people like you and me.

I was under the impression, also, that the min clock-to-out was 25% of the 
max time. I was later told that it's the inverse -- that the min 
clock-to-out is 75% of the max.

It's my opinion that Xilinx should include worst-case numbers, for all I/O 
standards, in the datasheet along with a note that says something like "It's 
possible that the timing may be better than what is printed in the 
datasheet. For most accurate results please use one of our timing analyzer 
tools."

The squeaky wheel gets the grease, so I suggest you voice your concerns with 
Xilinx.

Bob 



Article: 105662
Subject: Re: Hardware book like "Code Complete"?
From: Christer Ericson <christer_ericson@NOTplayTHISstationBIT.sony.com>
Date: Fri, 28 Jul 2006 06:41:51 GMT
Links: << >>  << T >>  << A >>
In article <peyp8xmjgc51.fsf@PXPL8591.amr.corp.intel.com>, 
first.last@employer.domain says...
> > But if anyone writes a book like this it will fly off the shelves!
> 
> Care to estimate the size of the market?

I don't know about hardware books, but for a specialist
book 10,000 copies over the lifetime of the book is a
bestseller!

A first printing may be something like 1,000-2,500
books I believe.  Many (probably most?) don't make it
past a first printing.
 

> I.e. how much would the author expect to make, given typical publishing contracts?

About 15% in royalties.

 
> (I've long wanted to write such a book, but have trouble with the
> business case - i.e. persuading my wife.  And, of course, I cannot
> write it as an employee of Intel.)

There's no business in it.  For the great majority, writing
specialist books is a losing proposition; you'd make more
money flipping burgers during the time it would take you to
write the book.  You write a (specialist) book because you
have a burning need to write one.

The only way there's business in it is if the book is picked
up as a textbook at lots of universities around the world or
is on some universally interesting topic.

Knuth, Hennessy and Patterson, Foley et al, and McConnell
have probably made good money from their books, but they are
the exceptions.

-- 
Christer Ericson
http://realtimecollisiondetection.net/

Article: 105663
Subject: Re: EDK : *.bit and *.elf Files
From: Olli <Emperor_@gmx.de>
Date: Fri, 28 Jul 2006 00:06:15 -0700
Links: << >>  << T >>  << A >>
Hi 

      There is more than one FLASH memory >on ML403




I'm using the platform flash 32p

      create a bootloader application Yes I did it already





      while writing your main *.elf file into the Linear FLASH. Then you >need
      to update your bitstream with >the bootloader elf (this by default >will
      create download.bit file) and >then program the Platform FLASH >using
      Impact.




Yes I updated the bitstream with the bootloader and download the hardware with Impact. Thats why I asked the question, it doesn't work ;). I download the *.srec at an high offset and the bootloader was generated automaticly.

Is there an other option?

cu Olli

Article: 105664
Subject: Spartan3 5V PCI
From: "yy" <yy7d6@yahoo.com.ph>
Date: 28 Jul 2006 01:54:34 -0700
Links: << >>  << T >>  << A >>
Hi,
I have a Working Universal PCI Evaluation Kit (Spartan3) without any
Bus Switches/resistors etc. The package name is 'TruePCI', and it works
fine with a motherboard that have 5V slots. The bank VCCO of Spartan 3
is wired to +3.3V, many have said that bus switches are needed in order
to connect Spartan 3 to PCI? But then this board seems to work pretty
well, Any ideas? BTW, what i'm building is a specialized pci board.

Thanks.


Article: 105665
Subject: Re: Spartan3 5V PCI
From: "PeteS" <PeterSmith1954@googlemail.com>
Date: 28 Jul 2006 02:23:23 -0700
Links: << >>  << T >>  << A >>
yy wrote:
> Hi,
> I have a Working Universal PCI Evaluation Kit (Spartan3) without any
> Bus Switches/resistors etc. The package name is 'TruePCI', and it works
> fine with a motherboard that have 5V slots. The bank VCCO of Spartan 3
> is wired to +3.3V, many have said that bus switches are needed in order
> to connect Spartan 3 to PCI? But then this board seems to work pretty
> well, Any ideas? BTW, what i'm building is a specialized pci board.
>
> Thanks.

Bus switches may be necessary in a system that pushes the PCI spec to
it's limits. What you can get away with on an eval kit is not what you
can get away with if you are making something that is required to meet
the PCI 2.2. Spec.

Note very carefully that you can get away with a LOT at 5V that simply
won't work at 3.3V, and indeed vice versa. I had an 'improved' part
some years ago from Intel where it quit working in an existing design
at 3.3V. Apart from that, have you tried it with a unit that has 3.3V
slots (to match your VIO)? That's a completely different test than you
are doing.

You don't say what the board you are designing is: is it a drop-in PCI
board, or a self contained unit that has a PCI interface between some
units on it? If it's self contained, there are things you can get away
with as you don't have to interface to the outside world (been there,
done that).

Cheers

PeteS


Article: 105666
Subject: Re: Hardware book like "Code Complete"?
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 28 Jul 2006 03:09:44 -0700
Links: << >>  << T >>  << A >>
Hi Christer,
I bought Knuth's books and McConnell's Pentium story. But I don't know
Hennessy and Patterson. What are their popular books?

Thank you.

Weng


Article: 105667
Subject: Re: Spartan 3 clock to output tristate timing
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 28 Jul 2006 03:11:10 -0700
Links: << >>  << T >>  << A >>
I dug into the design and found that there are *NO* registers in the
path from the RD signal to the output tristate control.  So I was right
that either I am being deliberately misled or the guy is incompetent.

I also found that in the last week since I have been saying that they
need a timing spec on this path, it has appeared in the UCF file.
Surprise, surprise.

Now I just have to finish up my analysis and figure out what other
timing specs they are missing.  It is likely that none of the others
will be any real issue since they will be in the 10s of ns and even
without the timing constraint would be very unlikely to be any problem.


Thanks for the support.  I don't get that from any of the managers and
it can be difficult to work in a job that is so distasteful.  I will be
looking for something new around here very shortly.


Article: 105668
Subject: Re: Rocket IO as a high speed sampler
From: "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch>
Date: Fri, 28 Jul 2006 14:05:11 +0200
Links: << >>  << T >>  << A >>
Ah, these are excellent points - Thanks everyone =)

The original purpose was to measure the length of a pulse to some hundreds 
of picoseconds.  2GS was chosen as a starting point, but ultimately faster 
is better... So, perhaps naively I was hoping that the actual phase of 
sample versus source clock was unimportant, but now that you mention it I 
have to have a rethink....

Interesting.

Cheers guys.
Ben






"John_H" <johnhandwork@mail.com> wrote in message 
news:_39yg.6528$Oh1.4695@news01.roc.ny...
> Do you want a 2GS/s sampler of 2GB/s data or do you just want high 
> resolution of a lower speed signal?  I'm getting a minimum of 9 GS/s in a 
> Spartan3E for a 600 MB/s signal (the sample rate isn't set as much as 
> detected).  Depending on requirements, there are alternatives to RocketIO. 
> See also XAPP671
>
>  http://www.xilinx.com/bvdocs/appnotes/xapp671.pdf
>
>
> "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> 
> wrote in message news:eaampt$pvr$1@sunnews.cern.ch...
>> Hi everyone, (especially those Xilinx chaps) :-)
>>
>> I've been having an interesting debate with a colleague here, regarding 
>> Virtex 4 Rocket IO (and Virtex II for that matter).  The challenge is to 
>> make a really high speed signal sampler in the fabric of one of these 
>> FPGAs by using the Rocket IO in a custom manner. I'm talking some GS/s
>>
>> We figure using a local clock of 100M, should be mutiplied by 20 inside 
>> the rocket IO, giving 20 bits per 100M period that can be shuffled to get 
>> some indication of the input waveform. i.e. a 2G sampler.
>>
>> Ok, ignoring the hugely important fact that FPGA has to be able to 
>> process this, and that the PCB has to be well designed, and that the 
>> input signal might have some new frequency and electrical constraints, 
>> are there any pitfalls we've missed?  btw: the idea comes from an 
>> expansion Figure-7 of:
>> http://www.eetkorea.com/ARTICLES/2004JUN/2004JUN22_PLD_RFD_AN05.PDF
>>
>> Are there any potential flaws in these ideas anyone can see?
>>
>> Thanks in advance,
>> Ben
>>
>
> 



Article: 105669
Subject: Re: OT (2nd try): do you get paid for your travel time?
From: "Dave Pollum" <vze24h5m@verizon.net>
Date: 28 Jul 2006 05:09:01 -0700
Links: << >>  << T >>  << A >>
Mike Treseler wrote:
> Dave Pollum wrote:
>
> > BTW I eventually did get my company to pay for my travel time, so I am
> > content.  But, is paying for travel time standard practice or not?
>
> I normally pay everything on my own card
> and file an expense report to get a refund.
> Salary is the same in the cube or on a plane.
>
>          -- Mike Treseler

Mike;
I agree that "Salary is the same in the cube or on a plane."  However,
I am no longer a salaried employee.  In this case, the other company
was paying my employer _per hour_ for my time, so I felt justified in
asking to be paid while traveling vs. getting paid zero.
-Dave P


Article: 105670
Subject: Re: OT (2nd try): do you get paid for your travel time?
From: fred <not@for.mail>
Date: Fri, 28 Jul 2006 13:06:16 GMT
Links: << >>  << T >>  << A >>
In article <7xgyg.38327$uy3.27935@tornado.socal.rr.com>, RobJ
<rob@abc.net> writes
>"Anonymous" <someone@microsoft.com> wrote in message 
>news:D_eyg.12448$4c7.3273@tornado.southeast.rr.com...
>>
>> Personally, I would be annoyed if I hired you and you held me up for 12
>> hours travel time. (a) no regular employees get paid for the hour a day 
>> they
>> spend in traffic jams (b) I have no way of knowing how long it really took
>> you to travel and (c) I'm probably already dropping a boat load of money 
>> on
>> you. I would suggest you bump your rate or pad you work hour report until
>> you feel compensated rather than ask me to pay you a bunch of money for
>> sitting on an airplane watching a DVD.
>>
>> Don't forget that regular employees already resent contractors to start 
>> with
>> (for several reasons) so I would keep my head down if I wanted to be hired
>> again the next time.
>>
>> -Clark
>>
>I disagree completely. It would be naive of a hiring manager to expect a 
>contractor's travel time to be a freebie. And it would be stupid and 
>dishonest for a contractor to recoup unbilled travel time by padding rate or 
>hours billed. Like any contract, everything should be out in the open and 
>agreed upon up front in writing.
>
I agree and think that Austin's summary is a good one, as a contractor I
have always charged for any time during which I am not able to do 'my own
thing', that means all time spent physically travelling or waiting in airports
but not time when I am chilling in a hotel outside normal working hours. If I
was required to spend time in a hotel awaiting the client's pleasure while
they get their act together I would charge for time during normal working
hours. If they don't agree to that then the journey is not undertaken but it is
important to agree the rules up front.
-- 
fred
Plusnet - I hope you like vanilla

Article: 105671
Subject: 4VSX35 LOC placements?
From: "ba@jb.man.ac.uk" <ba@jb.man.ac.uk>
Date: 28 Jul 2006 06:09:51 -0700
Links: << >>  << T >>  << A >>
Hi,

How does one find the legal values where "things" can be placed? Is it
me
or is the Xilinx documentation distinctly lacking in explicit detail?

I have a design in which ldvs is used to output 32 data pairs, 2 clock
pairs and
2 other pairs  from a clock input pair at 512MHz. The input clock
passes thru an
IBUFDS, a BUFIO, a BUFR dividing by 4 to a BUFG which drives things in
the
fabric.  The 512MHz and 128MHz from the BUFIO and BUFR drive OSERDES
and a pair of ODDR for the clock outputs.

There are no problems at the place and route stage if nothing is
constrained
but then the pin placements are not good for pcb layout. It bombs if I
try to use
a constraint in the ucf file to place even the clock input in bank 10
in an initial
attempt to persuade it to place the lvds outputs in banks  6, 8 and 10.

Bank 10 is "adjacent" to banks 6 and 8, right?

The error message is that "clk128 cannot possibly be routed to
component
bufg_inst (placed in clock region 6) since it is too far away from
source  BUFR
(placed in clock region 7)". I would like to LOC the BUFR and even the
BUFIO
but where? The relationship between banks and regions and the general
lack
of detail is confusing me. Maybe I need to take a break. IDELAYCTRL
will also
need to be placed but where? I know there are 16 of them!

Thanks,
Bryan


Article: 105672
Subject: Re: 4VSX35 LOC placements?
From: "Jim Wu" <jimwu88NOOOSPAM@yahoo.com>
Date: 28 Jul 2006 07:03:45 -0700
Links: << >>  << T >>  << A >>
ADEPT will answer most (if not all) of your questions. Check it out at

http://home.comcast.net/~jimwu88/tools/adept/

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com


ba@jb.man.ac.uk wrote:
> Hi,
>
> How does one find the legal values where "things" can be placed? Is it
> me
> or is the Xilinx documentation distinctly lacking in explicit detail?
>
> I have a design in which ldvs is used to output 32 data pairs, 2 clock
> pairs and
> 2 other pairs  from a clock input pair at 512MHz. The input clock
> passes thru an
> IBUFDS, a BUFIO, a BUFR dividing by 4 to a BUFG which drives things in
> the
> fabric.  The 512MHz and 128MHz from the BUFIO and BUFR drive OSERDES
> and a pair of ODDR for the clock outputs.
>
> There are no problems at the place and route stage if nothing is
> constrained
> but then the pin placements are not good for pcb layout. It bombs if I
> try to use
> a constraint in the ucf file to place even the clock input in bank 10
> in an initial
> attempt to persuade it to place the lvds outputs in banks  6, 8 and 10.
>
> Bank 10 is "adjacent" to banks 6 and 8, right?
>
> The error message is that "clk128 cannot possibly be routed to
> component
> bufg_inst (placed in clock region 6) since it is too far away from
> source  BUFR
> (placed in clock region 7)". I would like to LOC the BUFR and even the
> BUFIO
> but where? The relationship between banks and regions and the general
> lack
> of detail is confusing me. Maybe I need to take a break. IDELAYCTRL
> will also
> need to be placed but where? I know there are 16 of them!
> 
> Thanks,
> Bryan


Article: 105673
Subject: Re: EDK : *.bit and *.elf Files
From: "MM" <mbmsv@yahoo.com>
Date: Fri, 28 Jul 2006 10:14:30 -0400
Links: << >>  << T >>  << A >>
> I'm using the platform flash 32p

This will be storing your bitstream combined with the bootloader only, the
main program will be stored in the linear flash.

> I download the *.srec at an high offset and the bootloader was generated
automaticly.

You don't need an offset, as the *.srec gets loaded to a different flash.
However, unless the offset is too big for the memory it shouldn't be a
problem (provided it was set when you generated the bootloader as well)...

/Mikhail



Article: 105674
Subject: Re: 4VSX35 LOC placements?
From: "ba@jb.man.ac.uk" <ba@jb.man.ac.uk>
Date: 28 Jul 2006 07:52:01 -0700
Links: << >>  << T >>  << A >>
Hi Jim,

Jim Wu wrote:
> ADEPT will answer most (if not all) of your questions. Check it out at

I would love to use it but I am running ISE 8.1.03i on
linux ( fedora core 4). If I can't get an answer, I will
install on Windows and try it.

Are Xilinx hiding the information so you can give
away the tool with the answers for free? How did
you get the knowledge?

Bryan




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