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Threads Starting Jun 2006

103384: 06/06/01: Alexander Werger: Virtex4 FX12 - maximum frequency for Picoblaze
    103385: 06/06/01: Francesco: Re: Virtex4 FX12 - maximum frequency for Picoblaze
    103388: 06/06/01: Falk Brunner: Re: Virtex4 FX12 - maximum frequency for Picoblaze
        103429: 06/06/01: c d saunter: Re: Virtex4 FX12 - maximum frequency for Picoblaze
    103394: 06/06/01: John Adair: Re: Virtex4 FX12 - maximum frequency for Picoblaze
103389: 06/06/01: vssumesh: Problem with Mig1.5 when used to generate ddr sdram controller
103390: 06/06/01: subint: DDR SDRAM controller
103392: 06/06/01: Jon Beniston: Xilinx MapLib:661 errors
103393: 06/06/01: Paul Lee: Re: RocketIO signal polarity swap
103397: 06/06/01: <zhangxun0501@gmail.com>: is anyone knew the new version of HWICAP "opb_hwicap_v1_00_c" for
    103398: 06/06/01: Antti: Re: is anyone knew the new version of HWICAP "opb_hwicap_v1_00_c" for
103400: 06/06/01: Sylvain Munaut <SomeOne@SomeDomain.com>: Xilinx constraining : differential clocks and other details
    103547: 06/06/05: Gabor: Re: Xilinx constraining : differential clocks and other details
103402: 06/06/01: Marco: timings
    103422: 06/06/01: Mike Treseler: Re: timings
    103425: 06/06/01: Peter Alfke: Re: timings
    103509: 06/06/04: Marco: Re: timings
    103532: 06/06/05: Peter Alfke: Re: timings
103403: 06/06/01: Joel: Using ChipScope with EDK flow?
    103409: 06/06/01: Ben Jones: Re: Using ChipScope with EDK flow?
        103418: 06/06/01: Peter Ryser: Re: Using ChipScope with EDK flow?
            103452: 06/06/02: =?ISO-8859-1?Q?G=F6ran_Bilski?=: Re: Using ChipScope with EDK flow?
    103416: 06/06/01: Joel: Re: Using ChipScope with EDK flow?
    103446: 06/06/02: <saumyajit_tech@yahoo.co.in>: Re: Using ChipScope with EDK flow?
103405: 06/06/01: Brandon: Driving two DCMs with BUFG?
    103461: 06/06/02: Brad Smallridge: Re: Driving two DCMs with BUFG?
    103507: 06/06/05: Zara: Re: Driving two DCMs with BUFG?
103406: 06/06/01: Jon: ModelSim: Different SimPrim libraries needed for different Xilinx families?
103407: 06/06/01: pinku: Ethernet Snooping in the FPGA
    103408: 06/06/01: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Ethernet Snooping in the FPGA
        103414: 06/06/01: Aurelian Lazarut: Re: Ethernet Snooping in the FPGA
            103420: 06/06/01: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Ethernet Snooping in the FPGA
                103424: 06/06/01: Mike Treseler: Re: Ethernet Snooping in the FPGA
103410: 06/06/01: ABC: rise/fall clock edge constraint
103412: 06/06/01: Jim: Using version control for Xilinx 8.1i ISE projects and source files
    103417: 06/06/01: motty: Re: Using version control for Xilinx 8.1i ISE projects and source files
    103426: 06/06/01: Duane Clark: Re: Using version control for Xilinx 8.1i ISE projects and source
    103444: 06/06/01: Jim: Re: Using version control for Xilinx 8.1i ISE projects and source files
103435: 06/06/01: <be.geek@gmail.com>: Building custom ASIC solutions
    103437: 06/06/02: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Building custom ASIC solutions
    103440: 06/06/01: <be.geek@gmail.com>: Re: Building custom ASIC solutions
    103441: 06/06/01: <be.geek@gmail.com>: Re: Building custom ASIC solutions
        103448: 06/06/02: Dave: Re: Building custom ASIC solutions
    103442: 06/06/01: Dave: Re: Building custom ASIC solutions
103436: 06/06/01: radarman: XIlinx 7.1i ISE problem with Spartan 3e design
    103438: 06/06/01: Andrew FPGA: Re: XIlinx 7.1i ISE problem with Spartan 3e design
    103443: 06/06/01: radarman: Re: XIlinx 7.1i ISE problem with Spartan 3e design
103439: 06/06/01: Fizzy: Delay or latency
    103445: 06/06/02: Bob: Re: Delay or latency
    103458: 06/06/02: Hemang Parekh: Re: Delay or latency
103447: 06/06/02: vssumesh: Simulating post par simulation model
    103449: 06/06/02: mk: Re: Simulating post par simulation model
    103450: 06/06/02: vssumesh: Re: Simulating post par simulation model
    103451: 06/06/02: vssumesh: Re: Simulating post par simulation model
    103454: 06/06/02: vssumesh: Re: Simulating post par simulation model
    103624: 06/06/06: vssumesh: Re: Simulating post par simulation model
103456: 06/06/02: John Adair: Free Tools
103457: 06/06/02: <the.gaffar@googlemail.com>: Changing the random seed in Xilinx tools
    103462: 06/06/02: Brandon Jasionowski: Re: Changing the random seed in Xilinx tools
    103546: 06/06/05: Gabor: Re: Changing the random seed in Xilinx tools
103463: 06/06/02: Felix Bertram: WebPack on Linux
    103464: 06/06/02: Josh Rosen: Re: WebPack on Linux
    103473: 06/06/03: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: WebPack on Linux
    103480: 06/06/03: Bob Smith: Re: WebPack on Linux
        103494: 06/06/04: Josh Rosen: Re: WebPack on Linux
            103500: 06/06/04: Felix Bertram: Re: WebPack on Linux
103465: 06/06/02: radarman: Problem with Xilinx ISE 7.1i core generator
    103497: 06/06/04: radarman: Re: Problem with Xilinx ISE 7.1i core generator
103466: 06/06/02: <be.geek@gmail.com>: Adding a USB interface to Linksys WRT54G wifi router
    103467: 06/06/03: Fred Bloggs: Re: Adding a USB interface to Linksys WRT54G wifi router
    103469: 06/06/02: David Kelly: Re: Adding a USB interface to Linksys WRT54G wifi router
    103470: 06/06/02: <ghelbig@lycos.com>: Re: Adding a USB interface to Linksys WRT54G wifi router
103468: 06/06/03: Rich Grise: Xilinx ISE 7.1i Tutorial: Test Bench road block
    103483: 06/06/03: Roland: Re: Xilinx ISE 7.1i Tutorial: Test Bench road block
        103545: 06/06/05: Rich Grise: Re: Xilinx ISE 7.1i Tutorial: Test Bench road block
103471: 06/06/03: Mich: Difference Logic Cells <=> Slices
    103477: 06/06/03: Peter Alfke: Re: Difference Logic Cells <=> Slices
    103478: 06/06/03: Austin Lesea: Re: Difference Logic Cells <=> Slices
103472: 06/06/03: mailmekaran: VHDL code For Floating point adder and Multiplier
    103481: 06/06/03: Rene Tschaggelar: Re: VHDL code For Floating point adder and Multiplier
    103485: 06/06/03: <ghelbig@lycos.com>: Re: VHDL code For Floating point adder and Multiplier
    103505: 06/06/04: Ray Andraka: Re: VHDL code For Floating point adder and Multiplier
103474: 06/06/03: Dave Farrance: FPGA board for USB experiments?
    103475: 06/06/03: Jim: Re: FPGA board for USB experiments?
        103491: 06/06/04: Dave Farrance: Re: FPGA board for USB experiments?
            103499: 06/06/04: Dave Farrance: Re: FPGA board for USB experiments?
                103503: 06/06/04: Dave Farrance: Re: FPGA board for USB experiments?
                    103504: 06/06/04: Uwe Bonnes: Re: FPGA board for USB experiments?
                        103519: 06/06/05: Dave Farrance: Re: FPGA board for USB experiments?
                            103616: 06/06/07: Rich Grise: Re: FPGA board for USB experiments?
                            103623: 06/06/07: Dave Farrance: Re: FPGA board for USB experiments?
                    103516: 06/06/05: Thorsten Trenz: Re: FPGA board for USB experiments?
                        103520: 06/06/05: Dave Farrance: Re: FPGA board for USB experiments?
                            103521: 06/06/05: Dave Farrance: Re: FPGA board for USB experiments?
                103512: 06/06/05: =?ISO-8859-15?Q?St=E9phane_Goujet?=: Re: FPGA board for USB experiments?
                    103513: 06/06/05: Antti Lukats: Re: FPGA board for USB experiments?
                        103515: 06/06/05: =?ISO-8859-15?Q?St=E9phane_Goujet?=: Re: FPGA board for USB experiments?
                    103562: 06/06/06: =?ISO-8859-15?Q?St=E9phane_Goujet?=: Re: FPGA board for USB experiments?
    103496: 06/06/04: Antti: Re: FPGA board for USB experiments?
    103502: 06/06/04: Antti: Re: FPGA board for USB experiments?
    103517: 06/06/05: Antti: Re: FPGA board for USB experiments?
    103518: 06/06/05: Antti: Re: FPGA board for USB experiments?
    103533: 06/06/05: John Adair: Re: FPGA board for USB experiments?
        103573: 06/06/06: Dave Farrance: Re: FPGA board for USB experiments?
            103583: 06/06/06: John Adair: Re: FPGA board for USB experiments?
        103712: 06/06/09: Dave Farrance: Re: FPGA board for USB experiments?
            103929: 06/06/15: Vhdl.eu: Re: FPGA board for USB experiments?
    103605: 06/06/06: <langwadt@ieee.org>: Re: FPGA board for USB experiments?
    103662: 06/06/07: <langwadt@ieee.org>: Re: FPGA board for USB experiments?
    105150: 06/07/14: <chris.felton@gmail.com>: Re: FPGA board for USB experiments?
103479: 06/06/03: pablo: partial reconfiguration protocol on Spartan II and self reconfiguration
103484: 06/06/03: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Documentation miss? (sp3/xilinx)
    103493: 06/06/04: John_H: Re: Documentation miss? (sp3/xilinx)
        103495: 06/06/04: John_H: Re: Documentation miss? (sp3/xilinx)
    103536: 06/06/05: Marc A. Baker: Re: Documentation miss? (sp3/xilinx)
103488: 06/06/04: nezhate: Multi place and route
    103489: 06/06/04: nezhate: Re: Multi place and route
    103529: 06/06/05: Jim Wu: Re: Multi place and route
    103559: 06/06/05: nezhate: Re: Multi place and route
103492: 06/06/04: Pasacco: Asynchronous BRAM input ?
    103498: 06/06/04: Peter Alfke: Re: Asynchronous BRAM input ?
    103501: 06/06/04: Alan Nishioka: Re: Asynchronous BRAM input ?
    103522: 06/06/05: Pasacco: Re: Asynchronous BRAM input ?
    103526: 06/06/05: Peter Alfke: Re: Asynchronous BRAM input ?
    103530: 06/06/05: Pasacco: Re: Asynchronous BRAM input ?
    103548: 06/06/05: Peter Alfke: Re: Asynchronous BRAM input ?
103506: 06/06/05: j93005: How to use usb on Alter EPXA4??
103508: 06/06/04: subint: Help on DDR SDRAM contoller generated by MIG1.5
    103523: 06/06/05: Joseph Samson: Re: Help on DDR SDRAM contoller generated by MIG1.5
    103570: 06/06/06: Nagesh: Re: Help on DDR SDRAM contoller generated by MIG1.5
        103579: 06/06/06: Joseph Samson: Re: Help on DDR SDRAM contoller generated by MIG1.5
    103571: 06/06/06: subint: Re: Help on DDR SDRAM contoller generated by MIG1.5
    103572: 06/06/06: subint: Re: Help on DDR SDRAM contoller generated by MIG1.5
103511: 06/06/05: Marco T.: MIL Qualified RTOS for PowerPc 405
    103524: 06/06/05: Stephen Craven: Re: MIL Qualified RTOS for PowerPc 405
        103525: 06/06/05: Marco T.: Re: MIL Qualified RTOS for PowerPc 405
            103531: 06/06/05: Tim Wescott: Re: MIL Qualified RTOS for PowerPc 405
    103528: 06/06/05: Zara: Re: MIL Qualified RTOS for PowerPc 405
    103550: 06/06/05: bh: Re: MIL Qualified RTOS for PowerPc 405
103514: 06/06/05: Brian: Jumps in Reading out
103527: 06/06/05: ARRON: The simulation of Xilinx DDC(Digital Down Convert) IP Core can't gain the result
103534: 06/06/05: rickman: Webpack larger than CDs
    103535: 06/06/05: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Webpack larger than CDs
        103541: 06/06/05: Jan Panteltje: Re: Webpack larger than CDs
            103544: 06/06/05: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Webpack larger than CDs
                103551: 06/06/05: Ryan Laity: Re: Webpack larger than CDs
    103542: 06/06/05: Kolja Sulimma: Re: Webpack larger than CDs
    103543: 06/06/05: Jim Wu: Re: Webpack larger than CDs
    103553: 06/06/05: rickman: Re: Webpack larger than CDs
        103555: 06/06/06: Rich Grise: Re: Webpack larger than CDs
        103558: 06/06/05: Ryan Laity: Re: Webpack larger than CDs
        103563: 06/06/06: Kolja Sulimma: Re: Webpack larger than CDs
            103567: 06/06/06: Uwe Bonnes: Re: Webpack larger than CDs
            103582: 06/06/06: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Webpack larger than CDs
        103569: 06/06/06: Symon: Re: Webpack larger than CDs
    103554: 06/06/05: Peter Alfke: Re: Webpack larger than CDs
    103556: 06/06/05: rickman: Re: Webpack larger than CDs
    103557: 06/06/05: Peter Alfke: Re: Webpack larger than CDs
    103591: 06/06/06: rickman: Re: Webpack larger than CDs
    103698: 06/06/08: rickman: Re: Webpack larger than CDs
103537: 06/06/05: marco: ProjectMgmt WARNING from ISE 8.1i XST
    103538: 06/06/05: Gabor: Re: ProjectMgmt WARNING from ISE 8.1i XST
103539: 06/06/05: MM: Xilinx Floorplanner basic question
103549: 06/06/05: Brandon Jasionowski: ISE Timing Analysis Misreporting? Bug?
    103565: 06/06/06: Ben Jones: Re: ISE Timing Analysis Misreporting? Bug?
        103587: 06/06/06: Ben Jones: Re: ISE Timing Analysis Misreporting? Bug?
    103585: 06/06/06: Brandon Jasionowski: Re: ISE Timing Analysis Misreporting? Bug?
103552: 06/06/05: Colin Hankins: Re: Jtag Programmer
    103584: 06/06/06: Bubb: Re: Jtag Programmer
103560: 06/06/06: bh: FlipChip BGA Conformal Coating
    103588: 06/06/06: Austin Lesea: Re: FlipChip BGA Conformal Coating
        103615: 06/06/06: bh: Re: FlipChip BGA Conformal Coating
            103644: 06/06/07: Austin Lesea: Re: FlipChip BGA Conformal Coating
        103635: 06/06/07: se: Re: FlipChip BGA Conformal Coating
        103636: 06/06/07: Thomas Womack: Re: FlipChip BGA Conformal Coating
            103645: 06/06/07: Austin Lesea: Re: FlipChip BGA Conformal Coating
                103648: 06/06/07: Thomas Womack: Re: FlipChip BGA Conformal Coating
103566: 06/06/06: Srikanth BJ: Efficient implementation of Address Decoding logic
    103596: 06/06/06: Andy: Re: Efficient implementation of Address Decoding logic
        103599: 06/06/06: Mike Treseler: Re: Efficient implementation of Address Decoding logic
            103606: 06/06/06: Mike Treseler: Re: Efficient implementation of Address Decoding logic
                103637: 06/06/07: Mike Treseler: Re: Efficient implementation of Address Decoding logic
    103602: 06/06/06: Andy: Re: Efficient implementation of Address Decoding logic
    103610: 06/06/06: Andy: Re: Efficient implementation of Address Decoding logic
    103622: 06/06/06: Srikanth BJ: Re: Efficient implementation of Address Decoding logic
    103638: 06/06/07: Andy: Re: Efficient implementation of Address Decoding logic
    103680: 06/06/07: Srikanth BJ: Re: Efficient implementation of Address Decoding logic
    103721: 06/06/09: Andy: Re: Efficient implementation of Address Decoding logic
103574: 06/06/06: Sean Durkin: ISE8.1 on OpenSUSE 64bit
    103598: 06/06/06: Jim Wu: Re: ISE8.1 on OpenSUSE 64bit
        103604: 06/06/06: Sean Durkin: Re: ISE8.1 on OpenSUSE 64bit
            103625: 06/06/07: Sean Durkin: Re: ISE8.1 on OpenSUSE 64bit
    103641: 06/06/07: Jim Wu: Re: ISE8.1 on OpenSUSE 64bit
    105018: 06/07/12: Sean Durkin: Re: ISE8.1 on OpenSUSE 64bit => ISE8.2 works
103575: 06/06/06: subint: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
103576: 06/06/06: subint: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
    103578: 06/06/06: Joseph Samson: Re: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
    103581: 06/06/06: subint: Re: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
    103627: 06/06/06: Jochen: Re: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
103577: 06/06/06: Guru: Re: Jtag Programmer
103580: 06/06/06: <eascheiber@yahoo.com>: ppc instruction count
    103586: 06/06/06: Ben Jones: Re: ppc instruction count
    103595: 06/06/06: Siva Velusamy: Re: ppc instruction count
        103735: 06/06/09: Siva Velusamy: Re: ppc instruction count
    103724: 06/06/09: <eascheiber@yahoo.com>: Re: ppc instruction count
    103726: 06/06/09: Alan Nishioka: Re: ppc instruction count
103589: 06/06/06: jmariano: GPIO problem
    103592: 06/06/06: Paul Lee: Re: GPIO problem
    103947: 06/06/15: jmariano: Re: GPIO problem
103590: 06/06/06: misiu: Xlinix ML403 evaluation board
    103594: 06/06/06: =?UTF-8?B?TWljaGFlbCBTY2jDtmJlcmw=?=: Re: Xlinix ML403 evaluation board
        103629: 06/06/07: misiu: Re: Xlinix ML403 evaluation board
103593: 06/06/06: <ghelbig@lycos.com>: Re: Jtag Programmer
103597: 06/06/06: folnar: Propagation delay sensitivity to temperature, voltage, and manufacturing
    103600: 06/06/06: Austin Lesea: Re: Propagation delay sensitivity to temperature, voltage, and manufacturing
    103601: 06/06/06: Peter Alfke: Re: Propagation delay sensitivity to temperature, voltage, and manufacturing
103603: 06/06/06: MM: EDK: TCL scripts in pcores directories
    103609: 06/06/06: John McCaskill: Re: EDK: TCL scripts in pcores directories
103607: 06/06/06: <langwadt@ieee.org>: ise8.1 picking local instead of global clk routing?
    103669: 06/06/07: Gabor: Re: ise8.1 picking local instead of global clk routing?
103618: 06/06/06: <boxi.yang@gmail.com>: API on Virtex 4 FPGA or the email of Delon Levi wanted
    103634: 06/06/07: Jacek Wawrzaszek: Re: API on Virtex 4 FPGA or the email of Delon Levi wanted
    103692: 06/06/08: <boxi.yang@gmail.com>: Re: API on Virtex 4 FPGA or the email of Delon Levi wanted
103619: 06/06/06: qysheng: IOBDELAY's delay value
    103665: 06/06/07: Eric Crabill: Re: IOBDELAY's delay value
        103668: 06/06/07: Uwe Bonnes: Re: IOBDELAY's delay value
            103686: 06/06/08: Hal Murray: Re: IOBDELAY's delay value
            103687: 06/06/08: Jim Granville: Re: IOBDELAY's delay value
103626: 06/06/06: Brian: Noise-like Vibration in Measurement Result
103628: 06/06/07: dmos: Problems with ISE logic optimization
    103631: 06/06/07: Zara: Re: Problems with ISE logic optimization
        103633: 06/06/07: Zara: Re: Problems with ISE logic optimization
    103632: 06/06/07: dmos: Re: Problems with ISE logic optimization
    103640: 06/06/07: Jim Wu: Re: Problems with ISE logic optimization
    103651: 06/06/07: dmos: Re: Problems with ISE logic optimization
    103658: 06/06/07: Kolja Sulimma: Re: Problems with ISE logic optimization
103630: 06/06/07: Sylvain Munaut <SomeOne@SomeDomain.com>: SGMII with Virtex 4 embedded MAC
103639: 06/06/07: Andy: Re: FlipChip BGA Conformal Coating
103642: 06/06/07: Peter Alfke: Re: FlipChip BGA Conformal Coating
103643: 06/06/07: Meres Five: ICAP Virtex4 32 bits
    103805: 06/06/12: Meres Five: Re: ICAP Virtex4 32 bits
103646: 06/06/07: kia rui: LVTTL, LVCMOS or 3.3V-PCI?
    103650: 06/06/07: John Smith: Re: LVTTL, LVCMOS or 3.3V-PCI?
    104108: 06/06/19: Kolja Sulimma: Re: LVTTL, LVCMOS or 3.3V-PCI?
103649: 06/06/07: James Ma: Easily add 4 Gb/s Ethernet link to FPGA systems for control & data transfer
    103660: 06/06/07: Tobias Weingartner: Re: Easily add 4 Gb/s Ethernet link to FPGA systems for control & data transfer
103652: 06/06/07: John Smith: Anyone with Xilinx SP305-board ?
    103653: 06/06/07: radarman: Re: Anyone with Xilinx SP305-board ?
        103737: 06/06/10: John Smith: Re: Anyone with Xilinx SP305-board ?
        103738: 06/06/10: John Smith: Re: Anyone with Xilinx SP305-board ?
            103739: 06/06/09: Austin Lesea: Re: Anyone with Xilinx SP305-board ?
                103742: 06/06/10: John Smith: Re: Anyone with Xilinx SP305-board ?
                    103748: 06/06/10: John Smith: Re: Anyone with Xilinx SP305-board ?
                        103749: 06/06/09: Ed McGettigan: Re: Anyone with Xilinx SP305-board ?
                            103750: 06/06/10: John Smith: Re: Anyone with Xilinx SP305-board ?
                                103762: 06/06/10: Austin Lesea: Re: Anyone with Xilinx SP305-board ?
                                    103768: 06/06/11: John Smith: Re: Anyone with Xilinx SP305-board ?
                            103751: 06/06/10: John Smith: Re: Anyone with Xilinx SP305-board ?
                103744: 06/06/10: John Smith: Re: Anyone with Xilinx SP305-board ?
                    103763: 06/06/10: Austin Lesea: Re: Anyone with Xilinx SP305-board ?
                        103770: 06/06/11: John Smith: Re: Anyone with Xilinx SP305-board ?
                            103772: 06/06/10: Austin Lesea: Re: Anyone with Xilinx SP305-board ?
                                103775: 06/06/11: John Smith: Re: Anyone with Xilinx SP305-board ?
                                    103832: 06/06/13: Daniel O'Connor: Re: Anyone with Xilinx SP305-board ?
                                        104057: 06/06/18: John Smith: Re: Anyone with Xilinx SP305-board ?
                                103777: 06/06/11: John Smith: Re: Anyone with Xilinx SP305-board ?
                                    103778: 06/06/11: John Smith: Re: Anyone with Xilinx SP305-board ?
            103769: 06/06/11: John Smith: Re: Anyone with Xilinx SP305-board ?
                103771: 06/06/11: Jim Granville: Re: Anyone with Xilinx SP305-board ?
                    103776: 06/06/11: John Smith: Re: Anyone with Xilinx SP305-board ?
                    103779: 06/06/11: John Smith: Re: Anyone with Xilinx SP305-board ?
    103657: 06/06/07: John Adair: Re: Anyone with Xilinx SP305-board ?
        103741: 06/06/10: John Smith: Re: Anyone with Xilinx SP305-board ?
    103743: 06/06/09: gallen: Re: Anyone with Xilinx SP305-board ?
    103766: 06/06/10: radarman: Re: Anyone with Xilinx SP305-board ?
    103786: 06/06/11: Peter Alfke: Re: Anyone with Xilinx SP305-board ?
    104060: 06/06/17: Peter Alfke: Re: Anyone with Xilinx SP305-board ?
103654: 06/06/07: <fpga_toys@yahoo.com>: Re: FlipChip BGA Conformal Coating
103655: 06/06/07: Henry: Xilinx SystemACE : Flash Memory
103656: 06/06/07: jjlindula@hotmail.com: Incrmental Compilation in Quartus 5.1
    103678: 06/06/08: Mark McDougall: Re: Incrmental Compilation in Quartus 5.1
    103693: 06/06/08: Shawn Malhotra: Re: Incrmental Compilation in Quartus 5.1
        103700: 06/06/08: pantxoa: Re: Incrmental Compilation in Quartus 5.1
103659: 06/06/07: Dale: Can ILMB and DLMB of Microblaze be 24kByte?
    103679: 06/06/08: John Williams: Re: Can ILMB and DLMB of Microblaze be 24kByte?
        103682: 06/06/08: Zara: Re: Can ILMB and DLMB of Microblaze be 24kByte?
103664: 06/06/07: Garrick: Xilinx EDK: Connecting interrupt to MicroBlaze requires stdout?
    103672: 06/06/07: Siva Velusamy: Re: Xilinx EDK: Connecting interrupt to MicroBlaze requires stdout?
103666: 06/06/07: Peter Alfke: Re: IOBDELAY's delay value
103674: 06/06/07: Peter Alfke: Re: IOBDELAY's delay value
103675: 06/06/07: jjlindula@hotmail.com: Rumor Control:: Will Quartus phase out supporting AHDL?
    103676: 06/06/07: Subroto Datta: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
        103731: 06/06/09: czerstwy: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
            103733: 06/06/09: Josh Rosen: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
                103736: 06/06/10: Simon Peacock: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
            103757: 06/06/10: Subroto Datta: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
    103677: 06/06/08: Jim Granville: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
        103696: 06/06/08: Mike Treseler: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
        103699: 06/06/09: Jim Granville: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
            103822: 06/06/13: Jim Granville: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
                103839: 06/06/13: Subroto Datta: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
    103695: 06/06/08: Andy: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
    103806: 06/06/12: Andy: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
    103849: 06/06/13: Andy: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
103681: 06/06/07: Ashish: Block Ram vs Distributed Ram
    103683: 06/06/08: Zara: Re: Block Ram vs Distributed Ram
        103691: 06/06/08: Josh Rosen: Re: Block Ram vs Distributed Ram
    103684: 06/06/07: Peter Alfke: Re: Block Ram vs Distributed Ram
    103685: 06/06/07: Ashish: Re: Block Ram vs Distributed Ram
    103688: 06/06/08: vssumesh: Re: Block Ram vs Distributed Ram
    103694: 06/06/08: Peter Alfke: Re: Block Ram vs Distributed Ram
103689: 06/06/08: MikeJ: Space invaders on Spartan3e starter board
    103690: 06/06/08: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Space invaders on Spartan3e starter board
    104397: 06/06/26: Michael: Re: Space invaders on Spartan3e starter board
        104406: 06/06/27: Mark McDougall: Re: Space invaders on Spartan3e starter board
    104409: 06/06/26: Michael: Re: Space invaders on Spartan3e starter board
        104411: 06/06/27: Mark McDougall: Re: Space invaders on Spartan3e starter board
103697: 06/06/08: <aiiadict@gmail.com>: stable, tested 6502 core
    103701: 06/06/08: MikeJ: Re: stable, tested 6502 core
    103702: 06/06/08: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: stable, tested 6502 core
        103787: 06/06/11: Hal Murray: Re: stable, tested 6502 core
            103790: 06/06/11: MikeJ: Re: stable, tested 6502 core
    103703: 06/06/08: <aiiadict@gmail.com>: Re: stable, tested 6502 core
    103704: 06/06/08: <jaxato@gmail.com>: Re: stable, tested 6502 core
    103705: 06/06/08: Kryten: Re: stable, tested 6502 core
    103774: 06/06/10: Keith: Re: stable, tested 6502 core
103706: 06/06/08: Weng Tianxiang: Good free or paid merge software that edits two similar files?
    103707: 06/06/08: Markus Svilans: Re: Good free or paid merge software that edits two similar files?
    103708: 06/06/08: Weng Tianxiang: Re: Good free or paid merge software that edits two similar files?
    103710: 06/06/08: <grigsoft@gmail.com>: Re: Good free or paid merge software that edits two similar files?
    103713: 06/06/09: filox: Re: Good free or paid merge software that edits two similar files?
    103714: 06/06/09: colin: Re: Good free or paid merge software that edits two similar files?
    103716: 06/06/09: <charles.elias@wpafb.af.mil>: Re: Good free or paid merge software that edits two similar files?
    103717: 06/06/09: David R Brooks: Re: Good free or paid merge software that edits two similar files?
    103718: 06/06/09: Nial Stewart: Re: Good free or paid merge software that edits two similar files?
    103719: 06/06/09: Marcus Harnisch: Re: Good free or paid merge software that edits two similar files?
    103720: 06/06/09: dalai lamah: Re: Good free or paid merge software that edits two similar files?
    103725: 06/06/09: Weng Tianxiang: Re: Good free or paid merge software that edits two similar files?
    103727: 06/06/09: Alain: Re: Good free or paid merge software that edits two similar files?
    103752: 06/06/09: Paul Leventis: Re: Good free or paid merge software that edits two similar files?
    103755: 06/06/10: Weng Tianxiang: Re: Good free or paid merge software that edits two similar files?
    103802: 06/06/12: <charles.elias@wpafb.af.mil>: Re: Good free or paid merge software that edits two similar files?
103711: 06/06/09: <jamil.khatib@googlemail.com>: The 3rd International Electronics Design Contest for Students
103715: 06/06/09: Ams: Linux 2.6 for PPC on Xilinx XUP-V2PRO board!
103722: 06/06/09: Jerome: PCI Express - Root Complex ?
    103723: 06/06/09: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: PCI Express - Root Complex ?
    103828: 06/06/12: Aashish Malhotra: Re: PCI Express - Root Complex ?
    104121: 06/06/19: Aashish Malhotra: Re: PCI Express - Root Complex ?
103728: 06/06/09: <m_oylulan@hotmail.com>: Current from FPGA pins to ADC
    103729: 06/06/09: Peter Alfke: Re: Current from FPGA pins to ADC
        103890: 06/06/14: Falk Brunner: Re: Current from FPGA pins to ADC
        103982: 06/06/16: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Current from FPGA pins to ADC
    103730: 06/06/09: MM: Re: Current from FPGA pins to ADC
    103887: 06/06/14: <m_oylulan@hotmail.com>: Re: Current from FPGA pins to ADC
    103989: 06/06/16: johnp: Re: Current from FPGA pins to ADC
103732: 06/06/09: blisca: xilinx cable 3 doesn't talk with pc,but test ok
    103740: 06/06/10: John Smith: Re: xilinx cable 3 doesn't talk with pc,but test ok
        103747: 06/06/10: blisca: R: xilinx cable 3 doesn't talk with pc,but test ok
            103753: 06/06/10: John Smith: Re: xilinx cable 3 doesn't talk with pc,but test ok
                103754: 06/06/10: blisca: R: xilinx cable 3 doesn't talk with pc,but test ok
                    103788: 06/06/11: blisca: R: R: xilinx cable 3 doesn't talk with pc,but test ok
    103761: 06/06/10: John Adair: Re: R: xilinx cable 3 doesn't talk with pc,but test ok
    103780: 06/06/11: Leon: Re: R: xilinx cable 3 doesn't talk with pc,but test ok
103734: 06/06/09: <irfan.mohammed@gmail.com>: Requesting for an Actel Library
    103745: 06/06/09: Daniel Leu: Re: Requesting for an Actel Library
103746: 06/06/09: cwoodring: edk 8.1
103756: 06/06/10: Subhasri krishnan: initialization sequence and auto refresh for sdr-sdram
    103758: 06/06/10: Alan Nishioka: Re: initialization sequence and auto refresh for sdr-sdram
        103784: 06/06/11: Joseph Samson: Re: initialization sequence and auto refresh for sdr-sdram
            103793: 06/06/12: Joseph Samson: Re: initialization sequence and auto refresh for sdr-sdram
    103759: 06/06/10: Subhasri krishnan: Re: initialization sequence and auto refresh for sdr-sdram
    103760: 06/06/10: Alan Nishioka: Re: initialization sequence and auto refresh for sdr-sdram
    103782: 06/06/11: Joseph Samson: Re: initialization sequence and auto refresh for sdr-sdram
        103794: 06/06/12: Joseph Samson: Re: initialization sequence and auto refresh for sdr-sdram
    103791: 06/06/11: Alan Nishioka: Re: initialization sequence and auto refresh for sdr-sdram
    103792: 06/06/11: Subhasri krishnan: Re: initialization sequence and auto refresh for sdr-sdram
103764: 06/06/10: Rich Grise: Xilinx ISE S/W Install kernel version "mismatch"
    103765: 06/06/10: Rich Grise: Re: Xilinx ISE S/W Install kernel version "mismatch"
        103773: 06/06/10: Chris Sorenson: Re: Xilinx ISE S/W Install kernel version "mismatch"
            103783: 06/06/11: Daniel O'Connor: Re: Xilinx ISE S/W Install kernel version "mismatch"
    103767: 06/06/10: Nico Coesel: Re: Xilinx ISE S/W Install kernel version "mismatch"
    103781: 06/06/11: Felix Bertram: Re: Xilinx ISE S/W Install kernel version "mismatch"
        103817: 06/06/12: Rich Grise: Re: Xilinx ISE S/W Install kernel version "mismatch"
            103819: 06/06/12: MH: Re: Xilinx ISE S/W Install kernel version "mismatch"
    104033: 06/06/17: joseph2k: Re: Xilinx ISE S/W Install kernel version "mismatch"
    104142: 06/06/20: Adam Goldman: Re: Xilinx ISE S/W Install kernel version "mismatch"
        104250: 06/06/21: Rich Grise: Re: Xilinx ISE S/W Install kernel version "mismatch"
            104251: 06/06/21: Duane Clark: Re: Xilinx ISE S/W Install kernel version "mismatch"
                104281: 06/06/22: Rich Grise: Re: Xilinx ISE S/W Install kernel version "mismatch"
                    104315: 06/06/23: Duane Clark: Re: Xilinx ISE S/W Install kernel version "mismatch"
                    104351: 06/06/25: Stephen Williams: Re: Xilinx ISE S/W Install kernel version "mismatch"
103789: 06/06/11: elesser: from VHDL to FPGA
    103795: 06/06/11: JJ: Re: from VHDL to FPGA
        103810: 06/06/12: Eric Crabill: Re: from VHDL to FPGA
            103824: 06/06/12: Mike Treseler: Re: from VHDL to FPGA
    103798: 06/06/12: elesser: Re: from VHDL to FPGA
    103799: 06/06/12: JJ: Re: from VHDL to FPGA
    103814: 06/06/12: elesser: Re: from VHDL to FPGA
103796: 06/06/11: prav: Xilinx timing viloations
    103801: 06/06/12: Aurelian Lazarut: Re: Xilinx timing viloations
        103846: 06/06/13: Aurelian Lazarut: Re: Xilinx timing viloations
        103848: 06/06/13: John_H: Re: Xilinx timing viloations
    103812: 06/06/12: John_H: Re: Xilinx timing viloations
        103816: 06/06/12: Aurelian Lazarut: Re: Xilinx timing viloations
    103845: 06/06/13: prav: Re: Xilinx timing viloations
    104680: 06/07/03: prav: Re: Xilinx timing viloations
103797: 06/06/11: xilinx_user: How do I use the DDS core in a verilog flow?
    103800: 06/06/12: Aurelian Lazarut: Re: How do I use the DDS core in a verilog flow?
        103815: 06/06/12: Aurelian Lazarut: Re: How do I use the DDS core in a verilog flow?
            103893: 06/06/14: Joseph Samson: Re: How do I use the DDS core in a verilog flow?
                103894: 06/06/14: Aurelian Lazarut: Re: How do I use the DDS core in a verilog flow?
                104005: 06/06/16: Joseph Samson: Re: How do I use the DDS core in a verilog flow?
    103809: 06/06/12: xilinx_user: Re: How do I use the DDS core in a verilog flow?
    103825: 06/06/12: <langwadt@ieee.org>: Re: How do I use the DDS core in a verilog flow?
    103858: 06/06/13: xilinx_user: Re: How do I use the DDS core in a verilog flow?
    103869: 06/06/13: <langwadt@ieee.org>: Re: How do I use the DDS core in a verilog flow?
    103871: 06/06/13: xilinx_user: Re: How do I use the DDS core in a verilog flow?
    103872: 06/06/13: <langwadt@ieee.org>: Re: How do I use the DDS core in a verilog flow?
    103875: 06/06/13: xilinx_user: Re: How do I use the DDS core in a verilog flow?
    103991: 06/06/16: xilinx_user: Re: How do I use the DDS core in a verilog flow?
    104020: 06/06/16: xilinx_user: Re: How do I use the DDS core in a verilog flow?
103804: 06/06/12: Eric: xc3sprog -- any updates?
    103807: 06/06/12: Sandro: Re: xc3sprog -- any updates?
    103808: 06/06/12: Eric: Re: xc3sprog -- any updates?
    103837: 06/06/13: Daniel O'Connor: Re: xc3sprog -- any updates?
        103840: 06/06/13: Uwe Bonnes: Re: xc3sprog -- any updates?
            104336: 06/06/24: Uwe Bonnes: Re: xc3sprog -- any updates?
    103847: 06/06/13: Eric: Re: xc3sprog -- any updates?
    104213: 06/06/21: Sandro: Re: xc3sprog -- any updates?
    104245: 06/06/21: Eric: Re: xc3sprog -- any updates?
    104267: 06/06/22: Sandro: Re: xc3sprog -- any updates?
    104275: 06/06/22: Sandro: Re: xc3sprog -- any updates?
    104310: 06/06/23: Eric: Re: xc3sprog -- any updates?
    104339: 06/06/24: Eric: Re: xc3sprog -- any updates?
103811: 06/06/12: Roger: RocketIO AC coupling
    103852: 06/06/13: MM: Re: RocketIO AC coupling
103818: 06/06/12: Weng Tianxiang: How to get lowest price for a ModelSim license?
    103820: 06/06/12: oneweek: Re: How to get lowest price for a ModelSim license?
        103951: 06/06/15: Stephen Williams: Re: How to get lowest price for a ModelSim license?
            103956: 06/06/16: Jim Granville: Re: How to get lowest price for a ModelSim license?
                104025: 06/06/16: Stephen Williams: Re: How to get lowest price for a ModelSim license?
        104040: 06/06/17: Mike Treseler: Re: How to get lowest price for a ModelSim license?
            104046: 06/06/17: Mike Treseler: Re: How to get lowest price for a ModelSim license?
            104064: 06/06/18: Stephen Williams: Re: How to get lowest price for a ModelSim license?
            104183: 06/06/20: Ron: Re: How to get lowest price for a ModelSim license?
    103821: 06/06/12: Andy: Re: How to get lowest price for a ModelSim license?
    103823: 06/06/12: Mike Treseler: Re: How to get lowest price for a ModelSim license?
        103842: 06/06/13: Nial Stewart: Re: How to get lowest price for a ModelSim license?
            103853: 06/06/13: Mike Treseler: Re: How to get lowest price for a ModelSim license?
    103833: 06/06/12: bart: Re: How to get lowest price for a ModelSim license?
    103841: 06/06/13: Francesco: Re: How to get lowest price for a ModelSim license?
    103851: 06/06/13: rnbrady: Re: How to get lowest price for a ModelSim license?
    103854: 06/06/13: Nial Stewart: Re: How to get lowest price for a ModelSim license?
    103867: 06/06/13: <burn.sir@gmail.com>: Re: How to get lowest price for a ModelSim license?
        103874: 06/06/13: Ray Andraka: Re: How to get lowest price for a ModelSim license?
    103873: 06/06/13: Weng Tianxiang: Re: How to get lowest price for a ModelSim license?
    103944: 06/06/15: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: How to get lowest price for a ModelSim license?
    103946: 06/06/15: Colin Marquardt: Re: How to get lowest price for a ModelSim license?
    103949: 06/06/15: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: How to get lowest price for a ModelSim license?
    104045: 06/06/17: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: How to get lowest price for a ModelSim license?
    104049: 06/06/17: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: How to get lowest price for a ModelSim license?
    104052: 06/06/17: gallen: Re: How to get lowest price for a ModelSim license?
103826: 06/06/12: Guru: Virtex4 DCM in DRP mode
    103830: 06/06/12: Peter Alfke: Re: Virtex4 DCM in DRP mode
    103831: 06/06/12: Peter Alfke: Re: Virtex4 DCM in DRP mode
    103844: 06/06/13: Guru: Re: Virtex4 DCM in DRP mode
103827: 06/06/12: HT Chang: Looking for patent attorney specialized in programmable logic
    103829: 06/06/12: Austin Lesea: Re: Looking for patent attorney specialized in programmable logic
        103834: 06/06/13: Jim Granville: Re: Looking for patent attorney specialized in programmable logic
            103835: 06/06/13: Rob: Re: Looking for patent attorney specialized in programmable logic
                103836: 06/06/12: Austin Lesea: Re: Looking for patent attorney specialized in programmable logic
103838: 06/06/12: xuweijun1983@gmail.com: Can i use "burstcount" in my userlogic while using Altera SOPC builder 5.1?
103843: 06/06/13: backhus: FSM state minimization with ISE?
    103866: 06/06/13: Mike Treseler: Re: FSM state minimization with ISE?
        103878: 06/06/13: Tommy Thorn: Re: FSM state minimization with ISE?
            103880: 06/06/13: Tommy Thorn: Re: FSM state minimization with ISE?
                103885: 06/06/14: backhus: Re: FSM state minimization with ISE?
                    103909: 06/06/14: Mike Treseler: Re: FSM state minimization with ISE?
                        103924: 06/06/15: backhus: Re: FSM state minimization with ISE?
                            103972: 06/06/16: backhus: Re: FSM state minimization with ISE?
                                104104: 06/06/19: backhus: Re: FSM state minimization with ISE?
                            104042: 06/06/17: Mike Treseler: Re: FSM state minimization with ISE?
    103877: 06/06/13: JustJohn: Re: FSM state minimization with ISE?
    103879: 06/06/13: JustJohn: Re: FSM state minimization with ISE?
    103881: 06/06/13: Tommy Thorn: Re: FSM state minimization with ISE?
        103883: 06/06/14: backhus: Re: FSM state minimization with ISE?
        103969: 06/06/16: backhus: Re: FSM state minimization with ISE? Apology:Tommys solution was
    103958: 06/06/15: JustJohn: Re: FSM state minimization with ISE?
103850: 06/06/13: Vivek Menon: Virtex-4 FX12: Mini module board from avnet
103855: 06/06/13: Symon: IDELAY clock spec. in Xilinx V4
    103856: 06/06/13: Aurelian Lazarut: Re: IDELAY clock spec. in Xilinx V4
        103860: 06/06/13: Symon: Re: IDELAY clock spec. in Xilinx V4
    103859: 06/06/13: Austin Lesea: Re: IDELAY clock spec. in Xilinx V4
        103862: 06/06/13: Symon: Re: IDELAY clock spec. in Xilinx V4
            103863: 06/06/13: Austin Lesea: Re: IDELAY clock spec. in Xilinx V4
                103891: 06/06/14: Symon: Re: IDELAY clock spec. in Xilinx V4
103857: 06/06/13: Peter Alfke: Re: IDELAY clock spec. in Xilinx V4
    103861: 06/06/13: Symon: Re: IDELAY clock spec. in Xilinx V4
103864: 06/06/13: bart: ANNC: VHDL Coding for FPGA Webcast
103865: 06/06/13: John_H: S3E Starter Kit webcast
    103908: 06/06/14: Tommy Thorn: Time for a new "Largest FPGA with free tool support"?
        103910: 06/06/14: Austin Lesea: Re: Time for a new "Largest FPGA with free tool support"?
            103916: 06/06/14: mk: Re: Time for a new "Largest FPGA with free tool support"?
                104021: 06/06/16: Austin Lesea: Re: Time for a new "Largest FPGA with free tool support"?
                    104026: 06/06/17: Jim Granville: Re: Time for a new "Largest FPGA with free tool support"?
                        104044: 06/06/17: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Time for a new "Largest FPGA with free tool support"?
                    104061: 06/06/18: David Brown: Re: Time for a new "Largest FPGA with free tool support"?
                104062: 06/06/18: David Brown: Re: Time for a new "Largest FPGA with free tool support"?
            103917: 06/06/15: Jim Granville: Re: Time for a new "Largest FPGA with free tool support"?
        103921: 06/06/15: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Time for a new "Largest FPGA with free tool support"?
    103913: 06/06/14: Tommy Thorn: Re: Time for a new "Largest FPGA with free tool support"?
    103914: 06/06/14: rickman: Re: Time for a new "Largest FPGA with free tool support"?
    103937: 06/06/15: <fpga_toys@yahoo.com>: Re: Time for a new "Largest FPGA with free tool support"?
    104001: 06/06/16: bart: Re: Time for a new "Largest FPGA with free tool support"?
    104009: 06/06/16: Tommy Thorn: Re: Time for a new "Largest FPGA with free tool support"?
    104023: 06/06/16: John Smith: Re: S3E Starter Kit webcast
103868: 06/06/13: Peter Alfke: Re: IDELAY clock spec. in Xilinx V4
103870: 06/06/13: nylander: Does anyone have documentation for an insight DS-V2LC board
103876: 06/06/14: Michael Laajanen: Quartus 6.0 and VCS
103882: 06/06/13: nomalus: null waveform element and webpack
    103888: 06/06/14: backhus: Re: null waveform element and webpack
    103920: 06/06/14: Dave Pollum: Re: null waveform element and webpack
103889: 06/06/14: subint: ARM9 DDR interface
103892: 06/06/14: Vivek Menon: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
    103902: 06/06/14: Duane Clark: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
        103911: 06/06/14: Duane Clark: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
            103918: 06/06/14: Duane Clark: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
                103933: 06/06/15: Duane Clark: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
                    103948: 06/06/15: Duane Clark: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
    103904: 06/06/14: Vivek Menon: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
    103912: 06/06/14: Vivek Menon: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
    103926: 06/06/15: Vivek Menon: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
    103934: 06/06/15: Vivek Menon: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
103895: 06/06/14: Marco: boot mode pins on Spartan3
    103897: 06/06/14: Ed McGettigan: Re: boot mode pins on Spartan3
        103919: 06/06/14: Ed McGettigan: Re: boot mode pins on Spartan3
    103898: 06/06/14: Aurelian Lazarut: Re: boot mode pins on Spartan3
    103899: 06/06/14: Marco: Re: boot mode pins on Spartan3
    103900: 06/06/14: Marco: Re: boot mode pins on Spartan3
    103907: 06/06/14: rickman: Re: boot mode pins on Spartan3
103896: 06/06/14: Alex McHale: Xilinx XST Error
    103901: 06/06/14: johnp: Re: Xilinx XST Error
    103903: 06/06/14: Duane Clark: Re: Xilinx XST Error
    103905: 06/06/14: Alex: Re: Xilinx XST Error
    103906: 06/06/14: rickman: Re: Xilinx XST Error
103915: 06/06/14: kia rui: LVTTL or LVCMOS for PCI Signaling?
    103978: 06/06/16: KJ: Re: LVTTL or LVCMOS for PCI Signaling?
        104056: 06/06/18: John Smith: Re: LVTTL or LVCMOS for PCI Signaling?
            104066: 06/06/18: Kolja Sulimma: Re: LVTTL or LVCMOS for PCI Signaling?
    104003: 06/06/16: Peter Alfke: Re: LVTTL or LVCMOS for PCI Signaling?
    104059: 06/06/17: Peter Alfke: Re: LVTTL or LVCMOS for PCI Signaling?
    104067: 06/06/18: Peter Alfke: Re: LVTTL or LVCMOS for PCI Signaling?
103922: 06/06/14: Brian Davis: open inputs and Unisim libraries
103923: 06/06/15: Maroc: XPLA3 bidirectional bus
    103963: 06/06/16: Jim Granville: Re: XPLA3 bidirectional bus
103925: 06/06/15: sjulhes: ARM cores in FPGA ?
    103930: 06/06/15: Vhdl.eu: Re: ARM cores in FPGA ?
        103936: 06/06/15: Joseph: Re: ARM cores in FPGA ?
        103940: 06/06/15: Antti Lukats: Re: ARM cores in FPGA ?
            103943: 06/06/15: Ed McGettigan: Re: ARM cores in FPGA ?
                103945: 06/06/16: Jim Granville: Re: ARM cores in FPGA ?
                103986: 06/06/16: Ed McGettigan: Re: ARM cores in FPGA ?
    103967: 06/06/16: sjulhes: Re: ARM cores in FPGA ?
        103973: 06/06/16: Jim Granville: Re: ARM cores in FPGA ?
        104055: 06/06/17: Ulf Samuelsson: Re: ARM cores in FPGA ?
    103970: 06/06/16: Antti: Re: ARM cores in FPGA ?
    103994: 06/06/16: Jeremy Ralph: Re: ARM cores in FPGA ?
103927: 06/06/15: Vivek Menon: Virtex-4 with Rocket IO capability??
    103928: 06/06/15: Ed McGettigan: Re: Virtex-4 with Rocket IO capability??
        103938: 06/06/15: Ed McGettigan: Re: Virtex-4 with Rocket IO capability??
            104024: 06/06/17: Sylvain Munaut: Re: Virtex-4 with Rocket IO capability??
    103931: 06/06/15: Vivek Menon: Re: Virtex-4 with Rocket IO capability??
    104022: 06/06/16: mike_la_jolla: Re: Virtex-4 with Rocket IO capability??
103932: 06/06/15: lecroy7200@chek.com: Bug in Altera Quartus
103935: 06/06/15: Bluespace Technologies: Anyone get a Pictiva OLED to work?
    103939: 06/06/15: Antti Lukats: Re: Anyone get a Pictiva OLED to work?
        103942: 06/06/15: Andrew Lohbihler: Re: Anyone get a Pictiva OLED to work?
            103960: 06/06/15: bh: Re: Anyone get a Pictiva OLED to work?
    103971: 06/06/16: Antti: Re: Anyone get a Pictiva OLED to work?
    104030: 06/06/16: Eric Smith: Re: Anyone get a Pictiva OLED to work?
        104035: 06/06/17: Jim Granville: Re: Anyone get a Pictiva OLED to work?
        104036: 06/06/17: Jim Granville: Re: Anyone get a Pictiva OLED to work?
        104048: 06/06/17: Eric Smith: Re: Anyone get a Pictiva OLED to work?
        104093: 06/06/19: Bluespace Technologies: Re: Anyone get a Pictiva OLED to work?
            104112: 06/06/19: Bluespace Technologies: Re: Anyone get a Pictiva OLED to work?
    104034: 06/06/16: Peter Alfke: Re: Anyone get a Pictiva OLED to work?
    104053: 06/06/17: Antti: Re: Anyone get a Pictiva OLED to work?
    104094: 06/06/18: Antti: Re: Anyone get a Pictiva OLED to work?
    104097: 06/06/19: Marco: Re: Anyone get a Pictiva OLED to work?
    104098: 06/06/19: Antti: Re: Anyone get a Pictiva OLED to work?
    104105: 06/06/19: Marco: Re: Anyone get a Pictiva OLED to work?
    104117: 06/06/19: Antti: Re: Anyone get a Pictiva OLED to work?
103941: 06/06/15: johnp: Virtex2-Pro local clocking...
    103957: 06/06/15: Brian Davis: Re: Virtex2-Pro local clocking...
    103984: 06/06/16: Jim Wu: Re: Virtex2-Pro local clocking...
    103998: 06/06/16: johnp: Re: Virtex2-Pro local clocking...
    104002: 06/06/16: johnp: Re: Virtex2-Pro local clocking...
103950: 06/06/15: ZHI: How process statement works in vhdl
    103974: 06/06/16: backhus: Re: How process statement works in vhdl
    104177: 06/06/20: ZHI: Re: How process statement works in vhdl
103954: 06/06/15: Adam Megacz: anybody doing self-timed/asynchronous on post-jbits xilinx parts?
    104027: 06/06/16: <fpga_toys@yahoo.com>: Re: anybody doing self-timed/asynchronous on post-jbits xilinx parts?
103955: 06/06/15: Peter Alfke: Re: clockless arbiters on fpgas?
103959: 06/06/15: <james7uw@yahoo.ca>: Xilinx MicroBlaze and Multimedia Demo. board: Debugging: 8.1.03i EDK - Unable to sync with stub on board
    103961: 06/06/15: <james7uw@yahoo.ca>: Re: Xilinx MicroBlaze and Multimedia Demo. board: Debugging: 8.1.03i EDK - Unable to sync with stub on board
103965: 06/06/15: Peter Alfke: Re: clockless arbiters on fpgas? [here's how it's done in ASICs]
103976: 06/06/16: savs: library for lmb
103977: 06/06/16: Marco: bga routing
    103979: 06/06/16: Symon: Re: bga routing
        104037: 06/06/17: Philip Freidin: Re: bga routing
    103980: 06/06/16: dp: Re: bga routing
        103985: 06/06/16: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: bga routing
            103988: 06/06/16: Austin Lesea: Re: bga routing
            103992: 06/06/16: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: bga routing
    103981: 06/06/16: Aurelian Lazarut: Re: bga routing
    103987: 06/06/16: dp: Re: bga routing
    104017: 06/06/16: John Adair: Re: bga routing
    104039: 06/06/16: Marco: Re: bga routing
103983: 06/06/16: pinku: Hold margin for asynchronous Interface
    104047: 06/06/17: Genome: Re: Hold margin for asynchronous Interface
103990: 06/06/16: vssumesh: Doubts on IBUFGDP
    104008: 06/06/16: Joseph Samson: Re: Doubts on IBUFGDP
103993: 06/06/16: fslearner: Floppy to FPGA?
    103995: 06/06/16: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Floppy to FPGA?
    103996: 06/06/16: Antti: Re: Floppy to FPGA?
        104004: 06/06/16: Roberto Waltman: Re: Floppy to FPGA?
    104010: 06/06/16: Leon: Re: Floppy to FPGA?
        104031: 06/06/16: Eric Smith: Re: Floppy to FPGA?
    104029: 06/06/16: Ed McGettigan: Re: Floppy to FPGA?
        104041: 06/06/17: Alex Freed: Re: Floppy to FPGA?
            104043: 06/06/17: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Floppy to FPGA?
                104058: 06/06/17: Alex Freed: Re: Floppy to FPGA?
    104038: 06/06/16: <ghelbig@lycos.com>: Re: Floppy to FPGA?
    104071: 06/06/18: fslearner: Re: Floppy to FPGA?
    104085: 06/06/19: Mark McDougall: Re: Floppy to FPGA?
        104130: 06/06/19: Alex Freed: Re: Floppy to FPGA?
            104138: 06/06/20: Mark McDougall: Re: Floppy to FPGA?
                117712: 07/04/08: Kryten: Re: Floppy to FPGA?
    104092: 06/06/18: <ghelbig@lycos.com>: Re: Floppy to FPGA?
104012: 06/06/16: vans: High speed differential to single ended
    104013: 06/06/16: Antti: Re: High speed differential to single ended
        104016: 06/06/16: Falk Brunner: Re: High speed differential to single ended
            104019: 06/06/16: Falk Brunner: Re: High speed differential to single ended
    104014: 06/06/16: Falk Brunner: Re: High speed differential to single ended
        104065: 06/06/18: Kolja Sulimma: Re: High speed differential to single ended
            104069: 06/06/18: mk: Re: High speed differential to single ended
            104070: 06/06/18: Falk Brunner: Re: High speed differential to single ended
                104074: 06/06/18: Falk Brunner: Re: High speed differential to single ended
                104100: 06/06/19: Thomas Womack: Re: High speed differential to single ended
            104073: 06/06/18: Thomas Womack: Re: High speed differential to single ended
                104089: 06/06/19: John_H: Re: High speed differential to single ended
    104015: 06/06/16: vans: Re: High speed differential to single ended
    104018: 06/06/16: vans: Re: High speed differential to single ended
        104099: 06/06/19: Thomas Womack: Re: High speed differential to single ended
            104111: 06/06/19: John_H: Re: High speed differential to single ended
            104116: 06/06/19: Thomas Womack: Re: High speed differential to single ended
    104032: 06/06/16: Jecel: Re: High speed differential to single ended
    104068: 06/06/18: Peter Alfke: Re: High speed differential to single ended
    104072: 06/06/18: Peter Alfke: Re: High speed differential to single ended
    104077: 06/06/18: vans: Re: High speed differential to single ended
    104078: 06/06/18: Peter Alfke: Re: High speed differential to single ended
    104081: 06/06/18: <eternal_nan@yahoo.com>: Re: High speed differential to single ended
    104083: 06/06/18: Peter Alfke: Re: High speed differential to single ended
    104095: 06/06/19: Antti: Re: High speed differential to single ended
    104096: 06/06/19: Antti: Re: High speed differential to single ended
    104103: 06/06/19: Antti: Re: High speed differential to single ended
    104109: 06/06/19: vans: Re: High speed differential to single ended
    104113: 06/06/19: vans: Re: High speed differential to single ended
    104114: 06/06/19: Antti: Re: High speed differential to single ended
    104115: 06/06/19: Antti: Re: High speed differential to single ended
    104118: 06/06/19: Antti: Re: High speed differential to single ended
    104137: 06/06/19: vans: Re: High speed differential to single ended
    104139: 06/06/19: <eternal_nan@yahoo.com>: Re: High speed differential to single ended
104050: 06/06/17: Vassili Savinov: Temperature sensing diode on Vertex 4
    104051: 06/06/17: Bob: Re: Temperature sensing diode on Vertex 4
    104054: 06/06/17: Austin Lesea: Re: Temperature sensing diode on Vertex 4
104063: 06/06/18: kelvins: pad issue
104075: 06/06/18: anand: Newbie to FPGA
    104076: 06/06/18: anand: Re: Newbie to FPGA
    104079: 06/06/18: Peter Alfke: Re: Newbie to FPGA
    104080: 06/06/18: anand: Re: Newbie to FPGA
    104082: 06/06/18: Peter Alfke: Re: Newbie to FPGA
    104084: 06/06/18: Tim Wescott: Re: Newbie to FPGA
        104106: 06/06/19: John Adair: Re: Newbie to FPGA
            104124: 06/06/19: John Adair: Re: Newbie to FPGA
                104349: 06/06/25: Falk Brunner: Re: Newbie to FPGA
    104087: 06/06/18: anand: Re: Newbie to FPGA
    104119: 06/06/19: <ekrads@gmail.com>: Re: Newbie to FPGA
    104347: 06/06/25: <frankgerlach@gmail.com>: Re: Newbie to FPGA
104086: 06/06/18: t2531998@126.com: --.-Low Cost High quality pcb prototype and Assembly manufacturer(CHINA).
    104088: 06/06/18: Stephen Williams: Re: --.-Low Cost High quality pcb prototype and Assembly manufacturer(CHINA).
        104090: 06/06/19: John_H: Re: --.-Low Cost High quality pcb prototype and Assembly manufacturer(CHINA).
        104091: 06/06/19: Philip Freidin: Re: --.-Low Cost High quality pcb prototype and Assembly manufacturer(CHINA).
104101: 06/06/19: Wojtek Zabolotny: Utility to generate pin assignments (UCF, QSF) from the Protel netlist
    104102: 06/06/19: Wojciech Zabolotny: Correction: Utility to generate pin assignments (UCF, QSF) from the
104107: 06/06/19: Steven P: ABEL to VHDL translate
    114744: 07/01/23: Thomas W.: Re: ABEL to VHDL translate
    114745: 07/01/23: Thomas Wesenberg: Re: ABEL to VHDL translate
104110: 06/06/19: Morten Leikvoll: xst:What happened here?
    104146: 06/06/20: subint: Re: xst:What happened here?
        104151: 06/06/20: Morten Leikvoll: Re: xst:What happened here?
104120: 06/06/19: Antti: using Impulse-C free edition for VHDL only FPGA designs.
    104143: 06/06/20: backhus: Re: using Impulse-C free edition for VHDL only FPGA designs.
        104157: 06/06/20: David Pellerin: Re: using Impulse-C free edition for VHDL only FPGA designs.
            104186: 06/06/20: David Pellerin: Re: using Impulse-C free edition for VHDL only FPGA designs.
    104144: 06/06/20: Antti: Re: using Impulse-C free edition for VHDL only FPGA designs.
    104166: 06/06/20: Antti: Re: using Impulse-C free edition for VHDL only FPGA designs.
104122: 06/06/19: Catherine Trammell: Aurora core example simulation
    104127: 06/06/19: MikeJ: Re: Aurora core example simulation
104123: 06/06/19: johnp: Xilinx bitgen vs output file name
    104145: 06/06/20: subint: Re: Xilinx bitgen vs output file name
104125: 06/06/19: Marc Kelly: Virtex-4FX embeded MAC and Rocket-IO data corruption??
    104126: 06/06/19: Sylvain Munaut: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
        104132: 06/06/19: Marc Kelly: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
    104128: 06/06/19: MikeJ: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
        104131: 06/06/19: Marc Kelly: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
            104133: 06/06/19: MikeJ: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
                104134: 06/06/19: MikeJ: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
                    104135: 06/06/19: Marc Kelly: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
                        104136: 06/06/19: bh: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
                            104178: 06/06/20: Marc Kelly: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104129: 06/06/19: Hans Rhein: Processor Design
    104140: 06/06/20: Philip Freidin: Re: Processor Design
104147: 06/06/20: subint: Programmable clock ics8442
104148: 06/06/20: Zara: Microblaze, -mxl-gp-opt and small data areas
104149: 06/06/20: Fred: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
    104152: 06/06/20: Antti: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
        104154: 06/06/20: Fred: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
            104160: 06/06/20: Fred: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
    104164: 06/06/20: Antti: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
    104265: 06/06/22: Kolja Sulimma: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
    104465: 06/06/27: fpgaguy: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
104150: 06/06/20: Manfred Balik: Quartus 6.0 Fitter Critical Warning
    104174: 06/06/20: KJ: Re: Quartus 6.0 Fitter Critical Warning
        104188: 06/06/21: Manfred Balik: Re: Quartus 6.0 Fitter Critical Warning
            104197: 06/06/21: KJ: Re: Quartus 6.0 Fitter Critical Warning
                104203: 06/06/21: Manfred Balik: Re: Quartus 6.0 Fitter Critical Warning
    104202: 06/06/21: Subroto Datta: Re: Quartus 6.0 Fitter Critical Warning
104153: 06/06/20: backhus: FSM State Minimization on FPGAs
    104155: 06/06/20: Andy: Re: FSM State Minimization on FPGAs
        104156: 06/06/20: Jonathan Bromley: Re: FSM State Minimization on FPGAs
            104181: 06/06/20: Mike Treseler: Re: FSM State Minimization on FPGAs
            104182: 06/06/21: Jim Granville: Re: FSM State Minimization on FPGAs
            104199: 06/06/21: Hal Murray: Re: FSM State Minimization on FPGAs
    104163: 06/06/20: Phil Hays: Re: FSM State Minimization on FPGAs
    104176: 06/06/20: Mike Treseler: Re: FSM State Minimization on FPGAs
    104179: 06/06/21: Jim Granville: Re: FSM State Minimization on FPGAs
    104180: 06/06/20: JustJohn: Re: FSM State Minimization on FPGAs
    104185: 06/06/20: JustJohn: Re: FSM State Minimization on FPGAs
    104192: 06/06/21: backhus: Re: FSM State Minimization on FPGAs
        104215: 06/06/21: Mike Treseler: Re: FSM State Minimization on FPGAs
        104218: 06/06/21: Mike Treseler: Re: FSM State Minimization on FPGAs
        104254: 06/06/22: backhus: Re: FSM State Minimization on FPGAs
    104209: 06/06/21: Andy: Re: FSM State Minimization on FPGAs
    104232: 06/06/21: JustJohn: Re: FSM State Minimization on FPGAs
    104257: 06/06/22: <fpga_toys@yahoo.com>: Re: FSM State Minimization on FPGAs
104158: 06/06/20: Jonathan Schneider: Google FPGA Designer beta release
    104173: 06/06/20: R! Tafas Jr: Re: Google FPGA Designer beta release
104159: 06/06/20: Alex: Xilinx ISE 8.1i Trouble
    104167: 06/06/20: <girmann@gmail.com>: Re: Xilinx ISE 8.1i Trouble
    104168: 06/06/20: Alex: Re: Xilinx ISE 8.1i Trouble
    104170: 06/06/20: Ben Jones: Re: Xilinx ISE 8.1i Trouble
        104201: 06/06/21: Ben Jones: Re: Xilinx ISE 8.1i Trouble
            104225: 06/06/21: MM: Re: Xilinx ISE 8.1i Trouble
    104171: 06/06/20: Duane Clark: Re: Xilinx ISE 8.1i Trouble
    104172: 06/06/20: Alex: Re: Xilinx ISE 8.1i Trouble
    104204: 06/06/21: Alex: Re: Xilinx ISE 8.1i Trouble
    104206: 06/06/21: Alex: Re: Xilinx ISE 8.1i Trouble
        104210: 06/06/21: Mike Treseler: Re: Xilinx ISE 8.1i Trouble
            104219: 06/06/21: Mike Treseler: Re: Xilinx ISE 8.1i Trouble
                104235: 06/06/21: Mike Treseler: Re: Xilinx ISE 8.1i Trouble
        104217: 06/06/21: c d saunter: Re: Xilinx ISE 8.1i Trouble
        104228: 06/06/21: MM: Re: Xilinx ISE 8.1i Trouble
    104214: 06/06/21: Alex: Re: Xilinx ISE 8.1i Trouble
    104240: 06/06/21: Alex: Re: Xilinx ISE 8.1i Trouble
104161: 06/06/20: <iluvmylife@gmail.com>: Need help reg Power Estimation using PowerPlay
104162: 06/06/20: Streetcat: Instrumentation Technologies
104165: 06/06/20: John Adair: For Broaddown2 Owners
104169: 06/06/20: Austin Lesea: keys to the Kingdom
    104194: 06/06/21: backhus: Locks for the peasants :-)
        104224: 06/06/21: Austin Lesea: Re: Locks for the peasants :-)
            104226: 06/06/21: Austin Lesea: Re: Locks for the peasants :-) Let them eat cake! Off with their
            104227: 06/06/21: Austin Lesea: Re: Locks for the peasants :-)
            104256: 06/06/22: backhus: Re: Locks for the peasants :-)
                104276: 06/06/22: Austin Lesea: Re: Locks for the peasants :-)
    104258: 06/06/22: Thomas Stanka: Re: keys to the Kingdom
        104277: 06/06/22: Austin Lesea: Re: keys to the Kingdom
            104278: 06/06/22: Hal Murray: Re: keys to the Kingdom
                104280: 06/06/22: Austin Lesea: Re: keys to the Kingdom
                104293: 06/06/23: Jim Granville: Re: keys to the Kingdom
                104294: 06/06/22: Austin Lesea: Re: keys to the Kingdom
                    104295: 06/06/23: Jim Granville: Re: keys to the Kingdom
                        104308: 06/06/23: Austin Lesea: Re: keys to the Kingdom
                            104309: 06/06/23: Austin Lesea: Re: keys to the Kingdom
                            104324: 06/06/24: Jim Granville: Re: keys to the Kingdom
                                104445: 06/06/27: mk: Re: keys to the Kingdom
                                    104452: 06/06/27: David Brown: Re: keys to the Kingdom
                                        104458: 06/06/27: Austin Lesea: Re: keys to the Kingdom
                                        104460: 06/06/27: Austin Lesea: Re: keys to the Kingdom
                                            104471: 06/06/28: David Brown: Re: keys to the Kingdom
                                                104477: 06/06/28: Austin Lesea: Re: keys to the Kingdom
                                                    104479: 06/06/28: David Brown: Re: keys to the Kingdom
                                                        104481: 06/06/28: Austin Lesea: Re: keys to the Kingdom
                                            104503: 06/06/28: David R Brooks: Re: keys to the Kingdom
                                                104509: 06/06/28: Austin Lesea: Re: keys to the Kingdom
                                                    104517: 06/06/29: David R Brooks: Re: keys to the Kingdom
                                                        104522: 06/06/29: Jim Granville: Re: keys to the Kingdom
                                        104470: 06/06/28: David Brown: Re: keys to the Kingdom
    104292: 06/06/22: Dave Greenfield: Re: keys to the Kingdom
    104314: 06/06/23: Andy Peters: Re: keys to the Kingdom
    104405: 06/06/26: Dave Greenfield: Re: keys to the Kingdom
    104407: 06/06/26: Peter Alfke: Re: keys to the Kingdom
    104450: 06/06/27: Peter Alfke: Re: keys to the Kingdom
    104454: 06/06/27: Peter Alfke: Re: keys to the Kingdom
104175: 06/06/20: Tim Verstraete: Synplicity PREMIER
104187: 06/06/20: Pravin G: comp.arch.fpga : Selection of Device
    104189: 06/06/20: Peter Alfke: Re: comp.arch.fpga : Selection of Device
        104190: 06/06/21: Zara: Re: comp.arch.fpga : Selection of Device
            104195: 06/06/21: Symon: Re: comp.arch.fpga : Selection of Device
                104196: 06/06/21: Zara: Re: comp.arch.fpga : Selection of Device
    104200: 06/06/21: John Adair: Re: comp.arch.fpga : Selection of Device
    104259: 06/06/22: Kolja Sulimma: Re: comp.arch.fpga : Selection of Device
104191: 06/06/21: Morten Leikvoll: xst can, but vcomp can't
    104216: 06/06/21: Ralf Hildebrandt: Re: xst can, but vcomp can't
        104255: 06/06/22: Morten Leikvoll: Re: xst can, but vcomp can't
            104282: 06/06/22: Ralf Hildebrandt: Re: xst can, but vcomp can't
                104316: 06/06/23: Ralf Hildebrandt: Re: xst can, but vcomp can't
104193: 06/06/21: <rreuter@gmx.net>: Stratix column and row pins
    104205: 06/06/21: Subroto Datta: Re: Stratix column and row pins
    104299: 06/06/23: <rreuter@gmx.net>: Re: Stratix column and row pins
104198: 06/06/21: <johnnynorthener@yahoo.co.uk>: PCI Express - Root Complex Emulation
104207: 06/06/21: Antti: Actel FUSIN chips are real !
    104212: 06/06/21: Jon Beniston: Re: Actel FUSIN chips are real !
104208: 06/06/21: <eascheiber@yahoo.com>: cache aware programming
    104211: 06/06/21: Jon Beniston: Re: cache aware programming
        104231: 06/06/21: Siva Velusamy: Re: cache aware programming
    104221: 06/06/21: JJ: Re: cache aware programming
    104222: 06/06/21: Hans: Re: cache aware programming
    104238: 06/06/21: Ben Jackson: Re: cache aware programming
    104306: 06/06/23: <eascheiber@yahoo.com>: Re: cache aware programming
    104307: 06/06/23: <eascheiber@yahoo.com>: Re: cache aware programming
104220: 06/06/21: jmariano: Spartan-3 starter kit strange problem
    104230: 06/06/21: Siva Velusamy: Re: Spartan-3 starter kit strange problem
    104264: 06/06/22: jmariano: Re: Spartan-3 starter kit strange problem
104223: 06/06/21: Peter Moreton: Xilinx XC4VSX25 development board?
    104239: 06/06/21: siva.velusamy@gmail.com: Re: Xilinx XC4VSX25 development board?
    104249: 06/06/21: Peter Moreton: Re: Xilinx XC4VSX25 development board?
104229: 06/06/21: chriskoh: using Celoxica's RC10 with microblaze's EDK kit
104233: 06/06/21: Vivek Menon: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104236: 06/06/21: Peter Alfke: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
        104243: 06/06/21: Sean Durkin: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
            104247: 06/06/21: Falk Brunner: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
                104273: 06/06/22: Falk Brunner: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104237: 06/06/21: Vivek Menon: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104244: 06/06/21: Vivek Menon: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104253: 06/06/21: Peter Alfke: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104270: 06/06/22: Vivek Menon: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
104234: 06/06/21: Vivek Menon: Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
    104241: 06/06/21: Ed McGettigan: Re: Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
    104246: 06/06/21: Vivek Menon: Re: Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
    104260: 06/06/22: John Adair: Re: Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
104242: 06/06/21: Tommy Thorn: XST crashes & websupport denies access
104248: 06/06/21: <sgfallows@gmail.com>: Linking/mapping code sections with Xilinx EDK
    104252: 06/06/21: Joseph: Re: Linking/mapping code sections with Xilinx EDK
    104291: 06/06/22: <sgfallows@gmail.com>: Re: Linking/mapping code sections with Xilinx EDK
104261: 06/06/22: dougeh: Xilinx Library Conversion
104262: 06/06/22: subint: Newbie in Chipscope-changes need to route bidirectional data port
    104279: 06/06/22: Symon: Re: Newbie in Chipscope-changes need to route bidirectional data port
        104303: 06/06/23: Joseph Samson: Re: Newbie in Chipscope-changes need to route bidirectional data
            104365: 06/06/26: Joseph Samson: Re: Newbie in Chipscope-changes need to route bidirectional data
    104302: 06/06/23: subint: Re: Newbie in Chipscope-changes need to route bidirectional data port
    104363: 06/06/26: subint: Re: Newbie in Chipscope-changes need to route bidirectional data port
104263: 06/06/22: Wojciech Zabolotny: Remote access to Altera FPGA via jtagd in Linux
    104266: 06/06/22: Wojciech Zabolotny: One significant correction: Remote access to Altera FPGA via jtagd
104268: 06/06/22: blisca: newbie:my ISE doesn't include old xcs30 spartan how........
    104269: 06/06/22: Aurelian Lazarut: Re: newbie:my ISE doesn't include old xcs30 spartan how........
        104274: 06/06/22: blisca: R: newbie:my ISE doesn't include old xcs30 spartan how........
    104284: 06/06/22: <ghelbig@lycos.com>: Re: newbie:my ISE doesn't include old xcs30 spartan how........
    104327: 06/06/23: blisca: R: newbie:my ISE doesn't include old xcs30 spartan how........
104271: 06/06/22: Klaus Mitskowski: Amirix AP120, U-Boot and uartlite
104272: 06/06/22: <rashid.karimov@gmail.com>: Any eval SW comes with Spartan 3E Dev board from Xilinx/Digilent ?
    104311: 06/06/23: Dave Pollum: Re: Any eval SW comes with Spartan 3E Dev board from Xilinx/Digilent ?
104283: 06/06/22: Vivek Menon: RS232 to access TX registers of Aurora
    104285: 06/06/22: Hal Murray: Re: RS232 to access TX registers of Aurora
        104456: 06/06/27: Duane Clark: Re: RS232 to access TX registers of Aurora using PPC (EDK)
            104463: 06/06/28: Duane Clark: Re: RS232 to access TX registers of Aurora using PPC (EDK)
                104488: 06/06/28: Duane Clark: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104449: 06/06/27: Vivek Menon: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104453: 06/06/27: Nathan Bialke: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104455: 06/06/27: Vivek Menon: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104457: 06/06/27: Vivek Menon: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104459: 06/06/27: Vivek Menon: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104476: 06/06/28: Vivek Menon: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104483: 06/06/28: Vivek Menon: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104495: 06/06/28: Vivek Menon: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104527: 06/06/29: Vivek Menon: Re: RS232 to access TX registers of Aurora using Chapman's UART macros (xapp 223)
104286: 06/06/22: Christopher Cole: Spartan 3E Starter Kit - diff b/t rev. C and D?
    104287: 06/06/22: Uwe Bonnes: Re: Spartan 3E Starter Kit - diff b/t rev. C and D?
104288: 06/06/22: bajaj: Aurora 4 byte interface
104289: 06/06/22: johnp: Xilinx RocketIO receiver reset problem
    104290: 06/06/22: johnp: Re: Xilinx RocketIO receiver reset problem
        104354: 06/06/25: MikeJ: Re: Xilinx RocketIO receiver reset problem
104296: 06/06/22: anand: stimulus for FPGA
    104297: 06/06/22: Mike Treseler: Re: stimulus for FPGA
        104317: 06/06/23: Ralf Hildebrandt: Re: stimulus for FPGA
            104340: 06/06/24: Ralf Hildebrandt: Re: stimulus for FPGA
    104298: 06/06/23: Mark McDougall: Re: stimulus for FPGA
        104318: 06/06/23: Mike Treseler: Re: stimulus for FPGA
        104321: 06/06/23: Hal Murray: Re: stimulus for FPGA
    104305: 06/06/23: Ricardo: Re: stimulus for FPGA
    104312: 06/06/23: anand: Re: stimulus for FPGA
    104332: 06/06/23: <ekrads@gmail.com>: Re: stimulus for FPGA
    104335: 06/06/24: Hans: Re: stimulus for FPGA
104300: 06/06/23: Marco: is picoblaze worth in my project?
    104301: 06/06/23: Falk Brunner: Re: is picoblaze worth in my project?
    104304: 06/06/23: John McCaskill: Re: is picoblaze worth in my project?
    104468: 06/06/28: Hal Murray: Re: is picoblaze worth in my project?
104313: 06/06/23: Andy: Re: xst can, but vcomp can't
104319: 06/06/23: agou: Optimization of Multiplication in FPGA
    104320: 06/06/23: Falk Brunner: Re: Optimization of Multiplication in FPGA
    104331: 06/06/23: Peter Alfke: Re: Optimization of Multiplication in FPGA
104322: 06/06/23: MM: Achieving timing in Xilinx EDK designs
    104333: 06/06/24: Joseph Samson: Re: Achieving timing in Xilinx EDK designs
        104334: 06/06/23: MM: Re: Achieving timing in Xilinx EDK designs
            104348: 06/06/25: Joseph Samson: Re: Achieving timing in Xilinx EDK designs
                104400: 06/06/26: Salil Raje: Re: Achieving timing in Xilinx EDK designs
    104469: 06/06/28: Andi: Re: Achieving timing in Xilinx EDK designs
        104480: 06/06/28: MM: Re: Achieving timing in Xilinx EDK designs
    104521: 06/06/29: Andi: Re: Achieving timing in Xilinx EDK designs
        104546: 06/06/29: MM: Re: Achieving timing in Xilinx EDK designs
104323: 06/06/23: =?iso-8859-1?q?Jaime_Andr=E9s_Aranguren_Cardona?=: Spartan3 or 3E pins to GND
    104329: 06/06/23: John_H: Re: Spartan3 or 3E pins to GND
    104330: 06/06/23: Peter Alfke: Re: Spartan3 or 3E pins to GND
    104337: 06/06/24: Dave Pollum: Re: Spartan3 or 3E pins to GND
104325: 06/06/23: Wojciech Zabolotny: Xilinx cable drivers for Linux 2.6.16?
    104328: 06/06/23: Wojciech Zabolotny: Solved: Xilinx cable drivers for Linux 2.6.16?
104326: 06/06/23: blisca: no ram core simulation with free Ise ?
    104358: 06/06/25: Joseph: Re: no ram core simulation with free Ise ?
        104369: 06/06/26: blisca: R: no ram core simulation with free Ise ?
    104377: 06/06/26: Duane Clark: Re: R: still having same error
        104383: 06/06/26: Duane Clark: Re: R: R: stillcan't access xilinxcorelib,where does modelsim looks
            104392: 06/06/26: Duane Clark: Re: R: R: R: stillcan't access xilinxcorelib,where does modelsim
            104394: 06/06/26: blisca: R: R: R: stillcan't access xilinxcorelib,where does modelsim looksfor it?
        104385: 06/06/26: blisca: R: R: still having same error
            104388: 06/06/26: blisca: R: R: stillcan't access xilinxcorelib,where does modelsim looks for it?
    104380: 06/06/26: blisca: R: still having same error
        104381: 06/06/26: Ben Jones: Re: still having same error
            104404: 06/06/27: blisca: R: still having same error
104338: 06/06/24: Eric Brombaugh: Spartan3E Starter kit on Linux?
104341: 06/06/24: <frankgerlach@gmail.com>: newbie wants to do VHDL on an FPGA
    104342: 06/06/24: Phil Hays: Re: newbie wants to do VHDL on an FPGA
    104343: 06/06/24: anand: Re: newbie wants to do VHDL on an FPGA
    104346: 06/06/25: <frankgerlach@gmail.com>: Re: newbie wants to do VHDL on an FPGA
    104350: 06/06/25: John Adair: Re: newbie wants to do VHDL on an FPGA
        104361: 06/06/26: Mike Harrison: Re: newbie wants to do VHDL on an FPGA
    104355: 06/06/25: <frankgerlach@gmail.com>: Re: newbie wants to do VHDL on an FPGA
    104356: 06/06/25: <frankgerlach@gmail.com>: Re: newbie wants to do VHDL on an FPGA
    104357: 06/06/25: John Adair: Re: newbie wants to do VHDL on an FPGA
    104370: 06/06/26: radarman: Re: newbie wants to do VHDL on an FPGA
    104378: 06/06/26: Philip Freidin: Re: newbie wants to do VHDL on an FPGA
104344: 06/06/25: savs: multisource on signal in XPS
    104345: 06/06/25: savs: Re: multisource on signal in XPS
        104359: 06/06/26: Zara: Re: multisource on signal in XPS
            104362: 06/06/26: Zara: Re: multisource on signal in XPS
        104374: 06/06/26: MM: Re: multisource on signal in XPS
            104396: 06/06/26: Sean Durkin: Re: multisource on signal in XPS
    104360: 06/06/26: savs: Re: multisource on signal in XPS
    104384: 06/06/26: savs: Re: multisource on signal in XPS
    104391: 06/06/26: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: multisource on signal in XPS
    104416: 06/06/27: savs: Re: multisource on signal in XPS
104352: 06/06/25: avl: Test:PRBS
    104353: 06/06/25: Peter Alfke: Re: Test:PRBS
104364: 06/06/26: tamania: problem in simulating FFT core on ISE 7.1
    105218: 06/07/18: bijoy: Re: problem in simulating FFT core on ISE 7.1
104366: 06/06/26: sjulhes: VHDL model for Micron SDRAM simulation ?
    104368: 06/06/26: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: VHDL model for Micron SDRAM simulation ?
    104371: 06/06/26: Sean Durkin: Re: VHDL model for Micron SDRAM simulation ?
        104375: 06/06/26: sjulhes: Re: VHDL model for Micron SDRAM simulation ?
            104379: 06/06/26: Duane Clark: Re: VHDL model for Micron SDRAM simulation ?
                104434: 06/06/27: sjulhes: Re: VHDL model for Micron SDRAM simulation ?
            104433: 06/06/27: Nial Stewart: Re: VHDL model for Micron SDRAM simulation ?
104367: 06/06/26: Hendrik: Synthesis problem with ranged integer
104372: 06/06/26: Simon Heinzle: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
    104373: 06/06/26: Ben Jones: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
    104389: 06/06/26: <fpga_toys@yahoo.com>: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
        104398: 06/06/26: c d saunter: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
            104424: 06/06/27: Simon Heinzle: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
                104437: 06/06/27: c d saunter: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
                    104443: 06/06/27: Simon Heinzle: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
    104390: 06/06/26: Hans: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
        104425: 06/06/27: Simon Heinzle: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
104376: 06/06/26: karrelsj: PicoBlaze and DDR Ram
    104382: 06/06/26: Peter Alfke: Re: PicoBlaze and DDR Ram
    104386: 06/06/26: Falk Brunner: Re: PicoBlaze and DDR Ram
    104393: 06/06/27: Jim Granville: Re: PicoBlaze and DDR Ram
    104462: 06/06/27: karrelsj: Re: PicoBlaze and DDR Ram
104387: 06/06/26: John Adair: Raggedstone1 Brackets
104395: 06/06/26: lecroy7200@chek.com: Xilinx ML461 memory board, whats the real story?
    104446: 06/06/27: Peter Alfke: Re: Xilinx ML461 memory board, whats the real story?
    104484: 06/06/28: lecroy7200@chek.com: Re: Xilinx ML461 memory board, whats the real story?
    104797: 06/07/06: lecroy7200@chek.com: Re: Xilinx ML461 memory board, whats the real story?
104399: 06/06/26: Roger: ISE WebPack 8.2
    104401: 06/06/26: Tommy Thorn: Re: ISE WebPack 8.2
        104402: 06/06/26: Roger: Re: ISE WebPack 8.2
            104403: 06/06/27: Jim Granville: Re: ISE WebPack 8.2
            104412: 06/06/27: Mike Harrison: Re: ISE WebPack 8.2
                104414: 06/06/27: Uwe Bonnes: Re: ISE WebPack 8.2
104408: 06/06/26: <tali.cliff@gmail.com>: Accelerated Bioinformatics Data Processing Solutions
104410: 06/06/26: Srikanth BJ: Xilinx 7.1 ISE : Problem while doing post place and route simulation
104413: 06/06/27: Vassili Savinov: Webpack ISE 8 and Vertex4 XC4VLX60
    104418: 06/06/27: Aurelian Lazarut: Re: Webpack ISE 8 and Vertex4 XC4VLX60
    104419: 06/06/27: Jon Beniston: Re: Webpack ISE 8 and Vertex4 XC4VLX60
104415: 06/06/27: Uwe Bonnes: XC3SE available
104417: 06/06/27: savs: Number of bonded IOB's
    104420: 06/06/27: Aurelian Lazarut: Re: Number of bonded IOB's
    104421: 06/06/27: Uwe Bonnes: Re: Number of bonded IOB's
104422: 06/06/27: Gilles GEORGES: Synplify & Fedora core 5
    104426: 06/06/27: Simon Heinzle: Re: Synplify & Fedora core 5
        104432: 06/06/27: Gilles GEORGES: Re: Synplify & Fedora core 5
    104441: 06/06/27: Duane Clark: Re: Synplify & Fedora core 5
        104442: 06/06/27: Gilles GEORGES: Re: Synplify & Fedora core 5
104423: 06/06/27: lenile84: need help plz.
    104430: 06/06/27: <lb.edc@telenet.be>: Re: need help plz.
104427: 06/06/27: subint: Help in the platform studio(EDK)
    104473: 06/06/28: subint: Help in the platform studio(EDK)
    104475: 06/06/28: Antti: Re: Help in the platform studio(EDK)
    104505: 06/06/28: Erik Widding: Re: Help in the platform studio(EDK)
    104511: 06/06/28: subint: Re: Help in the platform studio(EDK)
    104512: 06/06/28: subint: Re: Help in the platform studio(EDK)
    104514: 06/06/28: subint: Re: Help in the platform studio(EDK)
    104515: 06/06/29: Antti: Re: Help in the platform studio(EDK)
    104523: 06/06/29: subint: Re: Help in the platform studio(EDK)
104428: 06/06/27: The Mighty Shaman: XilFatFS and CF...
    104444: 06/06/27: Eli Hughes: Re: XilFatFS and CF...
        104634: 06/07/03: TheMightyShaman: Re: XilFatFS and CF...
104429: 06/06/27: <user@domain.invalid>: Once synthesized RAMs are vanishing in WebPACK 8.1i03
    104431: 06/06/27: <user@domain.invalid>: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
    104438: 06/06/27: Aurelian Lazarut: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
        104439: 06/06/27: Aurelian Lazarut: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
            104447: 06/06/27: Sietse Achterop: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
                104448: 06/06/27: mk: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
                    104451: 06/06/27: Sietse Achterop: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
                104472: 06/06/28: Aurelian Lazarut: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
                    104545: 06/06/29: Sietse Achterop: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
104435: 06/06/27: Matt Blanton: dcm clkin_divide_by_2
    104440: 06/06/27: Austin Lesea: Re: dcm clkin_divide_by_2
104436: 06/06/27: tester: Montavista linux Xilinx Virtex4 ML403
104461: 06/06/27: Weng Tianxiang: Preserve patent materials through a notary
    104474: 06/06/28: Gabor: Re: Preserve patent materials through a notary
        104489: 06/06/29: Jim Granville: Re: Preserve patent materials through a notary
    104478: 06/06/28: Weng Tianxiang: Re: Preserve patent materials through a notary
    104499: 06/06/28: Weng Tianxiang: Re: Preserve patent materials through a notary
    104530: 06/06/29: Rene Tschaggelar: Re: Preserve patent materials through a notary
    104534: 06/06/29: Weng Tianxiang: Re: Preserve patent materials through a notary
104464: 06/06/27: <zhanglingmu@gmail.com>: X-Ray Inspection System
104466: 06/06/27: <andrewgschmidt@gmail.com>: PLB IPIF Master Read Failure
104467: 06/06/28: MikeJ: Spartan3e starter kit vga mod
    104574: 06/06/29: <deunhido@gmail.com>: Re: Spartan3e starter kit vga mod
        104575: 06/06/30: Mark McDougall: Re: Spartan3e starter kit vga mod
            104592: 06/06/30: Eric Crabill: Re: Spartan3e starter kit vga mod
                104598: 06/06/30: John_H: Re: Spartan3e starter kit vga mod
            104706: 06/07/04: MikeJ: Re: Spartan3e starter kit vga mod
    104597: 06/06/30: <deunhido@gmail.com>: Re: Spartan3e starter kit vga mod
    104608: 06/06/30: JJ: Re: Spartan3e starter kit vga mod
    104768: 06/07/05: Keith: Re: Spartan3e starter kit vga mod
104482: 06/06/28: Weng Tianxiang: Reverse engineering has the protection of law in the U.S.
    104508: 06/06/28: Austin Lesea: Re: Reverse engineering has the protection of law in the U.S.
    104510: 06/06/28: rickman: Re: Reverse engineering has the protection of law in the U.S.
104485: 06/06/28: Alex: Spartan 3E, Output File
    104491: 06/06/28: Duane Clark: Re: Spartan 3E, Output File
104486: 06/06/28: <jacob.bower@gmail.com>: Synplify prepending Z's to top level signal names in Verilog
    104490: 06/06/28: John_H: Re: Synplify prepending Z's to top level signal names in Verilog
    104500: 06/06/28: <jacob.bower@gmail.com>: Re: Synplify prepending Z's to top level signal names in Verilog
    104551: 06/06/29: Arnaud: Re: Synplify prepending Z's to top level signal names in Verilog
104487: 06/06/28: <jeffnewcomb@nci-usa.com>: Virtex5 Availability
    104492: 06/06/28: John Adair: Re: Virtex5 Availability
    104498: 06/06/28: Ed McGettigan: Re: Virtex5 Availability
        104506: 06/06/28: Ed McGettigan: Re: Virtex5 Availability
            104507: 06/06/28: Austin Lesea: Re: Virtex5 Availability
    104502: 06/06/28: <jeffnewcomb@nci-usa.com>: Re: Virtex5 Availability
104493: 06/06/28: <visualfor@gmail.com>: DDR2 at 125MHz or lower with Cyclone2
    104496: 06/06/28: John_H: Re: DDR2 at 125MHz or lower with Cyclone2
    104497: 06/06/28: Tim: Re: DDR2 at 125MHz or lower with Cyclone2
104494: 06/06/28: Kolja Waschk: How to comm with Altera JTAG UART (from custom host software)?
    104593: 06/06/30: The Big Lebowski: Re: How to comm with Altera JTAG UART (from custom host software)?
    104623: 06/07/02: Antti: Re: How to comm with Altera JTAG UART (from custom host software)?
104501: 06/06/28: mk: xilinx ml423 boards available ?
104504: 06/06/28: bart: ANNC: x8 PCI Express w/ FPGA Webcast
104513: 06/06/28: rajeev: NCO Clock driven Designs in FPGA
    104536: 06/06/29: John_H: Re: NCO Clock driven Designs in FPGA
    104547: 06/06/29: Ray Andraka: Re: NCO Clock driven Designs in FPGA
    104552: 06/06/29: Ben Jackson: Re: NCO Clock driven Designs in FPGA
104516: 06/06/29: my.king: EDK: Using DCR bus on ML310-based project
    104602: 06/06/30: Guru: Re: EDK: Using DCR bus on ML310-based project
        104685: 06/07/04: eric: Re: EDK: Using DCR bus on ML310-based project
    104688: 06/07/04: my.king: Re: EDK: Using DCR bus on ML310-based project
104518: 06/06/29: Ndf: Stopping the clock for power management
    104561: 06/06/29: Gabor: Re: Stopping the clock for power management
    104563: 06/06/30: Jim Granville: Re: Stopping the clock for power management
    104565: 06/06/29: <mikeandmax@aol.com>: Re: Stopping the clock for power management
        104579: 06/06/30: Ndf: Re: Stopping the clock for power management
104519: 06/06/29: tester: Problem to extend Xilinx GSRD Design
    104533: 06/06/29: Ed McGettigan: Re: Problem to extend Xilinx GSRD Design
    104538: 06/06/29: MM: Re: Problem to extend Xilinx GSRD Design
        104554: 06/06/29: Ed McGettigan: Re: Problem to extend Xilinx GSRD Design
            104560: 06/06/29: MM: Re: Problem to extend Xilinx GSRD Design
                104567: 06/06/29: Ed McGettigan: Re: Problem to extend Xilinx GSRD Design
                    104571: 06/06/29: MM: Re: Problem to extend Xilinx GSRD Design
                        104591: 06/06/30: Ed McGettigan: Re: Problem to extend Xilinx GSRD Design
                            104644: 06/07/03: tester: Re: Problem to extend Xilinx GSRD Design
104520: 06/06/29: Uwe Bonnes: Xilinx BUFGMUX Setup Time requirement clarification needed
    104558: 06/06/29: Eric Crabill: Re: Xilinx BUFGMUX Setup Time requirement clarification needed
    104566: 06/06/29: Peter Alfke: Re: Xilinx BUFGMUX Setup Time requirement clarification needed
        104587: 06/06/30: Austin Lesea: Re: Xilinx BUFGMUX Setup Time requirement clarification needed
104524: 06/06/29: rnbrady: Generic synthesis target in Synplify Pro
    104525: 06/06/29: Ben Jones: Re: Generic synthesis target in Synplify Pro
    104526: 06/06/29: subint: Re: Generic synthesis target in Synplify Pro
    104529: 06/06/29: rnbrady: Re: Generic synthesis target in Synplify Pro
    104531: 06/06/29: Andy: Re: Generic synthesis target in Synplify Pro
    104578: 06/06/30: Thomas Stanka: Re: Generic synthesis target in Synplify Pro
104528: 06/06/29: Vivek Menon: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
    104532: 06/06/29: Aurelian Lazarut: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
        104549: 06/06/29: Ray Andraka: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
    104540: 06/06/29: Vivek Menon: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
    104548: 06/06/29: Ray Andraka: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
    104550: 06/06/29: Vivek Menon: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
    104711: 06/07/04: <frank.frankli@gmail.com>: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
104535: 06/06/29: Vivek Menon: help downloading picoblaze from xilinx
    104537: 06/06/29: dscolson@rcn.com: Re: help downloading picoblaze from xilinx
    104539: 06/06/29: Vivek Menon: Re: help downloading picoblaze from xilinx
    104541: 06/06/29: Vivek Menon: Re: help downloading picoblaze from xilinx (xapp627.zip)
    104542: 06/06/29: Andy Peters: Re: help downloading picoblaze from xilinx (xapp627.zip)
104543: 06/06/29: <burn.sir@gmail.com>: Altium Designer LiveDesign Evaluation Kits (once again)
    104544: 06/06/29: Roland: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104553: 06/06/29: Kolja Waschk: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104570: 06/06/30: Mark McDougall: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104588: 06/06/30: Rene Tschaggelar: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104605: 06/06/30: radarman: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104609: 06/06/30: Antti: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104617: 06/07/01: radarman: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104622: 06/07/02: Antti: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104640: 06/07/03: radarman: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104641: 06/07/03: Antti: Re: Altium Designer LiveDesign Evaluation Kits (once again)
    104766: 06/07/05: <burn.sir@gmail.com>: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104555: 06/06/29: Paul Marciano: How to evaluate the space efficiency of a historic design.
    104556: 06/06/29: Paul Marciano: Re: How to evaluate the space efficiency of a historic design.
    104557: 06/06/29: mk: Re: How to evaluate the space efficiency of a historic design.
    104562: 06/06/30: Jim Granville: Re: How to evaluate the space efficiency of a historic design.
    104564: 06/06/29: Tommy Thorn: Re: How to evaluate the space efficiency of a historic design.
    104568: 06/06/29: JJ: Re: How to evaluate the space efficiency of a historic design.
    104569: 06/06/30: M.Randelzhofer: Re: How to evaluate the space efficiency of a historic design.
    104577: 06/06/30: backhus: Re: How to evaluate the space efficiency of a historic design.
104559: 06/06/29: blisca: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
    104590: 06/06/30: Dave Pollum: Re: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
    104596: 06/06/30: blisca: R: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
        104618: 06/07/01: blisca: R: R: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
    104616: 06/07/01: Dave Pollum: Re: R: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
104572: 06/06/29: PeterC: Carry-chain based tapped delay line in Spartan3 - resolution? PVT variability?
    104573: 06/06/30: John_H: Re: Carry-chain based tapped delay line in Spartan3 - resolution?
        104606: 06/06/30: John Larkin: Re: Carry-chain based tapped delay line in Spartan3 - resolution? PVT variability?
    104583: 06/06/30: Gabor: Re: Carry-chain based tapped delay line in Spartan3 - resolution? PVT variability?
104576: 06/06/29: orthogonal: Help on simulating ddr controler generated by MIG!!
    104581: 06/06/30: subint: Re: Help on simulating ddr controler generated by MIG!!
104580: 06/06/30: <eem3kc@gmail.com>: Nu Horizon Xilinx 1500 fpga board
104582: 06/06/30: colin: rocketIO simulation
    104585: 06/06/30: MM: Re: rocketIO simulation
104584: 06/06/30: Hampus Thorell: lwIP on Xilinx Virtex 2 Pro
104586: 06/06/30: Morten Leikvoll: Missing ISE HTML online help (pdf sucks!)
    104589: 06/06/30: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Missing ISE HTML online help (pdf sucks!)
104594: 06/06/30: Vivek Menon: Pointers for sending data using ethernet connection from V2Pro
    104595: 06/06/30: Symon: Re: Pointers for sending data using ethernet connection from V2Pro
    104626: 06/07/02: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Pointers for sending data using ethernet connection from V2Pro
    104947: 06/07/10: Vivek Menon: Re: Pointers for sending data using ethernet connection from V2Pro
    105237: 06/07/18: Vivek Menon: Re: Pointers for sending data using ethernet connection from V2Pro
104600: 06/06/30: blisca: minimal connections so that a xcv200e talks with pc
104601: 06/06/30: Guru: Re: Problem to extend Xilinx GSRD Design
104603: 06/06/30: ZHI: How to control the uart
    104604: 06/06/30: radarman: Re: How to control the uart
    104613: 06/07/01: Duane Clark: Re: How to control the uart
    104615: 06/07/01: ZHI: Re: How to control the uart
    104627: 06/07/02: ZHI: Re: How to control the uart
104607: 06/06/30: <john.orlando@gmail.com>: Re: Problem to extend Xilinx GSRD Design


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