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Messages from 104500

Article: 104500
Subject: Re: Synplify prepending Z's to top level signal names in Verilog
From: jacob.bower@gmail.com
Date: 28 Jun 2006 15:15:34 -0700
Links: << >>  << T >>  << A >>
Oh well, I guess I'm at the mercy of Synplicity and/or my perl skills.

Thanks for trying though,
- Jacob

John_H wrote:
> I tried a few workaround possibilities with no joy.  It looks like you're
> stuck with the Z (or z).  \Literals, no.  Attribute syn_keep, no.  Attribute
> syn_edif_scalar_format in three flavors, no.  IBUF instantiated, no.
>
> Sounds like it's time for an enhancement request!  I'd love to know if there
> *was* a workaround outside of filtering the edif.
>
> <jacob.bower@gmail.com> wrote in message
> news:1151521299.696601.186170@i40g2000cwc.googlegroups.com...
> > Hi,
> >
> > Does anyone know of a way to stop Synplify from pre-pending a "Z" to
> > names of top-level entity I/O signals which begin with an underscore
> > ("_") when generating EDIF?
> >
> > Thanks.
> > - Jacob
> >


Article: 104501
Subject: xilinx ml423 boards available ?
From: mk <kal*@dspia.*comdelete>
Date: Wed, 28 Jun 2006 22:36:33 GMT
Links: << >>  << T >>  << A >>
Hi,
I have seen mention of a board called ML423 here
http://www.xilinx.com/bvdocs/userguides/ug087.pdf. Hitechglobal seems
to carry ML421 but I can't find any more info on any other boards. Is
ML423 available ?

Article: 104502
Subject: Re: Virtex5 Availability
From: jeffnewcomb@nci-usa.com
Date: 28 Jun 2006 15:49:29 -0700
Links: << >>  << T >>  << A >>

Ed McGettigan wrote:
> jeffnewcomb@nci-usa.com wrote:
> > Can anyone tell me the true availability of Xilinx Virtex5 Engineering
> > samples ? I have talked to distributors who say they can't get V5 parts
> > until next year but I keep seeing Xilinx ads for the V5 saying shipping
> > now. Does anyone know if samples would be available in the Sept time
> > frame and how does one go about getting a couple of parts?
> >
>
> We are shipping X5VLX50 and XC5VLX110 in the -CES1 speed grade and the
> FF676 and FF1153 packages.  There will be a lead time between placing
> an order and getting them as we are in the limited engineering sample
> phase, but your distributor sales person should take your order and
> then get back to you with a delivery date.
>
> Ed McGettigan
> --
> Xilinx Inc.

Thank you for the information. We are looking to use the  X5VLX50 in a
FF676 package but were discouraged from designing with the Virtex 5
because there wouldn't be any parts until next year. We wouldn't go
into to production with our product until next year but would need some
samples in Sep. in order to debug prototypes.

Jeff Newcomb
NCI


Article: 104503
Subject: Re: keys to the Kingdom
From: David R Brooks <davebXXX@iinet.net.au>
Date: Wed, 28 Jun 2006 15:23:00 -0800
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> David,
> 
> As to convenience,  place a lithium coin cell on the pcb per the app
> note.  Ask the software to generate a random key for you (or pick one
> yourself), send the key to the JTAG port.  Verify the key can be written
> and read, then write it in secure mode (so it can not be read out again
> without it being erased immediately).  Program eeprom or other memory
> with encrypted bitstream.
> 
[snip]
Regrettably, that puts Xilinx out of our new product development project 
(vehicle engine management). The safety people will not tolerate a 
battery in the unit: when the power is off, there must be *no* secondary 
energy source present.

Article: 104504
Subject: ANNC: x8 PCI Express w/ FPGA Webcast
From: "bart" <bart.borosky@latticesemi.com>
Date: 28 Jun 2006 16:38:59 -0700
Links: << >>  << T >>  << A >>
Lattice is holding a webcast tomorrow, Thursday, June 29, "Designing
FPGA-based PCI Express x1 / x4 / x8 Solutions." The presenters will be
Brian Daellenbach from Northwest Logic and Alex Gargarita, from our IP
marketing group.

If you're interested, the event takes place live at 11am Pacific, 18:00
GMT. In addition, you will be able to view this webcast archive
on-demand, at your convenience, starting 24-hours after the live event
takes place.

You can register by clicking:
http://www.latticesemi.com/corporate/webcasts/designingfpgabasedpciexpr/index.cfm

Bart Borosky, Lattice


Article: 104505
Subject: Re: Help in the platform studio(EDK)
From: "Erik Widding" <widding@birger.com>
Date: 28 Jun 2006 16:43:38 -0700
Links: << >>  << T >>  << A >>
> subint schrieb:
> > I am using the platform studio first time.I like to know how i can add
> > my testbenches and remove the microblaze processor from the setup.
> >        I am trying to generate the controller for my V4MB lx60 board
> > and i want to test the ddr in the board.From the tool(platform studio)
> > i can select the pheripherals and the processor etc but didnt have any
> > idea how can i use this to test my ddr.I tried to generate the hdl
> > code.But all the controllers are ipcores(black box) and i wont be able
> > to synthesize it using xilinx ise(library for these ipcores are
> > missing).

Subin,

You would have to create an IP core that is a either an OPB or PLB bus
master.  This is not a difficult task.  You would first want to
understand the IBM CoreConnect buses through the documentation from IBM
and Xilinx.  The IBM documentation is more complete, but the Xilinx
documentation is important as it will enlighten you as to the
limitations of the Xilinx implementation of the memory controllers and
such.


Antti wrote:
> EDK supports
>
> 1) MicroBlaze
> 2) PowerPC
>
> if you want to use EDK for any other purpose (eg no supported CPU from
> the list of supported CPU'S) then this is:
>
> "DO NOT"
>
> thing.


Antti,

As one of the more creative guys in the newsgroup, who likes to
experiment a good deal, I would have actually thought you would have
been supportive of the notion of using Platform Studio without a
processor.  The only limitation is that at least one IP core needs to
be a bus master, or the system created isn't going to do anything at
all.

We have done a number of designs like this, and have found it both very
useful and productive.  For example, we designed a PCI card that had a
bridge between the system's PCI bus and the PLB bus inside the chip.
The only master was the outside system communicating over PCI and a DMA
engine in the bridge.  It went remarkably well.  We did create our own
bridge by wrapping around the Xilinx PCI logicore.  No MicroBlaze or
PowerPC anywhere in the design.

On a scale of one to ten, I would rate using the Platform Studio
without a processor, and creating an OPB bus master about a three, only
because of the complexity of doing a first bus master.  The way the
question was asked by the original poster, might suggest that this idea
might not be a good recomendation for him just yet, as he may want to
start with something a little simpler.

So, respectfully, I would have to say, this is definitely a "DO" thing,
so long as the implementer has a good understanding of the Platform
Studio and the IBM CoreConnect architecture.


Regards,
Erik.

---
Erik Widding
President
Birger Engineering, Inc.

 (mail) 100 Boylston St #1070; Boston, MA 02116
(voice) 617.695.9233
  (fax) 617.695.9234
  (web) http://www.birger.com


Article: 104506
Subject: Re: Virtex5 Availability
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Wed, 28 Jun 2006 17:20:36 -0700
Links: << >>  << T >>  << A >>
jeffnewcomb@nci-usa.com wrote:
> 
> Thank you for the information. We are looking to use the  X5VLX50 in a
> FF676 package but were discouraged from designing with the Virtex 5
> because there wouldn't be any parts until next year. We wouldn't go
> into to production with our product until next year but would need some
> samples in Sep. in order to debug prototypes.
> 

If you want to design with Virtex-5 and understand that the devices
are engineering samples and not production devices then be insistent
with your sales contact and get an official order placed.  One thing
is for certain, if you don't place an order you'll never get the parts.

Ed McGettigan
--
Xilinx Inc.

Article: 104507
Subject: Re: Virtex5 Availability
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 28 Jun 2006 20:20:58 -0700
Links: << >>  << T >>  << A >>
I will second Ed's comments,

We have 5VLX110, 5VLX85, 5VLX50, and 5VLX30 ES parts.

There are not a lot of them, as we decided that the initial early 
release would be much smaller than what we did with V4.  We greatly 
reduced the number of customers we had to support for the early adoption 
phase.  We have not yet announced the beginning of general unrestricted ES.

If you wish to get general unrestricted ES parts, you must sign up NOW. 
  If you wish to be part of the early adoption program, I believe that 
is also possible.

We are being much more conservative after the V4 MGT issues.  To say we 
are "ready" now requires a much higher level of verification, and 
characterization.

If you have any concerns, then wait for the unrestricted ES 
announcement.  But you may find yourself at the end of a long line.

Austin


Ed McGettigan wrote:

> jeffnewcomb@nci-usa.com wrote:
> 
>>
>> Thank you for the information. We are looking to use the  X5VLX50 in a
>> FF676 package but were discouraged from designing with the Virtex 5
>> because there wouldn't be any parts until next year. We wouldn't go
>> into to production with our product until next year but would need some
>> samples in Sep. in order to debug prototypes.
>>
> 
> If you want to design with Virtex-5 and understand that the devices
> are engineering samples and not production devices then be insistent
> with your sales contact and get an official order placed.  One thing
> is for certain, if you don't place an order you'll never get the parts.
> 
> Ed McGettigan
> -- 
> Xilinx Inc.

Article: 104508
Subject: Re: Reverse engineering has the protection of law in the U.S.
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 28 Jun 2006 20:23:52 -0700
Links: << >>  << T >>  << A >>
Weng,

Yes, reverse engineering has a long, and honorable history.

If I see how it is done by another, and then do it for much less cost, 
with more features or more performance, without infringing on any 
existing patents, then I am well within the law.

Austin


Weng Tianxiang wrote:

> Hi,
> Do you know "reverse engineering has the protection of law"?
> 
> A good paper in
> http://www.fpgajournal.com/articles_2006/20060627_security2.htm
> tell the following story:
> the Supreme Court ruling that "A trade secret law, however, does not
> offer protection against discovery by fair and honest means, such as by
> independent invention, accidental disclosure, or by so-called reverse
> engineering, that is by starting with the known product and working
> backward to divine the process which aided in its development or
> manufacture."
> 
> I don't know it until today after reading a reference by Austin Lesea
> and I would like others to share the information.
> 
> Weng
> 

Article: 104509
Subject: Re: keys to the Kingdom
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 28 Jun 2006 20:31:23 -0700
Links: << >>  << T >>  << A >>
David,

OK.  Then you are also unable to comply with FIPS-140-2.

If you need not comply with that standard, then we are right back in 
with V5.

There are many tricks up our sleeves...remember my ONLY complaint is 
that an efuse solution is not compliant with NIST standards on secure 
SYSTEMS.

If you do not need to meet that standard, then, we have ways....

Austin

PS:  engine controls?  What engine needs the power of a FPGA???


David R Brooks wrote:

> Austin Lesea wrote:
> 
>> David,
>>
>> As to convenience,  place a lithium coin cell on the pcb per the app
>> note.  Ask the software to generate a random key for you (or pick one
>> yourself), send the key to the JTAG port.  Verify the key can be written
>> and read, then write it in secure mode (so it can not be read out again
>> without it being erased immediately).  Program eeprom or other memory
>> with encrypted bitstream.
>>
> [snip]
> Regrettably, that puts Xilinx out of our new product development project 
> (vehicle engine management). The safety people will not tolerate a 
> battery in the unit: when the power is off, there must be *no* secondary 
> energy source present.

Article: 104510
Subject: Re: Reverse engineering has the protection of law in the U.S.
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 28 Jun 2006 20:33:05 -0700
Links: << >>  << T >>  << A >>
Weng Tianxiang wrote:
> Hi,
> Do you know "reverse engineering has the protection of law"?
>
> A good paper in
> http://www.fpgajournal.com/articles_2006/20060627_security2.htm
> tell the following story:
> the Supreme Court ruling that "A trade secret law, however, does not
> offer protection against discovery by fair and honest means, such as by
> independent invention, accidental disclosure, or by so-called reverse
> engineering, that is by starting with the known product and working
> backward to divine the process which aided in its development or
> manufacture."
>
> I don't know it until today after reading a reference by Austin Lesea
> and I would like others to share the information.

Reverse Engineering is a valid means of circumventing a Trade Secret.
But it will not get around Copyright or Patent.  A Trade Secret
requires that the holder take all responsibility for keeping it a
secret.  Other than stealing your paperwork, pretty much any way of
figuring out the Trade Secret is valid, including Reverse Engineering.
That s why so many documents are labeled "Trade Secret" or
"Confidential".  They are only protected if labeled as such and you
only give them to persons who have signed an NDA (non-disclosure
agreement).  Then if the docs are leaked out and you can identify who
leaked, they are liable for damages for your losses.

The fear of reverse engineering is why chips are sometimes private
labeled or the chip markings removed or even the module completely
potted.  Of course there are always ways around most of these
techniques, but it ends up being a game of how much will one party
spend to protect a secret and how much will another party spend to
reveal a secret.


Article: 104511
Subject: Re: Help in the platform studio(EDK)
From: "subint" <subin.82@gmail.com>
Date: 28 Jun 2006 21:39:41 -0700
Links: << >>  << T >>  << A >>

Antti wrote:

> If you want to play around with DDR memory then take some DDR IP core
> any play with it.
>
> Antti

Hi Antti,
     Do you know from where i get a free DDR IP core.My ddr is
MT46V32M16 -6 and the board i am using is  a Memec V4
board(DS-BD-V4LX60MB rev-3).And there is daugter card through which i
connect the fpga to the 922T ARM core.
Thanks in advance
regards
subin


Article: 104512
Subject: Re: Help in the platform studio(EDK)
From: "subint" <subin.82@gmail.com>
Date: 28 Jun 2006 21:47:39 -0700
Links: << >>  << T >>  << A >>
Hai Erik,
        Thanks for the detailed reply.But i am realy a newcomer in this
field.I didn't fully understand it. and i wont be able to calculate how
much time it will take.
regards
subin

Erik Widding wrote:
>
> Subin,
>
> You would have to create an IP core that is a either an OPB or PLB bus
> master.  This is not a difficult task.  You would first want to
> understand the IBM CoreConnect buses through the documentation from IBM
> and Xilinx.  The IBM documentation is more complete, but the Xilinx
> documentation is important as it will enlighten you as to the
> limitations of the Xilinx implementation of the memory controllers and
> such.
> 
>


Article: 104513
Subject: NCO Clock driven Designs in FPGA
From: "rajeev" <shuklrajeev@gmail.com>
Date: 28 Jun 2006 23:25:26 -0700
Links: << >>  << T >>  << A >>
Hi everyone,
I have a few doubts that are not being addressed in fpga groups(at
least i could not find the one ) though it is very common in DSP design
using FPGAs.

1. In many a communication receiver systems a resampler (NCO based) is
required. The output of the resampler is fed to other logics. Can NCO
output be used to drive the portion of the design ? as is sayed that in
FPGA clock derived from (combinational/sequential) logics should be
avoided and whenever a rate change is required use enable signal
instead. But this approach requires the whole design to be run at the
highest clock consuming much more  power.What could be the power
efficent method of doing the same.
Most common example is a CIC filter used for large rate change (Not by
integer factor but rather rate change is driven by a NCO) where input
is at much higher rate while the output is at lower rate.

2. If at all NCO is used for clocking the design that is required to
run at much slower speed what care should be the taken for NCO  master
clock driving NCO , to NCO output clock ? (I feel higher the ratio
lower the jitter will be).

3. Can NCO clock be further used to drive a DCM to produce a high freq
clock that can be used for serial MAC fir (for efficient fpga fabric
usage.) 

regards.
rajeev shukla.


Article: 104514
Subject: Re: Help in the platform studio(EDK)
From: "subint" <subin.82@gmail.com>
Date: 28 Jun 2006 23:25:50 -0700
Links: << >>  << T >>  << A >>
Hi Erik,
          Tnaks for the reply.Actually i am a newbie in this field.Can
u please explain it in  more detail.like the steps i needed for this.
Thanks in advance
regards
subin

Erik Widding wrote:
> > subint schrieb:
> > > I am using the platform studio first time.I like to know how i can add
> > > my testbenches and remove the microblaze processor from the setup.
> > >        I am trying to generate the controller for my V4MB lx60 board
> > > and i want to test the ddr in the board.From the tool(platform studio)
> > > i can select the pheripherals and the processor etc but didnt have any
> > > idea how can i use this to test my ddr.I tried to generate the hdl
> > > code.But all the controllers are ipcores(black box) and i wont be able
> > > to synthesize it using xilinx ise(library for these ipcores are
> > > missing).
>
> Subin,
>
> You would have to create an IP core that is a either an OPB or PLB bus
> master.  This is not a difficult task.  You would first want to
> understand the IBM CoreConnect buses through the documentation from IBM
> and Xilinx.  The IBM documentation is more complete, but the Xilinx
> documentation is important as it will enlighten you as to the
> limitations of the Xilinx implementation of the memory controllers and
> such.
>
>
> Antti wrote:
> > EDK supports
> >
> > 1) MicroBlaze
> > 2) PowerPC
> >
> > if you want to use EDK for any other purpose (eg no supported CPU from
> > the list of supported CPU'S) then this is:
> >
> > "DO NOT"
> >
> > thing.
>
>
> Antti,
>
> As one of the more creative guys in the newsgroup, who likes to
> experiment a good deal, I would have actually thought you would have
> been supportive of the notion of using Platform Studio without a
> processor.  The only limitation is that at least one IP core needs to
> be a bus master, or the system created isn't going to do anything at
> all.
>
> We have done a number of designs like this, and have found it both very
> useful and productive.  For example, we designed a PCI card that had a
> bridge between the system's PCI bus and the PLB bus inside the chip.
> The only master was the outside system communicating over PCI and a DMA
> engine in the bridge.  It went remarkably well.  We did create our own
> bridge by wrapping around the Xilinx PCI logicore.  No MicroBlaze or
> PowerPC anywhere in the design.
>
> On a scale of one to ten, I would rate using the Platform Studio
> without a processor, and creating an OPB bus master about a three, only
> because of the complexity of doing a first bus master.  The way the
> question was asked by the original poster, might suggest that this idea
> might not be a good recomendation for him just yet, as he may want to
> start with something a little simpler.
>
> So, respectfully, I would have to say, this is definitely a "DO" thing,
> so long as the implementer has a good understanding of the Platform
> Studio and the IBM CoreConnect architecture.
>
>
> Regards,
> Erik.
>
> ---
> Erik Widding
> President
> Birger Engineering, Inc.
>
>  (mail) 100 Boylston St #1070; Boston, MA 02116
> (voice) 617.695.9233
>   (fax) 617.695.9234
>   (web) http://www.birger.com


Article: 104515
Subject: Re: Help in the platform studio(EDK)
From: "Antti" <Antti.Lukats@xilant.com>
Date: 29 Jun 2006 00:09:02 -0700
Links: << >>  << T >>  << A >>
subint schrieb:

> Antti wrote:
>
> > If you want to play around with DDR memory then take some DDR IP core
> > any play with it.
> >
> > Antti
>
> Hi Antti,
>      Do you know from where i get a free DDR IP core.My ddr is
> MT46V32M16 -6 and the board i am using is  a Memec V4
> board(DS-BD-V4LX60MB rev-3).And there is daugter card through which i
> connect the fpga to the 922T ARM core.
> Thanks in advance
> regards
> subin

http://www.opencores.org/projects.cgi/web/ddr_sdr/overview

http://www.xilinx.com/bvdocs/appnotes/xapp709.pdf

takes 2 minutes to find those BTW

Antti


Article: 104516
Subject: EDK: Using DCR bus on ML310-based project
From: "my.king" <king.azman@gmail.com>
Date: 29 Jun 2006 00:47:15 -0700
Links: << >>  << T >>  << A >>
Hi,

I'm working with the ML310 eval board. Is there anyone who has a
working example on how to create a custom IP on the DCR bus (and
accessing it from the PPC405)?

Thanks.


Article: 104517
Subject: Re: keys to the Kingdom
From: David R Brooks <davebXXX@iinet.net.au>
Date: Thu, 29 Jun 2006 01:48:48 -0800
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> David,
> 
> OK.  Then you are also unable to comply with FIPS-140-2.
> 
> If you need not comply with that standard, then we are right back in 
> with V5.
> 
> There are many tricks up our sleeves...remember my ONLY complaint is 
> that an efuse solution is not compliant with NIST standards on secure 
> SYSTEMS.
> 
> If you do not need to meet that standard, then, we have ways....
> 
> Austin
> 
[snip]
FIPS140 is not an issue for us: we are trying to stop people reverse 
engineering our design. A well-resourced adversary can hack EPROM bits, 
but it's felt to be a low enough risk to be tolerable (these aren't my 
decisions.)
 >
 > PS:  engine controls?  What engine needs the power of a FPGA???
 >
More ways to skin the cat... Options considered included a relatively 
simple CPU, with a small FPGA alongside, generating the waveforms; or a 
larger CPU doing it all. We finally settled for the large CPU route.

Article: 104518
Subject: Stopping the clock for power management
From: "Ndf" <ndf123456789@yahoo.fr>
Date: Thu, 29 Jun 2006 11:49:08 +0200
Links: << >>  << T >>  << A >>
Hello,

For a low power application I would like to stop the clock feed into a FPGA
when enter  “sleep mode”. This is a common practice or can be dangerous? And
if is dangerous why? Maybe a silly question but I want to be sure about
that! I use Lattice XP parts.



Thanks,

Dan.



Article: 104519
Subject: Problem to extend Xilinx GSRD Design
From: tester <test@test.de>
Date: Thu, 29 Jun 2006 12:06:53 +0200
Links: << >>  << T >>  << A >>
Hi i'm using the Xilinx GSRD design.

Now i try to connect a simple IP core to the reference design.
The problem is that i can not connect my IP to the OPB or PLB bus. The 2 
PLB Bus controllers supports only 1 Master and 1 Slave and they are 
alread connected.

The connection over the OPB does not work because they use a DCR2OPB 
bridge. May be the way over the DCR is a solution? How can i manage this 
connection. Are there some examples?

Eric

Article: 104520
Subject: Xilinx BUFGMUX Setup Time requirement clarification needed
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Thu, 29 Jun 2006 10:17:52 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hello,

e.g. the XC3SE Datasheet ds312 tells on page 59 in the Clock
Buffers/Multiplexers  section:

"As specified in DC and Switching Characteristics (Module 3), the select
input has a setup time requirement."

This is probaly Tgsi on page 139. 

What can happen if the setup time is not met ("End of the world as we knew
it?:-)) ? Does the select signal need to be aligned to both input clock
edges? If it needs to be aligned to both clocks, how does one achieve
that. An if there are that harsh requirements on the select signal, what's
the whole point in the BUFGMUX?

Or does the select signal only needs to be aligned with the active
edge. Simple latching the enable signal with the BUFGMUX output clock and
feeding the latch output to the select of BUFGMUX would do the job (beside
the case where the active clock is slow, where the time to the next clock
would be needed before the clocks would switch.

Some clarification would be fine.

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 104521
Subject: Re: Achieving timing in Xilinx EDK designs
From: Andi <00andi@web.de>
Date: Thu, 29 Jun 2006 03:34:14 -0700
Links: << >>  << T >>  << A >>
use xst ( ISE 8.1 SP3 ). I used the edk wizard to see what files i need for adding cores and then created the user ips with those files as often as i needed.

Is it possible to use other tool than xst for edk synthesis?

Article: 104522
Subject: Re: keys to the Kingdom
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 29 Jun 2006 22:52:35 +1200
Links: << >>  << T >>  << A >>
David R Brooks wrote:

> Austin Lesea wrote:
> 
>> David,
>>
>> OK.  Then you are also unable to comply with FIPS-140-2.
>>
>> If you need not comply with that standard, then we are right back in 
>> with V5.
>>
>> There are many tricks up our sleeves...remember my ONLY complaint is 
>> that an efuse solution is not compliant with NIST standards on secure 
>> SYSTEMS.
>>
>> If you do not need to meet that standard, then, we have ways....
>>
>> Austin
>>
> [snip]
> FIPS140 is not an issue for us: we are trying to stop people reverse 
> engineering our design. A well-resourced adversary can hack EPROM bits, 
> but it's felt to be a low enough risk to be tolerable (these aren't my 
> decisions.)
>  >
>  > PS:  engine controls?  What engine needs the power of a FPGA???
>  >
> More ways to skin the cat... Options considered included a relatively 
> simple CPU, with a small FPGA alongside, generating the waveforms; or a 
> larger CPU doing it all. We finally settled for the large CPU route.

The FLASH CPLD/FPGAs from Altera/Lattice/Actel could assist here.

Of course, the 'larger CPU' guys are not standing still either:

I see TI's recent announcement of TMS320F28015 : $3.25/10K, gets you
32 bit DSP, 32KF, 12KR, PWM steps well under 1ns, and 12 bit
ADCs well over 1MSPS. - Just the ADC alone is worth $3.25, and
the high end PWM is similar, means the FLASH + 32 bit CPU is
almost 'for free' :)

-jg




Article: 104523
Subject: Re: Help in the platform studio(EDK)
From: "subint" <subin.82@gmail.com>
Date: 29 Jun 2006 05:22:32 -0700
Links: << >>  << T >>  << A >>
Thanks antti
           But it's for MT46V16M16 and for the virtex2 fpga.does it
work for me?
regards
subin
Antti wrote:
> subint schrieb:
>
> > Antti wrote:
> >
> > > If you want to play around with DDR memory then take some DDR IP core
> > > any play with it.
> > >
> > > Antti
> >
> > Hi Antti,
> >      Do you know from where i get a free DDR IP core.My ddr is
> > MT46V32M16 -6 and the board i am using is  a Memec V4
> > board(DS-BD-V4LX60MB rev-3).And there is daugter card through which i
> > connect the fpga to the 922T ARM core.
> > Thanks in advance
> > regards
> > subin
>
> http://www.opencores.org/projects.cgi/web/ddr_sdr/overview
>
> http://www.xilinx.com/bvdocs/appnotes/xapp709.pdf
> 
> takes 2 minutes to find those BTW
> 
> Antti


Article: 104524
Subject: Generic synthesis target in Synplify Pro
From: "rnbrady" <rnbrady@gmail.com>
Date: 29 Jun 2006 05:37:31 -0700
Links: << >>  << T >>  << A >>
Hi folks

I'm working with Synplify Pro (8.5.1) and I'm trying to test whether
VHDL code is synthesizable. How can I do this without selecting a
specific vendor or chip? Is it possible? I thought there might be some
concept of a generic target, but can't find anything of the sort.

In particular, I want to get the mapped VHDL file from Synplify and
bring it back into ModelSim for simulation and functional verification.
So, to tell whether my code is synthesizable, I have to do the
following:

1. Select a specific chip
2. Run the synthesis
3. Bring the mapped VHDL netlist file into ModelSim
4. Bring vendor specific files into ModelSim because they are required
by mapped file.
5. simulate for that chip.

Is there another way?

Thanks in advance,
Richard




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